DATASHEET

HFA1109
®
Data Sheet
April 23, 2007
450MHz, Low Power, Current Feedback
Video Operational Amplifier
FN4019.5
Features
• Wide - 3dB Bandwidth (AV = +2) . . . . . . . . . . . . . 450MHz
The HFA1109 is a high speed, low power, current feedback
amplifier built with Intersil’s proprietary complementary
bipolar UHF-1 process. This amplifier features a unique
combination of power and performance specifically tailored
for video applications.
The HFA1109 is a standard pinout op amp. It is a higher
performance, drop-in replacement (no feedback resistor
change required) for the CLC409.
• Gain Flatness (To 250MHz) . . . . . . . . . . . . . . . . . . . 0.8dB
• Very Fast Slew Rate (AV = +2). . . . . . . . . . . . . . 1100V/μs
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . 1.7MΩ
• Differential Gain/Phase . . . . . . . . . . . . . . . . . 0.02%/0.02°
• Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
• Pb-Free Plus Anneal Available (RoHS Compliant)
If a comparably performing op amp with an output disable
function (useful for video multiplexing) is required, please
refer to the HFA1149 data sheet..
Applications
Ordering Information
• Video Switchers and Routers
PART
NUMBER
PART
MARKING
TEMP.
RANGE
(°C)
• Professional Video Processing
• Medical Imaging
PKG.
DWG. #
PACKAGE
HFA1109IB
1109IB
-40 to +85 8 Ld SOIC (150MIL) M8.15
HFA1109IBZ
(Note 1)
HFA1109
IBZ
-40 to +85 8 Ld SOIC (150MIL) M8.15
(Pb-free)
HFA1109IBZ96 HFA1109
(Note 1)
IBZ
-40 to +85 8 Ld SOIC (150MIL) M8.15
(Pb-free)
• PC Multimedia Systems
• Video Distribution Amplifiers
• Flash Converter Drivers
• Radar/IF Processing
Pinout
HFA11XXEVAL DIP Evaluation Board for High Speed Op Amps
(Note 2)
HFA1109
(8 LD SOIC)
TOP VIEW
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Requires a SOIC-to-DIP adapter. See “Evaluation Board” section
inside.
1
NC
1
8
NC
-IN
2
7
V+
+IN
3
6
OUT
V-
4
5
NC
+
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999, 2004, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HFA1109
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V
Output Current (Note 4) . . . . . . . . . . . . . . . . . Short Circuit Protected
30mA Continuous
60mA ≤ 50% Duty Cycle
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .1400V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . . .2000V
Machine Model (Per EIAJ ED-4701Method C-111) . . . . . . . . . .50V
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . +175°C
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle) output
current must not exceed 30mA for maximum reliability.
VSUPPLY = ±5V, AV = +2, RF = 250Ω, RL = 100Ω, Unless Otherwise Specified.
Electrical Specifications
PARAMETER
TEST CONDITIONS
(NOTE 5)
TEST
LEVEL
TEMP. (°C)
MIN
TYP
MAX
UNITS
A
25
-
1
5
mV
A
Full
-
2
8
mV
B
Full
-
10
-
μV/°C
A
25
47
50
-
dB
A
Full
45
48
-
dB
A
25
50
53
-
dB
A
Full
47
51
-
dB
A
25
-
4
10
μA
A
Full
-
5
15
μA
B
Full
-
30
-
nA/°C
A
25
-
0.5
1
μA/V
A
Full
-
0.5
3
μA/V
A
25
-
2
10
μA
A
Full
-
3
15
μA
B
Full
-
40
-
nA/°C
A
25
-
3
6
μA/V
A
Full
-
3
8
μA/V
A
25
-
1.6
5
μA/V
A
Full
-
1.6
8
μA/V
A
25, 85
0.8
1.7
-
MΩ
A
-40
0.5
1.4
-
MΩ
B
25
-
60
-
Ω
INPUT CHARACTERISTICS
Input Offset Voltage
Average Input Offset Voltage Drift
Input Offset Voltage
Common-Mode Rejection Ratio
DVCM = ±2V
Input Offset Voltage
Power Supply Rejection Ratio
DVPS = ±1.25V
Non-Inverting Input Bias Current
Non-Inverting Input Bias Current Drift
Non-Inverting Input Bias Current
Power Supply Sensitivity
DVPS = ±1.25V
Inverting Input Bias Current
Inverting Input Bias Current Drift
Inverting Input Bias Current
Common-Mode Sensitivity
DVCM = ±2V
Inverting Input Bias Current
Power Supply Sensitivity
DVPS = ±1.25V
Non-Inverting Input Resistance
DVCM = ±2V
Inverting Input Resistance
2
FN4019.5
April 23, 2007
HFA1109
VSUPPLY = ±5V, AV = +2, RF = 250Ω, RL = 100Ω, Unless Otherwise Specified. (Continued)
Electrical Specifications
(NOTE 5)
TEST
LEVEL
TEMP. (°C)
MIN
TYP
MAX
UNITS
Input Capacitance
B
25
-
1.6
-
pF
Input Voltage Common Mode Range
(Implied by VIO CMRR, +RIN, and -IBIAS CMS
tests)
A
Full
±2
±2.5
-
V
B
25
-
4
-
nV/√Hz
B
25
-
2.4
-
pA/√Hz
B
25
-
40
-
pA/√Hz
Open Loop Transimpedance Gain (Note 6)
B
25
-
500
-
kΩ
Minimum Stable Gain
B
Full
-
1
-
V/V
B
25
300
375
-
MHz
B
Full
290
360
-
MHz
AV = +1, +RS = 550Ω (PDIP),
+RS = 700Ω (SOIC)
B
25
280
330
-
MHz
B
Full
260
320
-
MHz
AV = +2
B
25
390
450
-
MHz
B
Full
350
410
-
MHz
B
25
-
0
0.2
dB
B
Full
-
0
0.5
dB
B
25
-1.0
-0.45
-
dB
B
Full
-1.1
-0.45
-
dB
B
25
-1.6
-0.75
-
dB
B
Full
-1.7
-0.75
-
dB
B
25
-1.9
-0.85
-
dB
B
Full
-2.2
-0.85
-
dB
B
25
±0.3
±0.1
-
dB
B
Full
±0.4
±0.1
-
dB
B
25
±0.8
±0.35
-
dB
B
Full
±0.9
±0.35
-
dB
B
25
±1.3
±0.6
-
dB
B
Full
±1.4
±0.6
-
dB
A
25
±3
±3.2
-
V
A
Full
±2.8
±3
-
V
A
25, 85
±33
±36
-
mA
A
-40
±30
±33
-
mA
PARAMETER
TEST CONDITIONS
Input Noise Voltage Density (Note 6)
f = 100kHz
Non-Inverting Input Noise Current Density
(Note 4)
Inverting Input Noise Current Density
(Note 4)
f = 100kHz
TRANSFER CHARACTERISTICS
AC CHARACTERISTICS
-3dB Bandwidth
(VOUT = 0.2VP-P, Note 6)
AV = -1, RF = 200Ω
Gain Peaking
AV = +2, VOUT = 0.2VP-P
Gain Flatness
(AV = +2, VOUT = 0.2VP-P, Note 6)
To 125MHz
To 200MHz
To 250MHz
Gain Flatness
(AV = +1, +RS = 550Ω (PDIP),
+RS = 700Ω (SOIC), VOUT = 0.2VP-P,
(Note 6)
To 125MHz
To 200MHz
To 250MHz
OUTPUT CHARACTERISTICS
Output Voltage Swing, Unloaded
(Note 6)
AV = -1, RL = Infinity
Output Current
(Note 6)
AV = -1, RL = 75Ω
Output Short Circuit Current
AV = -1
B
25
-
120
-
mA
Closed Loop Output Resistance (Note 6)
DC, AV = +1
B
25
-
0.05
-
W
3
FN4019.5
April 23, 2007
HFA1109
VSUPPLY = ±5V, AV = +2, RF = 250Ω, RL = 100Ω, Unless Otherwise Specified. (Continued)
Electrical Specifications
PARAMETER
TEST CONDITIONS
(NOTE 5)
TEST
LEVEL
TEMP. (°C)
MIN
TYP
MAX
UNITS
Second Harmonic Distortion
(VOUT = 2VP-P, Note 6)
20MHz
B
25
-
-55
-
dBc
60MHz
B
25
-
-57
-
dBc
Third Harmonic Distortion
(VOUT = 2VP-P, Note 6)
20MHz
B
25
-
-68
-
dBc
60MHz
B
25
-
-60
-
dBc
Reverse Isolation (S12)
30MHz
B
25
-
-65
-
dB
VOUT = 0.5VP-P
B
25
-
1.1
1.3
ns
B
Full
-
1.1
1.4
ns
B
25
-
0
2
%
B
Full
-
0.5
5
%
B
25
2300
2600
-
V/μs
B
Full
2200
2500
-
V/μs
B
25
475
550
-
V/μs
B
Full
430
500
-
V/μs
B
25
940
1100
-
V/μs
B
Full
800
950
-
V/μs
To 0.1%
B
25
-
19
-
ns
To 0.05%
B
25
-
23
-
ns
To 0.01%
B
25
-
36
-
ns
VIN = ±2V
B
25
-
5
-
ns
RL = 150Ω
B
25
-
0.02
0.06
%
B
Full
-
0.03
0.09
%
B
25
-
0.04
0.09
%
B
Full
-
0.05
0.12
%
B
25
-
0.02
0.06
°
B
Full
-
0.02
0.06
°
B
25
-
0.05
0.09
°
B
Full
-
0.06
0.13
°
Power Supply Range
C
25
±4.5
-
±5.5
V
Power Supply Current (Note 6)
A
25
-
9.6
10
mA
A
Full
-
10
11
mA
TRANSIENT CHARACTERISTICS
Rise and Fall Times
Overshoot
VOUT = 0.5VP-P
Slew Rate
AV = -1, RF = 200Ω
VOUT = 5VP-P
AV = +1, VOUT = 4VP-P,
+RS = 550Ω (PDIP),
+RS = 700Ω (SOIC)
AV = +2, VOUT = 5VP-P
Settling Time
(VOUT = +2V to 0V step, Note 6)
Overdrive Recovery Time
VIDEO CHARACTERISTICS
Differential Gain
(f = 3.58MHz)
RL = 75Ω
Differential Phase
(f = 3.58MHz)
RL = 150Ω
RL = 75Ω
POWER SUPPLY CHARACTERISTICS
NOTES:
5. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
6. See Typical Performance Curves for more information.
4
FN4019.5
April 23, 2007
HFA1109
Application Information
ground plane is a must! Attention should be given to
decoupling the power supplies. A large value (10μF)
tantalum in parallel with a small value (0.1μF) chip capacitor
works well in most cases.
Optimum Feedback Resistor
Although a current feedback amplifier’s bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
amplifier’s unique relationship between bandwidth and RF.
All current feedback amplifiers require a feedback resistor,
even for unity gain applications, and RF, in conjunction with
the internal compensation capacitor, sets the dominant pole
of the frequency response. Thus, the amplifier’s bandwidth is
inversely proportional to RF. The HFA1109 design is
optimized for a 250Ω RF at a gain of +2. Decreasing RF
decreases stability, resulting in excessive peaking and
overshoot (Note: Capacitive feedback will cause the same
problems due to the feedback impedance decrease at higher
frequencies). At higher gains the amplifier is more stable, so
RF can be decreased in a trade-off of stability for bandwidth.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
Care must also be taken to minimize the capacitance to ground
seen by the amplifier’s inverting input (-IN). The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and possible instability. Thus it is recommended that
the ground plane be removed under traces connected to -IN,
and connections to -IN should be kept as short as possible.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
TABLE 1. OPTIMUM FEEDBACK RESISTOR
GAIN (ACL)
RF (W)
BANDWIDTH (MHz)
-1
200
400
+1
250 (+RS = 550W) PDIP
250 (+RS = 700W) SOIC
350
+2
250
450
+5
100
160
+10
90
70
RS and CL form a low pass network at the output, thus
limiting system bandwidth well below the amplifier
bandwidth. By decreasing RS as CL increases, the
maximum bandwidth is obtained without sacrificing stability.
In spite of this, bandwidth still decreases as the load
capacitance increases.
Evaluation Board
Table 1 lists recommended RF values, and the expected
bandwidth, for various closed loop gains. For a gain of +1, a
resistor (+RS) in series with +IN is required to reduce gain
peaking and increase stability
The performance of the HFA1105 may be evaluated using
the HFA11XX Evaluation Board and a SOIC to DIP adaptor
like the Aries Electronics Part Number 14-350000-10. The
layout and schematic of the board are shown in Figure 1.
PC Board Layout
Please contact your local sales office for information. When
evaluating this amplifier, the two 510Ω gain setting resistors
on the evaluation board should be changed to 250Ω..
The frequency response of this amplifier depends greatly on
the care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
510Ω
510Ω
50Ω
VH
1
8
2
7
VH
0.1µF
10µF
50Ω
IN
10µF
3
6
4
5
+5V
OUT
VL
GND
0.1µF
-5V
1
+IN
OUT V+
VL VGND
GND
FIGURE 1A. BOARD SCHEMATIC
FIGURE 1B. TOP LAYOUT
FIGURE 1C. BOTTOM LAYOUT
FIGURE 1. EVALUATION BOARD SCHEMATICS AND LAYOUT
5
FN4019.5
April 23, 2007
HFA1109
Typical Performance Curves
VSUPPLY = ±5V, TA = +25°C, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω,
Unless Otherwise Specified
200
2.0
AV = +2
150
1.5
100
1.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
AV = +2
50
0
-50
-100
-150
0.5
0
-0.5
-1.0
-1.5
-200
-2.0
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 2. SMALL SIGNAL PULSE RESPONSE
FIGURE 3. LARGE SIGNAL PULSE RESPONSE
200
2.0
AV = +1
150
1.5
100
1.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
AV = +1
50
0
-50
-100
0.5
0
-0.5
-1.0
-150
-1.5
-200
TIME (5ns/DIV)
FIGURE 4. SMALL SIGNAL PULSE RESPONSE
6
-2.0
TIME (5ns/DIV)
FIGURE 5. LARGE SIGNAL PULSE RESPONSE
FN4019.5
April 23, 2007
HFA1109
Typical Performance Curves
VSUPPLY = ±5V, TA = +25°C, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω,
Unless Otherwise Specified (Continued)
2.0
200
AV = -1
150
1.5
100
1.0
OUTPUT VOLTAGE (V)
50
0
-50
0.5
0
-0.5
-100
-1.0
-150
-1.5
-2.0
-200
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 7. LARGE SIGNAL PULSE RESPONSE
FIGURE 6. SMALL SIGNAL PULSE RESPONSE
2.0
200
1.5
100
AV = +5
50
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
150
AV = +10
AV = +10
0
-50
AV = +5
-100
1.0
0.5
AV = +10
0
AV = +10
-0.5
-1.0
-150
-2.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
VOUT = 200mVP-P
AV = + 1
GAIN
0
-3
AV = +1
PHASE
A V = -1
0
90
AV = +1
180
A V = -1
1M
10M
100M
FREQUENCY (Hz)
FIGURE 10. FREQUENCY RESPONSE
7
270
700M
NORMALIZED GAIN (dB)
FIGURE 9. LARGE SIGNAL PULSE RESPONSE
NORMALIZED PHASE (DEGREES)
GAIN (dB)
FIGURE 8. SMALL SIGNAL PULSE RESPONSE
0.3M
AV = +5
-1.5
-200
3
AV = +5
3
VOUT = 200mVP-P
AV = +2
GAIN
0
AV = +10
-3
AV = +5
PHASE
AV = + 2
90
AV = +10
A V = +5
0.3M
1M
10M
0
100M
180
PHASE (°)
OUTPUT VOLTAGE (mV)
AV = -1
270
700M
FREQUENCY (Hz)
FIGURE 11. FREQUENCY RESPONSE
FN4019.5
April 23, 2007
HFA1109
Typical Performance Curves
VSUPPLY = ±5V, TA = +25°C, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω,
Unless Otherwise Specified (Continued)
116
VOUT = 200mVP-P
( VIOI ) )
96
-0.1
-0.2
-0.3
-0.4
-0.5
86
76
AZOL (dB, 20 LOG
NORMALIZED GAIN (dB)
106
AV = + 1
0
AV = + 2
-0.6
-0.7
1M
10M
FREQUENCY (Hz)
100M
66
0
56
45
46
90
36
135
26
180
0.01M
500M
FIGURE 13. OPEN LOOP TRANSIMPEDANCE
-30
-20
AV = +1
AV = +1
100MHz
-30
-40
100MHz
-40
DISTORTION (dBc)
-50
50MHz
-60
20MHz
10MHz
-70
-80
-90
-50
50MHz
-60
-70
20MHz
-90
-6
-3
0
3
6
OUTPUT POWER (dBm)
9
12
-100
-6
-3
0
3
6
OUTPUT POWER (dBm)
9
12
FIGURE 15. 3rd HARMONIC DISTORTION vs POUT
-30
-30
AV = +2
AV = +2
-40
-40
100MHz
DISTORTION (dBc)
100MHz
-50
50MHz
-60
10MHz
-70
-50
50MHz
-60
20MHz
-70
20MHz
10MHz
-80
-90
10MHz
-80
FIGURE 14. 2nd HARMONIC DISTORTION vs POUT
DISTORTION (dBc)
500M
FREQUENCY (Hz)
FIGURE 12. GAIN FLATNESS
DISTORTION (dBc)
0.1M 0.3M 1M 3M 6M10M30M 100M
PHASE (°)
0.1
-80
-6
-3
0
3
6
9
OUTPUT POWER (dBm)
12
FIGURE 16. 2nd HARMONIC DISTORTION vs POUT
8
15
-90
-6
-3
0
3
6
9
OUTPUT POWER (dBm)
12
15
FIGURE 17. 3rd HARMONIC DISTORTION vs POUT
FN4019.5
April 23, 2007
HFA1109
Typical Performance Curves
VSUPPLY = ±5V, TA = +25°C, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω,
Unless Otherwise Specified (Continued)
-20
-20
VOUT = 2VP-P
VOUT = 2VP-P
-30
-30
DISTORTION (dBc)
DISTORTION (dBc)
AV = +1
-40
-40
-50
AV = -1
-50
AV = +2, -1
-60
AV = +2
-60
AV = +1
-70
-70
AV = +1
-80
0M
10M 20M 30M 40M 50M 60M 70M 80M 90M 100M
FREQUENCY (Hz)
FIGURE 18. 2nd HARMONIC DISTORTION vs FREQUENCY
-80
0M
10M 20M 30M 40M 50M 60M 70M 80M 90M 100M
FREQUENCY (Hz)
FIGURE 19. 3rd HARMONIC DISTORTION vs FREQUENCY
3.6
3.4
1k
+VOUT (RL = 100Ω)
|-VOUT| (RL = 100Ω)
3.2
OUTPUT VOLTAGE (V)
OUTPUT RESISTANCE (Ω)
AV = +2
100
10
1
0.1
0.01
3.0 +VOUT (RL = 50Ω)
+VOUT (RL = 50Ω)
2.8
2.6
|-VOUT| (RL = 100Ω)
2.4
2.2
|-VOUT| (RL = 50Ω)
2.0
1.8
0.3
1M
10M
100M
1.6
-75
1000M
-50
-25
FREQUENCY (Hz)
14.0
17
13.5
16
50
75
100
125
15
13.0
12.5
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
25
FIGURE 21. OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 20. CLOSED LOOP OUTPUT RESISTANCE
12.0
11.5
11.0
10.5
10.0
9.50
14
13
VS = ±8V
12
11
10
9
VS = ±5V
8
7
VS = ±4V
6
9.00
8.50
0
TEMPERATURE (°C)
5
4
4.5
5
5.5
6.5
6
SUPPLY VOLTAGE (±V)
7
7.5
FIGURE 22. SUPPLY CURRENT vs SUPPLY VOLTAGE
9
8
4
-75
-50
-25
0
25
50
TEMPERATURE (°C)
75
100
125
FIGURE 23. SUPPLY CURRENT vs TEMPERATURE
FN4019.5
April 23, 2007
HFA1109
Typical Performance Curves
VSUPPLY = ±5V, TA = +25°C, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω,
Unless Otherwise Specified (Continued)
100
100
AV = +2
VOUT = 2V
10
10
ENI
INI+
SETTLING ERROR (%)
INI+
NOISE CURRENT (pA/√Hz)
NOISE VOLTAGE (nV/√Hz)
0.1
INI-
0.05
0.025
0
-0.025
-0.05
-0.1
1
1
0.1k
1k
10k
FREQUENCY (Hz)
100k
FIGURE 24. INPUT NOISE CHARACTERISTICS
10
10
20
30
40
50
60
70
80
90
100
TIME (ns)
FIGURE 25. SETTLING RESPONSE
FN4019.5
April 23, 2007
HFA1109
Die Characteristics
GLASSIVATION:
Type: Nitride
Thickness: 4kÅ ±0.5kÅ
DIE DIMENSIONS:
59milsx80milsx19mils
1500μmx2020μmx483μm
TRANSISTOR COUNT:
130
METALLIZATION:
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8kÅ ±0.4kÅ
SUBSTRATE POTENTIAL (POWERED UP):
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kÅ ±0.8kÅ
Metallization Mask Layout
Floating (Recommend Connection to V-)
HFA1109
NC
NC
NC
NC
V+
-IN
OUT
NC
NC
+IN
11
V-
NC
NC
FN4019.5
April 23, 2007
HFA1109
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN4019.5
April 23, 2007
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