DATASHEET

HFA1110
ESIGNS
NEW D
R
O
F
D
PART
E
E ME N T
MMEND
C
O
A
C
L
E
P
R
E
N OT
ED R
2
MME N D
Data
June 6, 2006
RECOSheet
HFA111
750MHz, Low Distortion Unity Gain,
Closed Loop Buffer
FN2944.8
Features
• Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . 750MHz
The HFA1110 is a unity gain closed loop buffer that achieves
-3dB bandwidth of 750MHz, while offering excellent video
performance and low distortion. Manufactured on Intersil’s
proprietary complementary bipolar UHF-1 process, the
HFA1110 also offers very fast slew rate, and high output
current. It is one more example of Intersil’s intent to enhance
its leadership position in products for high speed signal
processing applications.
The HFA1110’s settling time of 11ns to 0.1%, low distortion
and ability to drive capacitive loads make it an ideal flash
A/D driver.
The HFA1110 is an enhanced, pin compatible upgrade for
the AD9620, AD9630, CLC110, EL2072, BUF600 and
BUF601.
For buffer applications requiring a standard op amp pinout,
or selectable gain (-1, +1, +2), see the HFA1112 data sheet.
For output limiting see the HFA1113 data sheet.
• Very Fast Slew Rate. . . . . . . . . . . . . . . . . . . . . . 1300V/s
• Fast Settling Time (0.2%). . . . . . . . . . . . . . . . . . . . . . 7ns
• High Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 60mA
• Fixed Gain of +1
• Gain Flatness (100MHz) . . . . . . . . . . . . . . . . . . . . 0.03dB
• Differential Phase . . . . . . . . . . . . . . . . . . . . . . . . . . 0.025°
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.04%
• 3rd Harmonic Distortion (50MHz). . . . . . . . . . . . . . -80dBc
• 3rd Order Intercept (100MHz) . . . . . . . . . . . . . . . . 30dBm
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Video Switching and Routing
• RF/IF Processors
For military grade product please refer to the HFA1110/883
data sheet.
• Driving Flash A/D Converters
Pinout
• Impedance Transformation
HFA1110
(SOIC)
TOP VIEW
V+
1
OPT V+
2
NC
IN
• Line Driving
• Radar Systems
8
OUT
7
NC
3
6
OPT V-
4
5
V-
- +
• High-Speed Communications
Ordering Information
PART
NUMBER
PART
TEMP.
MARKING RANGE (°C) PACKAGE
PKG.
DWG. #
HFA1110IB
1110IB
-40 to 85
8 Ld SOIC
M8.15
HFA1110IBZ
(Note)
1110IBZ
-40 to 85
8 Ld SOIC
(Pb-free)
M8.15
HFA1110EVAL High Speed Buffer DIP Evaluation Board
Pin Descriptions
NAME
PIN
NUMBER
V+
1
Positive Supply
Opt V+
2
Optional Positive Supply
NC
3
No Connection
IN
4
Input
V-
5
Negative Supply
Opt V-
6
Optional Negative Supply
NC
7
No Connection
OUT
8
Output
DESCRIPTION
1
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HFA1110
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA
Thermal Resistance (Typical, Note 1)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
JA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
158
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
VSUPPLY = 5V, RL = 100, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
TEMP (°C)
MIN
TYP
MAX
UNITS
Output Offset Voltage (Note 2)
25
-
8
25
mV
Full
-
-
35
mV
Output Offset Voltage Drift
Full
-
10
-
V/°C
25
39
45
-
dB
Full
35
-
-
dB
INPUT CHARACTERISTICS
PSRR
Input Noise Voltage (Note 2)
100kHz
25
-
14
-
nV/Hz
Input Noise Current (Note 2)
100kHz
25
-
51
-
pA/Hz
25
-
10
40
A
Full
-
-
65
A
Input Resistance
25
25
50
-
k
Input Capacitance
25
-
2
-
pF
25
0.980
0.990
1.02
V/V
Full
0.975
-
1.025
V/V
25
-
0.003
-
%
25
3.0
3.3
-
V
Input Bias Current (Note 2)
TRANSFER CHARACTERISTICS
Gain
VOUT = 2VP-P
DC Non-Linearity (Note 2)
2V Full Scale
OUTPUT CHARACTERISTICS
Output Voltage (Note 2)
Full
2.5
3.0
-
V
25, 85
50
60
-
mA
-40
35
50
-
mA
Supply Voltage Range
Full
4.5
-
5.5
V
Supply Current (Note 2)
25
-
21
26
mA
Full
-
-
33
mA
RL = 50
Output Current (Note 2)
POWER SUPPLY CHARACTERISTICS
AC CHARACTERISTICS
-3dB Bandwidth (Note 2)
VOUT = 0.2VP-P
25
-
750
-
MHz
Slew Rate
VOUT = 5VP-P
25
-
1300
-
V/s
Full Power Bandwidth (Note 2)
VOUT = 4VP-P
25
-
150
-
MHz
Gain Flatness (Note 2)
To 100MHz
25
-
0.03
-
dB
To 30MHz
25
-
0.01
-
dB
Linear Phase Deviation (Note 2)
DC to 100MHz
25
-
0.3
-
°
2nd Harmonic Distortion (Note 2)
50MHz, VOUT = 2VP-P
25
-
-60
-
dBc
3rd Harmonic Distortion (Note 2)
50MHz, VOUT = 2VP-P
25
-
-80
-
dBc
3rd Order Intercept (Note 2)
100MHz
25
-
30
-
dBm
2
FN2944.8
June 6, 2006
HFA1110
Electrical Specifications
VSUPPLY = 5V, RL = 100, Unless Otherwise Specified (Continued)
TEMP (°C)
MIN
TYP
MAX
UNITS
-1dB Gain Compression
PARAMETER
100MHz
TEST CONDITIONS
25
-
14
-
dBm
Reverse Gain (S12, Note 2)
100MHz, VOUT = 1VP-P
25
-
-60
-
dB
TRANSIENT RESPONSE
Rise Time
VOUT = 0.5V Step
25
-
0.5
-
ns
Overshoot (Note 2)
VOUT = 1.0V Step, Input Signal
Rise/Fall = 1ns
25
-
2.5
-
%
0.2% Settling Time (Note 2)
VOUT = 1V to 0V
25
-
7
-
ns
0.1% Settling Time (Note 2)
VOUT = 1V to 0V
Overdrive Recovery Time
25
-
11
-
ns
25
-
15
-
ns
Differential Gain
3.58MHz, RL = 75
25
-
0.04
-
%
Differential Phase
3.58MHz, RL = 75
25
-
0.025
-
°
NOTE:
2. See Typical Performance Curves for more information.
Application Information
50
0.1F
PC Board Layout
The frequency performance of this amplifier depends a great
deal on the amount of care taken in designing the PC board.
The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10F) tantalum in parallel with a small value
chip (0.1F) capacitor works well in most cases.
1
+5V
10F
2
3
IN
8
OUT
RS
7
HFA1110
4
6
-5V
5
10F
50
0.1F
SCHEMATIC DIAGRAM
BOTTOM LAYOUT
Terminated microstrip signal lines are recommended at the
input and output of the device. Output capacitance, such as
that resulting from an improperly terminated transmission
line will degrade the frequency response of the amplifier and
may cause oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output.
See the “Recommended RS vs Load Capacitance” graph for
specific recommendations.
An example of a good high frequency layout is the
Evaluation Board shown below.
Evaluation Board
An evaluation board is available for the HFA1110 (part
number HFA1110EVAL). Please contact your local sales
office for information.
TOP LAYOUT
The layout and schematic of the board are shown here:
NOTE: The SOIC version may be evaluated in the DIP board by
using a SOIC-to-DIP adapter such as Aries Electronics Part Number
08-350000-10.
3
1
FN2944.8
June 6, 2006
HFA1110
Typical Performance Curves
VSUPPLY = 5V, TA = 25°C, RL = 100Unless Otherwise Specified
1.2
80
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
120
40
0
-40
-80
-120
0.8
0.4
0
-0.4
-0.8
-1.2
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 1. SMALL SIGNAL PULSE RESPONSE
FIGURE 2. LARGE SIGNAL PULSE RESPONSE
2
-45
-2
-90
-3
-135
-4
-180
PHASE
VOUT = 200mVP-P
-5
-6
RL = 100
3
0
RL = 50
-3
-6
0
-225
-90
-270
-180
-7
-8
0
200M
400M
600M
800M
1M
1G
-360
1G
100M
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE
FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
890
1
870
BANDWIDTH (MHz)
0
-1
-2
VOUT = 200mVP-P
VOUT = 2.5VP-P
VOUT = 4VP-P
-3
-4
-5
850
830
810
790
770
750
-6
730
-7
710
-8
10M
FREQUENCY (Hz)
2
GAIN (dB)
-270
RL = 1k
PHASE (°)
0
-1
GAIN (dB)
GAIN (dB)
0
RL = 1k
6
PHASE (°)
GAIN
VOUT = 200mVP-P
VOUT = 1VP-P
1
1M
10M
100M
FREQUENCY (Hz)
1G
FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
4
-50
-30
-10
10
30
50
70
90
110
130
TEMPERATURE (°C)
FIGURE 6. -3dB BANDWIDTH vs TEMPERATURE
FN2944.8
June 6, 2006
HFA1110
VSUPPLY = 5V, TA = 25°C, RL = 100Unless Otherwise Specified (Continued)
0.25
2.0
0.20
1.5
0.15
1.0
DEVIATION (°)
GAIN (dB)
Typical Performance Curves
0.10
0.05
0
0.5
0
-0.5
-1.0
-0.05
-1.5
-0.10
-2.0
1M
10M
FREQUENCY (Hz)
0
100M 200M
15M 30M 45M 60M 75M 90M 105M 120M 135M 150M
FREQUENCY (Hz)
FIGURE 7. GAIN FLATNESS
FIGURE 8. DEVIATION FROM LINEAR PHASE
-30
+90
PHASE
GAIN
-40
+45
0
-50
-60
INTERCEPT POINT (dBm)
+135
PHASE (°)
GAIN (dB)
50
-20
40
30
20
10
VOUT = 1VP-P
0
200M
400M
600M
800M
0
1G
0
50M
100M
150M
200M
250M
400M
FIGURE 9. REVERSE GAIN AND PHASE (S12)
FIGURE 10. TWO-TONE, THIRD ORDER INTERMODULATION
INTERCEPT
-30
-40
-40
100MHz
-50
DISTORTION (dBc)
DISTORTION (dBc)
350M
FREQUENCY (Hz)
-30
50MHz
-60
-70
30MHz
-80
100MHz
-50
-60
-70
50MHz
-80
30MHz
-90
-90
-100
300M
FREQUENCY (Hz)
-100
-5
-3
-1
1
3
5
7
9
11
OUTPUT POWER (dBm)
FIGURE 11. SECOND HARMONIC DISTORTION vs POUT
5
13
-5
-3
-1
1
3
5
7
9
11
13
OUTPUT POWER (dBm)
FIGURE 12. THIRD HARMONIC DISTORTION vs POUT
FN2944.8
June 6, 2006
HFA1110
Typical Performance Curves
VSUPPLY = 5V, TA = 25°C, RL = 100Unless Otherwise Specified (Continued)
0.8
0.4
0.2
0
-0.2
-0.4
RS ()
SETTLING ERROR (%)
VOUT = 1V
-0.8
-5
0
5
10
15
20
25
30
35
40
50
45
40
35
30
25
20
15
10
5
0
0
40
80
120
45
200
240
280
320
360
CL (pF)
TIME (ns)
FIGURE 13. SETTLING RESPONSE
160
FIGURE 14. RECOMMENDED SERIES OUTPUT RESISTOR vs
CLOAD
0.04
21
RL = 200
0.02
15
RL = 100
12
VO = 2.0VP-P
VO = 1.0VP-P
9
RL = 1k
ERROR (%)
OVERSHOOT (%)
18
6
0
-0.02
VO = 0.5VP-P
3
0
200
300
400
500
600
700
800
900
-0.04
1000
-3.0
-2.0
-1.0
0
1.0
INPUT VOLTAGE (V)
INPUT RISE TIME (ps)
3.0
FIGURE 16. INTEGRAL LINEARITY ERROR
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
25
24
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
FIGURE 15. OVERSHOOT vs INPUT RISETIME
2.0
23
22
21
20
19
18
17
5
6
7
8
9
TOTAL SUPPLY VOLTAGE (V+ - V-, V)
FIGURE 17. SUPPLY CURRENT vs SUPPLY VOLTAGE
6
10
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 18. SUPPLY CURRENT vs TEMPERATURE
FN2944.8
June 6, 2006
HFA1110
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
-60
VSUPPLY = 5V, TA = 25°C, RL = 100Unless Otherwise Specified (Continued)
10
OUTPUT OFFSET VOLTAGE (mV)
BIAS CURRENT (A)
Typical Performance Curves
-40
-20
0
20
40
60
80
100
9.8
9.6
9.4
9.2
9
8.8
8.6
8.4
8.2
8
7.8
-60
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 19. BIAS CURRENT vs TEMPERATURE
FIGURE 20. OFFSET VOLTAGE vs TEMPERATURE
3.8
100
200
80
160
60
120
3.5
+VOUT (RL = 100)
3.4
3.3
+VOUT (RL = 50)
|-VOUT |(RL = 100)
3.2
3.1
|-VOUT |(RL = 50)
3
40
80
INI
20
40
2.9
2.8
-60
NOISE CURRENT (pA/Hz)
3.6
NOISE VOLTAGE (nV/Hz)
OUTPUT VOLTAGE (V)
3.7
ENI
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 21. OUTPUT VOLTAGE vs TEMPERATURE
7
120
0
100
1k
10k
0
100k
FREQUENCY (Hz)
FIGURE 22. INPUT NOISE vs FREQUENCY
FN2944.8
June 6, 2006
HFA1110
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
63 mils x 44 mils x 19 mils
1600m x 1130m x 483m
Type: Nitride
Thickness: 4kÅ 0.5kÅ
METALLIZATION:
TRANSISTOR COUNT:
Type: Metal 1: AlCu(2%)/TiW
Thickness: Metal 1: 8kÅ 0.4kÅ
Type: Metal 2: AlCu(2%)
Thickness: Metal 2: 16kÅ 0.8kÅ
52
SUBSTRATE POTENTIAL (POWERED UP):
Floating (Recommend Connection to V-)
Metallization Mask Layout
HFA1110
NC
IN
V-
NC
NC
NC
NC
V+
OUT
8
FN2944.8
June 6, 2006
HFA1110
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
0.25(0.010) M
H
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e

B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N

NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN2944.8
June 6, 2006
Similar pages