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1-888-IN
850MHz, Low Distortion, Output Limiting,
Programmable Gain, Buffer Amplifier
The HFA1113 is a high speed Buffer featuring user
programmable gain and output limiting coupled with ultra
high speed performance. This buffer is the ideal choice for
high frequency applications requiring output limiting,
especially those needing ultra fast overload recovery times.
The output limiting function allows the designer to set the
maximum positive and negative output levels, thereby
protecting later stages from damage or input saturation. The
sub-nanosecond overdrive recovery time quickly returns the
amplifier to linear operation following an overdrive condition.
A unique feature of the pinout allows the user to select a
voltage gain of +1, -1, or +2, without the use of any external
components, as described in the “Application Information”
section. Compatibility with existing op amp pinouts provides
flexibility to upgrade low gain amplifiers, while decreasing
component count. Unlike most buffers, the standard pinout
provides an upgrade path should a higher closed loop gain
be needed at a future date.
HFA1113
FN1342.6
July 11, 2005
Features
• User Programmable Output Voltage Limiting
• User Programmable For Closed-Loop Gains of +1, -1 or
+2 Without Use of External Resistors
• Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . 850MHz
• Excellent Gain Flatness (to 100MHz). . . . . . . . . . 0.07dB
• Low Differential Gain and Phase . . . 0.02%/0.04 Degrees
• Low Distortion (HD3, 30MHz) . . . . . . . . . . . . . . . . -73dBc
• Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . 2400V/s
• Fast Settling Time (0.1%). . . . . . . . . . . . . . . . . . . . . 13ns
• High Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 60mA
• Excellent Gain Accuracy . . . . . . . . . . . . . . . . . . . 0.99V/V
• Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . . <1ns
• Standard Operational Amplifier Pinout
• Pb-Free Plus Anneal Available (RoHS Compliant)
Component and composite video systems will also benefit
from this buffer’s performance, as indicated by the excellent
gain flatness, and 0.02%/0.04 Degree Differential
Gain/Phase specifications (RL = 150).
Applications
For Military product, refer to the HFA1113/883 data sheet.
• High-Speed Communications
TEMP.
RANGE (oC)
PACKAGE
-40 to 85
8 Ld SOIC
PKG.
DWG. #
M8.15
-40 to 85
8 Ld SOIC
M8.15
(Pb-free)
8 Ld SOIC Tape and Reel
M8.15
(Pb-free)
DIP Evaluation Board For High Speed Op Amps
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
HFA1113
(SOIC)
TOP VIEW
NC
300
1
• Driving Flash A/D Converters
• Impedance Transformation
Ordering Information
PART NUMBER
(BRAND)
HFA1113IB
(H1113I)
HFA1113IBZ
(H1113I) (Note)
HFA1113IBZ96
(H1113I) (Note)
HFA11XXEVAL
• RF/IF Processors
-
• Radar Systems
• Medical Imaging Systems
Pin Descriptions
NAME
PIN NUMBER
DESCRIPTION
NC
1
No Connection
-IN
2
Inverting Input
+IN
3
Non-Inverting Input
V-
4
Negative Supply
VL
5
Lower Output Limit
OUT
6
Output
VH
V+
7
Positive Supply
7
V+
VH
8
Upper Output Limit
-IN
2
+IN
3
6
OUT
V-
4
5
VL
1
• Video Switching and Routing
8
300
+
• Line Driving
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HFA1113
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Voltage at VH or VL Terminal . . . . . . . . . . . . . . (V+) + 2V to (V-) - 2V
Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . 60mA
Thermal Resistance (Typical, Note 1)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
158
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
VSUPPLY = 5V, AV = +1, RL = 100, Unless Otherwise Specified
TEMP.
(oC)
MIN
TYP
MAX
UNITS
25
-
8
25
mV
Full
-
-
35
mV
Output Offset Voltage Drift
Full
-
10
-
V/oC
PSRR
25
39
45
-
dB
Full
35
-
-
dB
PARAMETER
TEST CONDITIONS
INPUT CHARACTERISTICS
Output Offset Voltage
Input Noise Voltage (Note 3)
100kHz
25
-
9
-
nV/Hz
+Input Noise Current (Note 3)
100kHz
25
-
37
-
pA/Hz
25
-
25
40
A
Full
-
-
65
A
Non-Inverting Input Resistance
25
25
50
-
k
Inverting Input Resistance (Note 2)
25
240
300
360

Input Capacitance
25
-
2
-
pF
Input Common Mode Range
Full
2.5
2.8
-
V
25
0.980
0.990
1.020
V/V
Full
0.975
-
1.025
V/V
25
1.96
1.98
2.04
V/V
Full
1.95
-
2.05
V/V
AV = +2, 2V Full Scale
25
-
0.02
-
%
AV = -1
25
3.0
3.3
-
V
Full
2.5
3.0
-
V
25, 85
50
60
-
mA
-40
35
50
-
mA
25
-
0.3
-

Supply Voltage Range
Full
4.5
-
5.5
V
Supply Current (Note 3)
25
-
21
26
mA
Full
-
-
33
mA
Non-Inverting Input Bias Current
TRANSFER CHARACTERISTICS
Gain
AV = +1, VIN = +2V
AV = +2, VIN = +1V
DC Non-Linearity (Note 3)
OUTPUT CHARACTERISTICS
Output Voltage (Note 3)
Output Current (Note 3)
RL = 50
Closed Loop Output Impedance
DC, AV = +2
POWER SUPPLY CHARACTERISTICS
2
FN1342.6
July 11, 2005
HFA1113
Electrical Specifications
VSUPPLY = 5V, AV = +1, RL = 100, Unless Otherwise Specified (Continued)
PARAMETER
TEMP.
(oC)
MIN
TYP
MAX
UNITS
AV = -1
25
450
800
-
MHz
AV = +1
25
500
850
-
MHz
AV = +2
25
350
550
-
MHz
TEST CONDITIONS
AC CHARACTERISTICS
-3dB Bandwidth
(VOUT = 0.2VP-P, Notes 2, 3)
Slew Rate
(VOUT = 5VP-P, Note 2)
AV = -1
25
1500
2400
-
V/s
AV = +1
25
800
1500
-
V/s
AV = +2
25
1100
1900
-
V/s
AV = -1
25
-
300
-
MHz
AV = +1
25
-
150
-
MHz
AV = +2
25
-
220
-
MHz
AV = -1
25
-
0.02
-
dB
AV = +1
25
-
0.1
-
dB
AV = +2
25
-
0.015
0.04
dB
AV = -1
25
-
0.05
-
dB
AV = +1
25
-
0.2
-
dB
AV = +2
25
-
0.036
0.08
dB
Gain Flatness
(to 100MHz, Notes 2, 3)
AV = -1
25
-
0.10
-
dB
AV = +2
25
-
0.07
0.22
dB
Linear Phase Deviation
(to 100MHz, Note 3)
AV = -1
25
-
0.13
-
Degrees
AV = +1
25
-
0.83
-
Degrees
AV = +2
25
-
0.05
-
Degrees
2nd Harmonic Distortion
(30MHz, VOUT = 2VP-P, Notes 2, 3)
AV = -1
25
-
-52
-
dBc
AV = +1
25
-
-57
-
dBc
AV = +2
25
-
-52
-45
dBc
AV = -1
25
-
-71
-
dBc
AV = +1
25
-
-73
-
dBc
AV = +2
25
-
-72
-65
dBc
AV = -1
25
-
-47
-
dBc
AV = +1
25
-
-53
-
dBc
AV = +2
25
-
-47
-40
dBc
AV = -1
25
-
-63
-
dBc
AV = +1
25
-
-68
-
dBc
AV = +2
25
-
-65
-55
dBc
AV = -1
25
-
-41
-
dBc
AV = +1
25
-
-50
-
dBc
AV = +2
25
-
-42
-35
dBc
Full Power Bandwidth
(VOUT = 5VP-P, Note 3)
Gain Flatness
(to 30MHz, Notes 2, 3)
Gain Flatness
(to 50MHz, Notes 2, 3)
3rd Harmonic Distortion
(30MHz, VOUT = 2VP-P, Notes 2, 3)
2nd Harmonic Distortion
(50MHz, VOUT = 2VP-P, Notes 2, 3)
3rd Harmonic Distortion
(50MHz, VOUT = 2VP-P, Notes 2, 3)
2nd Harmonic Distortion
(100MHz, VOUT = 2VP-P , Notes 2, 3)
3rd Harmonic Distortion
(100MHz, VOUT = 2VP-P , Notes 2, 3)
3
AV = -1
25
-
-55
-
dBc
AV = +1
25
-
-49
-
dBc
AV = +2
25
-
-62
-45
dBc
FN1342.6
July 11, 2005
HFA1113
Electrical Specifications
VSUPPLY = 5V, AV = +1, RL = 100, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
TEMP.
(oC)
MIN
TYP
MAX
UNITS
3rd Order Intercept
(AV = +2, Note 3)
100MHz
25
-
28
-
dBm
300MHz
25
-
13
-
dBm
1dB Compression
(AV = +2, Note 3)
100MHz
25
-
19
-
dBm
300MHz
25
-
12
-
dBm
Reverse Isolation
(S12, Note 3)
40MHz
25
-
-70
-
dB
100MHz
25
-
-60
-
dB
600MHz
25
-
-32
-
dB
AV = -1
25
-
500
800
ps
AV = +1
25
-
480
750
ps
AV = +2
25
-
700
1000
ps
AV = -1
25
-
0.82
-
ns
AV = +1
25
-
1.06
-
ns
AV = +2
25
-
1.00
-
ns
AV = -1
25
-
12
30
%
AV = +1
25
-
45
65
%
AV = +2
25
-
6
20
%
0.1% Settling Time (Note 3)
VOUT = 2V to 0V
25
-
13
20
ns
0.05% Settling Time
VOUT = 2V to 0V
25
-
20
33
ns
Differential Gain
AV = +1, 3.58MHz, RL = 150
25
-
0.03
-
%
AV = +2, 3.58MHz, RL = 150
25
-
0.02
-
%
Differential Phase
AV = +1, 3.58MHz, RL = 150
25
-
0.05
-
Degrees
AV = +2, 3.58MHz, RL = 150
25
-
0.04
-
Degrees
TRANSIENT CHARACTERISTICS
Rise Time
(VOUT = 0.5V Step, Note 2)
Rise Time
(VOUT = 2V Step)
Overshoot
(VOUT = 0.5V Step,
Input tR/tF = 200ps, Notes 2, 3, 4)
OUTPUT LIMITING CHARACTERISTICS
AV = +2, VH = +1V, VL = -1V, Unless Otherwise Specified
VIN = 1.6V, AV = -1
Clamp Accuracy (Note 3)
25
-
100
150
mV
Full
-
-
200
mV
Clamp Overshoot
VIN = 1V, Input tR/tF = 500ps
25
-
7
-
%
Overdrive Recovery Time (Note 3)
VIN = 1V
25
-
0.75
1.5
ns
Negative Clamp Range
25
-
-5.0 to
+2.0
-
V
Positive Clamp Range
25
-
-2.0 to
+5.0
-
V
Clamp Input Bias Current (Note 3)
25
-
50
200
A
Full
-
-
300
A
25
-
500
-
MHz
Clamp Input Bandwidth (Note 3)
VH or VL = 100mVP-P
NOTES:
2. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-lot variation.
3. See Typical Performance Curves for more information.
4. Overshoot decreases as input transition times increase, especially for AV = +1. Please refer to Typical Performance Curves.
4
FN1342.6
July 11, 2005
HFA1113
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
Application Information
Closed Loop Gain Selection
The HFA1113 features a novel design which allows the user
to select from three closed loop gains, without any external
components. The result is a more flexible product, fewer part
types in inventory, and more efficient use of board space.
This “buffer” operates in closed loop gains of -1, +1, or +2,
and gain selection is accomplished via connections to the
Inputs. Applying the input signal to +IN and floating -IN
selects a gain of +1, while grounding -IN selects a gain of
+2. A gain of -1 is obtained by applying the input signal to
-IN with +IN grounded.
The table below summarizes these connections:
CONNECTIONS
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the RS and CL
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
RS and CL form a low pass network at the output, thus
limiting system bandwidth well below the amplifier bandwidth
of 850MHz. By decreasing RS as CLincreases (as illustrated
in the curves), the maximum bandwidth is obtained without
sacrificing stability. Even so, bandwidth does decrease as
you move to the right along the curve. For example, at
AV = +1, RS = 50, CL = 30pF, the overall bandwidth is
limited to 300MHz, and bandwidth drops to 100MHz at
AV = +1, RS = 5, CL = 340pF.
GAIN (ACL)
+INPUT
(PIN 3)
-INPUT
(PIN 2)
-1
GND
Input
+1
Input
NC (Floating)
50
+2
Input
GND
45
AV = +1
40
35
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
30
Attention should be given to decoupling the power supplies.
A large value (10F) tantalum in parallel with a small value
chip (0.1F) capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
For unity gain applications, care must also be taken to
minimize the capacitance to ground seen by the amplifier’s
inverting input. At higher frequencies this capacitance will
tend to short the -INPUT to GND, resulting in a closed loop
gain which increases with frequency. This will cause
excessive high frequency peaking and potentially other
problems as well.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
5
RS ()
PC Board Layout
25
20
15
10
5
AV = +2
0
0
40
80
120
160
200
240
280 320
360 400
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
CAPACITANCE
Evaluation Board
The performance of the HFA1113 may be evaluated using
the HFA11XX Evaluation Board, slightly modified as follows:
1. Remove the 500 feedback resistor (R2), and leave the
connection open.
2. a. For AV = +1 evaluation, remove the 500 gain setting
resistor (R1), and leave pin 2 floating.
b. For AV = +2, replace the 500 gain setting resistor with
a 0 resistor to GND.
The modified schematic and layout of the board are shown
in Figures 2 and 3.
To order evaluation boards (part number HFA11XXEVAL),
please contact your local sales office.
NOTE: The SOIC version may be evaluated in the DIP board by
using a SOIC-to-DIP adapter such as Aries Electronics Part Number
08-350000-10.
FN1342.6
July 11, 2005
HFA1113
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
 (AV = +1)
OR 0 (AV = +2)
.
VH
R1
50
IN
10F
1
8
2
7
3
6
4
5
(V-IN - VOUT)/RF + V-IN/RG
0.1F
10F
+5V
50
0.1F
OUT
VL
GND
GND
-5V
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
TOP LAYOUT
This current is mirrored onto the high impedance node (Z) by
QX3-QX4, where it is converted to a voltage and fed to the
output via another unity gain buffer. If no clamping is utilized,
the high impedance node may swing within the limits defined
by QP4 and QN4. Note that when the output reaches its
quiescent value, the current flowing through -IN is reduced
to only that small current (-IBIAS) required to keep the output
at the final voltage.
Tracing the path from VH to Z illustrates the effect of the
clamp voltage on the high impedance node. VH decreases
by 2VBE (QN6 and QP6) to set up the base voltage on QP5.
V+
VH
QP3
1
50K
(30K
FOR VL )
QP4
+IN
QN2
OUT
V+
VL
VGND
QP1
+IN
R1
Z
ICLAMP
VV+
+1
200
QN1
BOTTOM LAYOUT
QN5
QP2
QP6
QN3
QN4
V300
VH
QN6
QP5
V-IN
RG
(INTERNAL)
RF = 300
(INTERNAL)
-IN
VOUT
FIGURE 4. HFA1113 SIMPLIFIED VH CLAMP CIRCUITRY
FIGURE 3. EVALUATION BOARD LAYOUT
Limiting Operation
General
The HFA1113 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the VH and VL terminals (pins 8 and
5) of the amplifier. VH sets the upper output limit, while VL
sets the lower clamp level. If the amplifier tries to drive the
output above VH, or below VL, the clamp circuitry limits the
output voltage at VH or VL ( the clamp accuracy),
respectively. The low input bias currents of the clamp pins
allow them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.
Clamp Circuitry
Figure 4 shows a simplified schematic of the HFA1113 input
stage, and the high clamp (VH) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (QX1 - QX2)
6
QP5 begins to conduct whenever the high impedance node
reaches a voltage equal to QP5’s base voltage + 2VBE (QP5
and QN5). Thus, QP5 clamps node Z whenever Z reaches
VH. R1 provides a pull-up network to ensure functionality
with the clamp inputs floating. A similar description applies to
the symmetrical low clamp circuitry controlled by VL.
When the output is clamped, the negative input continues to
source a slewing current (ICLAMP) in an attempt to force the
output to the quiescent voltage defined by the input. QP5
must sink this current while clamping, because the -IN
current is always mirrored onto the high impedance node.
The clamping current is calculated as:
ICLAMP = (V-IN - VOUT CLAMPED)/300 + V-IN/RG.
As an example, a unity gain circuit with VIN = 2V, and VH = 1V,
would have ICLAMP = (2V - 1V)/300 + 2V/ = 3.33mA
(RG =  because -IN is floated for unity gain applications).
Note that ICC will increase by ICLAMP when the output is
clamp limited.
FN1342.6
July 11, 2005
HFA1113
Clamp Accuracy
The clamped output voltage will not be exactly equal to the
voltage applied to VH or VL. Offset errors, mostly due to VBE
mismatches, necessitate a clamp accuracy parameter which
is found in the device specifications. Clamp accuracy is a
function of the clamping conditions. Referring again to
Figure 4, it can be seen that one component of clamp
accuracy is the VBE mismatch between the QX6 transistors,
and the QX5 transistors. If the transistors always ran at the
same current level there would be no VBE mismatch, and no
contribution to the inaccuracy. The QX6 transistors are
biased at a constant current, but as described earlier, the
current through QX5 is equivalent to ICLAMP. VBE increases
as ICLAMP increases, causing the clamped output voltage to
increase as well. ICLAMP is a function of the overdrive level
(AVCL x VIN - VOUT CLAMPED), so clamp accuracy
degrades as the overdrive increases. As an example, the
specified accuracy of 100mV (AV = -1, VH = 1V) for a 1.6X
overdrive degrades to 240mV for a 3X (200%) overdrive, as
shown in Figure 43.
Consideration must also be given to the fact that the clamp
voltages have an affect on amplifier linearity. The
“Nonlinearity Near Clamp Voltage” curve, Figure 48,
illustrates the impact of several clamp levels on linearity.
Clamp Range
Unlike some competitor devices, both VH and VL have
usable ranges that cross 0V. While VH must be more
positive than VL , both may be positive or negative, within the
Typical Performance Curves
range restrictions indicated in the specifications. For
example, the HFA1113 could be limited to ECL output levels
by setting VH = -0.8V and VL = -1.8V. VH and VL may be
connected to the same voltage (GND for instance) but the
result won’t be in a DC output voltage from an AC input
signal. A 150mV - 200mV AC signal will still be present at
the output.
Recovery from Overdrive
The output voltage remains at the clamp level as long as the
overdrive condition remains. When the input voltage drops
below the overdrive level (VCLAMP/AVCL) the amplifier will
return to linear operation. A time delay, known as the
Overdrive Recovery Time, is required for this resumption of
linear operation. The plots of “Unclamped Performance” and
“Clamped Performance” (Figures 41 and 42) highlight the
HFA1113’s subnanosecond recovery time. The difference
between the unclamped and clamped propagation delays is
the overdrive recovery time. The appropriate propagation
delays are 8.0ns for the unclamped pulse, and 8.8ns for the
clamped (2X overdrive) pulse yielding an overdrive recovery
time of 800ps. The measurement uses the 90% point of the
output transition to ensure that linear operation has
resumed. Note: The propagation delay illustrated is
dominated by the fixturing. The delta shown is accurate, but
the true HFA1113 propagation delay is 500ps.
Overdrive recovery time is also a function of the overdrive
level. Figure 47 details the overdrive recovery time for
various clamp and overdrive levels.
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified
200
1.5
100
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
150
2.0
AV = +2
50
0
-50
-100
-150
AV = +2
1.0
0.5
0
-0.5
-1.0
-1.5
-200
-2.0
TIME (5ns/DIV.)
FIGURE 5. SMALL SIGNAL PULSE RESPONSE
7
TIME (5ns/DIV.)
FIGURE 6. LARGE SIGNAL PULSE RESPONSE
FN1342.6
July 11, 2005
HFA1113
Typical Performance Curves
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
2.0
200
AV = +1
AV = +1
1.5
100
OUTPUT VOLTAGE (V)
50
0
-50
-100
-150
1.0
0.5
0
-0.5
-1.0
-1.5
-200
-2.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 7. SMALL SIGNAL PULSE RESPONSE
FIGURE 8. LARGE SIGNAL PULSE RESPONSE
200
2.0
AV = -1
AV = -1
1.5
100
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
150
50
0
-50
-100
1.0
0.5
0
-0.5
-1.0
-150
-1.5
-200
-2.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 10. LARGE SIGNAL PULSE RESPONSE
6
VOUT = 200mVP-P
AV = +1
GAIN
0
-3
AV = -1
AV = +2
PHASE
-6
9
0
-9
AV = +2
AV = -1
AV = +1
-90
-180
-270
-360
0.3
1
10
100
FREQUENCY (MHz)
FIGURE 11. FREQUENCY RESPONSE
8
1000
GAIN (dB)
3
NORMALIZED PHASE (DEGREES)
NORMALIZED GAIN (dB)
FIGURE 9. SMALL SIGNAL PULSE RESPONSE
AV = +2, VOUT = 200mVP-P
GAIN
6
3
RL = 50
RL = 100
RL = 1k
0
PHASE
0
RL = 100
RL = 50
RL = 1k
0.3
1
10
100
FREQUENCY (MHz)
-90
-180
-270
-360
1000
PHASE (DEGREES)
OUTPUT VOLTAGE (mV)
150
FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
FN1342.6
July 11, 2005
HFA1113
GAIN
0
RL = 1k
-3
RL = 100
-6
RL = 50
0
-90
RL = 100
-180
RL = 50
-270
RL = 1k
-360
1000
10
100
FREQUENCY (MHz)
FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
GAIN
4.0VP-P
2.5VP-P
3
PHASE
0
4.0VP-P
2.5VP-P
1VP-P
-180
-270
-360
1
GAIN (dB)
3
0
AV = -1
GAIN
10
100
FREQUENCY (MHz)
0
-90
-180
PHASE (DEGREES)
90
10
100
FREQUENCY (MHz)
1000
FIGURE 17. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
9
VOUT = 2.5VP-P
VOUT = 1VP-P
0
-90
VOUT = 4VP-P
-180
VOUT = 2.5VP-P
-270
VOUT = 1VP-P
-360
1
10
100
FREQUENCY (MHz)
1000
FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
VOUT = 5VP-P
12
180
1
-180
1000
VOUT = 4VP-P
-3
15
PHASE
0.3
-90
GAIN
0.3
-6
VOUT = 1VP-P
10
100
FREQUENCY (MHz)
0
VOUT = 4VP-P
VOUT = 2.5VP-P
1
0
AV = +1
3
VOUT = 2.5VP-P
VOUT = 4VP-P
180
FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
1000
VOUT = 1VP-P
-3
0.3
PHASE
FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
6
RL = 1k
-6
-90
0.3
RL = 50
GAIN (dB)
1VP-P
RL = 100
90
6
AV = +2
6
0
RL = 50
-6
PHASE
NORMALIZED GAIN (dB)
9
RL = 100
PHASE (DEGREES)
GAIN (dB)
12
0
-3
PHASE (DEGREES)
PHASE
1
RL = 1k
GAIN
-9
-9
0.3
AV = -1, VOUT = 200mVP-P
3
PHASE (DEGREES)
3
GAIN (dB)
6
AV = +1, VOUT = 200mVP-P
GAIN (dB)
6
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
PHASE (DEGREES)
Typical Performance Curves
9
6
3
0
AV = -1
-3
AV = +2
-6
AV = +1
-9
-12
-15
0.3
1
10
FREQUENCY (MHz)
100
1000
FIGURE 18. FULL POWER BANDWIDTH
FN1342.6
July 11, 2005
HFA1113
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
Typical Performance Curves
900
0.35
AV = +1
850
AV = -1
NORMALIZED GAIN (dB)
BANDWIDTH (MHz)
800
0.30
750
700
650
600
AV = +2
550
0.25
0.20
AV = -1
AV = +1
0.15
0.10
0.05
0
-0.05
AV = +2
-0.10
500
-50
-25
0
25
50
75
100
-0.15
125
TEMPERATURE (oC)
1
10
FREQUENCY (MHz)
FIGURE 19. -3dB BANDWIDTH vs TEMPERATURE
100
FIGURE 20. GAIN FLATNESS
4
AV = +2, VOUT = 2V
3
0.6
1
AV = -1
0
-1
AV = +2
-2
AV = +1
-3
SETTLING ERROR (%)
DEVIATION (DEGREES)
2
0.4
0.2
0.1
0
-0.1
-0.2
-0.4
-0.6
-4
-5
0
15
30
45
60
75
90
105
120
135
-2
150
3
8
13
FREQUENCY (MHz)
18
23
28
33
38
FIGURE 21. DEVIATION FROM LINEAR PHASE
48
FIGURE 22. SETTLING RESPONSE
235
-24
-30
AV = +1
PHASE
-36
AV = +1
-42
-24
-54
-30
AV = +2 AV = -1
AV = -1
-60
-66
AV = +2
-72
-78
180
90
45
AV = -1
-48
GAIN (dB)
GAIN (dB)
43
TIME (ns)
AV = +2
GAIN
AV = +2
0
PHASE (DEGREES)
-6
-36
-42
-48
AV = -1
AV = -1
-54
-84
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY (MHz)
FIGURE 23. LOW FREQUENCY REVERSE ISOLATION (S12)
10
-60
100 190
280 370 460 550 640 730
FREQUENCY (MHz)
820 910 1000
FIGURE 24. HIGH FREQUENCY REVERSE ISOLATION (S12)
FN1342.6
July 11, 2005
HFA1113
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
30
20
AV = -1
16
14
AV = +2
12
10
8
AV = +1
6
4
AV = -1
20
AV = +2
AV = +1
10
2
0
100
200
300
FREQUENCY (MHz)
400
-20
0
100
500
FIGURE 25. 1dB GAIN COMPRESSION vs FREQUENCY
-20
AV = +2
-30
-30
-40
-40
-50
-60
100MHz
30MHz
50MHz
-70
AV = +2
-60
-70
-80
-90
-90
-100
-6
-3
0
3
6
9
12
15
-6
-3
0
3
6
9
12
15
18
OUTPUT POWER (dBm)
FIGURE 27. SECOND HARMONIC DISTORTION vs POUT
FIGURE 28. THIRD HARMONIC DISTORTION vs POUT
-20
-20
AV = +1
-30
AV = +1
-30
-40
-40
DISTORTION (dBc)
DISTORTION (dBc)
30MHz
50MHz
100MHz
OUTPUT POWER (dBm)
-50
-60
-70
100MHz
50MHz
30MHz
-80
-50
-60
-70
100MHz
-80
50MHz
-90
-90
-100
400
-50
-80
-100
200
300
FREQUENCY (MHz)
FIGURE 26. THIRD ORDER INTERMODULATION INTERCEPT
vs FREQUENCY
DISTORTION (dBc)
DISTORTION (dBc)
2 - TONE
18
INTERCEPT POINT (dBm)
OUTPUT POWER AT 1dB COMPRESSION (dBm)
Typical Performance Curves
30MHz
-100
-6
-3
0
3
6
9
OUTPUT POWER (dBm)
12
15
FIGURE 29. SECOND HARMONIC DISTORTION vs POUT
11
-6
-3
0
3
6
9
OUTPUT POWER (dBm)
12
15
FIGURE 30. THIRD HARMONIC DISTORTION vs POUT
FN1342.6
July 11, 2005
HFA1113
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
Typical Performance Curves
-20
-20
-30
-30
-40
-40
DISTORTION (dBc)
DISTORTION (dBc)
AV = -1
-50
-60
-70
50MHz
100MHz
30MHz
AV = -1
-50
-60
-70
-80
-80
-90
-90
30MHz
50MHz
100MHz
-100
-100
-6
-3
0
3
6
9
OUTPUT POWER (dBm)
12
-6
15
-3
0
3
6
9
12
15
OUTPUT POWER (dBm)
FIGURE 31. SECOND HARMONIC DISTORTION vs POUT
FIGURE 32. THIRD HARMONIC DISTORTION vs POUT
60
0.04
VOUT = 0.5V
0.02
OVERSHOOT (%)
PERCENT ERROR (%)
50
0
AV = +1
40
30
20
-0.02
AV = -1
10
AV = +2
0
-0.04
-3.0
-2.0
-1.0
0
1.0
INPUT VOLTAGE (V)
2.0
100
3.0
500
700
900
1100
1300
INPUT RISE TIME (ps)
FIGURE 33. INTEGRAL LINEARITY ERROR
FIGURE 34. OVERSHOOT vs INPUT RISE TIME
60
60
VOUT = 1V
VOUT = 2V
50
50
40
OVERSHOOT (%)
OVERSHOOT (%)
300
AV = +1
30
20
40
30
AV = -1
20
AV = -1
10
AV = +1
AV = +2
10
0
100
AV = +2
300
500
700
900
1100
INPUT RISE TIME (ps)
FIGURE 35. OVERSHOOT vs INPUT RISE TIME
12
1300
0
100
300
500
700
900
INPUT RISE TIME (ps)
1100
1300
FIGURE 36. OVERSHOOT vs INPUT RISE TIME
FN1342.6
July 11, 2005
HFA1113
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
25
24
SUPPLY CURRENT (mA)
23
22
21
20
19
18
17
16
5
6
7
8
9
TOTAL SUPPLY VOLTAGE (V+ - V-, V)
15
10
FIGURE 37. SUPPLY CURRENT vs SUPPLY VOLTAGE
3.5
AV = -1
+VOUT (RL= 50
OUTPUT VOLTAGE (V)
3.4
3.3
3.2
+VOUT (RL= 100
|-VOUT| (RL= 100
3.1
3.0
2.9
2.8
|-VOUT| (RL= 50
-25
0
25
50
75
TEMPERATURE (oC)
100
125
FIGURE 38. SUPPLY CURRENT vs TEMPERATURE
NOISE VOLTAGE (nV/Hz)
3.6
-50
50
130
40
110
30
90
20
70
ENI
10
50
NOISE CURRENT (pA/Hz)
SUPPLY CURRENT (mA)
Typical Performance Curves
INI
2.7
2.6
-50
-25
0
25
50
75
TEMPERATURE (oC)
100
125
0
0.1
FIGURE 39. OUTPUT VOLTAGE vs TEMPERATURE
1
10
FREQUENCY (kHz)
30
100
FIGURE 40. INPUT NOISE CHARACTERISTICS
AV = +2
IN
0V TO
0.5V
IN
0V TO
1V
OUT
0V TO
1V
OUT
0V TO
1V
TIME (20ns/DIV.)
FIGURE 41. UNCLAMPED PERFORMANCE
13
AV = +2
TIME (20ns/DIV.)
FIGURE 42. CLAMPED PERFORMANCE
FN1342.6
July 11, 2005
HFA1113
Typical Performance Curves
350
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
250
AV = 1
AV = 1
VL = -500mV
VH = 500mV
CLAMP ACCURACY (mV)
CLAMP ACCURACY (mV)
300
250
VH = 1V
200
150
VH = 2V
100
VH = 100mV
200
VL = -1V
150
100
VL = -2V
50
50
0
VL = -100mV
0
0
100
200
300
400
500
100
0
OVERDRIVE (% OF VH)
FIGURE 43. VH CLAMP ACCURACY vs OVERDRIVE
AV = +2
VH = 1V
300
CLAMP ACCURACY (mV)
CLAMP ACCURACY (mV)
400
500
250
AV = 2
VH = 2V
200
VH = 500mV
100
VH = 100mV
VL = -1V
200
VL = -500mV
150
VL = -2V
100
50
VL = -100mV
0
100
200
300
400
0
500
0
100
OVERDRIVE (% OF VH)
FIGURE 45. VH CLAMP ACCURACY vs OVERDRIVE
3500
20
3000
15
VH = 2V
2000
1500
VH = 1V
1000
VH = 0.5V
500
0
100
10
14
VL = -2V VL = -1V
5
0
-5
VH = 1V
-10
-20
FIGURE 47. OVERDRIVE RECOVERY vs OVERDRIVE
500
VH = 2V
VH = 3V
-15
VH = 0.1V
200
300
400
OVERDRIVE LEVEL (% OF CLAMP LEVEL)
400
AV = -1
VL = -3V
2500
200
300
OVERDRIVE (% OF VL)
FIGURE 46. VL CLAMP ACCURACY vs OVERDRIVE
VOUT - (AV x VIN) (mV)
OVERDRIVE RECOVERY TIME (ps)
300
FIGURE 44. VL CLAMP ACCURACY vs OVERDRIVE
400
0
200
OVERDRIVE (% OF VL)
500
-3
-2
-1
0
AV x VIN (V)
1
2
3
FIGURE 48. NON-LINEARITY NEAR CLAMP VOLTAGE
FN1342.6
July 11, 2005
HFA1113
Typical Performance Curves
140
130
AV = -1, VIN = 1.6V
VH = 1V, VL = -1V
VH = 1V, VL = -1V
120
120
CLAMP BIAS CURRENT (A)
130
CLAMP ACCURACY (mV)
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
VH
110
100
90
VL
80
70
110
100
90
VL
80
70
60
VH
50
40
30
60
-75
-50
-25
0
25
50
75
100
125
20
-75
150
-50
-25
75
25
0
50
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 49. CLAMP ACCURACY vs TEMPERATURE
125
150
FIGURE 50. CLAMP BIAS CURRENT vs TEMPERATURE
6
6
VH = 300mVP-P
3
0
-3
-6
VH = 600mVP-P
VH = 1.2VP-P
-9
10
100
FREQUENCY (MHz)
-3
-6
VL = 600mVP-P
VL = 1.2VP-P
-12
1000
FIGURE 51. VH CLAMP INPUT BANDWIDTH
15
0
-9
-12
1
VL = 300mVP-P
3
GAIN (dB)
GAIN (dB)
100
1
10
100
FREQUENCY (MHz)
1000
FIGURE 52. VL CLAMP INPUT BANDWIDTH
FN1342.6
July 11, 2005
HFA1113
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
63 mils x 44 mils x 19 mils
1600m x 1130m x 483m
Type: Nitride
Thickness: 4kÅ 0.5kÅ
METALLIZATION:
TRANSISTOR COUNT:
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8kÅ 0.4kÅ
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kÅ 0.8kÅ
52
SUBSTRATE POTENTIAL (POWERED UP):
Floating (Recommend Connection to V-)
Metallization Mask Layout
HFA1113
NC
+IN
V-
VL
-IN
VH
NC
V+
OUT
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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16
FN1342.6
July 11, 2005
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