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Data eSheet
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1- 888 -
HFA1212
®
Dual 350MHz, Low Power Closed Loop
Buffer Amplifier
July 2004
FN3607.6
Features
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . 0.025%
The HFA1212 is a dual closed loop Buffer featuring user
programmable gain and high speed performance.
Manufactured on Intersil’s proprietary complementary
bipolar UHF-1 process, these devices offer wide -3dB
bandwidth of 350MHz, very fast slew rate, excellent gain
flatness and high output current.
A unique feature of the pinout allows the user to select a
voltage gain of +1, -1, or +2, without the use of any external
components. Gain selection is accomplished via
connections to the inputs, as described in the “Application
Information” section. The result is a more flexible product,
fewer part types in inventory, and more efficient use of board
space.
Compatibility with existing op amp pinouts provides flexibility
to upgrade low gain amplifiers, while decreasing component
count. Unlike most buffers, the standard pinout provides an
upgrade path should a higher closed loop gain be needed at
a future date.
• Differential Phase. . . . . . . . . . . . . . . . . . . . . 0.03 Degrees
• Wide -3dB Bandwidth (AV = +2) . . . . . . . . . . . . . 350MHz
• Very Fast Slew Rate (AV = -1) . . . . . . . . . . . . . . 1100V/µs
• Low Supply Current . . . . . . . . . . . . . . . . . . . . 6mA/Buffer
• High Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 60mA
• Excellent Gain Accuracy . . . . . . . . . . . . . . . . . . . 0.99V/V
• User Programmable For Closed-Loop Gains of +1, -1 or
+2 Without Use of External Resistors
• Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns
• Standard Operational Amplifier Pinout
Applications
• High Resolution Monitors
• Professional Video Processing
• Medical Imaging
Part # Information
PART NUMBER
(BRAND)
• Video Digitizing Boards/Systems
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
• RF/IF Processors
• Battery Powered Communications
-40 to 85
8 Ld SOIC
M8.15
• Flash Converter Drivers
• High Speed Pulse Amplifiers
Pinout
HFA1212 (SOIC)
TOP VIEW
1
-IN1
2
+IN1
3
V-
4
+
+
-
1
OUT1
-
HFA1212IB
(H1212I)
8
V+
7
OUT2
6
-IN2
5
+IN2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1998, Copyright Intersil Americas Inc. 2002, 2004. All Rights Reserved
HFA1212
Absolute Maximum Rating
Thermal Information
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Output Current (Note 1) . . . . . . . . . . . . . . . . . Short Circuit Protected
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .600V
Thermal Resistance (Typical, Note 2)
Operating Conditions
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle)
output current should not exceed 30mA for maximum reliability.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified.
Electrical Specifications
(NOTE 3)
TEST
LEVEL
TEMP
(oC)
MIN
TYP
MAX
UNITS
A
25
-
2
10
mV
A
Full
-
3
15
mV
Average Output Offset Voltage Drift
B
Full
-
22
70
µV/oC
Channel-to-Channel Output Offset
Voltage Mismatch
A
25
-
-
15
mV
A
Full
-
-
30
mV
∆VCM = ±1.8V
A
25
42
45
-
dB
∆VCM = ±1.8V
A
85
40
44
-
dB
TEST
CONDITIONS
PARAMETER
INPUT CHARACTERISTICS
Output Offset Voltage
Common-Mode Rejection Ratio
∆VCM = ±1.2V
A
-40
40
45
-
dB
∆VPS = ±1.8V
A
25
45
49
-
dB
∆VPS = ±1.8V
A
85
43
48
-
dB
∆VPS = ±1.2V
A
-40
43
48
-
dB
A
25
-
1
15
µA
A
Full
-
3
25
µA
Input Bias Current Drift
B
Full
-
30
80
nA/oC
Channel-to-Channel Input Bias Current
Mismatch
A
25
-
-
15
µA
A
Full
-
-
25
µA
A
25
-
0.5
1
µA/V
A
Full
-
-
3
µA/V
∆VCM = ±1.8V
A
25
0.8
1.1
-
MΩ
∆VCM = ±1.8V
A
85
0.5
1.4
-
MΩ
∆VCM = ±1.2V
A
-40
0.5
1.3
-
MΩ
Inverting Input Resistance
C
25
-
350
-
Ω
Input Capacitance
C
25
-
2
-
pF
Input Voltage Common Mode Range
(Implied by VIO CMRR and +RIN tests)
A
25, 85
±1.8
±2.4
-
V
A
-40
±1.2
±1.7
-
V
Power Supply Rejection Ratio
Input Bias Current
Input Bias Current Power Supply Sensitivity
Input Resistance
∆VPS = ±1.25V
Input Noise Voltage Density (Note 4)
f = 100kHz
B
25
-
7
-
nV/√Hz
Input Noise Current Density (Note 4)
f = 100kHz
B
25
-
3.6
-
pA/√Hz
2
HFA1212
VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified. (Continued)
Electrical Specifications
(NOTE 3)
TEST
LEVEL
TEMP
(oC)
MIN
TYP
MAX
UNITS
A
25
-0.98
0.996
-1.02
V/V
A
Full
0.975
1.000
-1.025
V/V
AV = +1
A
25
0.98
0.992
1.02
V/V
A
Full
0.975
0.993
1.025
V/V
AV = +2
A
25
1.96
1.988
2.04
V/V
A
Full
1.95
1.990
2.05
V/V
A
25
-
-
±0.02
V/V
A
Full
-
-
±0.025
V/V
A
25
-
-
±0.025
V/V
A
Full
-
-
±0.025
V/V
A
25
-
-
±0.04
V/V
A
Full
-
-
±0.05
V/V
AV = -1
B
25
-
300
-
MHz
AV = +1, +RS = 620Ω
B
25
-
240
-
MHz
AV = +2
B
25
-
350
-
MHz
AV = -1
B
25
-
165
-
MHz
AV = +1, +RS = 620Ω
B
25
-
150
-
MHz
AV = +2
B
25
-
125
-
MHz
TEST
CONDITIONS
PARAMETER
TRANSFER CHARACTERISTICS
Gain (VIN = -1V to +1V)
AV = -1
Channel-to-Channel Gain Mismatch
AV = -1
AV = +1
AV = +2
AC CHARACTERISTICS
-3dB Bandwidth
(VOUT = 0.2VP-P, Note 4)
Full Power Bandwidth
(VOUT = 5VP-P at AV = +2 or -1,
VOUT = 4VP-P at AV = +1, Note 4)
AV = +2, To 25MHz
B
25
-
±0.03
-
dB
AV = +2, To 50MHz
B
25
-
±0.04
-
dB
5MHz
B
25
-
-65
-
dB
10MHz
B
25
-
-60
-
dB
Output Voltage Swing
(Note 4)
AV = -1
A
25
±3.0
±3.2
-
V
A
Full
±2.8
±3.0
-
V
Output Current
(Note 4)
AV = -1, RL = 50Ω
A
25, 85
50
55
-
mA
Gain Flatness
(VOUT = 0.2VP-P, Note 4)
Crosstalk
(All Channels Hostile, Note 4)
OUTPUT CHARACTERISTICS
Output Short Circuit Current
A
-40
28
42
-
mA
B
25
-
100
-
mA
DC Closed Loop Output Impedance
AV = +2
B
25
-
0.2
-
Ω
Second Harmonic Distortion
(AV = +2, VOUT = 2VP-P, Note 4)
10MHz
B
25
-
-60
-
dBc
20MHz
B
25
-
-50
-
dBc
Third Harmonic Distortion
(AV = +2, VOUT = 2VP-P, Note 4)
10MHz
B
25
-
-60
-
dBc
20MHz
B
25
-
-50
-
dBc
Reverse Isolation (S12, Note 4)
30MHz, AV = +2
B
25
-
-65
-
dB
Rise Time
B
25
-
1.0
-
ns
Fall Time
B
25
-
1.1
-
ns
TRANSIENT RESPONSE AV = +2, Unless Otherwise Specified
Rise and Fall Times
(VOUT = 0.5VP-P)
3
HFA1212
VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified. (Continued)
Electrical Specifications
TEST
CONDITIONS
PARAMETER
(NOTE 3)
TEST
LEVEL
TEMP
(oC)
MIN
TYP
MAX
UNITS
Overshoot
(VOUT = 0.5VP-P, VIN tRISE = 1ns, Note 5)
+OS
B
25
-
4
-
%
-OS
B
25
-
13
-
%
Slew Rate
(VOUT = 5VP-P at AV = +2 or -1,
VOUT = 4VP-P at AV = +1)
AV = -1
+SR
B
25
-
2000
-
V/µs
-SR
B
25
-
1150
-
V/µs
AV = +1,
+RS = 620Ω
+SR
B
25
-
1100
-
V/µs
-SR
B
25
-
850
-
V/µs
AV = +2
+SR
B
25
-
1300
-
V/µs
-SR
B
25
-
900
-
V/µs
To 0.1%
B
25
-
24
-
ns
To 0.05%
B
25
-
37
-
ns
To 0.02%
B
25
-
60
-
ns
VIN = ±2V
B
25
-
8.5
-
ns
Differential Gain (f = 3.58MHz, AV = +2)
RL = 150Ω
B
25
-
0.025
-
%
Differential Phase (f = 3.58MHz, AV = +2)
RL = 150Ω
B
25
-
0.03
-
Degrees
Power Supply Range
C
25
±4.5
-
±5.5
V
Power Supply Current
A
25
-
5.9
6.1
mA/Op Amp
A
Full
-
6.1
6.3
mA/Op Amp
Settling Time
(VOUT = +2V to 0V Step, Note 4)
Overdrive Recovery Time
VIDEO CHARACTERISTICS
POWER SUPPLY CHARACTERISTICS
NOTE:
3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
4. See Typical Performance Curves for more information.
5. Negative overshoot dominates for output signal swings below GND (e.g. 0.5VP-P), yielding a higher overshoot limit compared to the
VOUT = 0V to 0.5V condition. See the “Application Information” section for details.
Application Information
HFA1212 Advantages
The HFA1212 features a novel design which allows the user
to select from three closed loop gains, without any external
components. The result is a more flexible product, fewer part
types in inventory, and more efficient use of board space.
Implementing a dual, gain of 2, cable driver with this IC
eliminates the four gain setting resistors, which frees up
board space for termination resistors.
Like most newer high performance amplifiers, the HFA1212 is
a current feedback amplifier (CFA). CFAs offer high bandwidth
and slew rate at low supply currents, but can be difficult to use
because of their sensitivity to feedback capacitance and
parasitics on the inverting input (summing node). The HFA1212
eliminates these concerns by bringing the gain setting resistors
on-chip. This yields the optimum placement and value of the
feedback resistor, while minimizing feedback and summing
node parasitics. Because there is no access to the summing
node, the PCB parasitics do not impact performance at gains of
4
+2 or -1 (see “Unity Gain Considerations” for discussion of
parasitic impact on unity gain performance).
The HFA1212’s closed loop gain implementation provides
better gain accuracy, lower offset and output impedance,
and better distortion compared with open loop buffers.
Closed Loop Gain Selection
This “buffer” operates in closed loop gains of -1, +1, or +2, with
gain selection accomplished via connections to the ±inputs.
Applying the input signal to +IN and floating -IN selects a gain
of +1 (see next section for layout caveats), while grounding -IN
selects a gain of +2. A gain of -1 is obtained by applying the
input signal to -IN with +IN grounded through a 50Ω resistor.
The table below summarizes these connections:
CONNECTIONS
GAIN
(ACL)
+INPUT
-INPUT
-1
50Ω to GND
Input
+1
Input
NC (Floating)
+2
Input
GND
HFA1212
Unity Gain Considerations
PC Board Layout
Unity gain selection is accomplished by floating the -Input of
the HFA1212. Anything that tends to short the -Input to
GND, such as stray capacitance at high frequencies, will
cause the amplifier gain to increase toward a gain of +2. The
result is excessive high frequency peaking, and possible
instability. Even the minimal amount of capacitance
associated with attaching the -Input lead to the PCB results
in approximately 6dB of gain peaking. At a minimum this
requires due care to ensure the minimum capacitance at the
-Input connection.
This amplifier’s frequency response depends greatly on the
care taken in designing the PC board (PCB). The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must!
Table 1 lists five alternate methods for configuring the
HFA1212 as a unity gain buffer, and the corresponding
performance. The implementations vary in complexity and
involve performance trade-offs. The easiest approach to
implement is simply shorting the two input pins together, and
applying the input signal to this common node. The amplifier
bandwidth decreases from 430MHz to 280MHz, but
excellent gain flatness is the benefit. A drawback to this
approach is that the amplifier input noise voltage and input
offset voltage terms see a gain of +2, resulting in higher
noise and output offset voltages. Alternately, a 100pF
capacitor between the inputs shorts them only at high
frequencies, which prevents the increased output offset
voltage but delivers less gain flatness.
Another straightforward approach is to add a 620W resistor
in series with the amplifier’s positive input. This resistor and
the HFA1212 input capacitance form a low pass filter which
rolls off the signal bandwidth before gain peaking occurs.
This configuration was employed to obtain the data sheet
AC and transient parameters for a gain of +1.
Pulse Overshoot
The HFA1212 utilizes a quasi-complementary output stage
to achieve high output current while minimizing quiescent
supply current. In this approach, a composite device
replaces the traditional PNP pulldown transistor. The
composite device switches modes after crossing 0V,
resulting in added distortion for signals swinging below
ground, and an increased overshoot on the negative portion
of the output waveform (see Figure 6, Figure 9, and Figure
12). This overshoot isn’t present for small bipolar signals
(see Figure 4, Figure 7, and Figure 10) or large positive
signals (see Figure 5, Figure 8 and Figure 11).
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the RS and CL
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
RS and CL form a low pass network at the output, thus
limiting system bandwidth well below the amplifier bandwidth
of 350MHz. By decreasing RS as CL increases (as illustrated
in the curves), the maximum bandwidth is obtained without
sacrificing stability. In spite of this, bandwidth decreases as
the load capacitance increases.
TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS
IMPLEMENTATIONS
PEAKING
(dB)
BW
(MHz)
±0.1dB GAIN
FLATNESS (MHz)
4.5
430
21
0
220
27
+RS = 620Ω and
Remove -IN Pin
0.5
215
15
Short +IN to -IN (e.g.,
Pins 2 and 3)
0.6
280
70
100pF Capacitor
Between +IN and -IN
0.7
290
40
APPROACH
Remove -IN Pin
+RS = 620Ω
5
HFA1212
SERIES OUTPUT RESISTANCE (Ω)
50
40
50Ω
OUT
1
R1 (NOTE)
30
IN
20
3
50Ω
AV = +1
4
AV = +2
10
−5V
10µF
0
0
50
100
150
200
250
300
350
2
0.1µF
+5V
8
−
+
7
0.1µF
10µF
6
5
GND
GND
NOTE: R1 = ∞ (AV = +1)
or 0Ω (AV = +2)
400
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
CAPACITANCE
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
Evaluation Board
The performance of the HFA1212 may be evaluated using
the HA5023 Evaluation Board, slightly modified as follows:
1. Remove the two feedback resistors, and leave the connections open.
2. a. For AV = +1 evaluation, remove the gain setting
resistors (R1), and leave pins 2 and 6 floating.
b. For AV = +2, replace the gain setting resistors (R1) with
0Ω resistors to GND.
3. Replace the 0Ω series output resistors with 50Ω.
The modified schematic for amplifier 1, and the board layout
are shown in Figures 2 and 3.
NOTE: Note: The SOIC version may be evaluated in the DIP board
by using a SOIC-to-DIP adapter such as Aries Electronics Part
Number 08-350000-10.
To order evaluation boards (part number HA5023EVAL),
please contact your local sales office.
FIGURE 3A. TOP LAYOUT
6
FIGURE 3B. BOTTOM LAYOUT
FIGURE 3. EVALUATION BOARD LAYOUT
HFA1212
Typical Performance Curves
2.0
AV = +2
150
1.5
100
1.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
200
VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified
50
0
-50
-100
-150
AV = +2
0.5
0
-0.5
-1.0
-1.5
-200
-2.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 5. LARGE SIGNAL POSITIVE PULSE RESPONSE
FIGURE 4. SMALL SIGNAL PULSE RESPONSE
200
AV = +2
1.5
150
1.0
100
OUTPUT VOLTAGE (mV)
OUTPUT VOLTAGE (V)
2.0
0.5
0
-0.5
-1.0
AV = +1
50
0
-50
-100
-150
-1.5
-200
-2.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 6. LARGE SIGNAL BIPOLAR PULSE RESPONSE
2.0
AV = +1
1.5
1.5
1.0
1.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.0
FIGURE 7. SMALL SIGNAL PULSE RESPONSE
0.5
0
-0.5
-1.0
-1.5
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.0
TIME (5ns/DIV.)
FIGURE 8.
AV = +1
LARGE SIGNAL POSITIVE PULSE RESPONSE
7
TIME (5ns/DIV.)
FIGURE 9. LARGE SIGNAL BIPOLAR PULSE RESPONSE
HFA1212
Typical Performance Curves
(Continued) VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified
2.0
200
150
1.5
100
1.0
OUTPUT VOLTAGE (V)
50
0
-50
-100
0.5
0
-0.5
-1.0
-1.5
-150
-2.0
-200
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 10. SMALL SIGNAL PULSE RESPONSE
FIGURE 11.
2.0
NORMALIZED GAIN (dB)
AV = -1
1.5
1.0
OUTPUT VOLTAGE (V)
AV = −1
0.5
0
LARGE SIGNAL POSITIVE PULSE RESPONSE
6
3
AV = +2
GAIN
0
-3
AV = +1
-6
AV = -1
PHASE
-9
0
-90
-0.5
-1.0
VOUT = 200mVP-P
+RS = 620Ω (+1)
+RS = 0Ω (-1, +2)
-1.5
1
-2.0
-180
-270
-360
600
FIGURE 13. FREQUENCY RESPONSE
6
0.7
3
0.6
+RS = 620Ω (+1)
0
0.5
+RS = 0Ω (-1, +2)
VOUT = 200mVP-P
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
AV = +2
10
100
FREQUENCY (MHz)
TIME (5ns/DIV.)
FIGURE 12. LARGE SIGNAL BIPOLAR PULSE RESPONSE
AV = +1
NORMALIZED PHASE (DEGREES)
OUTPUT VOLTAGE (mV)
AV = -1
-3
-6
AV = -1
-9
AV = +2
AV = +1
VOUT = 4VP-P (+1)
VOUT = 5VP-P (-1, +2)
+RS = 620Ω (+1)
0.4
0.3
0.1
0
-0.1
AV = +1
-0.2
-0.3
1
AV = +2
0.2
10
FREQUENCY (MHz)
100
FIGURE 14. FULL POWER BANDWIDTH
8
300
1
10
FREQUENCY (MHz)
FIGURE 15. GAIN FLATNESS
AV = -1
100
HFA1212
Typical Performance Curves
(Continued) VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified
-10
-10
-20
-20
-30
-30
GAIN (dB)
CROSSTALK (dB)
AV = -1
-40
-50
AV = +1
-60
-70
-80
RL = ∞
-40
-50
RL = 100Ω
-60
-70
-80
-90
-90
AV = +2
-100
-110
0.3
1
-100
10
FREQUENCY (MHz)
-110
0.3
100
FIGURE 16. REVERSE ISOLATION
1
10
FREQUENCY (MHz)
100
500
FIGURE 17. ALL HOSTILE CROSSTALK
-40
-40
-45
-45
DISTORTION (dBc)
20MHz
DISTORTION (dBc)
AV = +2
-50
-55
10MHz
-60
-50
20MHz
-55
-60
10MHz
-65
-65
-70
-10
-5
0
5
10
-70
-10
15
OUTPUT POWER (dBm)
FIGURE 18. 2nd HARMONIC DISTORTION vs POUT
0
5
OUTPUT POWER (dBm)
10
15
FIGURE 19. 3rd HARMONIC DISTORTION vs POUT
20
20
16
16
12
12
NOISE VOLTAGE (nV/÷√Hz)
0.05
0
-0.05
-0.10
8
8
ENI
4
4
INI
13
33
53
FIGURE 20.
73
93
113
TIME (ns)
133
SETTLING RESPONSE
9
153
173
0
0.1
1
10
FREQUENCY (kHz)
0
100
FIGURE 21. INPUT NOISE CHARACTERISTICS
NOISE CURRENT (pA/÷√Hz)
AV = +1
0.10
SETTLING ERROR (%)
-5
HFA1212
Typical Performance Curves
(Continued) VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified
3.6
3.5
|-VOUT| (RL= 100Ω)
AV = -1
OUTPUT VOLTAGE (V)
+VOUT (RL= 100Ω)
3.4
3.3
3.2
|-VOUT| (RL= 50Ω)
3.1
+VOUT (RL= 50Ω)
3.0
2.9
2.8
2.7
2.6
-50
-25
0
25
50
75
100
TEMPERATURE (oC)
FIGURE 22. OUTPUT VOLTAGE vs TEMPERATURE
Die Characteristics
DIE DIMENSIONS:
69 mils x 92 mils x 19 mils
1750µm x 2330µm x 483µm
METALLIZATION:
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8kÅ ±0.4kÅ
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kÅ ±0.8kÅ
PASSIVATION:
Type: Nitride
Thickness: 4kÅ ±0.5kÅ
TRANSISTOR COUNT:
180
SUBSTRATE POTENTIAL (Powered Up):
Floating (Recommend Connection to V-)
10
125
HFA1212
Metallization Mask Layout
HFA1212
OUT1
-IN1
NC
V+
NC
OUT2
+IN1
NC
NC
-IN2
NC
V-
NC
11
+IN2
HFA1212
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
µα
e
A1
B
0.25(0.010) M
C
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
NOTES:
MAX
A1
e
0.10(0.004)
MIN
α
8
0o
8
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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