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1- 888-
Triple, 560MHz, Low Power, Video
Operational Amplifier
HFA1305
June 2004
FN4727.4
Features
• Low Supply Current . . . . . . . . . . . . . . . . . 5.8mA / Op Amp
The HFA1305 is a triple, high speed, low power current
feedback amplifier built with Intersil’s proprietary
complementary bipolar UHF-1 process.
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 1MΩ
• Wide -3dB Bandwidth (AV = +2). . . . . . . . . . . . . . 560MHz
These amplifiers deliver up to 560MHz bandwidth and
2500V/µs slew rate, on only 58mW of quiescent power. They
are specifically designed to meet the performance, power,
and cost requirements of high volume video applications.
The excellent gain flatness and differential gain/phase
performance make these amplifiers well suited for
component or composite video applications. Video
performance is maintained even when driving a double
terminated cable (RL = 150Ω), and degrades only slightly
when driving two double terminated cables (RL = 75Ω). RGB
applications will benefit from the high slew rates, and high
full power bandwidth.
• Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . . 2500V/µs
The HFA1305 is a pin compatible, low power, high
performance upgrade for the popular Intersil HA5013, and
for the AD8073 and CLC5623, in ±5V applications.
• Professional Video Processing
• Gain Flatness (to 50MHz). . . . . . . . . . . . . . . . . . . . . ±0.03dB
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02%
• Differential Phase . . . . . . . . . . . . . . . . . . . . . 0.03 Degrees
• All Hostile Crosstalk (5MHz) . . . . . . . . . . . . . . . . . . -60dB
• Pin Compatible Upgrade to HA5013, AD8073 and
CLC5623 in ±5V Supply Applications.
Applications
• Flash A/D Drivers
• Video Digitizing Boards / Systems
• Computer Video Plug-In Boards
Part # Information
PART NUMBER
• RGB Preamps
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
• Medical Imaging
• Hand Held and Miniaturized RF Equipment
HFA1305IB
-40 to 85
14 Ld SOIC
M14.15
• Battery Powered Communications
HA5025EVAL (Note)
High Speed Op Amp SOIC Evaluation
Board
• High Speed Oscilloscopes and Analyzers
NOTE: Requires a SOIC-to-DIP adapter. See “Evaluation Board”
section inside.
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Pinout
HFA1305 (SOIC)
TOP VIEW
14 OUT 3
NC 1
NC 2
13 -IN 3
+
-
NC 3
12 +IN 3
V+ 4
11 V-
OUT 1 7
1
+
-IN 1 6
+
+IN 1 5
-
-
10 +IN 2
9 -IN 2
8 OUT 2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HFA1305
Absolute Maximum Ratings TA = 25oC
Thermal Information
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Output Current (Note 2) . . . . . . . . . . . . . . . . .Short Circuit Protected
30mA Continuous
60mA ≤ 50% Duty Cycle
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . 600V
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
Moisture Sensitivity (see Technical Brief TB363)
All Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle) output
current must not exceed 30mA for maximum reliability.
Electrical Specifications
VSUPPLY = ±5V, AV = +1, RF = 510Ω , RL = 100Ω , Unless Otherwise Specified
PARAMETER
(NOTE 4)
TEST
LEVEL
TEMP.
(oC)
MIN
TYP
MAX
UNITS
A
25
-
2
5
mV
A
Full
-
3
8
mV
B
Full
-
1
10
µV/oC
∆VCM = ±1.8V
A
25
45
48
-
dB
∆VCM = ±1.8V
A
85
43
46
-
dB
∆VCM = ±1.2V
A
-40
43
46
-
dB
∆VPS = ±1.8V
A
25
48
52
-
dB
∆VPS = ±1.8V
A
85
46
48
-
dB
∆VPS = ±1.2V
A
-40
46
48
-
dB
A
25
-
6
15
µA
A
Full
-
10
25
µA
B
Full
-
5
60
nA/oC
∆VPS = ±1.8V
A
25
-
0.5
1
µA/V
∆VPS = ±1.8V
A
85
-
0.8
3
µA/V
∆VPS = ±1.2V
A
-40
-
0.8
3
µA/V
∆VCM = ±1.8V
A
25
0.8
1.2
-
MΩ
∆VCM = ±1.8V
A
85
0.5
0.8
-
MΩ
∆VCM = ±1.2V
A
-40
0.5
0.8
-
MΩ
A
25
-
2
7.5
µA
A
Full
-
5
15
µA
B
Full
-
60
200
nA/oC
∆VCM = ±1.8V
A
25
-
3
6
µA/V
∆VCM = ±1.8V
A
85
-
4
8
µA/V
∆VCM = ±1.2V
A
-40
-
4
8
µA/V
TEST CONDITIONS
INPUT CHARACTERISTICS
Input Offset Voltage
Average Input Offset Voltage Drift
Input Offset Voltage
Common-Mode Rejection Ratio
Input Offset Voltage
Power Supply Rejection Ratio
Non-Inverting Input Bias Current
Non-Inverting Input Bias Current Drift
Non-Inverting Input Bias Current
Power Supply Sensitivity
Non-Inverting Input Resistance
Inverting Input Bias Current
Inverting Input Bias Current Drift
Inverting Input Bias Current
Common-Mode Sensitivity
2
HFA1305
Electrical Specifications
VSUPPLY = ±5V, AV = +1, RF = 510Ω , RL = 100Ω , Unless Otherwise Specified (Continued)
(NOTE 4)
TEST
LEVEL
TEMP.
(oC)
MIN
TYP
MAX
UNITS
∆VPS = ±1.8V
A
25
-
2
5
µA/V
∆VPS = ±1.8V
A
85
-
4
8
µA/V
∆VPS = ±1.2V
A
-40
-
4
8
µA/V
Inverting Input Resistance
C
25
-
60
-
Ω
Input Capacitance
B
25
-
1.4
-
pF
Input Voltage Common Mode Range
(Implied by VIO CMRR, +RIN, and -IBIAS
CMS Tests)
A
25, 85
±1.8
±2.4
-
V
A
-40
±1.2
±1.7
-
V
PARAMETER
TEST CONDITIONS
Inverting Input Bias Current
Power Supply Sensitivity
Input Noise Voltage Density
f = 100kHz
B
25
-
3.5
-
nV/√Hz
Non-Inverting Input Noise Current Density
f = 100kHz
B
25
-
2.5
-
pA/√Hz
Inverting Input Noise Current Density
f = 100kHz
B
25
-
20
-
pA/√Hz
C
25
-
500
-
kΩ
AV = +1
B
25
-
375
-
MHz
AV = -1
B
25
-
420
-
MHz
AV = +2
B
25
-
560
-
MHz
AV = +1
B
25
-
160
-
MHz
AV = -1
B
25
-
260
-
MHz
AV = +2
B
25
-
165
-
MHz
AV = +1, To 25MHz
B
25
-
±0.03
-
dB
AV = +1, To 50MHz
B
25
-
±0.03
-
dB
AV = +1, To 100MHz
B
25
-
±0.07
-
dB
AV = -1, To 25MHz
B
25
-
±0.03
-
dB
AV = -1, To 50MHz
B
25
-
±0.04
-
dB
AV = -1, To 100MHz
B
25
-
±0.09
-
dB
AV = +2, To 25MHz
B
25
-
±0.03
-
dB
AV = +2, To 50MHz
B
25
-
±0.03
-
dB
AV = +2, To 100MHz
B
25
-
±0.07
-
dB
A
Full
-
1
-
V/V
5MHz
B
25
-
-60
-
dB
10MHz
B
25
-
-56
-
dB
A
25
±3
±3.4
-
V
A
Full
±2.8
±3
-
V
A
25, 85
50
60
-
mA
A
-40
28
42
-
mA
Output Short Circuit Current
B
25
-
90
-
mA
Closed Loop Output Impedance
B
25
-
0.2
-
Ω
TRANSFER CHARACTERISTICS
Open Loop Transimpedance Gain
AC CHARACTERISTICS (Note 3)
-3dB Bandwidth
(VOUT = 0.2VP-P, Notes 3, 5)
Full Power Bandwidth
(VOUT = 5VP-P, Notes 3, 5)
Gain Flatness
(VOUT = 0.2VP-P, Notes 3, 5)
Minimum Stable Gain
Crosstalk
(AV = +1, All Channels Hostile,
Note 5)
OUTPUT CHARACTERISTICS AV = +2 (Note 3), Unless Otherwise Specified
Output Voltage Swing
(Note 5)
AV = -1, RL = 100Ω
Output Current
(Note 5)
AV = -1, RL = 50Ω
3
HFA1305
Electrical Specifications
VSUPPLY = ±5V, AV = +1, RF = 510Ω , RL = 100Ω , Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
(NOTE 4)
TEST
LEVEL
TEMP.
(oC)
MIN
TYP
MAX
UNITS
Second Harmonic Distortion
(VOUT = 2VP-P, Note 5)
10MHz
B
25
-
-51
-
dBc
20MHz
B
25
-
-46
-
dBc
Third Harmonic Distortion
(VOUT = 2VP-P, Note 5)
10MHz
B
25
-
-63
-
dBc
20MHz
B
25
-
-56
-
dBc
TRANSIENT CHARACTERISTICS AV = +2 (Note 3), Unless Otherwise Specified
Rise and Fall Times
(VOUT = 0.5VP-P, Note 3)
Overshoot
(VOUT = 0.5VP-P, VIN tRISE = 1ns, Notes 3,
6)
Slew Rate
(VOUT = 5VP-P at AV = +2, -1,
VOUT = 4VP-P, at AV = +1,
Notes 3, 5)
Settling Time
(VOUT = +2V to 0V Step, Note 5)
Overdrive Recovery Time
VIDEO CHARACTERISTICS
AV = +1
B
25
-
1.0
-
ns
AV = -1
B
25
-
-
-
ns
AV = +2
B
25
-
0.8
-
ns
AV = +1, +OS
B
25
-
5
-
%
AV = +1, -OS
B
25
-
11
-
%
AV = -1, +OS
B
25
-
7
-
%
AV = -1, -OS
B
25
-
8
-
%
AV = +2, +OS
B
25
-
5
-
%
AV = +2, -OS
B
25
-
10
-
%
AV = +1, +SR
B
25
-
1230
-
V/µs
AV = +1, -SR
B
25
-
1350
-
V/µs
AV = -1, +SR
B
25
-
2500
-
V/µs
AV = -1, -SR
B
25
-
1900
-
V/µs
AV = +2, +SR
B
25
-
1700
-
V/µs
AV = +2, -SR
B
25
-
1700
-
V/µs
To 0.1%
B
25
-
23
-
ns
To 0.05%
B
25
-
30
-
ns
To 0.025%
B
25
-
37
-
ns
VIN = ±2V
B
25
-
8.5
-
ns
AV = +2 (Note 3), Unless Otherwise Specified
Differential Gain
(f = 3.58MHz)
RL = 150Ω
B
25
-
0.02
-
%
RL = 75Ω
B
25
-
0.03
-
%
Differential Phase
(f = 3.58MHz)
RL = 150Ω
B
25
-
0.03
-
Degrees
RL = 75Ω
B
25
-
0.06
-
Degrees
Power Supply Range
C
25
±4.5
-
±5.5
V
Power Supply Current (Note 5)
A
25
-
5.8
6.1
mA/Op Amp
A
Full
-
5.9
6.3
mA/Op Amp
POWER SUPPLY CHARACTERISTICS
NOTES:
3. The optimum feedback resistor depends on closed loop gain. See the “Optimum Feedback Resistor” table in the Application Information section
for details.
4. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
5. See Typical Performance Curves for more information.
6. Undershoot dominates for output signal swings below GND (e.g., 2VP-P), yielding a higher overshoot limit compared to the VOUT = 0V to 2V
condition. See the “Application Information” section for details.
4
HFA1305
Application Information
Performance
The amplifiers comprising the HFA1305 are high frequency
current feedback amplifiers. As such, they are sensitive to
feedback capacitance which destabilizes the op amp and
causes overshoot and peaking. Unfortunately, the standard
triple op amp pinout places the amplifier’s output next to its
inverting input, thus making the package capacitance an
unavoidable parasitic feedback capacitor.
Optimum Feedback Resistor
Although a current feedback amplifier’s bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
amplifier’s unique relationship between bandwidth and RF.
All current feedback amplifiers require a feedback resistor,
even for unity gain applications, and RF, in conjunction with
the internal compensation capacitor, sets the dominant
pole of the frequency response. Thus, the amplifier’s
bandwidth is inversely proportional to RF. The HFA1305
design is optimized for RF = 510Ω (SOIC) at a gain of +2.
Decreasing RF decreases stability, resulting in excessive
peaking and overshoot (Note: Capacitive feedback causes
the same problems due to the feedback impedance
decrease at higher frequencies). However, at higher gains
the amplifier is more stable so RF can be decreased in a
trade-off of stability for bandwidth.
The table below lists recommended RF values for various
gains, and the expected bandwidth. For good channel-tochannel gain matching, it is recommended that all resistors
(termination as well as gain setting) be ±1% tolerance or better.
OPTIMUM FEEDBACK RESISTOR
GAIN
(ACL)
RF (Ω)
SOIC
BANDWIDTH (MHz)
SOIC
-1
360
420
+1
464 (+RS = 649)
375
+2
510
560
+5
200
330
+10
180
140
Non-inverting Input Source Impedance
For best operation, the DC source impedance seen by the
non-inverting input should be ≥ 50Ω. This is especially
important in inverting gain configurations where the noninverting input would normally be connected directly to GND.
Pulse Undershoot
The HFA1305 utilizes a quasi-complementary output stage to
achieve high output current while minimizing quiescent supply
current. In this approach, a composite device replaces the
traditional PNP pulldown transistor. The composite device
switches modes after crossing 0V, resulting in added distortion
5
for signals swinging below ground, and an increased
undershoot on the negative portion of the output waveform (see
Figure 6). This undershoot isn’t present for small bipolar
signals, or large positive signals (see Figure 4 and Figure 5).
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance, parasitic or
planned, connected to the output must be minimized, or
isolated as discussed in the next section.
Care must also be taken to minimize the capacitance to
ground at the amplifier’s inverting input (-IN). The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and eventual instability. To reduce this
capacitance the designer should remove the ground plane
under traces connected to -IN, and keep connections to -IN
as short as possible.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the RS and CL
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
RS and CL form a low pass network at the output, thus limiting
system bandwidth well below the amplifier bandwidth of
560MHz. By decreasing RS as CL increases (as illustrated in
the curve), the maximum bandwidth is obtained without
sacrificing stability. In spite of this, bandwidth still decreases
as the load capacitance increases.
HFA1305
TOP LAYOUT
SERIES OUTPUT RESISTANCE (Ω)
50
40
30
20
AV = +2
10
0
0
50
100
150
200
250
300
350
400
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
BOTTOM LAYOUT
Evaluation Board
The performance of the HFA1305IB (SOIC) may be
evaluated using the HA5025 Evaluation Board and a SOIC
to DIP adaptor like the Aries Electronics Part Number
14-350000-10.
The schematic for the SOIC amplifier 1 and the
HA5025EVAL board layout are shown in Figure 2 and
Figure 3. Resistors RF, RG , and +RS may require a change
to values applicable to the HFA1305IB.
To order evaluation board (part number HA5025EVAL),
please contact your local sales office.
FIGURE 3. EVALUATION BOARD LAYOUT FOR SOIC
10µF
0.1µF
1
14
2
13
3
12
4
11
+5V
-5V
50Ω
+RS
5
IN
RG
OUT
50Ω
RF
6
10
+
-
0.1µF
10µF
9
GND
8
7
GND
FIGURE 2. EVALUATION BOARD SCHEMATIC FOR SOIC
6
HFA1305
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified
160
1.6
AV = +2
AV = +2
1.2
80
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
120
40
0
-40
-80
0.8
0.4
0
-0.4
-0.8
-120
-1.2
-160
-1.6
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 4. SMALL SIGNAL PULSE RESPONSE
FIGURE 5. LARGE SIGNAL POSITIVE PULSE RESPONSE
160
1.6
AV = -1
AV = +2
120
OUTPUT VOLTAGE (mV)
OUTPUT VOLTAGE (V)
1.2
0.8
0.4
0
-0.4
-0.8
80
40
0
-40
-80
-120
-1.2
-160
-1.6
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 6. LARGE SIGNAL BIPOLAR PULSE RESPONSE
FIGURE 7. SMALL SIGNAL PULSE RESPONSE
1.6
1.6
AV = -1
AV = -1
1.2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.2
0.8
0.4
0
-0.4
0.8
0.4
0
-0.4
-0.8
-0.8
-1.2
-1.2
-1.6
-1.6
TIME (5ns/DIV.)
FIGURE 8. LARGE SIGNAL POSITIVE PULSE RESPONSE
7
TIME (5ns/DIV.)
FIGURE 9. LARGE SIGNAL BIPOLAR PULSE RESPONSE
HFA1305
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
160
1.6
AV = +1
AV = +1
1.2
80
OUTPUT VOLTAGE (V)
40
0
-40
-80
0.4
0
-0.4
-0.8
-120
-1.2
-160
-1.6
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 11. LARGE SIGNAL BIPOLAR PULSE RESPONSE
VOUT = 200mVP-P
6
AV = +2
3
NORMALIZED PHASE (DEGREES)
GAIN
0
AV = -1
-3
AV = +1
PHASE
0
90
AV = +1
180
AV = -1
AV = +2
270
360
0.3
1
10
100
NORMALIZED GAIN (dB)
FIGURE 10. SMALL SIGNAL PULSE RESPONSE
NORMALIZED GAIN (dB)
0.8
2
AV = +2
VOUT = 200mVP-P
1
0
GAIN
-1
RF = 1kΩ
RF = 1.5kΩ
-2
-3
0
RF = 1.5kΩ
PHASE
90
180
270
RF = 500Ω
800
1
10
FREQUENCY (MHz)
100
360
800
FREQUENCY (MHz)
FIGURE 12. FREQUENCY RESPONSE
FIGURE 13. FREQUENCY RESPONSE vs FEEDBACK RESISTOR
0.2
0.3
VOUT = 200mVP-P
0.2
AV = +2
VOUT = 200mVP-P
0.1
AV = -1
RF = 500Ω
0
0
-0.1
AV = +1
AVV == +2
+2
A
-0.2
-0.3
-0.4
NORMALIZED GAIN (dB)
0.1
NORMALIZED GAIN (dB)
RF = 500Ω
RF = 683Ω
RF = 750Ω
PHASE (DEGREES)
OUTPUT VOLTAGE (mV)
120
-0.1
-0.2
-0.3
-0.6
-0.7
10
FREQUENCY (MHz)
FIGURE 14. GAIN FLATNESS
8
100
RF = 1kΩ
-0.5
-0.6
1
RF = 750Ω
-0.4
-0.5
-0.7
RF = 683Ω
-0.8
RF = 1.5kΩ
1
10
100
FREQUENCY (MHz)
FIGURE 15. GAIN FLATNESS vs FEEDBACK RESISTOR
HFA1305
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
-10
-20
0.2
-30
0.15
CROSSTALK (dB)
SETTLING ERROR (%)
RL = 100Ω
-40
-50
-60
RL = ∞
-70
-80
0.1
0.05
0.025
0
-0.025
-0.05
-0.1
-90
-0.15
-100
-0.2
-110
0.3
AV = +2
VOUT = 2V
1
10
FREQUENCY (MHz)
100
0
200
FIGURE 16. ALL HOSTILE CROSSTALK
|-VOUT| (RL= 100Ω)
|-VOUT| (RL= 50Ω)
3.2
3.1
+VOUT (RL= 50Ω)
3.0
2.9
2.8
2.7
2.6
-50
-25
20
25
30
TIME (ns)
35
40
45
50
6.5
+VOUT (RL= 100Ω)
SUPPLY CURRENT (mA/AMPLIFIER)
OUTPUT VOLTAGE (V)
3.3
15
6.6
AV = -1
3.4
10
FIGURE 17. SETTLING RESPONSE
3.6
3.5
5
0
25
50
75
100
TEMPERATURE (oC)
FIGURE 18. OUTPUT VOLTAGE vs TEMPERATURE
9
125
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
5.5
4.5
5
5.5
6
6.5
SUPPLY VOLTAGE (±V)
FIGURE 19. SUPPLY CURRENT vs SUPPLY VOLTAGE
7
HFA1305
Die Characteristics
DIE DIMENSIONS
SUBSTRATE POTENTIAL (POWERED UP)
79 mils x 118 mils
2000µm x 3000µm
Floating (Recommend Connection to V-)
PASSIVATION
METALLIZATION
Type: Nitride
Thickness: 4kÅ ±0.5kÅ
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8kÅ ±0.4kÅ
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kÅ ±0.8kÅ
TRANSISTOR COUNT
240
Metallization Mask Layout
HFA1305
NC
NC
OUT3
-IN3
NC
+IN3
V+
V-
+IN1
+IN2
-IN1
10
OUT1
V-
OUT2
-IN2
HFA1305
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
µα
e
A1
B
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3367
0.3444
8.55
8.75
3
E
0.1497
0.1574
3.80
4.00
4
e
C
0.10(0.004)
B S
0.050 BSC
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
NOTES:
MILLIMETERS
α
14
0o
14
8o
0o
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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11
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