ICs for TV
AN5392FBQ
Luminance and color difference drive/cutoff signal processor IC
with I2C bus
Unit: mm
16.2±0.3
■ Overview
32
14.0±0.2
16.2±0.3
49
64
16
+0.10
0.35–0.05
Seating plane
+0.10
0.8
0.15–0.05
(1.0)
0.9±0.1
1
1.95±0.2
• A wider band signal processing (Y: 30 MHz/−3 dB,
color difference: 15 MHz/−3 dB)
• High picture quality thanks to a large variety of built-in
correction circuit for Y signal
• Y, C−Y signal conversion circuit built in for RGB signal
for a personal computer
• Possible to mount in a high density thanks to SMD package
17
0.9±0.1
■ Features
(1.0)
33
0.1±0.1
The AN5392FBQ is an RGB processor IC which
converts the luminance and color difference signal into a
primary color signal. This IC supports all kinds of input
signal from hi-vision, wide, NTSC, PAL, VGA, etc. for
maximum rationalization and high performance of the
end products.
14.0±0.2
48
0.55±0.2
QFS064-P-1414
■ Applications
• Hi-vision TV, wide TV, projection TV, plasma display
panel (PDP)
1
AN5392FBQ
ICs for TV
VM out 49
ABL/ACL in 50
Spot killer in
R, G, B limiter in
33
34
48
M
DC regenaration rate
47 Analog V
CC
46
Blooming level in
45
Black peak det.
44
White peak det.
43
APL det.
42
R-CLP
41
G-CLP
40
B-CLP
39
OSD-R in
38
OSD-G in
37
OSD-B in
36 Y in
S
35 Y in
■ Block Diagram
32 G-V
CC
31 G-out
ABL/ACL
block
R−Y (S) in 51
Y (S) in 52
R
Y
B−Y (S) in 53
54
Y, U, V V
Video
block
Y
Matrix
block
G
B
30 G-GND
29 B-V
R
SW
block
G
B
Output
block
CC
M/S in 55
CLP (M1) in 56
R−Y (M1) in 57
Y (M1) in 58
B−Y (M1) in 59
CLP (M2) in 60
R−Y (M2) in 61
Y (M2) in 62
R−Y
R−Y
Chrominance
block
B−Y
G−Y
26 R-V
CC
25 R-out
24 R-GND
23 Analog GND
B−Y
R, G, B → Y, U, V
block
22 Pulse V
CC
21 DI in
I2C DAC
block
BLK
block
1
I2L GND
2
R,G,B GND
3
B−Y out
4
Y-out
5
R−Y out
6
CLP (R, G, B) in
7
R-in
8
G-in
9
B-in
10
R, G, B VCC
11
VP in
12
Slave address SW
13
SDA
14
SCL
15
I2L VCC
16
Pulse GND
B−Y (M2) in 63
Y, U, V GND 64
Input
block
2
CC
28 B-out
27 B-GND
20 CRT mute
19 Neck mute
18 R,G,B mute
17 BLK in
ICs for TV
AN5392FBQ
■ Pin Descriptions
Pin No.
Description
Pin No.
Description
1
I2L
GND
33
Spot killer input
2
R, G, B GND
34
R, G, B limiter input
3
B−Y output
35
YM input
4
Y-output
36
YS input
5
R−Y output
37
OSD-B input
6
CLP (R, G, B) input
38
OSD-G input
7
R-input
39
OSD-R input
8
G-input
40
B-CLP filter
9
B-input
41
G-CLP filter
10
R, G, B VCC
42
R-CLP filter
11
VP input
43
APL detection filter
12
Slave address SW
44
White peak detection filter
13
SDA
45
Black peak detection filter
14
SCL
46
Blooming level input
15
I2L
VCC
47
Analog VCC
16
Pulse GND
48
DC regenaration rate
17
BLK input
49
VM output
18
R, G, B mute input
50
ABL/ACL input
19
Neck mute input
51
R−Y (S) input (Pr (S) input)
20
CRT mute input
52
Y (S) input
21
DI input
53
B−Y (S) input (Pb (S) input)
22
Pulse VCC
54
Y, U, V VCC
23
Analog GND
55
M/S input
24
R-GND
56
CLP (M1) input
25
R-output
57
R−Y (M1) input (Pr (M1) input)
26
R-VCC
58
Y (M1) input
27
B-GND
59
B−Y (M1) input (Pb (M1) input)
28
B-output
60
CLP (M2) input
29
B-VCC
61
R−Y (M2) input (Pr (M2) input)
30
G-GND
62
Y (M2) input
31
G-output
63
B−Y (M2) input (Pb (M2) input)
32
G-VCC
64
Y, U, V GND
3
AN5392FBQ
ICs for TV
■ Absolute Maximum Ratings
Parameter
Symbol
Supply voltage
VCC
Supply current
Power dissipation
ICC
*2
Operating ambient temperature
Storage temperature
*1
*1
Rating
Unit
VCC1
10.0
V
VCC2
5.6
ICC1
70.0
ICC2
34.0
mA
PD
685
mW
Topr
−20 to + 70
°C
Tstg
−55 to + 150
°C
Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C.
*2: The power dissipation PD shown is for the independent IC without a heat sink in the free air at Ta = 70°C.
■ Recommended Operating Range
Parameter
Supply voltage
Symbol
Range
Unit
VCC1
8.1 to 9.9
V
VCC2
4.5 to 5.5
■ Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25°C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DC characteristics
Circuit current 1 *1
ICC1
VCC1 = 9 V, VCC2 = 5 V
No signal input
39
51
63
mA
Circuit current 2 *1
ICC2
VCC1 = 9 V, VCC2 = 5 V
No signal input
20
25
30
mA
Video voltage gain
AYG
Input: Sine wave 0.2 V[p-p]
f = 1 MHz, contrast: max.
4.7
5.6
6.7
Times
Video voltage gain
variation amount
∆AY
Ratio between R,G and B
Drive: typ.
−2.5
0
+2.5
dB
Input: Sine wave 0.2 V[p-p]
f = 30 MHz, contrast: max.
−6
−3
+1
dB
Y-system
Frequency characteristics
fY
Typical output pedestal
DCP
Brightness: typ.
2.6
3.0
3.4
V
Brightness variable range
VBR
Brightness: min. → max.
1.8
2.2
2.6
V
Contrast ratio
ACON
Contrast: min. → max.
25
30
dB
APL detection voltage
VAPL
Input: Total white 0.7 V[0-p]
APL detection pin 43 voltage
0.7
1.0
1.3
V
APL detection ratio
∆APL
Input: Total white 0.7 V[0-p] → 0.35 V[0-p] 0.46
APL detection pin 43 voltage ratio
0.54
0.66
Times
Note) *1: ICC1 is a total amount of the current flowing through pin 10, pin 26, pin 29, pin 32, pin 47 and pin 54.
ICC2 is a total amount of the current flowing through pin 15 and pin 33.
4
ICs for TV
AN5392FBQ
■ Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Y-system (continued)
DC regeneration ratio 1
DC1
Input signal: APL 10% → 90%,
APL det. pin 0 V
96
102
107
%
DC regeneration ratio 2
DC2
Input signal: APL 10% → 90%,
DC regeneration SW/on, polarity: −
65
75
85
%
DC regeneration ratio 3
DC3
Input signal: APL 10% → 90%,
DC regeneration SW: On, polarity: +
115
125
135
%
Output blooming level
VBL
Blooming DC = 3.8 V,
pin 43: 0 V, brightness: max.
5.7
6.7
7.7
V
Output blooming level
variation amount
∆VBL
Blooming DC = 3.8 V → 4.2 V,
pin 43: 0 V, brightness: max.
White gradation correction 1 *2
Yγ1
Gain: max., level: typ. → max.
White gradation SW: On
9.0
14
18.0
%
White gradation correction 2 *2
Yγ2
Gain: max., level: typ. → min.
White gradation SW: On
−24
−18
−12
%
Black extension
characteristics 1 *3
YBL1
Output amplitude: 0 V[p-p]
Level: typ., gain: min. → max.
− 0.1
0
+0.1
V
Black extension
characteristics 2 *3
YBL2
Output amplitude: 1.0 V[0-p]
Level: typ., gain: min. → max.
− 0.49 − 0.37 − 0.25
V
Black extension
characteristics 3 *3
YBL3
Output amplitude: 2.2 V[0-p]
Level: typ., gain: min. → max.
− 0.1
V
Black extension
characteristics 4 *4
YBL4
Black detection: Open → 3 V
Level: typ., gain: typ.
−1.10 − 0.82 − 0.55
V
Black extension
characteristics 5 *4
YBL5
Black detection: Open → 3 V
Level: typ., gain: max.
−2.00 −1.55 −1.00
V
Black extension
characteristics 6 *4
YBL6
Black detection: Open → 3 V
Level: min. → max., gain: typ.
− 0.48 − 0.30 − 0.12
V
White character correction 1 *2
VW1
Blooming DC adjustment
Level: max., gain: min. → typ.
10.0
25.0
40.0
%
White character correction 2 *2
VW2
Blooming DC adjustment
Level: min., gain: min. → max.
−9.3
0
9.3
%
White character correction off *2 WOFF
PR, PB input: +0.2 V[p-p]
Level: max., gain: min. → max.
− 0.2
0
+0.2
V
ABL off *5
VABL1
ABL/ACL pin: 7.5 V
Level: min., gain: min. → max.
− 0.1
0
+0.1
V
ABL start 1*5
VABL2
ABL/ACL pin: 3 V
Level: min. → max., gain: max.
0.28
0.39
0.50
V
−1.18 − 0.93 − 0.68
0
+0.1
V
Note) *2: Control a blooming DC voltage (pin 46)
*3: Black gradation SW: On
*4: Black gradation SW: On, brightness: max.
*5: ABL SW: On, brightness: max.
5
AN5392FBQ
ICs for TV
■ Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Y-system (continued)
ABL start 2*5
VABL3
ABL/ACL pin: 3 V
Level: min., gain: min. → max.
− 0.84 − 0.64 − 0.44
V
ABL gain 1*5
AABL
ABL/ACL pin: 5 V → 3 V
Level: typ., gain: max.
− 0.48 − 0.37 − 0.26
V
ACL off *6
AACL1
ABL/ACL pin: 7.5 V
Level: min., gain: min. → max.
−5
0
+5
%
ACL start 1 *6
AACL2
ABL/ACL pin: 3 V
Level: min. → max., gain: typ.
10
20
30
%
ACL start 2 *6
AACL3
ABL/ACL pin: 3 V
Level: min., gain: min. → typ.
−45
−35
−25
%
ACL gain 1 *6
AACL4
ABL/ACL pin: 5 V → 3 V
Level: typ., gain: typ.
−34
−22
−10
%
Color difference-system
Color difference voltage gain *7
GR
Input: Sine wave 0.2 V[p-p]
f = 1 MHz, R−Y in → R-out
9.5
11.4
13.7
Times
Color difference frequency
characteristics *7
fc
Input: Sine wave 0.2 V[p-p]
f = 10 MHz
−6
−3
+2
dB
B−Y axis gain adjusting range
NTSC 1 *7
GB-Y1
B−Y gain: min., brightness: max.
Tint SW: NTSC
0.28
0.45
0.61
Times
B−Y axis gain adjusting range
NTSC 2 *7
GB-Y2
B−Y gain: max., brightness: max.
Tint SW: NTSC
1.00
1.25
1.60
Times
B−Y axis gain adjusting range
HD 1 *7
GB-Y3
B−Y gain: min., brightness: max.
Tint SW: HD
0.50
0.78
1.18
Times
B−Y axis gain adjusting range
HD 2 *7
GB-Y4
B−Y gain: max., brightness: max.
Tint SW: HD
1.18
2.00
2.80
Times
TC
Tint: min. → max.
B−Y gain, drive RB: Adjustment
± 33
± 48
± 68
°
3
6
9
dB
− 50
0
+50 mV[p-p]
10
17
24
Tint variable range
Color control *7
CCON
Color: typ. → max.
Contrast: typ.
Color residue *7
CMIN
Color: min., B−Y gain: max.
Contrast: max.
R−Y angle adjusting range *7
Note) *5: ABL SW: On, brightness: max.
*6: ACL SW: On
*7: Adjust tint, drive R, B.
6
θR
R−Y axis: min. → max.
°
ICs for TV
AN5392FBQ
■ Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Color difference-system (continued)
Matrix ratio
(G−Y/R−Y) HD *7
M1
Tint SW: HD
G−Y matrix: HD
0.23
0.30
0.35
Times
Matrix ratio
(G−Y/R−Y) NTSC 1 *7
M2
Tint SW: NTSC
G−Y matrix: NTSC 1
0.38
0.51
0.58
Times
Matrix ratio
(G−Y/R−Y) NTSC 2 *7
M3
Tint SW: NTSC
G−Y matrix: NTSC 2
0.26
0.34
0.40
Times
Matrix ratio
(G−Y/R−Y) NTSC 3 *7
M4
Tint SW: NTSC
G−Y matrix: NTSC 3
0.26
0.34
0.40
Times
Matrix ratio
(G−Y/B−Y) HD *7
M5
Tint SW: HD
G−Y matrix: HD
0.07
0.10
0.13
Times
Matrix ratio
(G−Y/B−Y) NTSC 1 *7
M6
Tint SW: NTSC
G−Y matrix: NTSC 1
0.15
0.19
0.23
Times
Matrix ratio
(G−Y/B−Y) NTSC 2 *7
M7
Tint SW: NTSC
G−Y matrix: NTSC 2
0.22
0.28
0.34
Times
Matrix ratio
(G−Y/B−Y) NTSC 3 *7
M8
Tint SW: NTSC
G−Y matrix: NTSC 3
0.13
0.17
0.21
Times
Pin 36 > 2.1 V: OSD
Pin 36 < 0.9 V: Main & sub
0.9
1.5
2.1
V
OSD
YS input threshold voltage *8
YSTH
M/S input threshold voltage *8
M/STH
Pin 55 > 2.1 V: Sub
Pin 55 < 0.9 V: Main (M1, M2)
0.9
1.5
2.1
V
YM input threshold voltage *8
YMTH
Pin 35 > 2.1 V: Half tone
Pin 35 < 0.9 V: Main & sub
0.9
1.5
2.1
V
CLP input threshold voltage
CLPTH
Pin 56, 60 (main, sub, OSD)
Pin 6 (RGB)
0.9
15
2.1
V
Pulse width can be clamped
WM
Pin 56, 60 (main, sub, OSD)
Pin 6 (RGB)
0.8
µs
OSD gain
GOSD
Input: Sine wave 0.2 V[p-p]
f = 1 MHz, YS pin: 5 V
5.0
6.0
7.2
Times
OSD frequency characteristics
fOSD
Input: Sine wave 0.2 V[p-p]
f = 30 MHz, YS pin: 5 V
−7
−3
+1
dB
OSD contrast ratio 1
OSDC1
Contrast: max. → typ.
YS pin: 5 V
−3
−1
+1
dB
OSD contrast ratio 2
OSDC2
Contrast: typ. → min.
YS pin: 5 V
−16
−11
−7
dB
Note) *7: Adjust tint, drive R, B
*8: SW priority: YS > M/S > M1/M2 (I2C), YS: YM is valid at low.
7
AN5392FBQ
ICs for TV
■ Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25°C (continued)
Parameter
Symbol
Y, U, V frequency characteristics
fYUV
Conditions
Min
Typ
Max
Unit
−6
−2
+2
dB
Y, U, V
Input: Sine wave 0.2 V[p-p], f = 30 MHz
Y, U, V output pedestal
DCYUV
2.6
3.0
3.4
V
Y, U, V output pedestal
potential difference
∆VYUV
− 0.3
0
+0.3
V
Y, U, V matrix ratio 1
MYUV1
R-in: Sine wave 0.2 V[p-p],
f = 1 MHz → Y-out
0.24
0.3
0.36
Times
Y, U, V matrix ratio 2
MYUV2
G-in: Sine wave 0.2 V[p-p],
f = 1 MHz → Y-out
0.47
0.59
0.71
Times
Y, U, V matrix ratio 3
MYUV3
B-in: Sine wave 0.2 V[p-p],
f = 1 MHz → Y-out
0.08
0.11
0.14
Times
BLKTH
BLK SW: On
0.9
1.5
2.1
V
Cutoff drive
BLK input threshold voltage*9
Neck mute
input threshold voltage *9
NTH
0.9
1.5
2.1
V
CRT mute
input threshold voltage *9
CTH
0.9
1.5
2.1
V
RGB mute
input threshold voltage *9
MTH
0.9
1.5
2.1
V
DI input threshold voltage
DTH
Pin 21 > 2.1 V: Detection inhibited
Pin 21 < 0.9 V: Normal
0.9
1.5
2.1
V
Cutoff variable range (R, B)*10
∆LRB
Cutoff R, B: min. → max.
Cutoff SW: min. → max.
1.6
2.0
2.4
V
Cutoff variable range (G)
∆LG
Cutoff G: min. → max.
0.7
1.0
1.3
V
Drive variable range (R, B)
∆GD
Drive R, B: min. → max.
9.0
11.5
14.0
dB
R, G, B pedestal potential difference
∆VP
Cutoff: typ., brightness: typ.
− 0.3
0
+0.3
V
Output blanking level
BLK
BLK SW: On, BLK (pin 17): 5 V
1.1
1.5
1.9
V
SCL · SDA
input threshold voltage
VTH
VCC2 = 5 V
1.5
3.0
V
Sink ability at ACK
VACK
I = 3 mA, when pull-up is 1.6 kΩ
0.4
V
VCC2 = 5 V
100
kHz
0.7
2.2
4.0
V
0.9
1.5
2.1
V
I2C
· DAC
Maximum clock frequency
Slave address changeover
threshold voltage
ADTH
VCC2 = 5 V
VP input threshold voltage
VPTH
VCC2 = 5 V
Note) *9: Priority: RGB mute, CRT mute, neck mute > single color adjustment
*10: Drive R, B adjustment
8
(I2C)
> BLK SW
(I2C)
> BLK pulse
ICs for TV
AN5392FBQ
■ Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25°C (continued)
• Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Y system
Y (M1)
input dynamic range
DYIN1
VCC1 = 9 V, V46 = 1.5 V
Contrast: typ.
1.4
V[p-p]
Y (M2)
input dynamic range
DYIN2
VCC1 = 9 V, V46 = 1.5 V
Contrast: typ.
1.4
V[p-p]
Y (sub)
input dynamic range
DYIN3
VCC1 = 9 V, V46 = 1.5 V
Contrast: typ.
1.4
V[p-p]
R, G, B
output dynamic range
DOUT
VCC1 = 9 V
for pedestal 3 V
4.5
V[p-p]
APL detection stop
APLS
BLK, DI = 5 V
0
V
Black extension inhibition delay tHBLACK
BLK, delay from DI input
60
ns
DC regeneration ratio 4
DC4
Input signal: APL10% → 90%
DC regeneration pin: Open
100
%
S/N
S/N
Band width 20 MHz
−56
dB
−20°C to +70°C
±2
%
f = 5 MHz
15
ns
Input: Sine wave 0.2 V[p-p], f = 1 MHz
1.0
Times
3.9
V
At high speed switching within
1H period
±50
mV
Y output amplitude dependence
on ambient temperature
Y signal delay time
VM out gain
Y/∆T
tdY
AVM
VM out pedestal level
DCVM
Pedestal level fluctuation
at M/S changeover
∆VPM/S
Color difference system
Pr, Pb input (M1)
dynamic range
DCIN1
Tint SW: HD mode
±0.7
V[p-p]
Pr, Pb input (M2)
dynamic range
DCIN2
Tint SW: HD mode
±0.7
V[p-p]
Pr, Pb input (sub)
dynamic range
DCIN3
Tint SW: HD mode
±0.7
V[p-p]
B−Y input (M1)
dynamic range
DPB1N
Tint SW: NTSC mode
±1.3
V[p-p]
B−Y input (M2)
dynamic range
DPB2N
Tint SW: NTSC mode
±1.3
V[p-p]
B−Y input (sub)
dynamic range
DPB3N
Tint SW: NTSC mode
±1.3
V[p-p]
R−Y axis: min.
0
°
Contrast: min. → max.
29
dB
R−Y angle adjusting range 2
θR2
Color difference contrast ratio
CCONT
9
AN5392FBQ
ICs for TV
■ Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25°C (continued)
• Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Color difference system (continued)
Tint dependence on
ambient temperature
TC/T
−20°C to +70°C
±2
°
(C−Y)/Y ratio HD
C/YHD
Tint SW: HD mode
Contrast: max., color: typ.
1.3
Times
C/YNTSC
Tint SW: NTSC mode
Contrast: max., color: typ.
1.0
Times
f = 5 MHz
30
ns
(C−Y)/Y ratio NTSC
Color difference signal delay time
tdC
Color difference output amplitude
ambient temperature dependence
C/∆T
−20°C to +70°C
±4
%
Y cross-talk
Y (M1 ⇔ M2)
CT1
f = 10 MHz
−52
dB
Y cross-talk
(M1, M2 ⇔ Sub)
CT2
f = 10 MHz
−54
dB
Y cross-talk
(M1, M2, sub ⇔ OSD)
CT3
f = 10 MHz
−53
dB
Color difference cross-talk
(M1 ⇔ M2)
CT4
f = 10 MHz
−52
dB
Color difference cross-talk
Pr, Pb (M1, M2 ⇔ Sub)
CT5
f = 10 MHz
−54
dB
Color difference cross-talk
(M1, M2, sub ⇔ OSD)
CT6
f = 10 MHz
−52
dB
Color difference cross-talk
(OSD ⇔ M1, M2, sub)
CT7
f = 10 MHz
−47
dB
Cross-talk between OSDs
CT8
f = 10 MHz
−42
dB
OSD signal delay
tdOSD
f = 5 MHz
10
ns
YS rise delay
tRYS
19
ns
YS fall delay
tFYS
18
ns
YM rise delay
tRYM
20
ns
YM fall delay
tFYM
15
ns
M/S rise delay
tRM/S
24
ns
M/S fall delay
tFM/S
25
ns
Cross-talk
OSD
Pedestal fluctuation
at YS changeover
∆VPYS
YS: Variation amount from
low to high
−60
mV
Pedestal fluctuation
at YM changeover
∆VPYM
YM: Variation amount from
low to high
−10
mV
10
ICs for TV
AN5392FBQ
■ Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25°C (continued)
• Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
1.4
V[p-p]
−20°C to +70°C
±2
%
OSD (continued)
OSD input dynamic range
DOSD
OSD output amplitude
OSD
ambient temperature dependency ∆T
Cutoff drive
Drive variable range (G)
∆GD
Drive G: min. → max.
2.6
dB
Blanking delay
tdBLK1
BLK → BLK output
40
ns
Pedestal fluctuation
to contrast variation
∆VPCONT
Contrast: min. → max.
0
mV
Pedestal fluctuation
to color variation
∆VPCOLOR
Contrast: min. → max.
0
mV
Pedestal fluctuation
to tint variation
∆VPTINT
0
mV
Output pedestal potential
ambient temperature dependency
∆VP
∆T
−20°C to +70°C
−1.2
mV/°C
Spot killer operation
VSP
Lower 9 V-system VCC, pin 33: C = 10 µF
7.8
V
4 · 5 · 6 DAC DNLE
L1
1LSB = {data (max.) − data (min.)}/
(2N−1)
0.1
1.0
1.9
LSB
Step
8-bit DAC DNLE
(excluding 40, 80, C0)
L2
1LSB = {data (max.) − data (min.)}/
(2N−1)
0.1
1.0
1.9
LSB
Step
8-bit DAC DNLE
(only for 40, 80, C0)
L3
1LSB = {data (max.) − data (min.)}/
(2N−1)
−1.0
1.0
+2.0
LSB
Step
7-bit DAC DNLE
(excluding 40)
L4
1LSB = {data (max.) − data (min.)}/
(2N−1)
0.1
1.0
1.9
LSB
Step
7-bit DAC DNLE
(only for 40)
L5
1LSB = {data (max.) − data (min.)}/
(2N−1)
−1.0
1.0
+2.0
LSB
Step
Y, U, V signal delay
tdYUV
R, G, B in → Y, C−Y out, f = 5 MHz
5
ns
Y, U, V input dynamic range
DYUV
1.4
V
Y, U, V matrix ratio 4
MYUV4
R-in: Sine wave 0.2 V[p-p],
f = 1 MHz → R-Y out
0.7
Times
Y, U, V matrix ratio 5
MYUV5
R-in: Sine wave 0.2 V[p-p],
f = 1 MHz → B-Y out
− 0.3
Times
Y, U, V matrix ratio 6
MYUV6
G-in: Sine wave 0.2 V[p-p],
f = 1 MHz → R-Y out
− 0.59
Times
Y, U, V matrix ratio 7
MYUV7
G-in: Sine wave 0.2 V[p-p],
f = 1 MHz → B-Y out
− 0.59
Times
I2C
DAC
Y, U, V
11
AN5392FBQ
ICs for TV
■ Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25°C (continued)
• Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Y, U, V (continued)
Y, U, V matrix ratio 8
MYUV8
B-in: Sine wave 0.2 V[p-p],
f = 1 MHz → R-Y out
− 0.11
Times
Y, U, V matrix ratio 9
MYUV9
B-in: Sine wave 0.2 V[p-p],
f = 1 MHz → B-Y out
0.89
Times
■ Terminal Equivalent Circuits
Pin No.
Equivalent circuit
Description
1
2
3
4
5
1
2
16
23
24
27
30
64
GND:
GND pin
• Pin 1: I2L GND pin
• Pin 2: Y,U,V → R,G,B conversion circuit GND pin
• Pin 16: Pulse-system GND pin
• Pin 23: Main signal-system GND pin
• Pin 24: R signal output circuit GND pin
• Pin 27: B signal output circuit GND pin
• Pin 30: G signal output circuit GND pin
• Pin 64: Input circuit GND pin
Y, R−Y, B−Y out:
Y, R-Y, B-Y output pin for R, G, B → Y, U, V
conversion circuit
• Pin 3: B−Y output pin
VCC 9 V (R,G,B→Y,U,V VCC /pin 10)
200 µA 200 Ω
• Pin 4: Y output pin
80 Ω
200 µA
Pins 3, 4, 5
200 Ω
6
CLP (R, G, B) in:
6
5V
0V
12
• Pin 5: R−Y output pin
• Output dynamic range: 1.5 V to 7.5 V
• Output pedestal is about 3 V.
• Recommended use range: −4 mA to +4 mA
VCC 9 V (R,G,B→Y,U,V VCC /pin 10)
Clamp pulse input pin for R, G, B → Y, U, V
40 µA
conversion circuit
• Input threshold voltage: 1.5 V (to clamp at
high)
• Clamps the signal inputted from the next pin
Pin 7, pin 8, pin 9
• Recommended clamp pulse width
NTSC: 2.5 µs
HD: 1.0 µs
• Recommended use range: 0 V to 5 V
200 Ω
40 µA
2.25 V
ICs for TV
AN5392FBQ
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
7
8
9
Description
VCC 9 V (R,G,B→Y,U,V VCC /pin 10)
0.7 V[0-p]
1 kΩ
1 kΩ
4.5 V
Pins 7, 8, 9
NP, 1 µF
200 Ω
40 µA
3.75 V
400 µA
R, G, B in:
R, G, B input pin for R, G, B → Y, U, V
conversion circuit
• Pin 7: R signal input pin
• Pin 8: G signal input pin
• Pin 9: B signal input pin
• Input 0.7 V[0-p] for both HD and NTSC.
• Drive this pin with a low impedance. High
impedance is likely to cause variation on
white balance with user volume.
• Clamps the input signal with pin 6 clamp
pulse
• Recommended use range: Do not apply DC
voltage from outside.
VCC 9 V:
Signal-system power supply pin
10
• Pin 10: Power supply pin for Y, U, V → R, G,
9V
47 µF
Pins 10, 26, 29
32, 47, 54
Circuit
0.01 µF
B conversion circuit
(pair with Pin 2 GND)
• Pin 26: R signal output circuit power supply
pin
(pair with pin 24 GND)
• Pin 29: B signal output circuit power supply
pin
(pair with pin 27 GND)
• Pin 32: G signal output circuit power supply
pin
(pair with pin 30 GND)
• Pin 47: Main power supply pin
(pair with pin 23 GND)
• Pin 54: Input circuit power supply pin
(pair with pin 64 GND)
• Apply 9 V for use.
• Recommended use range: 8.1 V to 9.9 V
13
AN5392FBQ
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
11
VCC 5 V (I2L VCC /pin 15)
5V
40 µA
40 µA
0V
1.5 V
200 Ω
11
5 kΩ
500 Ω
12
40 kΩ
Slave address SW:
Slave address changeover pin for this IC
• V12 = 5 V: Slave address 86
V12 = 0 V: Slave address 84
Set a slave address carefully so as not to overlap with the other ICs in the same set.
• Recommended use range: 0 V to 5 V
VCC 5 V (I2L VCC /pin 15)
DC
0 V to 5 V
41 kΩ
12
20 kΩ
13
VCC 5 V (I2L VCC /pin 15)
20 µA
50 µA
3.25 V
2.75 V
Data
VP in:
V-latch DAC VP pulse input pin
• Input threshold voltage: 1.5 V
High input: V11 > 2.1 V
Low input: V11 > 0.9 V
• The data for color, tint, brightness and contrast are rewritten at the timing of high-tolow-going VP pulse in DAC SW13-6 (V-latch
mode). In the through mode, the data are rewritten at the timing of the data sent, regardless of VP pulse.
• This pin does not affect a blanking operation.
• Recommended use range: 0 V to 5 V
SDA:
I2C bus data input pin
• Input threshold voltage: 2 V
• Recommended use range: 0 V to 5 V
1 kΩ
13
200 Ω
14
VCC 5 V (I2L VCC /pin 15)
20 µA
3.25 V
50 µA
2.75 V
Data
14
SCL:
I2C clock input pin
• Input threshold voltage: 2 V
• Recommended use range: 0 V to 5 V
1 kΩ
200 Ω
15
5V
47 µF
14
Pins 15, 22
Circuit
0.01 µF
VCC 5 V:
Power supply pin for I2L and pulse-system
• Pin 15: I2L power supply pin
(pair with pin 1 GND)
• Pin 22: Pulse-system power supply pin
(pair with pin 16 GND)
• Apply 5 V for use.
• Recommended use range: 4.5 V to 5.5 V
ICs for TV
AN5392FBQ
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
16
Refer to pin 1
17
Description
Refer to pin 1
VCC 5 V (pulse VCC /pin 22)
5V
16 µA
40 µA
0V
17
2.25 V
200 Ω
500 Ω
18
19
20
5 kΩ
VCC 5 V (pulse VCC /pin 22)
5V
16 µA
40 µA
0V
Pins
18, 19, 20
200 Ω
500 Ω
21
5 kΩ
R, G, B mute, neck mute, CRT mute:
Input pin for R, G, B mute, neck mute, CRT
mute
• Pin 18: R, G, B mute
• Pin 19: Neck mute
• Pin 20: CRT mute
• Input threshold voltage: 1.5 V
2.25 V
High-level input: V18,19,20 ≥ 2.1 V
Low-level input: V18,19,20 ≤ 0.9 V
• If input is high, R, G and B output are
forcibly given BLK. And as pin 18, pin 19 are
ORed, BLK is given whenever any of those
pins are given high level. At this time, BLK in
(pin 17), BLK-SW (I2C) and single color
adjustment SW (I2C) become invalid.
• Recommended use range: 0 V to 5 V
VCC 5 V (pulse VCC /pin 22)
5V
16 µA
40 µA
0V
21
2.25 V
200 Ω
500 Ω
5 kΩ
BLK in:
BLK input pin
• Input threshold voltage: 1.5 V
High-level input: V17 ≥ 2.1 V
Low-level input: V17 ≤ 0.9 V
• Gives BLK to R, G, B output at input = high
• Inhibits black gradation correction, white
gradation correction and APL detection (DC
transfer amount correction) at input = high.
• Recommended use range: 0 V to 5 V
DI in:
DI input pin
• Input threshold voltage: 1.5 V
High-level input: V21 ≥ 2.1 V
Low-level input: V21 ≤ 0.9 V
• Inhibiting black gradation correction, white
gradation correction and APL detection (DC
transmission amount correction) at input =
high.
• Recommended use range: 0 V to 5 V
22
Refer to pin 15
Refer to pin 15
23
Refer to pin 1
Refer to pin 1
24
Refer to pin 1
Refer to pin 1
15
AN5392FBQ
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
25
Equivalent circuit
Description
VCC 9 V (R,G,B output VCC/pins 26, 29, 32)
200 µA
50 Ω
80 Ω
Pins 25, 28, 31
200 µA
R, G, B out:
R, G, B output pin
• Pin 25: R output pin
• Pin 28: B output pin
• Pin 31: G output pin
• Output dynamic range: 1.5 V to 7.5 V
• Use output pedestal typ. value of approx. 3 V.
• Recommended use range: −4 mA to +4 mA
50 Ω
26
Refer to pin 10
Refer to pin 10
27
Refer to pin 1
Refer to pin 1
28
Refer to pin 25
Refer to pin 25
29
Refer to pin 10
Refer to pin 10
30
Refer to pin 1
Refer to pin 1
31
Refer to pin 25
Refer to pin 25
32
Refer to pin 10
33
Refer to pin 10
VCC 9 V (G output VCC /pin 32)
VCC 9 V
10 kΩ
1.75 kΩ
10 µF
To RGB
output
circuit
34
33
100 kΩ
VCC 9 V (G output VCC /pin 32)
DC
3 V to 9 V
34
RGB
output
circuit
5 kΩ
Spot killer in:
Spot killer pin
• Use this pin to discharge electricity on CRT
swiftly when the set is turned off.
• This pin raises DC voltage of R, G, B output
pins (pin 25, pin 28, pin 31) when G output
VCC 9 V (pin 32) is lowered.
R, G, B limiter in:
R, G, B output upper limiter pin
• Limits R, G, B output pin voltage (pin 25, pin
28, pin 31) so as not to become higher than
pin 34 voltage plus 1 VBE.
• Recommended use range: 3 V to 9 V
66 µA
35
VCC 5 V (pulse VCC /pin 22)
40 µA
35
5V
0V
16
200 Ω
40 µA
2.25 V
YM in:
Half tone switching signal input pin
• Input threshold voltage: 1.5 V
1) 2.1 V < V35
Lowers the signal amplitude inputted from
M1, M2 and sub by 9 dB.
2) V35 < 0.9 V
Normal
• Priority order of signal switching
M1/M2 (I2C SW) < M/S < YM < YS
• Recommended use range: 0 V to 5 V
ICs for TV
AN5392FBQ
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
36
Description
VCC 5 V (pulse VCC /pin 22)
40 µA
200 Ω
36
2.25 V
40 µA
5V
0V
37
38
39
VCC 9 V (main VCC /pin 47)
0.7 V[0-p]
1 kΩ
3.75 V
NP, 1 µF
1 kΩ
200 Ω
Pins 37
38
39
3.0 V
40 µA
500 µA
YS in:
OSD signal switching signal input pin
• Input threshold voltage: 1.5 V
1) 2.1 V < V36
Outputs OSD signal inputted from pin 37,
pin 38, pin 39.
2) V36 < 0.9 V
Normal
• Signal switching priority order
M1/M2 (I2C SW) < M/S < YM < YS
• Recommended use range: 0 V to 5 V
OSD in:
OSD signal input pin for analog signal
• Pin 37: B signal input pin
• Pin 38: G signal input pin
• Pin 39: R signal input pin
• Input signal typ. is 0.7 V[0-p] from black to
white level.
• Drive with a low impedance.
• Clamps the input signal with the clamp pulse
of the following pins:
Pin 56, I2C bus M1/M2 switch: M1
Pin 60, I2C bus M1/M2 switch: M2
• Recommended use range:
Do not apply DC voltage from outside.
VCC 9 V (main VCC /pin 47)
40
41
42
2 kΩ
DC voltage
0.1 µF
Pins 40
41
42
1 kΩ
200 Ω
14 kΩ
200 Ω
3V
1 kΩ
B, G, R CLP:
Pin to clamp the main signal with the voltage
proportioned to bright data.
• Pin 40: B signal clamp pin
400 µA
• Pin 41: G signal clamp pin
• Pin 42: R signal clamp pin
• Shorten the distance from the pin to the
3.75 V
external capacitor.
• Recommended use range: 0 V to 5 V
(Do not apply the DC voltage from outside.)
1 kΩ 1 kΩ
VCC 9 V (main VCC /pin 47)
43
3 kΩ
3 kΩ
50 µA
DC voltage
43
C
R
200 Ω
200 Ω
3V
APL det.:
Main signal APL detection pin
• Output the voltage in proportion to the APL
of main signal
• Fit an RC filter to this pin.
R: adjusts detection sensitivity
C: adjusts tracking characteristics
• Recommended use range: 0 V to 3 V
17
AN5392FBQ
ICs for TV
■ Terminal Equivalent Circuits (continued)
Equivalent circuit
Description
44
White peak det.:
Detects the brightest level of main signal
200 µA • Fit an external RC filter between this pin and
VCC
• Carrying out white gradation correction and
blooming control with this detection voltage
R: Adjusts detection sensitivity
C: Adjusts tracking characteristics
• Recommended use range: 0 V to 9 V
VCC 9 V (main VCC /pin 47)
9V
50 µA
C R
200 Ω
44
DC voltage
200 Ω
200 Ω
250 Ω 50 4 kΩ
kΩ
40
µA
45
VCC 9 V (main VCC /pin 47)
40 µA
DC voltage
45
C
1.5 kΩ
200 Ω
300 Ω
200 Ω
R
6 kΩ
7 kΩ
300 µA
40 µA
18 pF
46
VCC 9 V (main VCC /pin 47)
100 µA
50 µA
24 kΩ
DC voltage
46
3.3 kΩ
1 kΩ 300 Ω
5.25 V
100
50 µA µA
Black peak det.:
Detects the darkest level of main signal
• Fit an external RC filter
• Carries out black gradation correction with
this detected voltage
R: Adjusts detection sensitivity
C: Adjusts tracking characteristics
• Recommended use range: 0 V to 9 V
Blooming level in:
Input pin to determine a blooming level
Output clip level
Pin No.
3V
5V
• Recommended use range: 1.5 V to 5 V
47
18
Refer to pin 10
Refer to pin 10
ICs for TV
AN5392FBQ
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
48
VCC 9 V (main VCC /pin 47)
50
µA
DC
voltage
48
Description
50
µA
4 kΩ 4 kΩ
200 Ω
5.5 V
DC regeneration ratio:
Pin to determine DC regeneration ratio
• Adjusting DC regeneration ratio with the resistor to be connected between this pin and
GND
• DC regeneration ratio comes closer to 100%
when R is raised.
• Recommended use range: 0 µA to −200 µA
63 µA
49
VM out:
VM output pin
• Output dynamic range: 1.5 V to 7.5 V
• Use output pedestal typ. value of approx. 3 V
• Recommended use range: −4 mA to +4 mA
VCC 9 V (main VCC /pin 47)
50 Ω
200 µA
80 Ω
200 µA
50
49
50 Ω
VCC 9 V (main VCC /pin 47)
3.5 V
DC voltage
50
3.5 V
100 µA
40 kΩ
100 µA
40 kΩ
5.2 kΩ
7V
4 kΩ
5.2 kΩ
7V
4 kΩ
51
VCC 9 V (Y,U,V VCC /pin 54)
±0.35 V
1 kΩ
1 kΩ
4.5 V
Pins 51, 53
NP, 1 µF
200 Ω
16 µA
ABL/ACL in:
Control voltage input pin for ABL/ACL
• Apply the voltage inversely proportioned to
CRT screen brightness
• Operating range is 7 V to 2 V
• Possible to control contrast and brightness in
inverse proportion to the applied voltage
(controlling main signal and OSD signal)
• Recommended use range: 0 V to 9 V
3.75 V
400 µA
R−Y (S) in, B−Y (S) in:
Sub signal R−Y,B−Y input pin
• Pin 51: R−Y (S) signal input pin
• Pin 53: B−Y (S) signal input pin
• Input ±0.35 V for both HD and NTSC.
• Drive this pin with a low impedance. High
impedance is likely to cause variation of
white balance with the user volume.
• Clamps the input signal with the clamp pulse
of the following pins:
Pin 56, I2C bus M1/M2 switch: M1
Pin 60, I2C bus M1/M2 switch: M2
• Recommended use range:
Do not apply DC voltage from outside.
19
AN5392FBQ
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
52
VCC 9 V (Y,U,V VCC /pin 54)
0.7 V[0-p]
4.5 V
NP, 1 µF
52
1 kΩ
1 kΩ
200 Ω
40 µA
3.75 V
400 µA
Y (S) in:
Sub signal Y input pin
• Input 0.7 V[0-p] (B-W) for both HD and
NTSC.
• Drive this pin with a low impedance. High
impedance is likely to cause variation of
white balance with the user volume.
• Clamps the input signal with the clamp pulse
of the following pins:
Pin 56, I2C bus M1/M2 switch: M1
Pin 60, I2C bus M1/M2 switch: M2
• Recommended use range:
Do not apply DC voltage from outside
53
Refer to pin 51
Refer to pin 51
54
Refer to pin 10
Refer to pin 10
55
M/S in:
M/S (main/sub) switching signal input pin
• Input threshold voltage: 1.5 V
1) 2.1 V < V55
Outputs the signal inputted from M1 or
M2.
2) V55 < 0.9 V
Outputs the signal inputted from M1 or
M2.
VCC 9 V (Y,U,V VCC /pin 54)
40 µA
55
200 Ω
40 µA
5V
2.25 V
0V
Note) If you switch over a multi-screen in a high
speed within 1H period, WB will be changed.
Be careful on use. The degree of WB changes
depending upon the setting of DAC.
• Priority order of signal switching over
M1/M2 (I2C SW) < M/S < YM < YS
• Recommended use range: 0 V to 5 V
56
VCC 9 V (Y,U,V VCC /pin 54)
40 µA
56
5V
0V
20
200 Ω
40 µA
2.25 V
CLP (M1) in:
Main signal (M1) signal clamp pulse input pin
• Input threshold voltage: 1.5 V
(clamps at high)
• Clamps the signal inputted from the next pin
Pin 57, pin 58, pin 59
• Recommended clamp pulse width
NTSC: 2.5 µs, HD: 1.0 µs
• Recommended use range: 0 V to 5 V
ICs for TV
AN5392FBQ
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
57
VCC 9 V (Y,U,V VCC /pin 54)
±0.35 V
1 kΩ
1 kΩ
4.5 V
Pins 57, 59
NP, 1 µF
200 Ω
16 µA
58
3.75 V
400 µA
VCC 9 V (Y,U,V VCC /pin 54)
0.7 V[0-p]
4.5 V
NP, 1 µF
58
1 kΩ
200 Ω
40 µA
59
1 kΩ
3.75 V
400 µA
Refer to pin 57
VCC 9 V (Y,U,V VCC /pin 54)
40 µA
5V
200 Ω
40 µA
Y (M1) in:
Main signal (M1) Y input pin
• Input 0.7 VBW for both HD and NTSC.
• Drive this pin with a low impedance. If it is
driven with a high impedance, WB is likely to
be changed.
• Clamps the input signal with pin 56 clamp
pulse.
• Recommended use range:
Do not apply DC voltage from outside.
Refer to pin 57
60
60
R−Y (M1) in, B−Y (M1) in:
Main (M1) signal R−Y, B−Y input pin
• Pin 57: R−Y (M1) signal input pin
• Pin 59: B−Y (M1) signal input pin
• Input ±0.35 V for both HD and NTSC.
• Drive this pin with a low impedance. High
impedance is likely to cause variation of
white balance with the user volume.
• Clamps the input signal with the clamp pulse
of pin 56:
• Recommended use range:
Do not apply DC voltage from outside.
2.25 V
CLP (M1) in:
Main (M2) signal clamp pulse input pin
• Input threshold voltage: 1.5 V
(clamps at high)
• Clamps the signal inputted from the next pin.
Pin 61, pin 62, pin 63
• Recommended clamp pulse width
NTSC: 2.5 µs
HD: 1.0 µs
• Recommended use range: 0 V to 5 V
0V
21
AN5392FBQ
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
61
VCC 9 V (Y,U,V VCC /pin 54)
±0.35 V
1 kΩ
1 kΩ
4.5 V
Pins 61, 63
NP, 1 µF
200 Ω
16 µA
3.75 V
400 µA
62
VCC 9 V (Y,U,V VCC /pin 54)
0.7 V[0-p]
4.5 V
NP, 1 µF
62
1 kΩ
200 Ω
40 µA
22
1 kΩ
3.75 V
400 µA
R−Y (M2) in, B−Y (M2) in:
Main (M2) signal R−Y, B−Y input pin
• Pin 61: R−Y (M2) signal input pin
• Pin 63: B−Y (M2) signal input pin
• Input ±0.35 V for both HD and NTSC.
• Drive this pin with a low impedance. High
impedance is likely to cause variation of
white balance with the user volume.
• Clamps the input signal with the clamp pulse
of pin 60:
• Recommended use range:
Do not apply DC voltage from outside.
Y (M2) in:
Main (M2) signal Y input pin
• Input 0.7 VBW for both HD and NTSC.
• Drive this pin with a low impedance. High
impedance is likely to cause variation of
white balance with the user volume.
• Clamps the input signal with the clamp pulse
of pin 60:
• Recommended use range:
Do not apply DC voltage from outside.
63
Refer to pin 61
Refer to pin 61
64
Refer to pin 1
Refer to pin 1
ICs for TV
AN5392FBQ
ABL/ACL in
49
V50
50
10 µF
VCC 9 V
33
34
35
36
37
38
39
40
41
42
43
44
V34
YM in
OSD-B in
YS in
OSD-G in
OSD-R in
B-CLP
G-CLP
R-CLP
22 µF
Spot killer in
R, G, B limiter in
10 µF
White peak det.
APL det.
18 kΩ
Black peak det.
4.7 µF
V46
45
46
47
48
VM out
270 kΩ
82 kΩ
VCC
9V
6.4 kΩ
DC regenaration rate
Analog VCC (9 V)
Blooming level in
■ Application Circuit Example (Basic Circuit)
32
ABL/ACL
block
31
R−Y (S) in
51
30
Y (S) in
52
B−Y (S) in
53
Y, U, V VCC (9 V)
54
M/S in
55
26
CLP (M1) in
56
25
R−Y (M1) in
57
Y (M1) in
58
B−Y (M1) in
59
CLP (M2) in
60
21
R−Y (M2) in
61
20
Y (M2) in
62
B−Y (M2) in
63
Y, U, V GND
64
R
Y
Y
Video
block
R−Y
Input
block
R
G
Matrix
block
G
SW
block
B
29
Output
block
B
R−Y
28
27
24
Chrominance G−Y
block
B−Y
B−Y
23
22
R, G, B → Y, U, V
block
I2C
DAC
block
BLK
block
19
18
G-out
G-GND
B-VCC (9 V)
B-out
B-GND
R-VCC (9 V)
R-out
R-GND
Analog GND
Pulse VCC (5 V)
DI in
CRT mute
Neck mute
R,G,B mute
CC (5 V)
16
BLK in
Pulse GND
15
I2L V
14
SCL
12
13
SDA
VP in
Slave address SW
11
10
R,G,B VCC (9 V)
9
B-in
G-in
8
7
R-in
6
CLP (R, G, B) in
5
R−Y out
Y-out
4
3
B−Y out
2
R,G,B GND
I2L GND
1
17
G-VCC (9 V)
23