DATASHEET

40V Extended Temperature Range, Precision
Single-Supply, Rail-to-Rail Output, Operational Amplifier
ISL28118M
Features
The ISL28118M is a single, low-power precision amplifier
optimized for single-supply applications over the extended
temperature range of -55°C to +125°C. This device features a
common mode input voltage range extending to 0.5V below
the V- rail, a rail-to-rail differential input voltage range for use
as a comparator, and rail-to-rail output voltage swing, which
makes it ideal for single-supply applications where input
operation at ground is important.
• Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mV
The ISL28118M features low power, low offset voltage, and
low temperature drift, making it the ideal choice for
applications requiring both high DC accuracy and AC
performance. The op amp is designed to operate over a single
supply range of 3V to 40V or a split supply voltage range of
+1.8V/-1.2V to ±20V. The combination of precision and small
footprint provides the user with outstanding value and
flexibility relative to similar competitive parts.
• Low noise current. . . . . . . . . . . . . . . . . . . . . . . . . . . 355fA/√Hz
Applications include precision instrumentation, data
acquisition, precision power supply controls, and industrial
controls.
• Precision instruments
• Below-ground (V-) input capability to -0.5V
• Rail-to-rail input differential voltage range for comparator
applications
• Single-supply range . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V
• Low current consumption . . . . . . . . . . . . . . . . . . . . . . . . 850µA
• Low noise voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6nV/√Hz
• Low input offset voltage . . . . . . . . . . . . . . . . . . . . 150µV Max.
• Superb offset voltage temperature drift. . . . 1.2µV/°C, Max.
• Operating temperature range. . . . . . . . . . . .-55°C to +125°C
• No phase reversal
Applications
• Medical instrumentation
• Data acquisition
The ISL28118M is offered in the 8 Ld MSOP package and
operate over the extended temperature range of -55°C to
+125°C.
• Power supply control
• Industrial process control
RF
IN-
10kΩ
RIN+
IN+
10kΩ
V+
ISL28118M
V-
+3V
to 40V
300
200
VOUT
-55°C
-40°C
100
+
GAIN = 10
RREF+
VOS (µV)
RINRSENSE
400
100kΩ
LOAD
+25°C
+125°C
0
-100
-200
100kΩ
-300
VREF
-400
-16
-15
-14
-13 13
14
15
16
INPUT COMMON MODE VOLTAGE (V)
FIGURE 1. TYPICAL APPLICATION: SINGLE-SUPPLY, LOW-SIDE
CURRENT SENSE AMPLIFIER
March 7, 2014
FN7858.1
1
FIGURE 2. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE
VOLTAGE, -40°C to +125°C, VS = ±15V
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL28118M
Table of Contents
Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Specifications, VS ±15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Specifications, VS ±5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Stage Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Drive Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Phase Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISL28118M SPICE Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
15
15
15
15
16
Characterization vs Simulation Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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ISL28118M
Pin Configurations
ISL28118M
(8 LD MSOP)
TOP VIEW
NC
1
8
NC
-IN
2
7
V+
+IN
3
6
VOUT
V-
4
5
NC
- +
Pin Descriptions
ISL28118M
(8 LD MSOP)
PIN
NAME
EQUIVALENT
CIRCUIT
3
+IN
1
Amplifier A non-inverting input
2
-IN
1
Amplifier A inverting input
6
VOUT
2
Amplifier A output
4
V-
3
Negative power supply
7
V+
3
Positive power supply
1, 5, 8
NC
-
No Connect
IN-
DESCRIPTION
V+
V+
IN+
OUT
V-
VCIRCUIT 1
V+
CAPACITIVELY
TRIGGERED ESD
CLAMP
V-
CIRCUIT 2
CIRCUIT 3
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL28118MUZ
8118M
TEMP RANGE
(°C)
-55 to +125
PACKAGE
(Pb-Free)
8 Ld MSOP
PKG.
DWG. #
M8.118B
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL28118M. For more information on MSL, please see tech brief TB363.
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ISL28118M
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . .42V or V- - 0.5V to V+ + 0.5V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . .42V or V- - 0.5V to V+ + 0.5V
Max/Min Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Output Short-Circuit Duration (1 output at a time) . . . . . . . . . . . . . . Indefinite
ESD Tolerance
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per CDM-22CI0ID) . . . . . . . . . . . . . . . 2kV
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld MSOP Package (Notes 4, 5) . . . . . . . . .
165
57
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 3V (+1.8V/-1.2V) to 40V (±20V)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications, VS ±15 VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply across the
operating temperature range, -55°C to +125°C. Temperature data established by characterization.
PARAMETER
VOS
DESCRIPTION
CONDITIONS
Input Offset Voltage
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
-150
25
150
µV
270
µV
1.2
µV/°C
-270
TCVOS
Input Offset Voltage Temperature Coefficient
-1.2
0.2
IB
Input Bias Current
-575
-230
nA
-800
TCIB
Input Bias Current
Temperature Coefficient
IOS
Input Offset Current
nA
-0.8
-50
4
-75
CMRR
Common-Mode Rejection Ratio
VCM = V- - 0.5V to V+ - 1.8V
VCM = V- to V+ -1.8V
102
nA/°C
50
nA
75
nA
118
dB
118
dB
97
VCMIR
Common Mode Input Voltage Range
Guaranteed by CMRR test
dB
V- - 0.5
V+ - 1.8
V
V-
V+ - 1.8
V
PSRR
Power Supply Rejection Ratio
VS = 3V to 40V, VCMIR = Valid Input Voltage
109
AVOL
Open-Loop Gain
VO = -13V to +13V, RL = 10kΩ to ground
120
124
dB
136
dB
105
dB
114
VOL
VOH
IS
ISC+
Output Voltage Low,
VOUT to V-
RL = 10kΩ
Output Voltage High,
V+ to VOUT
RL = 10kΩ
Supply Current/Amplifier
RL = Open
Output Short Circuit Source Current
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4
RL = 10Ω to V-
dB
0.85
16
70
mV
85
mV
110
mV
120
mV
1.2
mA
1.6
mA
mA
FN7858.1
March 7, 2014
ISL28118M
Electrical Specifications, VS ±15 VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply across the
operating temperature range, -55°C to +125°C. Temperature data established by characterization. (Continued)
PARAMETER
DESCRIPTION
MIN
(Note 6)
CONDITIONS
ISC-
Output Short Circuit Sink Current
RL = 10Ω to V+
VSUPPLY
Supply Voltage Range
Guaranteed by PSRR
MAX
(Note 6)
TYP
28
UNIT
mA
3
40
V
AC SPECIFICATIONS
GBWP
Gain Bandwidth Product
ACL = 101, VOUT = 100mVP-P; RL = 2k
4
MHz
enp-p
Voltage Noise
0.1Hz to 10Hz, VS = ±18V
300
nVP-P
en
Voltage Noise Density
f = 10Hz, VS = ±18V
8.5
nV/√Hz
en
Voltage Noise Density
f = 100Hz, VS = ±18V
5.8
nV/√Hz
en
Voltage Noise Density
f = 1kHz, VS = ±18V
5.6
nV/√Hz
en
Voltage Noise Density
f = 10kHz, VS = ±18V
5.6
nV/√Hz
in
Current Noise Density
f = 1kHz, VS = ±18V
355
fA/√Hz
THD + N
Total Harmonic Distortion + Noise
1kHz, G = 1, VO = 3.5VRMS, RL = 10kΩ
0.0003
%
TRANSIENT RESPONSE
SR
Slew Rate
AV = 1, RL = 2kΩ, VO = 10VP-P
±1.2
V/µs
tr, tf, Small
Signal
Rise Time
10% to 90% of VOUT
AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to
VCM
100
ns
Fall Time
90% to 10% of VOUT
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,
RL = 2kΩ to VCM
100
ns
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = 1, VOUT = 10VP-P, Rf = 0Ω
RL = 2kΩ to VCM
8.5
µs
ts
Electrical Specifications, VS ±5V
VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
temperature range, -55°C to +125°C. Temperature data established by characterization.
PARAMETER
VOS
DESCRIPTION
CONDITIONS
Input Offset Voltage
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
-150
25
150
µV
270
µV
1.2
µV/°C
-270
TCVOS
Input Offset Voltage Temperature
Coefficient
-1.2
0.2
IB
Input Bias Current
-575
-230
nA
-800
TCIB
Input Bias Current
Temperature Coefficient
IOS
Input Offset Current
nA
-0.8
-50
4
-75
CMRR
Common-Mode Rejection Ratio
VCM = V- - 0.5V to V+ - 1.8V
VCM = V- to V+ -1.8V
101
nA/°C
50
nA
75
nA
119
dB
117
dB
96
VCMIR
PSRR
Common Mode Input Voltage
Range
Guaranteed by CMRR test
Power Supply Rejection Ratio
VS = 3V to 10V, VCMIR = Valid Input Voltage
V- - 0.5
V+ - 1.8
V
V-
V+ - 1.8
V
108
103
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5
dB
124
dB
dB
FN7858.1
March 7, 2014
ISL28118M
Electrical Specifications, VS ±5V
VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
temperature range, -55°C to +125°C. Temperature data established by characterization. (Continued)
PARAMETER
AVOL
DESCRIPTION
Open-Loop Gain
CONDITIONS
VO = -3V to +3V, RL = 10kΩ to ground
MIN
(Note 6)
TYP
120
132
MAX
(Note 6)
dB
110
VOL
UNIT
dB
Output Voltage Low,
VOUT to V-
RL = 10kΩ
Output Voltage High,
V+ to VOUT
RL = 10kΩ
IS
Supply Current/Amplifier
RL = Open
ISC+
Output Short Circuit Source Current RL = 10Ω to V-
13
mA
ISC-
Output Short Circuit Sink Current
RL = 10Ω to V+
20
mA
VOH
0.85
38
mV
45
mV
65
mV
70
mV
1.1
mA
1.4
mA
AC SPECIFICATIONS
GBWP
Gain Bandwidth Product
ACL = 101, VOUT = 100mVP-P; RL = 2k
3.2
MHz
enp-p
Voltage Noise
0.1Hz to 10Hz
320
nVP-P
en
Voltage Noise Density
f = 10Hz
9
nV/√Hz
en
Voltage Noise Density
f = 100Hz
5.7
nV/√Hz
en
Voltage Noise Density
f = 1kHz
5.5
nV/√Hz
en
Voltage Noise Density
f = 10kHz
5.5
nV/√Hz
in
Current Noise Density
f = 1kHz
380
fA/√Hz
THD + N
Total Harmonic Distortion + Noise
1kHz, G = 1, VO = 1.25VRMS, RL = 10kΩ
0.0003
%
TRANSIENT RESPONSE
SR
Slew Rate
AV = 1, RL = 2kΩ, VO = 4VP-P
±1
V/µs
tr, tf, Small
Signal
Rise Time
10% to 90% of VOUT
AV = 1, VOUT = 100mVP-P , Rf = 0Ω, RL = 2kΩ to
VCM
100
ns
Fall Time
90% to 10% of VOUT
AV = 1, VOUT = 100mVP-P , Rf = 0Ω,
RL = 2kΩ to VCM
100
ns
Settling Time to 0.01%
4V Step; 10% to VOUT
AV = 1, VOUT = 4VP-P, Rf = 0Ω
RL = 2kΩ to VCM
4
µs
ts
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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ISL28118M
80
VS = ±15V
70
FIGURE 3. ISL28118M INPUT OFFSET VOLTAGE DISTRIBUTION,
VS = ±15V
400
90
300
80
200
70
-55°C
VS = ±15V
50
40
30
120
80
100
60
-40°C
100
VOS (µV)
VOS (µV)
VOS (µV)
FIGURE 4. ISL28118M INPUT OFFSET VOLTAGE DISTRIBUTION,
VS = ±5V
100
60
0
0
40
10
120
80
VOS (µV)
100
40
60
0
20
-40
-20
-80
-60
0
-100
10
20
20
20
30
-20
30
40
-40
40
50
-60
50
60
-80
60
VS = ±5V
-100
70
-120
NUMBER OF AMPLIFIERS
80
NUMBER OF AMPLIFIERS
90
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified.
-120
Typical Performance Curves
+25°C
+125°C
0
-100
-200
20
VS = ±5V
-300
10
0
-60
-40
-20
0
20
40
60
80
100
120
-400
-16
-15
FIGURE 5. VOS vs TEMPERATURE
-14
-13 13
14
15
16
INPUT COMMON MODE VOLTAGE (V)
TEMPERATURE (°C)
FIGURE 6. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE
VOLTAGE, -55°C to +125°C, VS = ±15V
0
-150
VS = ±20V
-50
-200
-100
VS = ±15V
-200
IBIAS (nA)
IBIAS (nA)
-150
-250
-300
-250
VS = +2V/ -1V
-300
-350
VS = ±2.25V
-350
-400
VS = ±5V
-450
-500
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
VS (V)
FIGURE 7. IBIAS vs VS
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-400
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 8. IBIAS vs TEMPERATURE vs SUPPLY
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ISL28118M
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
124
124
122
122
120
120
CMRR (dB)
CMRR (dB)
Typical Performance Curves
118
116
118
116
114
114
112
112
110
-60
-40
-20
0
20
40
60
80
100
110
-60
120
-40
-20
TEMPERATURE (°C)
100
120
130
PSRR (dB)
CMRR (dB)
125
120
115
110
105
100
-60
10 100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
1M
FIGURE 13. PSRR vs FREQUENCY, VS = ±15V
8
-20
0
20
40
60
80
100
120
FIGURE 12. PSRR vs TEMPERATURE, VS = ±15V
VS = ±15V
AV = 1
CL = 4pF
RL = 10k
VCM = 1VP-P
1k
10k
100k
FREQUENCY (Hz)
-40
TEMPERATURE (°C)
PSRR (dB)
PSRR (dB)
80
135
PSRR-
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60
140
PSRR+
100
40
FIGURE 10. ISL28118M CMRR vs TEMPERATURE, VS = ±5V
FIGURE 11. CMRR vs FREQUENCY, VS = ±15V
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
10
20
TEMPERATURE (°C)
FIGURE 9. ISL28118M CMRR vs TEMPERATURE, VS = ±15V
140
130
120
110
100
90
80
70
60
50
40
30 VS = ±15V
20 SIMULATION
10
0
1m 0.01 0.1 1
0
10M
140
130
120
PSRR+
110
100
90
80
PSRR70
60
50
VS = ±5V
40
AV = 1
30
CL = 4pF
20
RL = 10k
10
VCM = 1VP-P
0
-10
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 14. PSRR vs FREQUENCY, VS = ±5V
FN7858.1
March 7, 2014
ISL28118M
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60 VS = ±15V
-80 RL = 1MΩ
-100
1m 0.01 0.1
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
70
60
PHASE
GAIN
RF = 10kΩ, RG = 100Ω
40
VS = ±5V & ±15V
CL = 4pF
RL = 2k
VOUT = 100mVP-P
ACL = 100
30
20
ACL = 10
10
0
1
RF = 10kΩ, RG = 10Ω
ACL = 1000
50
GAIN (dB)
GAIN (dB)
Typical Performance Curves
-10
100
10 100 1k 10k 100k 1M 10M100M 1G
RF = 10kΩ, RG = 1kΩ
ACL = 1
RF = 0, RG = ∞
1k
FIGURE 15. OPEN-LOOP GAIN, PHASE vs FREQUENCY, VS = ±15V
-1
-2
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
0
-1
RL = OPEN, 100k, 10k
-3
RL = 1k
-4
RL = 499
-5
VS = ±15V
RL = 100
CL = 4pF
-7 A = +1
V
-8 VOUT = 100mVp-p
-9
100
RL = 49.9
10k
1k
100k
1M
-3
RL = OPEN, 100k, 10k
-4
RL = 1k
-5
-6
-9
100
10M
RL = 499
VS = ±5V
1k
RL = 49.9
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 18. GAIN vs FREQUENCY vs RL, VS = ±5V
1
1
0
0
-1
-1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
RL = 100
CL = 4pF
-7
AV = +1
-8 VOUT = 100mVp-p
FIGURE 17. GAIN vs FREQUENCY vs RL, VS = ±15V
VOUT = 10mVP-P
-2
VOUT = 50mVP-P
-3
VOUT = 100mVP-P
-4
VOUT = 500mVP-P
VOUT = 1VP-P
VS = ±5V
CL = 4pF
-7 A = +1
V
-8 RL = INF
-9
10M
-2
FREQUENCY (Hz)
-6
1M
1
0
-5
100k
FIGURE 16. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
1
-6
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 19. GAIN vs FREQUENCY vs OUTPUT VOLTAGE
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9
10M
VS = ±1.5V
-2
-3
VS = ±5V
-4
-5
VS = ±15V
-6 CL = 4pF
R = 10k
-7 L
AV = +1
-8 VOUT = 100mVP-P
-9
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 20. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FN7858.1
March 7, 2014
ISL28118M
Typical Performance Curves
VOH AND VOL (mV)
90
40
VS = ±15V
RL = 10k
VS = ±5V
38 R = 10k
L
36
VOH
VOH AND VOL (mV)
100
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
80
70
60
50
-40
-20
0
20
40
60
34
32
30
28
26
24
VOL
40
-60
VOH
VOL
22
80
100
20
-60
120
-40
-20
TEMPERATURE (°C)
FIGURE 21. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE,
VS = ±15V, RL = 10k
1
20
40
60
80
100
120
FIGURE 22. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE,
VS = ±5V, RL = 10k
1
VS = ±5V and ±15V
0
TEMPERATURE (°C)
+125°C
VS = ±5V and ±15V
0.1
-40°C
0.01
0.001
0.001
0.01
0.1
LOAD CURRENT (mA)
10
1
+25°C
0.1
VOL - V- (V)
V+ - VOH (V)
+125°C
+25°C
-40°C
0.01
0.001
0.001
0.01
0.1
1
10
LOAD CURRENT (mA)
FIGURE 23. OUTPUT OVERHEAD VOLTAGE HIGH vs LOAD CURRENT,
-40°C to +125°C, VS = ±5V AND ±15V
1600
FIGURE 24. OUTPUT OVERHEAD VOLTAGE LOW vs LOAD CURRENT,
-40°C to +125°C, VS = ±5V AND ±15V
1100
ISUPPLY PER AMPLIFIER (µA)
1000
CURRENT (µA)
1400
1200
VS = ±21V
1000
VS = ±15V
800
600
400
VS = ±2.25V
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 25. ISL28118M SUPPLY CURRENT vs TEMPERATURE vs
SUPPLY VOLTAGE
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10
900
800
700
600
500
400
300
200
100
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42
VSUPPLY (V)
FIGURE 26. SUPPLY CURRENT vs SUPPLY VOLTAGE
FN7858.1
March 7, 2014
ISL28118M
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
10
INPUT NOISE CURRENT
1
0.1
0.1
1
10
100
1k
1
0.1
100k
10k
100
INPUT NOISE VOLTAGE
10
10
INPUT NOISE CURRENT
1
1
0.1
0.1
1
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 27. INPUT NOISE VOLTAGE (en) AND INPUT NOISE
CURRENT (in) vs FREQUENCY, VS = ±18V
500
300
INPUT NOISE VOLTAGE (nV)
INPUT NOISE VOLTAGE (nV)
VS = ±18V
AV = 10k
400
200
100
0
-100
-200
-300
-400
0
1
2
3
4
5
6
7
8
9
VS = ±5V
AV = 10k
400
300
200
100
0
-100
-200
-300
-400
-500
10
0
1
2
3
TIME (s)
AV = 10
+25°C
0.01
THD + N (%)
THD + N (%)
VS = ±15V
CL = 4pF
RL = 10k
VOUT = 10VP-P
-40°C
+125°C
5
6
7
8
9
10
FIGURE 30. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±5V
0.1
VS = ±15V
CL = 4pF
RL = 2k
VOUT = 10VP-P
4
TIME (s)
FIGURE 29. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±18V
0.1
0.1
100k
10k
FIGURE 28. INPUT NOISE VOLTAGE (en) AND INPUT NOISE
CURRENT (in) vs FREQUENCY, VS = ±5V
500
-500
100
VS = ±5V
INPUT NOISE CURRENT (fA/√Hz)
INPUT NOISE VOLTAGE
10
100
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE VOLTAGE (nV/√Hz)
VS = ±18V
INPUT NOISE CURRENT (fA/√Hz)
100
C = WEIGHTED
22Hz TO 500kHz
0.001
0.01
C = WEIGHTED
22Hz TO 500kHz
-40°C
+125°C
+25°C
AV = 10
0.001
AV = 1
+25°C
0.0001
10
AV = 1
+125°C
100
1k
FREQUENCY (Hz)
10k
FIGURE 31. THD+N vs FREQUENCY vs TEMPERATURE,
AV = 1,10, RL = 2k
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11
-40°C
100k
-40°C
0.0001
10
+25°C
100
+125°C
1k
10k
100k
FREQUENCY (Hz)
FIGURE 32. THD+N vs FREQUENCY vs TEMPERATURE,
AV = 1, 10,RL = 10k
FN7858.1
March 7, 2014
ISL28118M
Typical Performance Curves
1
1
VS = ±15V
CL = 4pF
RL = 10k
0.1 f = 1kHz
C = WEIGHTED
22Hz TO 22kHz
+125°C
-40°C
+25°C
AV = 10
0.01
AV = 1
0.001
0.0001
THD + N (%)
THD + N (%)
VS = ±15V
CL = 4pF
RL = 2k
0.1 f = 1kHz
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
5
10
15
0.01
+25°C
AV = 1
-40°C
20
25
30
0.0001
0
+25°C
10
5
VOUT (VP-P)
FIGURE 33. THD+N vs OUTPUT VOLTAGE (VOUT) vs TEMPERATURE,
AV = 1, 10, RL = 2k
-40°C
+125°C
15
VOUT (VP-P)
20
25
30
FIGURE 34. THD+N vs OUTPUT VOLTAGE (VOUT) vs TEMPERATURE,
AV = 1, 10, RL = 10k
2.4
6
VS = ±15V
AV = 1
4
RL = 2k
CL = 4pF
2
VS = ±5V
AV = 1
RL = 2k
CL = 4pF
2.0
1.6
1.2
0.8
VOUT (V)
VOUT (V)
+125°C
-40°C
AV = 10
0.001
+125°C
+25°C
0
C = WEIGHTED
22Hz TO 22kHz
0
-2
0.4
0
-0.4
-0.8
-1.2
-1.6
-2.0
-2.4
-4
-6
0
10
20
30
40
50
60
TIME (µs)
70
80
90
100
FIGURE 35. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V
100
VOUT (V)
40
20
5
0
-20
-40
-60
-80
-100
20
30
40
50
60
TIME (µs)
70
80
90
100
6
INPUT AND OUTPUT (V)
60
10
FIGURE 36. LARGE SIGNAL 4V STEP RESPONSE, VS = ±5V
VS = ±15V
AND
VS = ±5V
AV = 1
RL = 2k
CL = 4pF
80
0
VS = ±5V
VIN = ±5.9V
4
INPUT
3
2
1
OUTPUT
0
-1
-2
-3
-4
-5
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
TIME (µs)
FIGURE 37. SMALL SIGNAL TRANSIENT RESPONSE,
VS = ±5V, ±15V
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12
1.8
2
-6
0
1
2
TIME (ms)
3
4
FIGURE 38. NO PHASE REVERSAL
FN7858.1
March 7, 2014
ISL28118M
VS = ±15V
AV = 100
RL = 10k
VIN = 100mVP-P
OVERDRIVE = 1V
120
0
16
-40
-4
-80
-8
INPUT
12
OUTPUT
80
8
40
4
-160
0
-200
0
0
4
8
12
16
20
24
28
32
36
0
40
-120
OUTPUT
0
4
8
12
16
TIME (µs)
3
2
20
INPUT (mV)
OUTPUT
0
OUTPUT (V)
INPUT
40
INPUT (mV)
FIGURE 40. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±15V
6
VS = ±5V
AV = 100
5
RL = 10k
VIN = 50mVP-P
OVERDRIVE = 1V 4
60
30
24
TIME (µs)
FIGURE 39. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±15V
50
20
0
-10
-1
-20
-2
-30
-3
OUTPUT
-40
INPUT
1
-50
0
40
-60
10
0
0
4
8
12
16
20
24
28
32
36
0
4
8
12
FIGURE 41. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±5V
20
24
FIGURE 42. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±5V
100
100
VS = ±5V
VS = ±15V
AV = 10
10
AV = 10
10
AV = 100
ZOUT (Ω)
AV = 100
ZOUT (Ω)
16
-4
VS = ±5V
AV = 100
RL = 10k
-5
VIN = 50mVP-P
OVERDRIVE = 1V
-6
28
32
36
40
TIME (µs)
TIME (µs)
1
0.10
0.01
-12
VS = ±15V
AV = 100
-16
RL = 10k
VIN = 100mVP-P
OVERDRIVE = 1V
-20
28
32
36
40
OUTPUT (V)
INPUT (mV)
160
20
OUTPUT (V)
INPUT
INPUT (mV)
200
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
OUTPUT (V)
Typical Performance Curves
0.10
AV = 1
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 43. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±15V
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13
1
0.01
AV = 1
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 44. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±5V
FN7858.1
March 7, 2014
ISL28118M
Typical Performance Curves
OVERSHOOT (%)
50
60
VS = ±15V
VOUT = 100mVP-P
50
AV = 1
OVERSHOOT (%)
60
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
40
AV = 10
AV = -1
30
20
10
VS = ±5V
VOUT = 100mVP-P
AV = 1
40
20
10
0
0.001
0.010
0.100
1
10
0
0.001
100
LOAD CAPACITANCE (nF)
VS = ±15V
28 R = 10k
L
26
VOUT (VP-P)
ISC (mA)
24
ISC-SINK
20
18
16
ISC-SOURCE
14
12
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 47. ISL28118M SHORT CIRCUIT CURRENT vs
TEMPERATURE, VS = ±15V
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14
0.1
1
10
100
FIGURE 46. OVERSHOOT vs CAPACITIVE LOAD, VS = ±5V
30
22
0.01
LOAD CAPACITANCE (nF)
FIGURE 45. OVERSHOOT vs CAPACITIVE LOAD, VS = ±15V
10
-60
AV = 10
AV = -1
30
100
120
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
VS = ±15V
AV = 1
1k
10k
100k
FREQUENCY (Hz)
1M
FIGURE 48. MAX OUTPUT VOLTAGE vs FREQUENCY
FN7858.1
March 7, 2014
ISL28118M
Applications Information
V+
Functional Description
The ISL28118M is a 3.2MHz, single-supply, rail-to-rail output
amplifier with a common mode input voltage range extending to
a range of 0.5V below the V- rail. The input stage is optimized for
precision sensing of ground-referenced signals in single-supply
applications. The input stage is able to handle large input
differential voltages without phase inversion, making this
amplifier suitable for high-voltage comparator applications. The
bipolar design features high open loop gain, excellent DC
input/output temperature stability with a low quiescent current
of 850µV, and low temperature drift. The op amp is fabricated in
a new precision 40V complementary bipolar DI process and is
immune from latch-up.
Operating Voltage Range
The op amp is designed to operate over a single supply range of 3V
to 40V or a split supply voltage range of +1.8V, -1.2V to ±20V. The
device is fully characterized at 10V (±5V) and 30V (±15V). Both DC
and AC performance remain virtually unchanged over the
complete operating voltage range. Parameter variation with
operating voltage is shown in the “Typical Performance Curves”
beginning on page 7.
The input common mode voltage to the V+ rail (V+ -1.8V over the
full temperature range) may limit amplifier operation when
operating from split V+ and V- supplies. Figure 6 shows the
common mode input voltage range variation over-temperature.
Input Stage Performance
The ISL28118M PNP input stage has a common mode input range
extending up to 0.5V below ground at +25°C (Figure 6). Full
amplifier performance is guaranteed with input voltage down to
ground (V-) over the -55°C to +125°C temperature range. For
common mode voltages down to -0.5V below ground (V-), the
amplifiers are fully functional, but performance degrades slightly
over the full temperature range. This feature provides excellent
CMRR, AC performance, and DC accuracy when amplifying
low-level, ground-referenced signals.
The input stage has a maximum input differential voltage equal
to a diode drop greater than the supply voltage (max 42V) and
does not contain the back-to-back input protection diodes found
on many similar amplifiers. This feature enables the device to
function as a precision comparator by maintaining very high
input impedance for high-voltage differential input comparator
voltages. The high differential input impedance also enables the
device to operate reliably in large signal pulse applications,
without the need for anti-parallel clamp diodes required on
MOSFET and most bipolar input stage op amps. Thus, input
signal distortion caused by nonlinear clamps under high slew
rate conditions is avoided.
In applications where one or both amplifier input terminals are at
risk of exposure to voltages beyond the supply rails,
current-limiting resistors may be needed at each input terminal
(see Figure 49, RIN+, RIN-) to limit current through the
power-supply ESD diodes to 20mA.
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15
VINVIN+
RIN-
-
RIN+
+
RG
RF
RL
V-
FIGURE 49. INPUT ESD DIODE CURRENT LIMITING
Output Drive Capability
The bipolar rail-to-rail output stage features low saturation levels
that enable an output voltage swing to less than 15mV when the
total output load (including feedback resistance) is held below
50µA. With ±15V supplies, this can be achieved by using feedback
resistor values >300kΩ.
The output stage is internally current limited. The amplifiers can
withstand a short circuit to either rail as long as the power
dissipation limits are not exceeded. Continuous operation under
these conditions may degrade long-term reliability.
The amplifiers perform well when driving capacitive loads
(Figures 45 and 46). The unity gain, voltage follower (buffer)
configuration provides the highest bandwidth but is also the
most sensitive to ringing produced by load capacitance found in
BNC cables. Unity gain overshoot is limited to 35% at
capacitance values to 0.33nF. At gains of 10 and higher, the
device is capable of driving more than 10nF without significant
overshoot.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28118M is immune to output phase reversal for
input voltage to 0.5V beyond the rail (VABS MAX) limit (Figure 38).
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
T JMAX = T MAX + θ JA xPD MAXTOTAL
(EQ. 1)
where
• PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
FN7858.1
March 7, 2014
ISL28118M
PDMAX for each amplifier can be calculated using Equation 2:
V OUTMAX
PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × ---------------------------R
(EQ. 2)
L
where:
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
• IqMAX = Maximum quiescent supply current of one amplifier
• VOUTMAX = Maximum output voltage swing of the application
• RL = Load resistance
ISL28118M SPICE Model
Figure 50 shows the SPICE model schematic and Figure 51 shows
the net list for the SPICE model. The model is a simplified version
of the actual device and simulates important AC and DC
parameters. AC parameters incorporated into the model are: 1/f
and flatband noise voltage, slew rate, CMRR, and gain and phase.
The DC parameters are IOS, total supply current, and output
voltage swing. The model uses typical parameters given in the
“Electrical Specifications” table beginning on page 4. The AVOL is
adjusted for 136dB with the dominant pole at 0.6Hz. The CMRR is
set at 120dB, f = 50kHz. The input stage models the actual device
to present an accurate AC representation. The model is configured
for an ambient temperature of +25°C.
Figures 52 through 66 show the characterization vs simulation
results for the noise voltage, open loop gain phase, closed loop
gain vs frequency, gain vs frequency vs RL, CMRR, large signal
10V step response, small signal 0.1V step, and output voltage
swing ±15V supplies.
LICENSE STATEMENT
The information in the SPICE model is protected under United
States copyright laws. Intersil Corporation hereby grants users of
this macro-model, hereto referred to as “Licensee”, a
nonexclusive, nontransferable licence to use this model, as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to anyone
outside the Licensee’s company. The Licensee may modify the
macro-model to suit his/her specific applications, and the
Licensee may make copies of this macro-model for use within
their company only.
This macro-model is provided “AS IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral, incidental,
or consequential damages in connection with or arising out of
the use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior
notice.
Submit Document Feedback
16
FN7858.1
March 7, 2014
DX
D3
G1
+
-
I2
54E-6
I3
9
D13
DN
17
DN
R2
5e11
4 V8
750
2
R17
+
++
- -
0
D14
0
3 750
En
Q8
CinDif
1.33E-12
5
R1
5e11
Cin2
4.02e-12
DX
+
-
C1
R7
6.6667E-11
3.7304227e9
GAIN = 1.69138e-3
-0.91
V3
6
Input Stage
V+
1
GAIN = 0.65897
D4
1st Gain Stage
V++
V++
L3
3.18319E-09
V++
G9
+
-
R13
795.7981
D10
GAIN = 1.2566e-3
D7
D11
V5
DX 24
C3
10e-12
Vc
Vg
R6
V--
G5
+
+
18
21
GAIN = 1 R9 GAIN = 1 R11
1e-3
1e-3
19
G2
DX
16
15
R4
1k
DX
3.18319E-09
V2
-0.96
V--
GAIN = 1
L1
GAIN = 1
G13
GAIN = 12.5e-3
-0.4
23
26
R15
80
Vout
VOUT
27
Vmid
ISY
D8
DX
D6
22
L4
3.18319E-09
GAIN = 1.2566e-3
R14
795.7981
V--
FN7858.1
March 7, 2014
Mid Supply ref V
D9
G11
G12
D12
+
+
GAIN = 12.5e-3
GAIN = 12.5e-3
V-V-
2nd Gain Stage
-0.4
C4
10e-12
DY
G8
L2
3.18319E-09
GAIN = 1
GAIN = 1
G10
DY
+
-
GAIN = 1.69138e-3
3.7304227e9
20
G6
+
-
C2
6.6667E-11
17
R12
1e-3
+
-
G4
R10
1e-3
+
-
++
- GAIN = 0.5
-0.96
V6
25
DX
V4
Common Mode
Gain Stage
with Zero
E3
+ -+
GAIN = 1
V--
0
FIGURE 50. SPICE SCHEMATIC
Output Stage
Correction Current Sources
R16
+
-
2.5E-3
G14
GAIN = 12.5e-3
80
ISL28118M
D5
Q9
14
EOS
+
+
- -
12
11
Cin1
4.02e-12
E2
++
- 0
PNP_LATERAL
10
PNP_input PNP_input
D2 DBREAK
R3
1k
Vin+
GAIN = 0.3
Q6
8
IOS
4e-9
Vcm
R18
Q7
7
DX
V7
PNP_LATERAL
+-
1
-0.91
D1 DBREAK
0.1
0.1
1
GAIN = 0.65897
V1
54E-6
Vin-
R5
13
-
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I1
80e-6
ISL28118M
*ISL28118_218 Macromodel - covers
following *products
*ISL28118
*ISL28218
*
*Revision History:
* Revision B, LaFontaine January 22 2014
* Model for Noise, supply currents, CMRR
*120dB f = 40kHz, AVOL 136dB f = 0.5Hz
* SR = 1.2V/us, GBWP 4MHz.
*Copyright 2011 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT”
*Use of this model indicates your acceptance
*with the terms and provisions in the License
*Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
characteristics *under a wide range of
external circuit *configurations using
compatible simulation *platforms – such as
iSim PE.
*
*Device performance features supported by
this *model:
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances,
*Open loop gain and phase,
*Closed loop bandwidth and frequency
*response,
*Loading effects on closed loop frequency
*response,
*Input noise terms including 1/f effects,
*Slew rate,
*Input and Output Headroom limits to I/O
*voltage swing,
*Supply current at nominal specified supply
*voltages,
*
*Device performance features NOT
supported *by this model:
*Harmonic distortion effects,
*Output current limiting (current will limit at
*40mA),
*Disable operation (if any),
*Thermal effects and/or over temperature
*parameter variation,
*Limited performance variation vs. supply
*voltage is modeled,
*Part to part performance variation due to
*normal process parameter spread,
*Any performance difference arising from
*different packaging,
*Load current reflected into the power supply
*current.
* source ISL28118_218 SPICEmodel
*
* Connections:
+input
*
| -input
*
| | +Vsupply
*
| | | -Vsupply
*
| | | | output
.subckt ISL28118_218 Vin+ Vin-V+ V- VOUT
* source ISL28118_218_presubckt_0
*
*Voltage Noise
E_En
VIN+ 6 2 0 0.3
D_D13
1 2 DN
D_D14
1 2 DN
V_V7
1 0 0.1
V_V8
4 0 0.1
R_R17
2 0 750
*R_R18
3 0 750
*
*Input Stage
Q_Q6
11 10 9 PNP_input
Q_Q7
8 7 9 PNP_input
Q_Q8
V-- VIN- 7 PNP_LATERAL
Q_Q9
V-- 12 10 PNP_LATERAL
I_I1
V++ 9 DC 80e-6
I_I2
V++ 7 DC 54E-6
I_I3
V++ 10 DC 54E-6
I_IOS
6 VIN- DC 4e-9
D_D1
7 10 DBREAK
D_D2
10 7 DBREAK
R_R1
5 6 5e11
R_R2
VIN- 5 5e11
R_R3
V-- 8 1000
R_R4
V-- 11 1000
C_Cin1
V-- VIN- 4.02e-12
C_Cin2
V-- 6 4.02e-12
C_CinDif
6 VIN- 1.33E-12
*
*1st Gain Stage
G_G1
V++ 14 8 11 0.65897
G_G2
V-- 14 8 11 0.65897
V_V1
13 14 -0.91
V_V2
14 15 -0.96
D_D3
13 V++ DX
D_D4
V-- 15 DX
R_R5
14 V++ 1
R_R6
V-- 14 1
*
*2nd Gain Stage
G_G3
V++ VG 14 VMID 1.69138e-3
G_G4
V-- VG 14 VMID 1.69138e-3
V_V3
16 VG -0.91
V_V4
VG 17 -0.96
D_D5
16 V++ DX
D_D6
V-- 17 DX
R_R7
VG V++ 3.7304227e9
R_R8
V-- VG 3.7304227e9
C_C1
VG V++ 6.6667E-11
C_C2
V-- VG 6.6667E-11
*
*Mid supply Ref
E_E2
V++ 0 V+ 0 1
E_E3
V-- 0 V- 0 1
E_E4
VMID V-- V++ V-- 0.5
I_ISY
V+ V- DC 0.85E-3
*
*Common Mode Gain Stage with Zero
G_G5
V++ 19 5 VMID 1
G_G6
V-- 19 5 VMID 1
G_G7
V++ VC 19 VMID 1
G_G8
V-- VC 19 VMID 1
E_EOS
12 6 VC VMID 1
L_L1
18 V++ 3.18319E-09
L_L2
20 V-- 3.18319E-09
L_L3
21 V++ 3.18319E-09
L_L4
22 V-- 3.18319E-09
R_R9
19 18 1e-3
R_R10
20 19 1e-3
R_R11
VC 21 1e-3
R_R12
22 VC 1e-3
*
*Pole Stage
G_G9
V++ 23 VG VMID 1.2566e-3
G_G10
V-- 23 VG VMID 1.2566e-3
R_R13
23 V++ 795.7981
R_R14
V-- 23 795.7981
C_C3
23 V++ 10e-12
C_C4
V-- 23 10e-12
*
*Output Stage with Correction Current
Sources
G_G11
26 V-- VOUT 23 12.5e-3
G_G12
27 V-- 23 VOUT 12.5e-3
G_G13
VOUT V++ V++ 23 12.5e-3
G_G14
V-- VOUT 23 V-- 12.5e-3
D_D7
23 24 DX
D_D8
25 23 DX
D_D9
V-- 26 DY
D_D10
V++ 26 DX
D_D11
V++ 27 DX
D_D12
V-- 27 DY
V_V5
24 VOUT -0.4
V_V6
VOUT 25 -0.4
R_R15
VOUT V++ 80
R_R16
V-- VOUT 80
.model PNP_LATERAL pnp(is=1e-016
bf=250 va=80
+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0
af=1)
.model PNP_input pnp(is=1e-016 bf=100
va=80
+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0
af=1)
.model DBREAK D(bv=43 rs=1)
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28118_218
FIGURE 51. SPICE NET LIST
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18
FN7858.1
March 7, 2014
ISL28118M
Characterization vs Simulation Results
INPUT NOISE VOLTAGE
10
10
INPUT NOISE CURRENT
1
0.1
0.1
1
10
100
1k
10k
1
100
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE VOLTAGE (nV/√Hz)
VS = ±18V
INPUT NOISE CURRENT (fA/√Hz)
100
100
0.1
100k
10
1
0.1
0.1
1
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60 VS = ±15V
-80 RL = 1MΩ
-100
1m 0.01 0.1
PHASE
GAIN
1
10 100 1k 10k 100k 1M 10M100M 1G
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60 VS = ±15V
-80 RL = 1MΩ
-100
1m 0.01 0.1
FIGURE 54. CHARACTERIZED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
GAIN (dB)
40
VS = ±5V & ±15V
CL = 4pF
RL = 2k
VOUT = 100mVP-P
ACL = 100
30
20
ACL = 10
RF = 10kΩ, RG = 1kΩ
10
0
60
RF = 10kΩ, RG = 100Ω
50
40
30
20
0
RF = 0, RG = ∞
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 56. CHARACTERIZED CLOSED-LOOP GAIN vs FREQUENCY
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19
10 100 1k 10k 100k 1M 10M100M 1G
RF = 10kΩ, RG = 10Ω
ACL = 1000
RF = 10kΩ, RG = 100Ω
50
10
ACL = 1
-10
100
1
70
GAIN (dB)
60
GAIN
FIGURE 55. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY
RF = 10kΩ, RG = 10Ω
ACL = 1000
PHASE
FREQUENCY (Hz)
FREQUENCY (Hz)
70
100k
FIGURE 53. SIMULATED INPUT NOISE VOLTAGE
GAIN (dB)
GAIN (dB)
FIGURE 52. CHARACTERIZED INPUT NOISE VOLTAGE
10k
-10
VS = ±5V & ±15V
CL = 4pF
RL = 2k
VOUT = 100mVP-P
ACL = 100
ACL = 10
RF = 10kΩ, RG = 1kΩ
ACL = 1
RF = 0, RG = ∞
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 57. SIMULATED CLOSED-LOOP GAIN vs FREQUENCY
FN7858.1
March 7, 2014
ISL28118M
1
1
0
0
-1
-1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
Characterization vs Simulation Results (Continued)
-2
-3
RL = OPEN, 100k, 10k
-4
-5
RL = 1k
RL = 499k
RL = 100k
VS = ±15V
-6
CL = 4pF
-7 A = +1
V
-8 VOUT = 100mVp-p
-9
1k
100
RL = 49.9k
10k
100k
1M
-2
-3
-4
RL = OPEN, 100k, 10k
-5
-6
CL = 4pF
AV = +1
-8 VOUT = 100mVp-p
-7
-9
100
10M
1k
CMRR (dB)
CMRR (dB)
10 100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
140
130
120
110
100
90
80
70
60
50
40
30 VS = ±15V
20 SIMULATION
10
0
1m 0.01 0.1 1
6
2
0
0
-2
-2
-4
-4
30
40
50
60
TIME (µs)
70
80
90
100
FIGURE 62. CHARACTERIZED LARGE-SIGNAL 10V STEP RESPONSE
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20
10 100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
4
VOUT (V)
VOUT (V)
VS = ±15V
AV = 1
4
RL = 2k
CL = 4pF
2
20
10M
FIGURE 61. SIMULATED CMRR vs FREQUENCY
6
10
1M
FIGURE 59. SIMULATED GAIN vs FREQUENCY vs RL
FIGURE 60. CHARACTERIZED CMRR vs FREQUENCY
0
100k
FREQUENCY (Hz)
FIGURE 58. CHARACTERIZED GAIN vs FREQUENCY vs RL
-6
RL = 49.9k
10k
FREQUENCY (Hz)
140
130
120
110
100
90
80
70
60
50
40
30 VS = ±15V
20 SIMULATION
10
0
1m 0.01 0.1 1
RL = 1k
RL = 499k
RL = 100k
VS = ±15V
-6
0
10
20
30
40
50
60
TIME (µs)
70
80
90
100
FIGURE 63. SIMULATED LARGE-SIGNAL 10V STEP RESPONSE
FN7858.1
March 7, 2014
ISL28118M
Characterization vs Simulation Results (Continued)
100
40
20
60
40
0
-20
20
0
-20
-40
-40
-60
-60
-80
-80
-100
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VS = ±15V
AND
VS = ±5V
AV = 1
RL = 2k
CL = 4pF
80
VOUT (V)
60
VOUT (V)
100
VS = ±15V
AND
VS = ±5V
AV = 1
RL = 2k
CL = 4pF
80
-100
2.0
0
0.2
0.4
0.6
FIGURE 64. CHARACTERIZED SMALL-SIGNAL TRANSIENT RESPONSE
20V
OUTPUT VOLTAGE SWING (V)
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TIME (µs)
TIME (µs)
FIGURE 65. SIMULATED SMALL-SIGNAL TRANSIENT RESPONSE
VOH = 14.88V
10V
0V
-10V
VS = ±15V
RL = 10kΩ
-20V
0
VOL = -14.93V
0.5
1.0
TIME (ms)
1.5
2.0
FIGURE 66. SIMULATED OUTPUT VOLTAGE SWING
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21
FN7858.1
March 7, 2014
ISL28118M
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
March 7, 2014
FN7858.1
Updated Spice model netlist on page 18.
Changed POD:
FROM M8.118: Corrected lead width dimension in side view 1 from "0.25 - 0.036" to "0.25 - 0.36"
To M8.118B: Correct lead dimension in side view 2 from 0.15 - 0.05mm to 0.15+/-0.05mm
May 11, 2011
FN7858.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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22
FN7858.1
March 7, 2014
ISL28118M
Package Outline Drawing
M8.118B
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 3/12
3.0±0.10mm
5
A
D
8
4.9±0.20mm
DETAIL "X"
3.0±0.10mm
5
1.10 MAX
0.15±0.05mm
PIN# 1 ID
SIDE VIEW 2
1
2
B
0.65mm BSC
TOP VIEW
0.95 REF
0.86±0.05mm
H
GAUGE
PLANE
C
0.25
SEATING PLANE
0.23 - 0.36mm
0.08 M C A-B D
0.10 ± 0.05mm
3°±3°
0.10 C
0.53 ± 0.10mm
SIDE VIEW 1
DETAIL "X"
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
Submit Document Feedback
23
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
FN7858.1
March 7, 2014
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