DATASHEET

ISL28194
Data Sheet
Ultra-Small, 330nA and 1µA Single Supply,
Rail-to-Rail Input/Output (RRIO) Op Amps
The ISL28194 is micropower op amps optimized for
low-power applications. The part is designed for
single-supply operation from 1.8V to 5.5V, making it suitable
for applications with two 1.5V alkaline batteries. The
ISL28194 consumes typically 330nA of supply current . The
part feature rail-to-rail input and output swing (RRIO),
allowing for maximum battery usage.
January 14, 2014
Features
• Typical Supply Current 330nA
• Ultra-Low Single-Supply Operation Down to +1.8V
• Rail-to-Rail Input/Output Voltage Range (RRIO)
• Maximum 2mV Offset Voltage
• Maximum 60pA Input Bias Current
• 3.5kHz Gain Bandwidth Product
Equipped with a shutdown pin, the part draw typically 2nA
when off. The combination of small footprint, low power,
single supply, and rail-to-rail operation makes it ideally suited
for all battery operated device.
• ENABLE Pin Feature
Pinouts
Applications
ISL28194
(6 LD SOT-23)
TOP VIEW
OUT 1
V- 2
IN+ 3
• -40°C to +125°C Operation
• Pb-Free (RoHS Compliant)
• 2-Cell Alkaline Battery-Powered/Portable Systems
• Window Comparators
6 V+
+ -
FN6236.5
5 EN
4 IN-
• Threshold Detectors/Discriminators
• Mobile Communications
• Low Power Sensors
ISL28194
(6 LD 1.6X1.6X0.5 UTDFN)
TOP VIEW
6 V+
V- 2
5 EN
+ -
IN- 1
IN+ 3
4 OUT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2007, 2008, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL28194
Ordering Information
PART
NUMBER (Note 1)
PACKAGE
Tape and Reel
(Pb-Free)
PART
MARKING
ISL28194FHZ-T7 (Note 2)
PKG.
DWG. #
GABK (Note 4)
6 Ld SOT-23
P6.064A
ISL28194FRUZ-T7 (Note 3)
M3
6 Ld 1.6x1.6x0.5 UTDFN
L6.1.6x1.6A
ISL28194EVAL1Z
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. The part marking is located on the bottom of the part.
2
FN6236.5
January 14, 2014
ISL28194
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (V+, V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V
Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/μs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Resistance (Typical, Note 5)
θJA (°C/W)
6 Ld SOT-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
230
6 Ld UTDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
118
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite
Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, Unless Otherwise Specified.
Boldface limits apply over -40°C to +125°C.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
2
2.5
mV
mV
VOS
Input Offset Voltage
ΔV OS
--------------ΔT
Input Offset Voltage vs Temperature
IOS
Input Offset Current
-60
-100
10
60
100
pA
pA
IB
Input Bias Current
-80
-150
15
80
150
pA
pA
eN
Input Noise Voltage Peak-to-Peak
f = 0.1Hz to 10Hz
10
µVP-P
Input Noise Voltage Density
fo = 100Hz
265
nV/√Hz
-2
-2.5
-0.1
1.5
µV/°C
iN
Input Noise Current Density
fo = 100Hz
CMIR
Common Mode Input Range
Established by CMRR test
0
0.7
pA/√Hz
CMRR
Common-Mode Rejection Ratio
VCM = 0.5V to 3.5V
70
70
100
dB
VCM = 0V to 5V
55
90
dB
5
V
PSRR
Power Supply Rejection Ratio
V+ = 1.8V to 5.5V
70
70
100
dB
AVOL
Large Signal Voltage Gain
VO = 0.5V to 3.5V, RL = 100kΩ, RL = 10kΩ
75
115
dB
VOUT
Maximum Output Voltage Swing
RL terminated to V+/2
Output low, RL = 100kΩ
25
40
mV
Output low, RL = 10kΩ
50
70
mV
Output high, RL = 100kΩ
4.96
4.975
V
Output high, RL = 10kΩ
4.93
4.94
V
SR
Slew Rate
±1.5V, AV = 2
1.2
V/ms
GBW
Gain Bandwidth Product
AV = 101; RL = 10kΩ
3.5
kHz
IS,ON
Supply Current, Enabled
IS,OFF
Supply Current, Disabled
EN = 0.4V
ISC+
Short Circuit Sourcing Capability
RL = 10Ω
3
9
330
450
500
nA
2
20
50
nA
nA
11
mA
FN6236.5
January 14, 2014
ISL28194
Electrical Specifications
V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, Unless Otherwise Specified.
Boldface limits apply over -40°C to +125°C. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 6)
TYP
11
12
ISC-
Short Circuit Sinking Capability
RL terminated to V+/2
RL = 10Ω
V+
Supply Voltage Range
1.8
VINH
Enable Pin High Level
(V+)x(0.8)
VINL
Enable Pin Low Level
IENH
Enable Pin Input Current
VEN = 5V
IENL
Enable Pin Input Current
VEN = 0V
MAX
(Note 6)
UNIT
mA
5.5
V
ENABLE INPUT
V
0.4
V
30
150
200
nA
30
150
200
nA
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, Unless Otherwise Specified.
1
10
0
GAIN
-1
-10
CMRR (dB)
-3
-4
-5
-7
-8
-9
V+ = 5V
RL = 10k
AV = +1
VOUT = 10mVP-P
10
-30
-40
-50
100
1k
10k
-60
10
FIGURE 1. CLOSE LOOP GAIN vs FREQUENCY
100
1k
FREQUENCY (Hz)
10k
FIGURE 2. CMRR vs FREQUENCY
10
5
V+ = 5V
0 R = 10k
L
-10 AV = +1
VSOURCE = 1VP-P
-20
4
PSRRINPUT NOISE (µV)
3
-30
-40
-50
PSRR+
-60
2
1
0
-1
-2
V+ = 5V
RL = 10k
AV = 1000
-3
-70
-80
10
CMRR
-20
FREQUENCY (Hz)
PSRR (dB)
GAIN (dB)
-2
-6
V+ = 5V
RL = 10k
AV = +1
VSOURCE = 1VP-P
0
-4
100
1k
FREQUENCY (Hz)
FIGURE 3. PSRR vs FREQUENCY
4
10k
-5
0
1
2
3
4
5
6
TIME (s)
7
8
9
10
FIGURE 4. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
FN6236.5
January 14, 2014
ISL28194
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, Unless Otherwise Specified.
240
SUPPLY CURRENT (nA)
230
20
V+ = 5V
RL = INF
AV = +1
V+ = 5V
18 R = 10Ω
L
16 AV = +1
OUTPUT CURRENT (mA)
235
225
220
215
210
205
14
12
SINK
10
8
SOURCE
6
4
200
2
195
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
1.0
5.0
1.5
2.0
SUPPLY VOLTAGE (V)
2.5
3.0
3.5
4.0
4.5
FIGURE 5. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 6. OUTPUT SHORT CIRCUIT CURRENT
0.007
3
V+, V- = ±2.5V
RL = 10k
AV = +1
2
OUTPUT VOLTAGE (V)
INPUT
0.003
OUTPUT
0.001
-0.001
V+, V- = ±2.5V
RL = 10k
AV = +1
-0.003
-0.005
LARGE SIGNAL
1
0
-1
-2
VOUT = 10mVP-P
-0.007
-3.00E-04 -1.00E-04 1.00E-04
3.00E-04
5.00E-04 7.00E-04
-3
-2.0
9.00E-04
-10
0
10
FIGURE 7. SMALL SIGNAL TRANSIENT RESPONSE
5
5
4
EN PIN
3
OUTPUT
2
V+ = 5V
RL = 10k
AV = +1
VIN = 3.5V
1
0
0
2
4
6
8
TIME (ms)
FIGURE 9. ENABLE TO OUTPUT DELAY TIME
5
10
ENABLE/OUTPUT (V)
6
-2
30
40
50
60
70
80
FIGURE 8. LARGE SIGNAL TRANSIENT RESPONSE
6
-4
20
TIME (ms)
TIME (ms)
ENABLE/OUTPUT (V)
5.0
SUPPLY VOLTAGE (V)
0.005
OUTPUT VOLTAGE (mV)
(Continued)
EN PIN
V+ = 5V
RL = 10k
AV = +1
VIN = 3.5V
4
3
2
OUTPUT
1
0
-1.0
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TIME (µs)
FIGURE 10. DISABLE TO OUTPUT DELAY TIME
FN6236.5
January 14, 2014
ISL28194
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, Unless Otherwise Specified.
2.6
ENABLE TO OUTPUT DELAY (ms)
70
ENABLE THRESHOLD (V)
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
60
50
40
30
20
10
0
5.0
1.5
2.0
2.5
SUPPLY VOLTAGE (V)
3.5
4.0
4.5
5.0
FIGURE 12. ENABLE TO OUTPUT DELAY TIME vs SUPPLY
VOLTAGE
50000
450
N = 1000
45000
40000
SUPPLY CURRENT (nA)
DISABLE TO OUTPUT DELAY (ns)
3.0
SUPPLY VOLTAGE (V)
FIGURE 11. ENABLE THRESHOLD VOLTAGE vs SUPPLY
VOLTAGE
35000
30000
25000
20000
15000
10000
MAX
400
350
MEDIAN
300
250
MIN
5000
200
-40
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-20
0
SUPPLY VOLTAGE (V)
35
40
60
80
100
120
FIGURE 14. SUPPLY CURRENT ENABLED vs
TEMPERATURE, V+ = 5V, V- = 0V
30
N = 1000
N=1000
N
= 1000
30
25
25
20
15
IBIAS - (pA)
MAX
20
MEDIAN
10
5
0
-40
20
TEMPERATURE (°C)
FIGURE 13. ENABLE LOW TO OUTPUT TURN-OFF TIME vs
SUPPLY VOLTAGE
IBIAS + (pA)
(Continued)
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 15. IBIAS + vs TEMPERATURE V+ = 5V
6
15
MEDIAN
10
5
MIN
0
MIN
-20
MAX
-5
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 16. BIAS vs TEMPERATURE, V+ = 2.4V
FN6236.5
January 14, 2014
ISL28194
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, Unless Otherwise Specified.
30
-30
N = 1000
N = 1000
-50
20
MAX
-70
VOS (µV)
IOS (pA)
10
0
MEDIAN
-10
MEDIAN VIN = 2.5V
-90
-110
-130
-20
-20
0
20
40
60
MEDIAN VIN = 4.7V
-150
MIN
-30
-40
80
100
-170
-40
120
-20
0
FIGURE 17. IOS vs TEMPERATURE, V+ = 5V
0
98
MEDIAN VIN = 1.5V
-80
CMRR (dB)
VOS (µV)
80
100
120
N = 1000
96
-60
-100
-120
-140
MEDIAN VCM: +1.0V TO -2.0V
94
92
90
MEDIAN VCM: +5.1V TO -0.1V
MEDIAN VIN = 0.3V
-160
88
86
-180
-20
0
20
40
60
80
100
84
-40
120
-20
0
TEMPERATURE (°C)
FIGURE 19. VOS vs TEMPERATURE, V+ = 1.8V,VIN = 1.5V, 0.3V
140
118
MAX
120
110
120
N = 1000
114
AVOL (dB)
90
80
100
116
MEDIAN
100
20
40
60
80
TEMPERATURE (°C)
FIGURE 20. CMRR vs TEMPERATURE, VCM = +1.0V TO -2.0V,
+5.1V TO -0.1V
N = 1000
130
PSRR (dB)
60
100
-40
MIN
MEDIAN RL = 100k
112
110
MEDIAN RL = 10k
70
108
60
50
-40
40
FIGURE 18. VOS vs TEMPERATURE, V+ = 5V VIN = 2.5V, 4.7V
N = 1000
-200
-40
20
TEMPERATURE (°C)
TEMPERATURE (°C)
-20
(Continued)
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 21. PSRR vs TEMPERATURE, V+, V- = ±0.9V TO ±2.5V
7
106
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 22. AVOL vs TEMPERATURE, V+ = 5V
FN6236.5
January 14, 2014
ISL28194
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, Unless Otherwise Specified.
94
92
88
4.985
VOUT (V)
84
4.965
4.960
78
4.955
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
4.944
4.942
-20
0
20
40
60
80
TEMPERATURE (°C)
MAX
VOUT (mV)
4.938
MEDIAN
4.934
MAX
25
MEDIAN
20
MIN
MIN
4.930
120
N = 1000
30
4.936
100
FIGURE 24. VOUT HIGH vs TEMPERATURE, V+ = 5V, RL = 100k
35
4.932
MIN
4.950
-40
120
N = 1000
4.940
MEDIAN
4.970
80
FIGURE 23. AVOL vs TEMPERATURE, V+ = 1.8V
VOUT (V)
4.975
82
76
MAX
4.980
MEDIAN RL = 10k
86
N = 1000
4.990
MEDIAN RL = 100k
90
AVOL (dB)
4.995
N = 1000
(Continued)
15
4.928
4.926
-40
-20
0
20
40
60
80
100
10
120
-40
-20
0
FIGURE 25. VOUT HIGH vs TEMPERATURE, V+ = 5V, RL = 10k
57
56
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 26. VOUT LOW vs TEMPERATURE,V+, V- = ±2.5V,
RL = 100k
N = 1000
55
VOUT (mV)
54
MAX
53
52
MEDIAN
51
50
MIN
49
48
47
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 27. VOUT LOW vs TEMPERATURE V+, V- = ±2.5V, RL = 10
8
FN6236.5
January 14, 2014
ISL28194
Pin Descriptions
ISL28194
ISL28194
(6 LD SOT-23) (6 LD ΜTDFN) PIN NAME
EQUIVALENT
CIRCUIT
DESCRIPTION
1
4
OUT_A
Circuit 3
Amplifier output
2
2
V-
Circuit 4
Negative power supply
3
3
IN+
Circuit 1
Amplifier non-inverting input
4
1
IN-
Circuit 1
Amplifier inverting input
5
5
EN
Circuit 2
Amplifier enable pin; Logic “1” selects the enabled state, Logic “0” selects the
disabled state.
6
6
V+
Circuit 4
Positive power supply
V+
V+
IN-
100Ω
LOGIC
PIN
IN+
CIRCUIT 1
CIRCUIT 2
CAPACITIVELY
COUPLED
ESD CLAMP
OUT
V-
V-
V-
V+
V+
VCIRCUIT 3
CIRCUIT 4
AC Test Circuits
1k
5V
-
VOUT
+
VOUT
+
10k
VIN
5V
10
-
VIN
EN
10k
EN
VCM = V+/2
V+/2
FIGURE 28. TEST CIRCUIT FOR AV = +1
Applications Information
Introduction
The ISL28194 is a CMOS rail-to-rail input and output (RRIO)
micropower operational amplifier. This device is designed to
operate from single supply (1.8V to 5.5V) and has an input
common mode range that extends to the positive rail and to the
negative supply rail for true rail-to-rail performance. The CMOS
output can swing within tens of millivolts to the rails. Featuring
worst-case maximum supply current of 0.5µA, this amplifier is
ideally suited for solar and battery-powered applications.
Input Protection
All input terminals have internal ESD protection diodes to
both positive and negative supply rails, limiting the input
voltage to within one diode beyond the supply rails. The
ISL28194 has a maximum input differential voltage that
includes the rails (-V -0.5V to +V +0.5V).
9
FIGURE 29. TEST CIRCUIT FOR AV = +101
Rail-to-Rail Output
A pair of complementary MOSFET devices are used to
achieve the rail-to-rail output swing. The NMOS sinks current
to swing the output in the negative direction. The PMOS
sources current to swing the output in the positive direction.
The ISL28194 will typically swing to within 40mV or less to
either rail with a 100kΩ load (reference Figures 24 and 26).
Enable/Disable Feature
This part offers an EN pin that enables the device when pulled
high. The enable threshold is referenced to the -V terminal and
has a level proportional to the total supply voltage (reference
Figure 11 for EN threshold vs supply voltage). The enable
circuit has a delay time that changes as a function of supply
voltage. Figures 12 and 13 show the effect of supply voltage
on the enable and disable times. For supply voltages less
than 3V, it is recommended that the user account for the
increase enable/disable delay time.
FN6236.5
January 14, 2014
ISL28194
In the disabled state (output in a high impedance state), the
supply current is reduced to typical of only 2nA. By disabling
the devices, multiple parts can be connected together as a
MUX. In this configuration, the outputs are tied together in
parallel and a channel can be selected by the EN pin. The
EN pin should never be left floating. The EN pin should be
connected directly to the V+ supply when not in use.
The loading effects of the feedback resistors of the disabled
amplifier must be considered when multiple amplifier outputs
are connected together.
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power-supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all applications
to determine if power supply voltages, load conditions, or
package type need to be modified to remain in the safe
operating area. These parameters are related in Equation 1:
T JMAX = T MAX + ( θ JA xPD MAXTOTAL )
(EQ. 1)
Proper Layout Maximizes Performance
where:
To achieve the maximum performance of the high input
impedance, care should be taken in the circuit board layout.
The PC board surface must remain clean and free of moisture
to avoid leakage currents between adjacent traces. Surface
coating of the circuit board will reduce surface moisture and
provide a humidity barrier, reducing parasitic resistance on the
board. When input leakage current is a concern, the use of
guard rings around the amplifier inputs will further reduce
leakage currents. Figure 30 shows a guard ring example for a
unity gain amplifier that uses the low impedance amplifier
output at the same voltage as the high impedance input to
eliminate surface leakage. The guard ring does not need to be
a specific width, but it should form a continuous loop around
both inputs. For further reduction of leakage currents,
components can be mounted to the PC board using Teflon
standoff insulators.
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
V OUTMAX
PD MAX = 2*V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------RL
(EQ. 2)
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Supply voltage (Magnitude of V+ and V-)
• IMAX = Maximum supply current of 1 amplifier
• VOUTMAX = Maximum output voltage swing of the
application
V+
HIGH IMPEDANCE INPUT
• PDMAX for each amplifier can be calculated as shown in
Equation 2:
• RL = Load resistance
IN
FIGURE 30. GUARD RING EXAMPLE FOR UNITY GAIN
AMPLIFIER
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN6236.5
January 14, 2014
ISL28194
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
A
E
6
L6.1.6x1.6A
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
4
MILLIMETERS
D
PIN 1
REFERENCE
2X
0.15 C
1
2X
A
B
3
MIN
NOMINAL
MAX
NOTES
A
0.45
0.50
0.55
-
A1
-
-
0.05
-
A1
TOP VIEW
e
1.00 REF
4
6
L
CO.2
0.15
0.20
0.25
-
D
1.55
1.60
1.65
4
D2
0.40
0.45
0.50
-
E
1.55
1.60
1.65
4
E2
0.95
1.00
1.05
-
0.50 BSC
e
3
L
1
b 6X
0.10 M C A B
E2
0.25
0.30
0.35
Rev. 1 6/06
NOTES:
1. Dimensions are in MM. Angles in degrees.
BOTTOM VIEW
DETAIL A
0.10 C
-
b
DAP SIZE 1.30 x 0.76
6X
0.127 REF
A3
0.15 C
D2
SYMBOL
2. Coplanarity applies to the exposed pad as well as the terminals.
Coplanarity shall not exceed 0.08mm.
3. Warpage shall not exceed 0.10mm.
4. Package length/package width are considered as special
characteristics.
0.08 C
5. JEDEC Reference MO-229.
A3
SIDE VIEW
C
SEATING
PLANE
6. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
0.127±0.008
0.127 +0.058
-0.008
TERMINAL THICKNESS
A1
DETAIL A
0.25
0.50
1.00
0.45
1.00
2.00
0.30
1.25
LAND PATTERN
11
6
FN6236.5
January 14, 2014
ISL28194
Package Outline Drawing
P6.064A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
0.95
D
0.08-0.20
A
5
6
4
PIN 1
INDEX AREA
2.80
3
1.60
3
0.15 C D
2x
1
(0.60)
3
2
0.20 C
2x
0.40 ±0.05
B
5
SEE DETAIL X
3
0.20 M C A-B
D
TOP VIEW
2.90
5
END VIEW
10° TYP
(2 PLCS)
0.15 C A-B
2x
H
1.14 ±0.15
C
SIDE VIEW
0.10 C
0.05-0.15
1.45 MAX
SEATING PLANE
DETAIL "X"
(0.25) GAUGE
PLANE
0.45±0.1
4
(0.60)
(1.20)
NOTES:
(2.40)
(0.95)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
This dimension is measured at Datum “H”.
6.
Package conforms to JEDEC MO-178AA.
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
12
FN6236.5
January 14, 2014
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