Application Note 1569 ISL28233MSOPEVAL2Z Evaluation Board User’s Guide Introduction • Banana Jack Connectors for Power Supply and VREF Inputs The ISL28233MSOPEVAL2Z Evaluation Board is designed to evaluate the performance of the ISL28233 Chopper Stabilized op amp. The evaluation board contains the circuitry needed to evaluate the high performance of the ISL28233 amplifier. The ISL28233 chopper stabilized rail-to-rail dual op amp features a low 8µV maximum VOS over-temperature and a 0.1Hz 1/f noise corner frequency enabling very high gain single-stage DC amplifiers that can operate from single cell batteries while consuming only 20µA of current. The ISL28233MSOPEVAL2Z evaluation board can be configured as a precision high-gain (G = 10,000V/V) differential amplifier and demonstrates the level of performance possible with this type of amplifier while operating from battery voltages as low as 1.65V. • BNC Connectors for Op Amp Input and Output Terminals • Convenient PCB Pads for Op Amp Input/Output Impedance Loading. Power Supplies (Figure 2) External power connections are made through the V+, V-, VREF, and GND connections on the evaluation board. The circuit can operate from a single supply or from dual supplies. For single supply operation, the V- and GND pins are tied together to the negative or ground reference of the power supply. For split supplies, V+ and V- terminals connect to their respective supply terminals. De-coupling capacitors C2 and C4 provide low-frequency power-supply filtering, while additional capacitors, C3 and C5, which are connected close to the part, filter out high frequency noise. Anti-reverse diode D1 (optional) protects the circuit in the momentary case of accidentally reversing the power supplies to the evaluation board. The VREF pin can be connected to ground to establish a ground referenced input for split supply operation, or can be externally set to any reference level for single supply operation. Reference Documents • ISL28233 Data Sheet, FN7692 Evaluation Board Key Features • Single Supply Operation: +1.65V to +5.5V • Dual Supply Operation: ±0.825V to ±2.75V • Singled-Ended or Differential Input Operation with High Gain (G = 10,000V/V) • External VREF Input R13/R23 1MΩ IN IN- R11/R24 V+ 8 INA- 2 INB- 6 - 100Ω R14/R21 IN+ IN + VCM VREF VREF GND INA+ 3 INB+ 5 1/7 ISL28233 OUT R26/R27 + 100Ω 0Ω V- 4 R18/R19 100kΩ R28/R29 OPEN OPEN FIGURE 1. BASIC DIFFERENTIAL AMPLIFIER CONFIGURATION October 5, 2010 AN1569.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1569 1 1 The output (Figure 4) also has additional resistor and capacitor placements for filtering and loading. Amplifier Configuration (Figure 3) The schematic of the op amp input stage with the components supplied is shown in Figure 3, with a closed loop gain of 10,000. The circuit implements a Hi-Z differential input with unbalanced common mode impedance. The differential amplifier gain is expressed in Equation 1: V OUT = ( V IN+ – V IN- ) • ( R F ⁄ R IN ) + V REF NOTE: Operational amplifiers are sensitive to output capacitance and may oscillate. In the event of oscillation, reduce output capacitance by using shorter cables, or add a resistor in series with the output. C6 IN-A J1 R1 R4 R11 OPEN R13 0 100 1M DNP DNP FIGURE 2. POWER SUPPLY CIRCUIT FROM OUTA (EQ. 1) For single-ended input with an inverting gain G = -10,000V/V, the IN+ input is grounded and the signal is supplied to the IN- input. VREF must be connected to a reference voltage between the V+ and V- supply rails. For non-inverting operation with G = 10,001V/V, the IN- input is grounded and the signal is supplied to the IN+ input. The non-inverting gain is strongly dependent on any resistance from IN- to GND. For good gain accuracy, a 0Ω resistor should be installed on the empty R5 pad. TO INA - IN+A R14 J2 R2 TO INA + 100 DNP R15 R18 DNP 100k VREF FIGURE 3. INPUT STAGE R26 OUT_A J12 0 C6 OUT A DNP 0.01µF R5 0.01µF OPEN R28 1 TO DUT C5 1µF 2 CLOSE C5 Component pads are included to enable a variety of user-selectable circuits to be added to the amplifier inputs, the VREF input, outputs and the amplifier feedback loops. C8 3 D1 (Figures 3 and 4) A voltage divider (Figure 3, R18 and R15) can be added to establish a power supply-tracking common mode reference using the VREF input. The inverting and non-inverting inputs have additional resistor placements for adding input attenuation, or to establish input DC offsets through the VREF pin. 1 C4 1µF 0 R31 2 1 0 C2 1 R16 2 1 2 1 2 VREF J14 3 J13 J8 3 J12 V+ 1 J6 J11 User-Selectable Options V- FIGURE 4. OUTPUT STAGE TABLE 1. ISL28233MSOPEVAL2Z COMPONENTS PARTS LIST DEVICE # DESCRIPTION COMMENTS C2, C4 CAP, SMD, 1206, 1µF, 50V, 10%, X7R, ROHS Power Supply Decoupling C3, C5 CAP, SMD, 0603, 0.1µF, 50V, 10%, X7R, ROHS Power Supply Decoupling CAP, SMD, 0603, DNP-PLACE HOLDER, ROHS User selectable capacitors - not populated R11, R14, R21, R24 RESISTOR, SMD, 0603, 100Ω, 1%, 1/16W, ROHS Gain Setting Resistor R13, R23 RESISTOR, SMD, 0603, 10MΩ, 1%, 1/16W, ROHS Gain Setting Feedback Resistor C1, C6, C7, C8, C9, C10 R1, R2, R3, R5, R6, R7, R8, R10, RESISTOR, SMD, 0603, DNP-PLACE HOLDER, ROHS R12, R15, R17, R20, R22, R28, R29, R30, R32, R34, R35, R36 D1 40V SERIES SCHOTTKY BARRIER DIODE U1 (ISL28233FUZ) User selectable resistors - not populated Reverse Power Protection ISL28233FUZ, IC-RAIL-TO-RAIL OP AMP, MSOP, ROHS 2 AN1569.1 October 5, 2010 Application Note 1569 ISL28233MSOPEVAL2Z Top View Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 3 AN1569.1 October 5, 2010 ISL28233MSOPEVAL2Z Schematic Diagram J11 3 1 1 IN-B 1 2 4 3 J3 5 1 R7 2 DNP IN+B 4 3 J4 5 R15 DNP 1 2 1 R8 DNP 2 21 R18 100k 21 R19 100k 21 R22 DNP 2 3 4 DNP 1 OPEN R28 2 1 J24 DNP 2 1 OUT B 1 2 3 4 2 1 2 DNP 2 2 2 1 OPEN R27 0 VREF 1 J23 J22 2 C7 1 R21 100 2 OPEN R29 1 DNP 5 R36 5 1 6 1 OPEN DNP 6 2 0 R20 4 7 7 J15 5 2 1 4 DNP 8 100 1 3 8 DNP 2 3 U1 MSOP8 GENERIC PACK R24 R35 J21 J20 2 2 1 1M C10 21 2 0 1 2 2 R25 DNP 1 R30 DNP 2 1 DNP J18 J17 2 R6 1 1 R5 2 R3 DNP 4 3 4 3 1 2 R23 DNP OPEN R26 OUT A 1 2 1 OPEN R14 2 1 100 1 R34 1 1 2 2 21 DNP IN- 2 R2 2 1M C1 100 R32 1 IN+ 1 1 R13 2 2 1 2 J2 5 21 1 IN+A 2 DNP 0 R11 R12 DNP NODE 1 2 21 DNP 2 1 OUT 2 1 R4 OUT 1 1 R1 2 2 2 1 2 J1 5 R10 1 1 1 1 IN-A NODE 1 R17 IN+ J19 IN- C6 C8 2 2 0.01µ F 1 0.01µ F J16 5 Application Note 1569 TO DUT C5 C9 1 CLOSE C3 2 D1 1µF 2 4 1µF 1 C4 0 R31 2 1 1 1 2 0 C2 1 R16 J14 2 VREF J13 2 J12 J8 V+ 3 1 J6 V3 AN1569.1 October 5, 2010