CPLL58 4240 4240

M
ICROWAVE
A Division of Crystek Corporation
CPLL58-4240-4240
0.582" × 0.800" SMD
Features
4.240 GHz
Standard 3 Wire Interface
Small layout 0.582" × 0.8"
Applications
Digital Radio Equipment
Fixed Wireless Access
Satellite Communications Systems
Base Stations
Personal Communications Systems
Portable Radios
Test Instruments
Wireless Infrastructure
The CPLL58 is a complete PLL/Synthesizer needing only an external frequency reference and supply
voltages for the internal PLL (phase lock loop) and VCO (voltage controlled oscillator). The Crystek
CPLL58 is programmed using a standard three line interface (Data, Clock and Load Enable).
The CPLL58 family has been initially released to cover 1 GHz to 5 GHz in bands. It is housed in a
compact 0.582-in. × 0.8-in. × 0.15-in. SMD package which saves board space. Typical phase noise at
4 GHz is -90 dBc/Hz at 10 kHz offset with 0 dBm minimum output power.
Rev D
Page 1 of 7
CRYSTEK
CORPORATION
12730 Commonwealth Drive • Fort Myers, Florida 33913
Phone: 239-561-3311 • 800-237-3061
Fax: 239-561-1025 • www.crystek.com
M
ICROWAVE
A Division of Crystek Corporation
PERFORMANCE SPECIFICATION
CPLL58-4240-4240
0.582" × 0.800" SMD
MIN
TYP
MAX
UNITS
Frequency Range:
4.240
GHz
Step Size:
2500
kHz
1
msec
Settling Time, to within ± 1kHz (Freq. step < 25MHz):
Output Power:
0
+3.0
+6.0
dBm
@1kHz offset
-75
-70
dBc/Hz
@10kHz offset
-90
-85
dBc/Hz
@100kHz offset
-105
-100
dBc/Hz
@1MHz offset
-135
-130
dBc/Hz
Output Phase Noise: (See Plot Below)
Power Supply:
V1=VCO Supply
4.75
5.0
5.25
Volts
V2=PLL Supply
2.7
3.0
3.3
Volts
Supply Current:
I1=VCO Input Current
50
mA
I2=PLL Input Current
25
mA
Spurious Suppression
dBc
PFDSpur
-70
-60
dBc
Reference Feedthru
-80
-70
dBc
2nd
-15
-10
dBc
Reference Frequency
10
Harmonic Suppression:
RF Output Level
-5
Input Reference Level
0.8
Input Impedance
RF Output Impedance
Operating Temperature Range:
-40
0
MHz
+5
dBm
V2
Vp-p
100k
Ohm
50
Ohm
+85
°C
0.6
Volts
Logic Inputs (Clock, Data, and LE):
Input “High” Voltage
1.4
Input “Low” Voltage
Locked Detector (LD):
Locked
Un-Locked
Rev D
1.4
Volts
0.4
Volts
Page 2 of 7
CRYSTEK
CORPORATION
12730 Commonwealth Drive • Fort Myers, Florida 33913
Phone: 239-561-3311 • 800-237-3061
Fax: 239-561-1025 • www.crystek.com
M
ICROWAVE
A Division of Crystek Corporation
Rev D
CPLL58-4240-4240
0.582" × 0.800" SMD
Page 3 of 7
CRYSTEK
CORPORATION
12730 Commonwealth Drive • Fort Myers, Florida 33913
Phone: 239-561-3311 • 800-237-3061
Fax: 239-561-1025 • www.crystek.com
M
ICROWAVE
A Division of Crystek Corporation
0.582" × 0.800" SMD
GND
V1
GND
REF
GND
0.00
V2 [Pin1]
BOTTOM VIEW
0.200
0.280
0.360
0.440
0.520
0.600
0.800
TOP VIEW
CPLL58-4240-4240
0.00
GND
0.331
GND
GND
0.411
GND
GND
CLK
LE
0.582
RF
GND
GND
GND
GND
0.251
LD
0.171
DATA
CRYSTEK
CPLL58
4240-4240
YYWW
LE
= Load Enable, CMOS Input
DATA = Serial Data Input
CLK = Clock
LD
= Lock Detect
REF = Reference Input
V1
= Analog Supply Input (VCO)
V2
= Digital Supply Input (PLL)
RF
= RF Output
TOP ORIENTATION MARK
0.052
0.150
0.000
0.052
0.000
0.000
Pad Detail
RECOMMENDED REFLOW SOLDERING PROFILE
Ramp-Up
3°C/Sec Max.
Critical Temperature Zone
TEMPERATURE
260°C
Ramp-Down
6°C/Sec.
217°C
200°C
150°C
Preheat
180 Secs. Max.
90 Secs. Max.
8 Minutes Max.
260°C for
10 Secs. Max.
Rev D
Page 4 of 7
CRYSTEK
CORPORATION
12730 Commonwealth Drive • Fort Myers, Florida 33913
Phone: 239-561-3311 • 800-237-3061
Fax: 239-561-1025 • www.crystek.com
M
ICROWAVE
A Division of Crystek Corporation
CPLL58-4240-4240
0.582" × 0.800" SMD
ENVIRONMENTAL COMPLIANCE
Parameter
Conditions
Mechanical Shock
MIL-STD-883, Method 2002
Mechanical Vibration
MIL-STD-883, Method 2007
Solderability
MIL-STD-883, Method 1014
Resistance to Solvents
MIL-STD-883, Method 2016
Programming Guide for CPLL58-XXXX
Introduction
The CPLL58 uses a simple 3 wire interface to program four internal registers. See Figure 1.
t3
t4
CLOCK
t1
DATA
DB23 (MSB)
t2
DB22
DB2
DB1(CONTROL
BIT C2)
DB0(LSB)
(CONTROL BIT C1)
t6
LE
t5
LE
Figure 1. Timing Diagram
There are four 24 bit registers that need to be programmed. Which register is written into is simply
controlled by Control Bits C1 and C2. Table I summarizes the Truth Table for Control Bits C1 and C2.
Control Bits
C2
C1
Data Latch
0
0
R Counter
0
1
N Counter (A and B)
1
0
Function Latch (Including Prescaler)
1
1
Initialization Latch
Table I. C2, C1 Truth Table
Rev D
Page 5 of 7
CRYSTEK
CORPORATION
12730 Commonwealth Drive • Fort Myers, Florida 33913
Phone: 239-561-3311 • 800-237-3061
Fax: 239-561-1025 • www.crystek.com
M
ICROWAVE
A Division of Crystek Corporation
CPLL58-4240-4240
0.582" × 0.800" SMD
Table II shows the details of the four 24 bit registers.
LOCK DETECT
PRECISION
REFERENCE COUNTER LATCH
RESERVED
TEST MODE
BITS
ANTIBACKLASH
WIDTH
CONTROL
BITS
14-BIT REFERENCE COUNTER
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
0
0
LDP
T2
T1
ABP2
ABP1
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
C2(0)
C1(0)
CP GAIN
N COUNTER LATCH
RESERVED
DB23
DB22
13-BIT COUNTER
CONTROL
BITS
6-BIT COUNTER
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
G1
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A6
A5
A4
A3
A2
A1
C2(0)
C1(1)
MUXOUT CONTROL
FASTLOCK
MODE
FASTLOCK
ENABLE
CP THREESTATE
PD POLARITY
POWER-DOWN
1
COUNTER
RESET
POWER-DOWN
2
FUNCTION LATCH
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
P2
P1
PD2
CP16
CP15
CP14
CP13
CP12
CP11
TC4
TC3
TC2
TC1
F5
F4
F3
F2
M3
M2
M1
PD1
F1
C2(1)
C1(0)
PRESCALER
VALUE
CURRENT SETTING2
CURRENT SETTING 1
TIMER COUNTER CONTROL
CONTROL
BITS
FASTLOCK
MODE
FASTLOCK
ENABLE
CP THREESTATE
PD POLARITY
POWER-DOWN
1
COUNTER
RESET
POWER-DOWN
2
INITIALIZATION LATCH
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
P2
P1
PD2
CP16
CP15
CP14
CP13
CP12
CP11
TC4
TC3
TC2
TC1
F5
F4
F3
F2
M3
M2
M1
PD1
F1
C2(1)
C1(1)
PRESCALER
VALUE
CURRENT SETTING2
CURRENT SETTING 1
TIMER COUNTER CONTROL
MUXOUT CONTROL
CONTROL
BITS
Table II. Latch Summary
When using the CPLL58 family in a synthesizer application, all four 24 bit registers need to be written
into after power-up. After writing all four latches the first time, subsequent frequency step changes can
be accomplished by changing the N Counter Latch only.
Specifications subject to change without notice.
Rev D
Page 6 of 7
CRYSTEK
CORPORATION
12730 Commonwealth Drive • Fort Myers, Florida 33913
Phone: 239-561-3311 • 800-237-3061
Fax: 239-561-1025 • www.crystek.com
M
ICROWAVE
A Division of Crystek Corporation
CPLL58-4240-4240
0.582" × 0.800" SMD
Programming Crystek p/n: CPLL58-4240-4240
The following is specific programming for CPLL58-4240-4240 (4.240 GHz fixed
frequency with 2500 kHz Step Size and 10 MHz input reference frequency).
Program all four registers with the following:
R Counter Latch: 000010 H
N Counter Latch: 003501 H
Function Latch: 9F8083 H
The above values will set the CPLL58-4240-4240 to 2.240 GHz
Rev D
Page 7 of 7
CRYSTEK
CORPORATION
12730 Commonwealth Drive • Fort Myers, Florida 33913
Phone: 239-561-3311 • 800-237-3061
Fax: 239-561-1025 • www.crystek.com
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