DATASHEET ICS9DBL411 Four Output Differential Fanout Buffer for PCI Express Gen 1 & 2 Recommended Application: Features/Benefits: PCI-Express fanout buffer • Low power differential fanout buffer for PCIExpress and CPU clocks • 20-pin MLF or TSSOP packaging Output Features: General Description: • 4 - low power differential output pairs • Individual OE# control of each output pair The ICS9DBL411 is a 4 output lower power differential buffer. Each output has its own OE# pin. It has a maximum input frequency of 400 MHz. Key Specifications: • Output cycle-cycle jitter < 25ps additive • Output to output skew: < 50ps Power Groups Pin Number (TSSOP) VDD GND 9,18 10,17 4 5 Description DIF(3:0) Analog VDD & GND Pin Number (MLF) VDD GND 6,15 7,14 1 2 Description DIF(3:0) Analog VDD & GND Funtional Block Diagram 4 OE#(3:0) 4 DIF_INT STOP LOGIC DIF_INC IDTTM/ICSTM Four Output Differential Buffer for PCI Express DIF_LPR(3:0) 1250A—07/31/07 1 ICS9DBL411 Four Output Differential Buffer for PCI Express Advance Information Pin Configuration 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ICS9DBL411 OE0# DIF_INC DIF_INT VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR VDD_IO GND DIF0T_LPR DIF0C_LPR VDD_IO GND OE1# DIF1T_LPR DIF1C_LPR OE2# DIF2T_LPR DIF2C_LPR DIF0C_LPR DIF0T_LPR OE0# DIF_INC DIF_INT 20-pin TSSOP 20 19 18 17 16 7 8 9 10 15 14 13 12 11 VDD_IO GND OE1# DIF1T_LPR DIF1C_LPR OE2# VDD_IO 6 DIF2T_LPR 9DBL411 DIF2C_LPR 1 2 3 4 5 GND VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR 20-pin MLF IDTTM/ICSTM Four Output Differential Buffer for PCI Express 1250A—07/31/07 2 ICS9DBL411 Four Output Differential Buffer for PCI Express Advance Information TSSOP Pin Description PIN # (TSSOP) PIN NAME 1 OE0# 2 3 4 5 DIF_INC DIF_INT VDDA GNDA 6 OE3# 7 8 9 10 11 12 DIF3C_LPR DIF3T_LPR VDD_IO GND DIF2C_LPR DIF2T_LPR 13 OE2# 14 15 DIF1C_LPR DIF1T_LPR 16 OE1# 17 18 19 20 GND VDD_IO DIF0C_LPR DIF0T_LPR PIN TYPE IN IN IN PWR GND IN OUT OUT PWR GND OUT OUT IN OUT OUT IN GND PWR OUT OUT DESCRIPTION Output Enable for DIF0 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement side of differential input clock True side of differential input clock 3.3V Power for the Analog Core Ground for the Analog Core Output Enable for DIF3 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Power supply for low power differential outputs, nominal 1.05V to 3.3V Ground pin Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF2 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF1 output. Control is as follows: 0 = enabled, 1 = Low-Low Ground pin Power supply for low power differential outputs, nominal 1.05V to 3.3V Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) IDTTM/ICSTM Four Output Differential Buffer for PCI Express 1250A—07/31/07 3 ICS9DBL411 Four Output Differential Buffer for PCI Express Advance Information MLF Pin Description PIN # (MLF) 1 2 VDDA GNDA PWR GND 3 OE3# IN 4 DIF3C_LPR OUT 5 DIF3T_LPR OUT 6 7 VDD_IO GND PWR GND 8 DIF2C_LPR OUT 9 DIF2T_LPR OUT 10 OE2# 11 DIF1C_LPR OUT 12 DIF1T_LPR OUT 13 OE1# 14 15 GND VDD_IO GND PWR 16 DIF0C_LPR OUT 17 DIF0T_LPR OUT 18 OE0# IN 19 20 DIF_INC DIF_INT IN IN PIN NAME PIN TYPE IN IN DESCRIPTION 3.3V Power for the Analog Core Ground for the Analog Core Output Enable for DIF3 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Power supply for low power differential outputs, nominal 1.05V to 3.3V Ground pin Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF2 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF1 output. Control is as follows: 0 = enabled, 1 = Low-Low Ground pin Power supply for low power differential outputs, nominal 1.05V to 3.3V Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF0 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement side of differential input clock True side of differential input clock IDTTM/ICSTM Four Output Differential Buffer for PCI Express 1250A—07/31/07 4 ICS9DBL411 Four Output Differential Buffer for PCI Express Advance Information Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS Maximum Supply Voltage VDDxxx Supply Voltage Maximum Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply Maximum Input Voltage VIH 3.3V LVCMOS Inputs Minimum Input Voltage VIL Any Input MIN 0.99 MAX V 1,7 3.8 V 1,7 4.6 V 1,7,8 V 1,7 Vss - 0.5 Storage Temperature Ts - -65 Input ESD protection ESD prot Human Body Model 2000 UNITS Notes 4.6 150 ° C 1,7 V 1,7 Notes Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Ambient Operating Temp Tambient - 0 70 °C 1 Supply Voltage VDDxxx Supply Voltage 3.135 3.465 V 1 Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply 0.99 3.465 V 1 Input High Voltage VIHSE Single-ended inputs 2 VDD + 0.3 V 1 Input Low Voltage VILSE Single-ended inputs VSS - 0.3 0.8 V 1 Input High Voltage VIHDIF Differential inputs 600 1.15 V 1 Input Low Voltage VILDIF Differential inputs VSS - 0.3 300 V 1 Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 2 Input Leakage Current IIN VIN = VDD , VIN = GND -5 5 uA 1 IDD_3.3V 3.3V supply 25 mA 1 Operating Supply Current IDD_IO+100M VDD_IO supply @ fOP = 100MHz 15 mA 1 IDD_IO_400M VDD_IO supply @ fOP = 400MHz 54 mA 1 IDD_SB33 3.3V supply, Input stopped 25 mA 1 IDD_SBIO 0.8V IO supply, Input stopped 0.1 mA 1 Input Frequency Fi VDD = 3.3 V 33 400 MHz 2 Pin Inductance Lpin 7 nH 1 CIN Logic Inputs 1.5 5 pF 1 COUT Output pin capacitance Number of clocks to enable or disable output from assertion/deassertion of OE# Output enable after OE# de-assertion 6 pF 1 3 periods 1 10 ns 1 5 ns 1 5 ns 1 Standby Current Input Capacitance OE# latency T OE#LAT Tdrive_OE# TDROE# Tfall_OE# TFALL Trise_OE# TRISE Fall/rise time of OE# inputs IDTTM/ICSTM Four Output Differential Buffer for PCI Express 1 1250A—07/31/07 5 ICS9DBL411 Four Output Differential Buffer for PCI Express Advance Information AC Electrical Characteristics - DIF Low Power Differential Outputs PARAMETER SYMBOL CONDITIONS MIN MAX Rising Edge Slew Rate tSLR Differential Measurement 1 2.5 UNITS NOTES V/ns 1,2 1 2.5 V/ns 1,2 20 % 1 Falling Edge Slew Rate tFLR Differential Measurement Slew Rate Variation tSLVAR Single-ended Measurement Maximum Output Voltage VHIGH Includes overshoot mV 1 Minimum Output Voltage VLOW Includes undershoot -300 mV 1 Differential Voltage Swing VSWING Differential Measurement 300 mV 1 Crossing Point Voltage VXABS Single-ended Measurement 300 550 mV 1,3,4 Crossing Point Variation VXABSVAR Single-ended Measurement 140 mV 1,3,5 DCYCDIS1 Dif Measurement, fIN<=267MHz +5 % 1,6 DCYCDIS2 +7 % 1,6 25 ps 1 Duty Cycle Distortion DIF Jitter - Cycle to Cycle DIFJ C2C DIF[3:0] Skew DIFSKEW Dif Measurement, fIN>267MHz Differential Measurement, Additive Differential Measurement Propagation Delay PCIe Gen2 Phase Jitter Addtive PCIe Gen2 Phase Jitter Addtive tPD Input to output Delay tphase_addHI tphase_addLO 1150 50 ps 1 3.5 ns 1 1.5MHz < fIN < Nyquist (50MHz) 0.8 ps rms 1 10KHz < fIN < 1.5MHz 0.1 ps rms 1 2.5 Notes on Electrical Characteristics: 1 Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 4 Only applies to the differential rising edge (CLK rising and CLK# falling) Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. 6 Tthis is the figure refers to the maximum distortion of the input wave form. 5 7 Operation under these conditions is neither implied, nor guaranteed. 8 Maximum input voltage is not to exceed maximum VDD IDTTM/ICSTM Four Output Differential Buffer for PCI Express 1250A—07/31/07 6 ICS9DBL411 Four Output Differential Buffer for PCI Express Advance Information 20-Lead, 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 .169 .177 e 0.65 BASIC 0.0256 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0° 8° 0° 8° aaa -0.10 -.004 c N L E1 E INDEX AREA 1 2 α D A A2 VARIATIONS A1 -Ce b N SEATING PLANE 20 aaa C D mm. MIN 6.40 D (inch) MAX 6.60 MIN .252 MAX .260 Reference Doc.: JEDEC Publication 95, MO-153 10-0035 Ordering Information ICS 9DBL411yGLFT Example: ICS XXXX y G LF T Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) IDTTM/ICSTM Four Output Differential Buffer for PCI Express 1250A—07/31/07 7 ICS9DBL411 Four Output Differential Buffer for PCI Express Advance Information (Ref.) Seating Plane (ND -1)x e (Ref.) A1 Index Area ND & N Even A3 N L N 1 Anvil Singulation E2 (Ref.) b (Re f.) A Chamfer 4x 0.6 x 0.6 max OPTIONAL (N -1)x e E2 2 Sawn Singulation D are Even 2 OR Top View (Typ.) e 2 If N & N D e D2 2 ND & N Odd Thermal Base D2 0.08 C C THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS SYMBOL A A1 A3 b e DIMENSIONS MIN. MAX. 0.8 1.0 0 0.05 0.20 Reference 0.18 0.3 0.50 BASIC SYMBOL N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. ICS 20L TOLERANCE 20 5 5 4.00 x 4.00 2.00 / 2.25 2.00 / 2.25 0.45 / 0.65 Ordering Information ICS 9DBL411yKLFT Example: ICS XXXX y K LF T Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) IDTTM/ICSTM Four Output Differential Buffer for PCI Express 1250A—07/31/07 8 ICS9DBL411 Four Output Differential Buffer for PCI Express Advance Information Revision History Rev. 0.1 0.2 A Issue Date Description Page # 08/01/06 Initial Release. 09/22/06 Updated MLF Package Dimensions. 8 1. Updated electrical characteristics - additive jitter, cycle-to-cycle, tpd, skews, slew rates, Idd, etc. 2. Corrected power grouping table for TSSOP pkg 07/31/07 3. Final Release 1,5,6 Innovate with IDT and accelerate your future networks. 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All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA IDTTM/ICSTM Four Output Differential Buffer for PCI Express 1250A—07/31/07 9