CA3227 TM Data Sheet High-Frequency NPN Transistor Array For Low-Power Applications at Frequencies Up to 1.5GHz The CA3227 consists of five general purpose silicon NPN transistors on a common monolithic substrate. Each of the transistors exhibits a value of fT in excess of 3GHz, making them useful from DC to 1.5GHz. The monolithic construction of these devices provides close electrical and thermal matching of the five transistors. Ordering Information PART NUMBER (BRAND) May 2000 File Number 1345.5 Features • Gain-Bandwidth Product (fT) . . . . . . . . . . . . . . . . . >3GHz • Five Transistors on a Common Substrate Applications • VHF Amplifiers • VHF Mixers • Multifunction Combinations - RF/Mixer/Oscillator • IF Converter • IF Amplifiers TEMP. RANGE (oC) PACKAGE PKG. NO. • Sense Amplifiers CA3227E -55 to 125 16 Ld PDIP E16.3 • Synthesizers CA3227M (3227) -55 to 125 16 Ld SOIC M16.15 • Synchronous Detectors CA3227M96 (3227) -55 to 125 16 Ld SOIC Tape and Reel M16.15 • Cascade Amplifiers Pinout CA3227 (PDIP, SOIC) TOP VIEW 1 Q1 3 Q2 4 14 Q5 13 SUBSTRATE 5 12 6 11 7 8 1 16 15 2 Q3 Q4 10 9 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 CA3227 Absolute Maximum Ratings Thermal Information Collector to Emitter Voltage (VCEO). . . . . . . . . . . . . . . . . . . . . . . 8V Collector to Base Voltage (VCBO) . . . . . . . . . . . . . . . . . . . . . . . 12V Collector to Substrate Voltage (VCIO, Note 1) . . . . . . . . . . . . . . 20V Collector Current (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Thermal Resistance (Typical, Note 2) θJA (oC/W) 16 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 90 16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 185 Maximum Power Dissipation (Any One Transistor) . . . . . . . . 85mW Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The collector of each transistor of these devices is isolated from the substrate by an integral diode. The substrate (Terminal 5) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. 2. θJA is measured with the component mounted on an evaluation PC board in free air. TA = 25oC Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS DC CHARACTERISTICS FOR EACH TRANSISTOR Collector to Base Breakdown Voltage V(BR)CBO IC = 10µA, IE = 0 12 20 - V Collector to Emitter Breakdown Voltage V(BR)CEO IC = 1mA, IB = 0 8 10 - V Collector to Substrate Breakdown Voltage V(BR)CIO IC1 = 10µA, IB = 0, IE = 0 20 - - V Emitter Cutoff Current (Note 3) IEBO VEB = 4.5V, IC = 0 - - 10 µA Collector Cutoff Current ICEO VCE = 5V, IB = 0 - - 1 µA Collector Cutoff Current ICBO VCB = 8V, IE = 0 - - 100 nA DC Forward Current Transfer Ratio hFE VCE = 6V IC = 10mA - 110 - IC = 1mA 40 150 - - 150 - 0.62 0.71 0.82 V - 0.13 0.50 V - 0.94 V IC = 0.1mA Base to Emitter Voltage VBE VCE = 6V Collector to Emitter Saturation Voltage VCE SAT IC = 10mA, IB = 1mA Base to Emitter Saturation Voltage VBE SAT IC = 10mA, IB = 1mA IC = 1mA 0.74 NOTE: 3. On small-geometry, high-frequency transistors, it is very good practice never to take the Emitter Base Junction into reverse breakdown. To do so may permanently degrade the hFE. Hence, the use of IEBO rather than V(BR)EBO. These devices are also susceptible to damage by electrostatic discharge and transients in the circuits in which they are used. Moreover, CMOS handling procedures should be employed. 2 CA3227 TA = 25oC, 200MHz, Common Emitter, Typical Values Intended Only for Design Guidance Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS TYPICAL VALUES UNITS 4 mS 0.75 mS 2.7 mS 0.13 mS 29.3 mS -33 Degrees 0.38 mS -97 Degrees 4.8 mS 2.85 mS 2.75 mS 0.9 mS 95 mS -62 Degrees 0.39 mS -97 Degrees DYNAMIC CHARACTERISTICS FOR EACH TRANSISTOR Input Admittance Y11 b11 IC = 1mA, VCE = 5V g11 Output Admittance Y22 b22 IC = 1mA, VCE = 5V g22 Forward Transfer Admittance Y21 Y21 IC = 1mA, VCE = 5V θ21 Reverse Transfer Admittance Y12 Y12 IC = 1mA, VCE = 5V θ12 Input Admittance Y11 b11 IC = 10mA, VCE = 5V g11 Output Admittance Y22 b22 IC = 10mA, VCE = 5V g22 Forward Transfer Admittance Y21 Y21 IC = 10mA, VCE = 5V θ21 Reverse Transfer Admittance Y12 Y12 IC = 10mA, VCE = 5V θ12 Small Signal Forward Current Transfer Ratio h21 IC = 1mA, VCE = 5V 7.1 IC = 10mA, VCE = 5V 17 TYPICAL CAPACITANCE AT 1MHz, THREE-TERMINAL MEASUREMENT Collector to Base Capacitance CCB VCB = 6V 0.3 pF Collector to Substrate Capacitance CCI VCI = 6V 1.6 pF Collector to Emitter Capacitance CCE VCE = 6V 0.4 pF Emitter to Base Capacitance CEB VEB = 3V 0.75 pF Spice Model (Spice 2G.6) .model NPN + BF = 2.610E + 02 BR = 4.401E + 00 IS = 6.930E - 16 RB = 130.0E + 00 + RC = 1.000E + 01 RE = 7.396E - 01 VA = 6.300E + 01 VB = 2.208E + 00 + IK = 1.000E - 01 ISE = 1.87E - 14 NE = 1.653E + 00 IKR = 1.000E - 02 + ISC = 9.25E - 14 NC = 1.333E + 00 TF = 1.775E - 11 TR = 1.000E - 09 + CJS = 1.800E - 12 CJE = 1.010E - 12 PE = 8.350E - 01 ME = 4.460E - 01 + CJC = 9.100E - 13 PC = 3.850E - 01 MC = 2.740E - 01 KF = 0.000E + 00 + AF = 1.000E + 00 EF = 1.000E + 00 FC = 5.000E - 01 PJS = 5.410E - 01 + MJS = 3.530E - 01 RBM = 30.00 RBV = 100 IRB = 0.00 Please Note: No measurements have been made to model the reverse AC operation (tr is an estimation). 3 CA3227 160 150 140 130 120 110 100 90 80 70 60 50 40 VCE = 6V, TA = 25oC 30 20 0.1 1.0 3.5 VCE = 5V, TA = 25oC 3.0 2.5 fT (GHz) hFE Typical Performance Curves 2.0 1.5 1.0 0.5 10 0 100 0 5 IC (mA) FIGURE 1. hFE vs COLLECTOR CURRENT RSOURCE = 1kΩ, VCE = 6V, TA = 25oC 30 30 20 FREQUENCY = 10Hz NOISE FIGURE (dB) FREQUENCY = 10Hz 100Hz 1kHz 100Hz 20 1kHz 10 10 10kHz 10kHz 100kHz 100kHz 0.01 15 FIGURE 2. fT vs COLLECTOR CURRENT RSOURCE = 500Ω, VCE = 6V, TA = 25oC 0.1 1.0 0.01 10.0 IC (mA) FIGURE 3. NOISE FIGURE vs COLLECTOR CURRENT FIGURE 4. NOISE FIGURE vs COLLECTOR CURRENT 1.75 1.50 1.25 CCI 1.00 0.75 CEB 0.50 CCB 0.25 0 0 1 2 3 4 5 6 7 8 BIAS VOLTAGE (V) FIGURE 5. CAPACITANCE vs BIAS VOLTAGE 4 1.0 0.1 IC (mA) CAPACITANCE (pF) NOISE FIGURE (dB) 10 IC (mA) 9 10 10.0 CA3227 Die Characteristics DIE DIMENSIONS: 46 mils x 32 mils Metallization Mask Layout CA3227 (14) (13) (12) (11) (15) (10) (16) (9) (1) (8) (2) (7) (3) 5 (4) (5) SUBSTRATE (6) CA3227 Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 C D 0.735 0.775 D1 0.005 - E 0.300 0.325 E1 0.240 0.280 6.10 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 6 MILLIMETERS e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 16 0.204 0.355 18.66 - 19.68 5 0.13 - 5 7.62 8.25 6 7.11 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 16 10.92 7 3.81 4 9 Rev. 0 12/93 CA3227 Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) N INDEX AREA H 0.25(0.010) M 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- e α B 0.25(0.010) M C 0.10(0.004) C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. MAX MILLIMETERS MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e A1 MIN 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α 16 0o 16 8o 0o 7 8o Rev. 0 12/93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 7 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029