an1575

Application Note 1575
ISL28433SOICEVAL1Z, ISL28433TSSOPEVAL1Z
Evaluation Board User’s Guide
Introduction
Power Supplies (Figure 1)
The ISL28433SOICEVAL1Z and ISL28433TSSOPEVAL1Z
Evaluation Board is designed to evaluate the performance
of the ISL28433 Chopper Stabilized op amp. The evaluation
board contains the circuitry needed to evaluate the high
performance of the ISL28433 amplifier. The ISL28433
chopper stabilized rail-to-rail quad op amp features a low
8µV maximum VOS over-temperature and a 0.1Hz 1/f
noise corner frequency enabling very high gain single-stage
DC amplifiers that can operate from single cell batteries
while consuming only 20µA of current. The
ISL28433SOICEVAL1Z and ISL28433TSSOPEVAL1Z
evaluation board can be configured as a precision high-gain
(G = 10,000V/V) differential amplifier and demonstrates
the level of performance possible with this type of amplifier
while operating from battery voltages as low as 1.65V.
External power connections are made through the V+,
V-, VREF, and GND connections on the evaluation board.
The circuit can operate from a single supply or from dual
supplies. For single supply operation, the V- and GND
pins are tied together to the negative or ground
reference of the power supply. For split supplies, V+ and
V- terminals connect to their respective supply terminals.
De-coupling capacitors C1 and C2 provide low-frequency
power-supply filtering, while additional capacitors, C3
and C4, which are connected close to the part, filter out
high frequency noise. Anti-reverse diodes D1 and D2
(optional) protects the circuit in the momentary case of
accidentally reversing the power supplies to the
evaluation board. The VREF pin can be connected to
ground to establish a ground referenced input for split
supply operation, or can be externally set to any
reference level for single supply operation.
Reference Documents
• ISL28233, ISL28433 Data Sheet; FN7692
J3 V-
V+ J1
Evaluation Board Key Features
R1
C1
0
4.7µF
• External VREF input
D1
0
R37
D2
C4
• Banana Jack Connectors for Power Supply and VREF
Inputs
0.1µF
V-
• BNC Connectors for Op Amp Input and Output
Terminals
V- AND V+
IC SUPPLY PINS
J2
0
• Singled-Ended or Differential Input Operation with
High Gain (G= 10,000V/V)
GND
R48
R44
4.7µF 0
C3
C2
• Dual Supply Operation: ±0.825V to ±2.75V
0.1µF
• Single Supply Operation: +1.65V to +5.5V
VREF
J4
V+
FIGURE 1. POWER SUPPLY CIRCUIT
• Convenient PCB Pads for Op Amp Input/Output
Impedance Loading
R39, R47, R49, R50
R14, R16,
R18, R40
IN-
100Ω
R15, R17,
R19, R41
IN+
IN +
IN-A
IN-B
IN-C
IN-D
2
6
9
13
IN+A 3
IN+B 5
IN+C 10
IN+D 12
1MΩ
-
+
100Ω
VREF
VREF
GND
OPEN
V+
0Ω
ISL28433
R24, R27, R29, R45
VCM
4
11
V-
OUT_A
OUT_B
OUT_C
OUT_D
OUT
1 R51-R54
7
8
14
R67-R70
OPEN
OPEN
FIGURE 2. BASIC DIFFERENTIAL AMPLIFIER CONFIGURATION
October 1, 2010
AN1575.0
1
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Application Note 1575
R6
0
100
1M
R20
C23
OPEN
R39
DNP
IN-A
C6
OPEN
R14
DNP
FROM OUT_A
TO IN-A
R5
R15
100
0
C7
TO IN+A
R21
IN+A
DNP
For single-ended input with an inverting gain
G = -10,000V/V, the IN+ input is grounded and the
signal is supplied to the IN- input. VREF must be
connected to a reference voltage between the V+ and
V- supply rails. For non-inverting operation with
G = 10,001V/V, the IN- input is grounded and the
signal is supplied to the IN+ input. The non-inverting
gain is strongly dependent on any resistance from INto GND. For good gain accuracy, a 0Ω resistor should
be installed on the empty R11 pad.
R11
(EQ. 1)
NOTE: Operational amplifiers are sensitive to output
capacitance and may oscillate. In the event of oscillation,
reduce output capacitance by using shorter cables, or
add a resistor in series with the output.
OPEN
User-selectable Options
(Figures 3 and 4)
FIGURE 3. INPUT STAGE
R67
J13 OUT A
DNP
DNP
0
OPEN DNP
R59
R63
0
C15
A voltage divider can be added to establish a power
supply-tracking common mode reference using the VREF
input (see “ISL28433SOICEVAL1Z Schematic Diagram”
on page 4). The inverting and non-inverting inputs have
R51
R55
OUT_A
C14
Component pads are included to enable a variety of
user-selectable circuits to be added to the amplifier
inputs, the VREF input, outputs and the amplifier
feedback loops.
OPEN
V OUT = ( V IN+ – V IN- ) • ( R F ⁄ R IN ) + V REF
The output (Figure 4) also has additional resistor and
capacitor placements for filtering and loading.
R2
The schematic of the op amp input stage with the
components supplied is shown in Figure 3, with a closed
loop gain of 10,000V/V. The circuit implements a Hi-Z
differential input with unbalanced common mode
impedance. The differential amplifier gain is expressed in
Equation 1:
additional resistor and capacitor placements for adding
input attenuation or feedback capacitors (Figure 3).
DNP
Amplifier Configuration (Figure 3)
FIGURE 4. OUTPUT STAGE
TABLE 1. ISL28433TSSOPEVAL1Z and ISL28433MSOPEVAL1Z COMPONENTS PARTS LIST
DEVICE #
DESCRIPTION
COMMENTS
C1, C2
CAP, SMD, 1210, 4.7µF, 50V, 10%, X7R, ROHS
Power Supply Decoupling
C3, C4
CAP, SMD, 0805, 0.1µF, 50V, 10%, X7R, ROHS
Power Supply Decoupling
D1, D2
40V SCHOTTKY BARRIER DIODE
Reverse Power Protection
RESISTOR, SMD, 0603, DNP, 1%, ROHS
VREF Resistor Divider
C5
CAP, SMD, 1210, 4.7µF, 50V, 10%, X7R, ROHS
VREF Supply Decoupling
R5, R7, R9, R14, R16,
R18, R35, R40
RESISTOR, SMD, 0603, 100Ω, 1%, 1/16W, ROHS
Gain Setting Resistor
R39, R47, R49, R50
RESISTOR, SMD, 0603, 10MΩ, 1%, 1/16W, ROHS
Gain Setting Feedback Resistor
R32, R33
RESISTOR, SMD, 0603, DNP-PLACE HOLDER, ROHS
R2-R4, R11-R13,
R20-R23, R25,R26,R34,
R38, R42, R43, R55-R58,
R67-70, R24, R27-R31,
R33, R45, R46, R59-R62
U1 (ISL28433)
User selectable resistors - not populated
ISL28433FBZ (SOIC), ISL28433FVZ (TSSOP),
IC-RAIL-TO-RAIL OP AMP, ROHS
2
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October 1, 2010
Application Note 1575
ISL28433SOICEVAL1Z Top View
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the
reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
3
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R47
100k
DNP
0
IN+C
R42
R35
100k
1 C13 2
OPEN
DNP
1
2
OPEN
R38
DNP
R34
1
2
DNP
IN+D J12
5
R36
DNP
R46
100k
R45
100k
IN+D
R41
0
DNP
R19
OPEN
1
2
IN-D
R43
R29
100k
IN-D J11
5
4
3
DNP
R9
100k
1 C11 2
DNP
R4
4
3
4
3
100k
R25
1
2
OPEN
R26
IN+C J10
5
R31
DNP
DNP
1
2
R40
100k
C12
IN-C
R10
R13
J9
5
IN-C
DNP
R18
100k
1 C10 2
R53
R65
0
0
R69
R49
100k
1 C25 2
OPEN
IN+B
R23
0
1 C24 2
OPEN
R50
R54
R66
100k
0
0
R70
R17
1
14 14 OUTD
2
13 13 IN-D
U1
3 SOIC14 12 12 IN+D
4 GENERIC 11 11 V5 PACK. 10 10 IN+C
6
9 9 IN-C
7
8 8 OUTC
1 C20 2
OPEN
DNP
R27
100k
1
2
3
4
5
6
7
10k
R30
100k
4
3
RINA1+
R7
100k
1 C9 2
OPEN
1
2
R22
DNP
DNP
R12
R3
DNP
4
3
4
3
IN+B J8
5
1
2
OUTA
IN-A
IN+A
V+
IN+B
IN-B
OUTB
J14
5 OUT
1
2
J15
5 OUT
1
2
J16
5 OUT
DNP
3
4
1
2
Application Note 1575
IN-B J7
5
R8
1 C18 2
OPEN
IN-B
R16
100k
1 C8 2
OPEN
R67
0
R68
R64
0
DNP
3
4
R52
10k
1 C22 2
OPEN
100k
J13
5 OUT
DNP
3
4
V+
10k
1 C23 2
OPEN
R39
2 C19 1 R57
OPEN DNP
R61
0.1µF
1
2
DNP
3
4
C3
V-
2 C17 1 R56
OPEN DNP
R60
D1 4.7µF
1
10k
0
2 C15 1 R55
OPEN DNP
R59
R63
0
1 C14 2
OPEN
R51
2 C21 1 R58
OPEN DNP
R62
J1
J2
2
V+
R48
0
R37
0.1µF
0
C1
1 C16 2
OPEN
C5
4.7µF
C4
R1
1
1
1
1
0
R32
R44
C2
4.7µF D2 0
2
1
100k
IN+A
R15
0
10k
R20
DNP
R24
R21
1
2
R28
100k
R33
RINA1+
R5
100k
1 C7 2
OPEN
V-
DNP
DNP
R11
DNP
R2
4
4
3
IN+A J6
5
100k
1 C6 2
OPEN
R6
1
2
DNP
4
3
IN-A J5
5
REF1
J3
IN-A
R14
0
J4
ISL28433SOICEVAL1Z Schematic Diagram
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October 1, 2010
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