DATASHEET

ISL59311
®
Data Sheet
April 25, 2007
Differential Video Amplifier with Common
Mode Sync Encoder and Serial Digital
Interface
The ISL59311 is a high bandwidth triple differential amplifier
with integrated encoding of video sync signals. The inputs
are suitable for handling high speed video or other
communications signals in either single-ended or differential
form, and the common-mode input range extends all the way
to the negative rail enabling ground-referenced signaling in
single supply applications. The high bandwidth enables
differential signaling onto standard twisted-pair or coax with
very low harmonic distortion, while internal feedback
ensures balanced gain and phase at the outputs reducing
radiated EMI and harmonics.
Embedded logic encodes standard video horizontal and
vertical sync signals onto the common mode of the twisted
pair(s), transmitting this additional information without the
requirement for additional buffers or transmission lines. The
ISL59311 enables significant system cost savings when
compared with discrete line driver alternatives.
The digital block of the chip is a data transceiver which is
intended to drive one twisted pair line. The maximum
baudrate for this block is 50Mbps.
FN6372.3
Features
• Fully differential inputs, outputs, and feedback
• 650MHz -3dB bandwidth
• 1500V/µs slew rate
• -70dB distortion at 20MHz
• Single 5V operation
• 50mA minimum output current
• Low power: 57mA total supply current
• Pb-free plus anneal available (RoHS compliant)
Block Diagram
VCCA
VCCD
VCCA domain
VINA+
+
VOUTA+
VINA-
-
VOUTA-
VINB+
+
VOUTB+
VINB-
-
VOUTB-
VINC+
+
VOUTC+
VINC-
-
VOUTC-
Disable
CMA
The ISL59311 is available in a 32 Ld QFN package and is
specified for operation over the -40°C to +85°C temperature
range.
Applications
HSYNC
VSYNC
Sync to
CMB
Common Mode
Translation
CMC
• Twisted-pair drivers
VCCS domain
• Differential line drivers
VCCS
• VGA over twisted-pair
Transmit
VCCD domain
• Transmission of analog signals in a noisy environment
Ordering Information
PART
NUMBER
(Note)
ISL59311IRZ
SOUT+
TXDATA
SDATA
SOUT-
PART
TAPE & PACKAGE
MARKING REEL
(Pb-Free)
59311 IRZ
ISL59311IRZ-T13 59311 IRZ
PKG.
DWG. #
-
32 Ld QFN
L32.5x6A
13”
32 Ld QFN
L32.5x6A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
RXDATA
GNDA
+
SIN+
-
SIN-
GNDD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL59311
Pinout
26 GNDA
27 VCCA
28 VOUTA-
29 VOUTA+
30 Disable
31 VIINA+
32 VINA-
ISL59311
(32 LD QFN)
VSYNC 1
25 VOUTC-
HSYNC 2
24 VOUTB+
VINB+ 3
23 VOUTB-
VINB- 4
22 VOUTC+
THERMAL
PAD
VINC+ 5
21 GNDA
VINC- 6
20 GNDD
GNDA 7
19 VCCD
SIN+ 16
SIN- 15
NC 14
SOUT- 13
17 SOUT+
Transmit 12
VCCS 9
SDATA 11
18 NC
GNDD 10
VCCS 8
Pin Descriptions
PIN NAME
VINA±, VINB±, VINC±
DESCRIPTIONS
EQUIVALENT CIRCUIT
Differential video inputs
VOUTA±, VOUTB±, VOUTC± Differential video outputs to transmission line
HSYNC, VSYNC
Horizontal and Vertical Sync inputs to be encoded
H,V
GNDA
Disable
Transmit
Disable video amplifiers signal.
Logic low enables the video amplifiers.
Logic high disables the video amplifiers, reducing VCCA power
consumption.
The Serial Digital Interface is always enabled regardless of the state of the
Disable pin.
Transmit/receive logic input.
Logic high: Transmits data from the SDATA pin data down the transmission
line.
Logic low: Data received from the transmission line is output on the SDATA
pin.
SOUT±
Differential serial data outputs to transmission line
SIN±
Differential serial data inputs from transmission line
2
ENV
GNDA
TR
GNDA
FN6372.3
April 25, 2007
ISL59311
Pin Descriptions (Continued)
PIN NAME
SDATA
DESCRIPTIONS
Digital data input/output.
When Transmit is high, this is an input, receiving the serial data to be
transmitted over the SOUT± pins.
When Transmit is low, this is an output, representing the data received on
the SIN± pins.
VCCS
Power supply for SDATA I/O pin - sets input thresholds and output swing.
Typically set to 3.3V or 5V.
VCCD
VCC for line interface section (5V)
GNDD
Digital ground for the Serial Digital Interface
VCCA
VCC for the video amplifiers (5V)
GNDA
Analog ground for the video amplifiers
NC
EQUIVALENT CIRCUIT
TXRX
DIFF DATA
No Connection. Do not connect these pins to anything. Leave these
pins floating!
3
FN6372.3
April 25, 2007
ISL59311
Absolute Maximum Ratings (TA = +25°C)
Supply Voltage (VCCA, VCCD) . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V
Maximum Output Continuous Current . . . . . . . . . . . . . . . . . . ±70mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Input/Output Voltages
All signal (non-supply) pins . . . . . . . . . . . . -0.6V to VCCA + 0.6V
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000V
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250V
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all
tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
VCCA = VCCD = VCCS = +5V, GNDA = GNDD = 0V, TA = +25°C, VIN = 0V, RL = 200Ω, unless otherwise
specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
VCC - 1
V
Video Amplifier Electrical Characteristics
Output Voltage Range
1
Output Impedance, Disabled
10
MΩ
AV = 2, VOUT = 200mV
650
MHz
VOUT = 2V
600
MHz
VOUT = 2VP-P
1500
V/µs
20
ns
1300
MHz
AC PERFORMANCE
Bandwidth, -3dB
Differential Slew Rate,
Settling Time (0.1%, 2VP-P)
Gain Bandwidth Product
2nd Harmonic Distortion
20MHz, RL = 200Ω
-70
dBc
3rd Harmonic Distortion
20MHz, RL = 200Ω
-70
dBc
75
dB
Differential Phase @100MHz
0.01
°
Differential Gain @100MHz
0.01
%
Hostile Crosstalk
INPUT CHARACTERISTICS
Input Referred Offset Voltage
Input Bias Current
-10
±1
10
mV
2
6
12
µA
Differential Input Impedance
Differential Input Range
Common Mode Input Voltage Range
MΩ
±0.75
V
-0.3
Input Referred Noise
CMRR
10
VCM = 0V to 2V
VCCA - 2.6
V
15
nV/√Hz
60
75
dB
±40
±60
mA
OUTPUT CHARACTERISTICS
Output Peak Current
Output Voltage Range
1
VCC - 1
V
2.00
V/V
DC PERFORMANCE
Voltage Gain
1.90
4
1.95
FN6372.3
April 25, 2007
ISL59311
Electrical Specifications
VCCA = VCCD = VCCS = +5V, GNDA = GNDD = 0V, TA = +25°C, VIN = 0V, RL = 200Ω, unless otherwise
specified. (Continued)
DESCRIPTION
CONDITION
PSRR
Rejection of VCCA
MIN
TYP
MAX
UNIT
60
75
dB
VCCD
V
3.3
V
Digital Transceiver Block Electrical Characteristics
TRANSMITTER DC CHARACTERSTICS
SOUT± Differential Output Voltage
No load
RL = 100Ω (Figure 1A)
Change in Magnitude of Driver Differential
SOUT± for Complementary Output States
RL = 100Ω (Figure 1A)
|(SOUT+) - (SOUT-)|
SOUT± Common-Mode Voltage (deviation
from VCCD/2)
RL = 100Ω (Figure 1A)
SOUT± Short Circuit Current
SOUT± Leakage Current
3.0
.08
0.2
V
±0.06
+0.1
V
Driving high, output tied to GND
95
110
mA
Driving low, output tied to VCCD
95
110
mA
SOUT (Transmit = GND)
±2
±100
nA
-0.1
TRANSMITTER SWITCHING CHARACTERISTICS
Maximum Data Rate
RL = 100Ω, (Figure 1A)
Differential Propagation Delay
tPLH (Figure 2, RDIFF = 100Ω)
6
10
ns
tPHL (Figure 2, RDIFF = 100Ω)
6
10
ns
Differential Output Skew
|tPLH – tPHL| (Figure 2, RDIFF = 100Ω)
2
4
ns
Output Enable Time
tPZH: Driver Enable to Output High
(Figure 3, ISINK = 1mA, ISOURCE = off)
4
20
ns
tPZL: Driver Enable to Output Low
(Figure 3, ISINK = off, ISOURCE = 1mA)
6
20
ns
tPHZ: Output High to Output Disabled
(Figure 3, ISINK = 25mA, ISOURCE = off)
28
35
ns
tPLZ: Output Low to Output Disabled
(Figure 3, ISINK = off, ISOURCE = 25mA)
28
35
ns
±2
±100
nA
30
50
mV
VCC + 0.5
V
3.5
kΩ
Output Disable Time
50
Disabled Output Leakage
Mbps
RECEIVER DC CHARACTERISTICS
SIN± Input Hysteresis
VCM = 2.5V
SIN± Input Range
2
GND - 0.5
SIN± Input Resistance; Each Input to GND
2.5
3.0
RECEIVER SWITCHING CHARACTERISTICS
Maximum Data Rate
Driven with 100mV differential signal
(Figure 4, Note 4)
50
Mbps
Receiver Input to Output Propagation Delay
TPLH (Figure 4)
4.7
8
ns
TPHL (Figure 4)
5.5
8
ns
Receiver Skew
|tPLH – tPHL| (Figure 4)
0.8
2
ns
tRISE/tFALL
100kΩ II10pF load
2
ns
Receiver Enable to Output High
15
20
ns
Receiver Enable to Output Low
35
42
ns
Receiver High to Hi-Z
15
25
ns
5
FN6372.3
April 25, 2007
ISL59311
Electrical Specifications
VCCA = VCCD = VCCS = +5V, GNDA = GNDD = 0V, TA = +25°C, VIN = 0V, RL = 200Ω, unless otherwise
specified. (Continued)
DESCRIPTION
CONDITION
MIN
Receiver Low to Hi-Z
TYP
MAX
UNIT
10
20
ns
System Logic Inputs DC Characteristics
VSYNC, HSYNC, TRANSMIT, AND DISABLE INPUT CHARACTERISTICS
2
V
Input High Voltage
VIH
Input Low Voltage
VIL
VSYNC, HSYNC, Transmit Input Current
IIN
±1
Disable Pin Pull-down Resistance to GNDA
RDisable
500
0.8
V
±5
µA
kΩ
SDATA INPUT CHARACTERISTICS (Transmit = VCCD)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Current
IIN
0.7 VCCS
V
±0.001
0.3 VCCS
V
±1
µA
SDATA OUTPUT CHARACTERISTICS (Transmit = GND)
High Output Level
Sourcing 4mA to GND
4.5
4.7
V
Low Output Level
Sinking 4mA from VCCS
0.3
Short Circuit Output Current
Driving high, output tied to GND
20
mA
Driving low, output tied to VCCS
40
mA
0.4
V
Power Supply Characteristics
VCCA Operating Range
4.5
VCCA Supply Current (all 3 channels)
V
Operating (Disable = GND)
50
60
mA
Disabled (Disable = VCCA)
2.3
3
mA
5.5
V
7
12
mA
5
6
kΩ
VCCD Operating Range
4.5
VCCD Supply Current
VCCS Input Impedance
5.5
VCCS = 5V (Note 2)
4
NOTES:
1. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
2. VCCS current is equal to the VCCS voltage applied divided by the VCCS Input Impedance. Some additional current is consumed when SDATA is
driving high into the external load.
3. Applies to peak current. See “Typical Performance Curves” for more information.
4. Guaranteed by characterization but not tested.
6
FN6372.3
April 25, 2007
ISL59311
Test Circuits and Waveforms
50Ω
50Ω
SDATA
SOUT-
SDATA
VOD
D
SOUT-
VCM
VOD
D
0V to 5V
SOUT+
SOUT+
50Ω
VOC
50Ω
FIGURE 1B. VOD WITH COMMON MODE LOAD
FIGURE 1A. VOD AND VOC
FIGURE 1. DC DRIVER TEST CIRCUITS
5V
DI
2.5V
2.5V
0V
CL = 50pF
SOUT-
SDATA
tPHL
tPLH
SOUT-
VOH
SOUT+
VOL
100Ω
D
CL = 50pF
SOUT+
SIGNAL
GENERATOR
DIFF OUT
(SOUT+ - SOUT-)
90%
+VOD
90%
10%
10%
tR
-VOD
tF
SKEW = |tPLH - tPHL|
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES
TRANSMIT
SDATA
D
ISOURCE
SOUT±
50pF
2.5V
2.5V
tPHZ
90%
tPZH
3.5V
SOUT±
ISINK
SIGNAL
GENERATOR
tPLZ
tPZL
SOUT±
1.5V
10%
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3A. TEST CIRCUIT
FIGURE 3. DRIVER DATA RATE
4.0V
2.5V
SIN+
SINSIN+
R
SDATA
2.5V
2.5V
50pF
1.0V
tPHL
tPLH
VCCS = 5V
SIGNAL
GENERATOR
SDATA
1.5V
1.5V
0V
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. RECEIVER PROPAGATION DELAY AND DATA RATE
7
FN6372.3
April 25, 2007
ISL59311
Typical Performance Curves
VOLTAGE
(0.5V/DIV)
BLUE CM
OUT (CH C)
VCCA = 5V
CL = 0pF
CHAN A
RL = 500Ω
RL = 200Ω
GREEN CM
OUT (CH B)
VOLTAGE
(2.5V/DIV)
RED CM
OUT (CH A)
RL = 100Ω
RL = 50Ω
VSYNC
HSYNC
TIME (0.5ms/DIV)
FIGURE 5. COMMON MODE OUTPUT
VCCA = 5V
CL = 0pF
CHAN B
RL = 500Ω
FIGURE 6. DIFFERENTIAL FREQUENCY RESPONSE FOR
VARIOUS RL - DIFF (CHANNEL A)
VCCA = 5V
CL = 0pF
CHAN C
RL = 200Ω
RL = 500Ω
RL = 200Ω
RL = 100Ω
RL = 50Ω
RL = 100Ω
RL = 50Ω
FIGURE 7. DIFFERENTIAL FREQUENCY RESPONSE FOR
VARIOUS RL - DIFF (CHANNEL B)
VCCA = 5V
RL = 200Ω
CHAN A
CL = 12pF
CL = 8.2pF
CL = 4.7pF
CL = 2.2pF
FIGURE 9. DIFFERENTIAL FREQUENCY RESPONSE FOR
VARIOUS CL - DIFF (CHANNEL A)
8
FIGURE 8. DIFFERENTIAL FREQUENCY RESPONSE FOR
VARIOUS RL - DIFF (CHANNEL C)
VCCA = 5V
RL = 200Ω
CHAN B
CL = 12pF
CL = 8.2pF
CL = 4.7pF
CL = 2.2pF
FIGURE 10. DIFFERENTIAL FREQUENCY RESPONSE FOR
VARIOUS CL - DIFF (CHANNEL B)
FN6372.3
April 25, 2007
ISL59311
Typical Performance Curves
VCCA = 5V
RL = 200Ω
CHAN C
(Continued)
VCCA = 5V
RL = 200Ω
THD
CL = 12pF
CL = 8.2pF
OUTPUT C
OUTPUT A
CL = 4.7pF
OUTPUT B
CL = 2.2pF
FIGURE 11. DIFFERENTIAL FREQUENCY RESPONSE FOR
VARIOUS CL - DIFF (CHANNEL C)
FIGURE 12. TOTAL HARMONIC DISTORTION
VCCA = 5V
RL = 200Ω
3RD HARMONIC
VCCA = 5V
RL = 200Ω
2ND HARMONIC
OUTPUT C
OUTPUT B
OUTPUT A
OUTPUT A
OUTPUT B
OUTPUT C
FIGURE 13. 2ND HARMONIC DISTORTION
FIGURE 14. 3RD HARMONIC DISTORTION
RL = 200Ω DIFF
CL = 0pF
RISE
Δt = 1.2ns
FALL
Δt = 1.1ns
TIME (20ns/DIV)
FIGURE 15. DIFFERENTIAL LARGE SIGNAL TRANSIENT
RESPONSE
9
VOLTAGE (120mV/DIV)
VOLTAGE (235mV/DIV)
RL = 200Ω DIFF
CL = 0pF
RISE
Δt = 1.4ns
FALL
Δt = 1.3ns
TIME (20ns/DIV)
FIGURE 16. DIFFERENTIAL SMALL SIGNAL TRANSIENT
RESPONSE
FN6372.3
April 25, 2007
ISL59311
Typical Performance Curves
(Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
0.8
2.857W
0.5
A
1
3 2 /W
F N 5 °C
2
=1
3 2 /W
FN °C
5
=3
A
1.5
0.6
θJ
Q
2
0.7 758mW
Q
POWER DISSIPATION (W)
2.5
θJ
POWER DISSIPATION (W)
3
JEDEC JESD51-3 AND SEMI G42-88
(SINGLE LAYER) TEST BOARD
0.5
0.4
0.3
0.2
0.1
0
0
0
25
50
75 85 100
125
0
150
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 17. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Operational Description and Application
Information
consists of three fully differential video signals, with sync
encoded on the common mode of each of the three RGB
differential signals. HSYNC and VSYNC can easily be
separated from the differential output signals, decoded and
transmitted along with the RGB video signals to the video
monitor.
Introduction
The ISL59311 is designed to differentially drive composite
RGB video signals onto twisted pair lines, while
simultaneously encoding horizontal and vertical sync signals
as common mode output. The entire video signal plus sync
can therefore be transmitted on 3 twisted pairs of wire. When
utilizing CAT5 cable, the 4th available twisted pair can be
used for transmission of audio, data or control information.
The distribution of composite video over standard CAT5
cable enables enormous cost and labor savings compared
with traditional coaxial cable, when considering both the
relative low price and ease of pulling CAT5 cable.
The digital block of the chip is a data transceiver which is
intended to drive one twisted pair line. The maximum
baudrate for this block is 50Mbps.
Functional Description
The ISL59311 provides three fully differential high-speed
amplifiers, suitable for driving high-resolution composite
video signals onto twisted pair or standard coaxial cable.
The input common-mode range extends to the negative rail,
allowing simple ground-referenced input termination to be
used with a single supply. The amplifiers provide a fixed gain
of +2 to compensate for standard video cable termination
schemes. Horizontal and Vertical sync signals (HSYNC and
VSYNC) are passed to an internal Logic Encoding Block to
encode the sync information as three discrete signals of
different voltage levels. Generally, in differential amplifiers an
external VREF pin is used to control the common mode level
of the differential output; in the case of the ISL59311 the
VREF of each of the three internal amplifier channels
receives a signal from the Logic Encoding Block with
encoded HSYNC and VSYNC information. The final output
10
Sync Transmission
The ISL59311 encodes HSYNC and VSYNC signals on the
common mode output of the differential video signals; Red,
Green and Blue respectively. Data Sheet Table 1 shows the
common mode levels for the different SYNC input
combinations. Note that the sum of the common mode
voltages results in a fixed average DC level with no AC
content. This dramatically reduces EMI radiation into any
common mode signal along the twisted pairs of CAT5 cable.
Extract Common Mode Sync and Decode HSYNC
and VSYNC
HSYNC and VSYNC can be regenerated from the Common
Mode sync output voltages. The relationships between
HSYNC, VSYNC and the 3 common mode levels are given by
Table 1. The common mode levels are easily separated from
the differential outputs of the ISL59311 using this simple
resistor network at the cable receiver input of each
differential channel; see Figure 20.
TABLE 1. SYNC SIGNAL ENCODING
COMMON
MODE B
(GREEN)
COMMON
MODE C
(BLUE)
HSYNC
VSYNC
COMMON
MODE A
(RED)
Low
High
3.0
2.0
2.5
Low
Low
2.5
3.0
2.0
High
Low
2.0
3.0
2.5
High
High
2.5
2.0
3.0
FN6372.3
April 25, 2007
ISL59311
DISABLE
Long Distance Video Transmission
VSYNC
CMA
LOGIC
DECODING
HSYNC
DISABLE
+
VINA
-
DISABLE
+
+
VOUTA
VREF
+
VINB
-
DISABLE
+
+
VOUTB
VREF
+
VINC
-
DISABLE
+
+
VOUTC
VREF
CMB
CMC
FIGURE 19. VIDEO DRIVER BLOCK DIAGRAM
Twisted Pair Termination
The schematic in Figure 20 illustrates a termination scheme
for 50Ω series termination and a 100Ω twisted pair cable.
Note RCM is the common mode termination to allow
measurement of VCM and should not be too small since it
loads the ISL59311; a little over a 100Ω is recommended for
RCM.
50Ω
+
-
TWISTED
PAIR
+
50Ω
VCM
50Ω
ZO =100Ω
50Ω
-
VREF
120Ω
(RCM: SHOULD BE >100Ω)
(FOR LOADING
CONSIDERATIONS)
FIGURE 20. TWISTED PAIR TERMINATION
Video Transmission
The ISL59311 is a twisted pair differential line driver directed
at the transmission of Video Signals through cables up to
100 feet; however, as signal losses increase with
transmission line length the ISL59311 will need additional
support to equalize video signals along longer twisted pair
transmission lines. A full solution to accomplish this is the
SXGA Video Transmission System presented in the
ISL59311 Data Sheet. Note the inclusion of the EL9111 for
signal equalization of up to 1000ft of CAT5 cable and
common mode extraction; see Data Sheet for additional
information on the EL9111.
11
The SXGA Video Transmission System makes it possible to
transmit Red, Green and Blue (RGB) video plus sync up to
1000ft through CAT5 cable. The input to the SXGA Video
Transmission System is the output of a video source
transmitting RGB video signals plus sync. The signals are
received initially by the ISL59311; which converts the single
ended input RGB signals to three fully differential waveforms
with sync encoded on the discrete common modes of each
color channel and then drives the signals through a length of
CAT5 cable. The signal is received by the EL9111, which can
provide 6-pole equalization for both high and low frequency
signal transmission line losses. Then the EL9111 converts
the differential RGB video signals back into single ended
format while extracting the common mode component for
decoding. The single ended RGB signal is taken directly
from the output of the EL9111 and is ready for the output
device. The EL9111 Common Mode Decoder Circuit
receives the common mode signals and decodes them and
transmits HSYNC and VSYNC to the output device.
Disabling the Amplifiers with the Disable Pin
The Disable pin must be a logic low for normal operation of
the video amplifiers. When Disable is taken high, the
amplifiers are disabled, reducing supply VCCA supply
current. (The Disable pin has no effect on the Serial Digital
Transceiver - it is always enabled as long as power is
applied to VCCD.)
Serial Digital Transceiver Operation
The digital transceiver is a half-duplex design, either
receiving data on the SIN pins and sending it out on the
SDATA pin, or transmitting data from the SDATA pin out on
some the 2 SOUT pins. The digital transceiver operates in a
high speed (up to 50MBaud) differential mode. The SDATA
pin is the half-duplex logic-level transmit and receive data
pin. SDATA is an output when Transmit = low (receive mode)
and an input when Transmit = high (transmit mode). This can
be made to work with existing designs that use independent
transmit and receive pins by connecting SDATA directly to the
transmit pin and through a resistor to the receive pin.
Figure 21 shows an example of how to interface the
ISL59311 with an RS485 transceiver.
VCCD is the power source for the digital line interface drivers
and receivers.
FN6372.3
April 25, 2007
ISL59311
+5V
+5V
+
19
VCCS
SDATA
11
R
SIN+
15
SIN-
16
SOUT+
12
TRANSMIT
SOUT-
17
0.1μF
0.1μF
+
8
VCC
D
RT
RT
13
7
B/Z
DE 3
6
A/Y
RE 2
R
D
GND
ISL59311
DI 4
RO 1
GND
7
5 ISL83088
FIGURE 21. RS-485 SERIAL INTERFACE CONNECTION DIAGRAM
Digital Transceiver Block Diagram
Proper Layout Technique
TXEN
TXDATA
(SDATA)
ENCODING
SOUT-
TRANSMIT
R1
R3
TWISTED PAIR LINE
SOUT+
A critical concern with any PCB layout is the establishment
of a “healthy” ground plane. It is imperative to provide
ground planes terminated close to inputs to minimize input
capacitance. Additionally, the ground plane can be
selectively removed from inputs to prevent load and supply
currents from flowing near the input nodes.
In general the following guidelines apply to all PCB layout:
• Keep all traces as short as possible.
• Keep power supply bypass components as close to the
chip as possible - extremely close.
• Create a healthy ground with low impedance and
continuous ground pathways available to all grounded
components board-wide.
• In high frequency applications on multi-level boards try to
keep one level of board with continuous ground plane and
minimum via cutouts - providing it is affordable.
SIN+
RDATA
(SDATA)
SIN-
12
• Provide extremely short loops from power pin to ground.
• If it is affordable, a ferrite bead is always of benefit to
isolate device from Power Supply noise and the rest of the
circuit from the noise of the device.
FN6372.3
April 25, 2007
ISL59311
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the
ISL59311 drive capability is ultimately limited by the rise in die
temperature brought about by internal power dissipation. For
reliable operation die temperature must be kept below TJMAX
(+125°C). It is necessary to calculate the power dissipation for
a given application prior to selecting package type. Power
dissipation may be calculated:
4
2
2
PD = ( V S × I S ) × Σ ( C INT × V S × f ) + ( C L × V OUT × f )
1
where:
• VS is the total power supply to the ISL59311 (= VCCD)
• VOUT is the swing on the output (VH - VL)
• CL is the load capacitance
• CINT is the internal load capacitance (80pF max)
• IS is the quiescent supply current
• f is frequency
Having obtained the application's power dissipation, the
maximum junction temperature can be calculated:
T JMAX = T MAX + Θ JA × PD
where:
• TJMAX is the maximum junction temperature (+125°C)
• TMAX is the maximum ambient operating temperature
• PD is the power dissipation calculated above
θJA is the thermal resistance, junction to ambient, of the
application (package + PCB combination). Refer to the
Package Power Dissipation curves. See Technical Bulletin
389 (http://www.intersil.com/data/tb/TB389.pdf) for additional
QFN PCB layout information.
13
FN6372.3
April 25, 2007
ISL59311
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L32.5x6A (One of 10 Packages in MDP0046)
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220)
A
MILLIMETERS
D
N
(N-1)
(N-2)
B
1
2
3
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
0.00
0.02
0.05
-
D
PIN #1
I.D. MARK
E
5.00 BSC
-
D2
2.48 REF
-
E
6.00 BSC
-
E2
(N/2)
2X
0.075 C
2X
0.075 C
0.45
b
0.20
-
0.50
0.55
-
0.22
0.24
-
c
0.20 REF
b
L
-
e
0.50 BSC
-
N
32 REF
4
ND
7 REF
6
NE
9 REF
5
0.10 M C A B
Rev 0 9/05
NOTES:
(N-2)
(N-1)
N
N LEADS
TOP VIEW
3.40 REF
L
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
PIN #1 I.D.
2. Tiebar view shown is a non-functional feature.
3
1
2
3
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
(E2)
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
NE 5
(N/2)
7. Inward end of terminal may be square or circular in shape with
radius (b/2) as shown.
7
(D2)
BOTTOM VIEW
0.10 C
e
C
(c)
SEATING
PLANE
0.08 C
N LEADS
& EXPOSED PAD
C
2
A
(L)
SEE DETAIL "X"
A1
SIDE VIEW
N LEADS
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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14
FN6372.3
April 25, 2007
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