DATASHEET

ISL55004
®
Data Sheet
July 27, 2006
High Supply Voltage 200MHz Unity-Gain
Stable Operational Amplifier
The ISL55004 is a high speed, low power, low cost
monolithic operational amplifier. The ISL55004 is unity-gain
stable and features a 300V/µs slew rate and 200MHz
bandwidth while requiring only 8.5mA of supply current per
amplifier.
The power supply operating range of the ISL55004 is from
±15V down to ±2.5V. For single-supply operation, the
ISL55004 operates from 30V down to 5V.
FN6219.2
Features
• 200MHz -3dB bandwidth
• Unity-gain stable
• Low supply current: 8.5mA per amplifier
• Wide supply range: ±2.5V to ±15V dual-supply and 5V to
30V single-supply
• High slew rate: 300V/µs
• Fast settling: 75ns to 0.1% for a 10V step
• Wide output voltage swing: -12.75V/+13.4V with
VS = ±15V, RL = 1kΩ
The ISL55004 also features an extremely wide output
voltage swing of -12.75V/+13.4V with VS = ±15V and
RL = 1kΩ.
• Enhanced replacement for EL2444
At a gain of +1, the ISL55004 has a -3dB bandwidth of
200MHz with a phase margin of 55°. Because of its
conventional voltage-feedback topology, the ISL55004 allow
the use of reactive or non-linear elements in its feedback
network. This versatility combined with low cost and 140mA
of output-current drive makes the ISL55004 an ideal choice
for price-sensitive applications requiring low power and high
speed.
• Pb-free plus anneal available (RoHS compliant)
The ISL55004 is in a 14 Ld SO (0.150”) package and
specified for operation over the full -40°C to +85°C
temperature range.
• High speed signal processing
Ordering Information
• Pulse/RF amplifiers
TAPE
&
PART
PART NUMBER MARKING REEL
Applications
• Video amplifiers
• Single-supply amplifiers
• Active filters/integrators
• High speed sample-and-hold
• ADC/DAC buffers
• Pin diode receivers
PACKAGE
PKG.
DWG. #
ISL55004IB
55004IB
-
14 Ld SO (0.150”) MDP0027
ISL55004IB-T7
55004IB
7”
14 Ld SO (0.150”) MDP0027
ISL55004IB-T13
55004IB
13”
14 Ld SO (0.150”) MDP0027
ISL55004IBZ
(See Note)
55004IBZ
-
14 Ld SO (0.150”) MDP0027
(Pb-Free)
ISL55004IBZ-T7 55004IBZ
(See Note)
7”
14 Ld SO (0.150”) MDP0027
(Pb-Free)
ISL55004IBZ-T13 55004IBZ
(See Note)
13”
14 Ld SO (0.150”) MDP0027
(Pb-Free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
• Log amplifiers
• Photo multiplier amplifiers
• Difference amplifiers
Pinout
ISL55004
[14 LD SO (0.150”)]
TOP VIEW
OUT1 1
IN1- 2
- +
+ -
13 IN4-
IN1+ 3
12 IN4+
VS+ 4
11 VS-
IN2+ 5
10 IN3+
IN2- 6
OUT2 7
1
14 OUT4
- +
+ -
9 IN38 OUT3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL55004
Absolute Maximum Ratings (TA = 25°C)
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Temperature Range (TA). . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature (TST) . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . ±16.5V or 33V
Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±VS
Differential Input Voltage (dVIN). . . . . . . . . . . . . . . . . . . . . . . . .±10V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER
VS = ±15V, AV = +1, RL = 1kΩ, TA = 25°C, unless otherwise specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
1.2
5
mV
VOS
Input Offset Voltage
TCVOS
Average Offset Voltage Drift (Note 1)
IB
Input Bias Current
VS = ±15V
0.6
3.5
µA
IOS
Input Offset Current
VS = ±15V
0.2
2
µA
TCIOS
Average Offset Current Drift (Note 1)
AVOL
Open-loop Gain
VS = ±15V, VOUT = ±10V, RL = 1kΩ
PSRR
Power Supply Rejection Ratio
CMRR
VS = ±15V
17
µV/°C
0.2
nA/°C
12000
21000
V/V
VS = ±5V to ±15V
75
100
dB
Common-mode Rejection Ratio
VCM = ±10V, VOUT = 0V
75
90
dB
CMIR
Common-mode Input Range
VS = ±15V
13
V
VOUT
Output Voltage Swing
VO+, RL = 1kΩ
13.25
13.4
V
VO-, RL = 1kΩ
-12.6
-12.75
V
VO+, RL = 150Ω
9.6
10.7
V
VO-, RL = 150Ω
-8.3
-9.4
V
80
140
mA
ISC
Output Short Circuit Current
IS
Supply Current (per amplifier)
RIN
Input Resistance
CIN
Input Capacitance
ROUT
PSOR
VS = ±15V, no load
8.5
2.0
9.25
mA
3.2
MΩ
AV = +1
1
pF
Output Resistance
AV = +1
50
mΩ
Power Supply Operating Range
Dual supply
Single supply
±2.25
±15
V
4.5
30
V
MAX
UNIT
NOTE:
1. Measured from TMIN to TMAX.
AC Electrical Specifications
PARAMETER
BW
VS = ±15V, AV = +1, RL = 1kΩ, TA = 25°C, unless otherwise specified.
DESCRIPTION
-3dB Bandwidth (VOUT = 0.4VPP)
CONDITION
MIN
TYP
VS = ±15V, AV = +1
200
MHz
VS = ±15V, AV = -1
55
MHz
VS = ±15V, AV = +2
53
MHz
VS = ±15V, AV = +5
17
MHz
GBWP
Gain Bandwidth Product
VS = ±15V
70
MHz
PM
Phase Margin
RL = 1kΩ, CL = 5pF
55
°
SR
Slew Rate (Note 1)
300
V/µs
2
260
FN6219.2
July 27, 2006
ISL55004
AC Electrical Specifications
PARAMETER
VS = ±15V, AV = +1, RL = 1kΩ, TA = 25°C, unless otherwise specified. (Continued)
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
FPBW
Full-power Bandwidth (Note 2)
VS = ±15V
9.5
MHz
tS
Settling to +0.1% (AV = +1)
VS = ±15V, 10V step
75
ns
dG
Differential Gain (Note 3)
NTSC/PAL
0.01
%
dP
Differential Phase
NTSC/PAL
0.05
°
eN
Input Noise Voltage
10kHz
12
nV/√Hz
iN
Input Noise Current
10kHz
1.5
pA/√Hz
NOTES:
1. Slew rate is measured on rising edge.
2. For VS = ±15V, VOUT = 10VPP, for VS = ±5V, VOUT = 5VPP. Full-power bandwidth is based on slew rate measurement using FPBW = SR/(2π *
VPEAK).
3. Video performance measured at VS = ±15V, AV = +2 with two times normal video level across RL = 150Ω. This corresponds to standard video
levels across a back-terminated 75Ω load. For other values or RL, see curves.
Typical Performance Curves
FIGURE 1. OPEN-LOOP GAIN vs FREQUENCY
FIGURE 2. OPEN-LOOP PHASE vs FREQUENCY
4
2
3
1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
3
4
VS = ±15V
RF = 500Ω
RL = 500Ω
AV = +1
0
AV = +2
-1
-2
AV = +5
-3
-4
-5
-6
100k
2
VS = ±15V
RF = 500Ω
RL = 500Ω
1
0
AV = -1
-1
AV = -2
-2
-3
AV = -5
-4
-5
1M
10M
100M
FREQUENCY (Hz)
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS NONINVERTING GAIN SETTINGS
3
1G
-6
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS INVERTING
GAIN SETTINGS
FN6219.2
July 27, 2006
ISL55004
Typical Performance Curves
(Continued)
FIGURE 5. PHASE vs FREQUENCY FOR VARIOUS NONINVERTING GAIN SETTINGS
GAIN BANDWIDTH PRODUCT (MHz)
100
FIGURE 6. PHASE vs FREQUENCY FOR VARIOUS
INVERTING GAIN SETTINGS
350
RL=500Ω
AV=+2
RF=500Ω
300 RL=500Ω
CL=5pF
SLEW RATE (V/µs)
80
60
40
POSITIVE SLEW RATE
250
NEGATIVE SLEW RATE
200
20
150
0
100
0
3
6
9
12
15
0
3
6
SUPPLY VOLTAGES (±V)
4
3
2
RL = 1kΩ
0
RL = 150Ω
-1
-2
RL = 500Ω
-3
RL = 50Ω
-4
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
VS = ±15V
RF = 0Ω
CL = 5pF
AV = +1
1
VS = ±15V
RF = 500Ω
CL = 5pF
AV = +2
RL = 500Ω
1
0
-1
RL = 1kΩ
RL = 150Ω
-2
RL = 50Ω
-3
-4
-5
-5
-6
100k
15
FIGURE 8. SLEW RATE vs SUPPLY
4
2
12
SUPPLY VOLTAGES (±V)
FIGURE 7. GAIN BANDWIDTH PRODUCT vs SUPPLY
3
9
1M
10M
100M
FREQUENCY (Hz)
FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS RLOAD
(AV = +1)
4
1G
-6
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS RLOAD
(AV = +2)
FN6219.2
July 27, 2006
ISL55004
Typical Performance Curves
(Continued)
4
4
VS = ±15V
RF = 0Ω
RL = 500Ω
AV = +1
NORMALIZED GAIN (dB)
2
CL = 27pF
1
CL = 15pF
0
CL = 5pF
-1
-2
-3
CL = 0pF
-4
VS = ±15V
RF = 500Ω
RL = 500Ω
AV = +2
3
CL = 47pF
NORMALIZED GAIN (dB)
3
2
CL = 100pF
1
CL = 39pF
0
CL = 22pF
-1
CL = 5pF
-2
-3
-4
-5
-5
-6
100k
1M
10M
100M
-6
100k
1G
1M
FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS CLOAD
(AV = +1)
RF = 100Ω
RF = 250Ω
-1
RF = 0Ω
-2
VS = ±15V
RL = 500Ω
CL = 5pF
AV = +2
3
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
RF = 500Ω
0
-3
-4
-5
2
RF = 500Ω
1
0
RF = 1kΩ
RF = 250Ω
-1
-2
RF = 100Ω
-3
-4
-5
-6
100k
1M
10M
100M
-6
100k
1G
1M
FREQUENCY (Hz)
1G
4
VS = ±15V
RF = 500Ω
RL = 500Ω
CL = 5pF
AV = +2
CIN = 10pF
3
CIN = 6.8pF
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
100M
FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS RFEEDBACK
(AV = +2)
4
1
10M
FREQUENCY (Hz)
FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS RFEEDBACK
(AV = +1)
2
1G
4
VS = ±15V
RL = 500Ω
CL = 5pF
AV = +1
1
3
100M
FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS CLOAD
(AV = +2)
4
2
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
3
CL = 68pF
CIN = 4.7pF
0
-1
CIN = 2.2pF
-2
CIN = 0pF
-3
-4
-5
-6
100k
2
RF = 0Ω
RL = 500Ω
CL = 5pF
AV = +1
VS = ±2.5V
1
0
VS = ±10V
-1
VS = ±15V
-2
-3
VS = ±5V
-4
-5
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS INVERTING
INPUT CAPACITANCE (CIN)
5
-6
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 16. GAIN vs FREQUENCY FOR VARIOUS SUPPLY
SETTINGS
FN6219.2
July 27, 2006
ISL55004
Typical Performance Curves
(Continued)
FIGURE 17. COMMON-MODE REJECTION RATIO (CMRR)
FIGURE 18. POWER SUPPLY REJECTION RATIO (PSRR)
HARMONIC DISTORTION (dBc)
-20
VS=±15V
-30 AV=+1
RF=0Ω
-40 RL=500Ω
CL=5pF
-50 VOUT=2VP-P
THD
-60
2ND HD
-70
3RD HD
-80
-90
-100
500K
1M
10M
40M
FREQUENCY (Hz)
FIGURE 19. HARMONIC DISTORTION vs FREQUENCY
(AV = +1)
FIGURE 20. HARMONIC DISTORTION vs OUTPUT VOLTAGE
(AV = +2)
OUTPUT VOLTAGE SWING (Vp-p)
25
RL=500Ω
CL=5pF
AV=+1
20
AV=+2
RF=500Ω
15
10
5
0
0
3
6
9
12
15
SUPPLY VOLTAGES (±V)
FIGURE 21. OUTPUT SWING vs FREQUENCY FOR VARIOUS
GAIN SETTINGS
6
FIGURE 22. OUTPUT SWING vs SUPPLY VOLTAGE FOR
VARIOUS GAIN SETTINGS
FN6219.2
July 27, 2006
ISL55004
Typical Performance Curves
(Continued)
20% to 80% 80% to 20%
20% to 80%
80% to 20%
FIGURE 23. LARGE SIGNAL RISE AND FALL TIMES
FIGURE 24. SMALL SIGNAL RISE AND FALL TIMES
1.2
POWER DISSIPATION (W)
TOTAL SUPPLY CURRENT [mA]
25
20
15
10
AV=+1
RF=0Ω
RL=500Ω
CL=5pF
5
0
0
3
6
9
12
0.8
0.6
0.4
0.2
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 25. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.6
POWER DISSIPATION (W)
SO14
θJA=120°C/W
1 1.042W
0
15
SUPPLY VOLTAGES (±V)
1.8
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.420W
1.4
SO14
θJA=88°C/W
1.2
1
0.8
0.6
0.4
0.2
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
7
FN6219.2
July 27, 2006
ISL55004
Product Description
The ISL55004 is a wide bandwidth, low power, and low offset
voltage feedback operational amplifier. This device is
internally compensated for closed loop gain of +1 or greater.
Connected in voltage follower mode and driving a 500Ω
load, the -3dB bandwidth is around a 200MHz. Driving a
150Ω load and a gain of 2, the bandwidth is about 90MHz
while maintaining a 300V/µs slew rate.
The ISL55004 is designed to operate with supply voltage
from +15V to -15V. That means for single supply application,
the supply voltage is from 0V to 30V. For split supplies
application, the supply voltage is from ±15V. The amplifier
has an input common-mode voltage range from 1.5V above
the negative supply (VS- pin) to 1.5V below the positive
supply (VS+ pin). If the input signal is outside the above
specified range, it will cause the output signal to be distorted.
The outputs of the ISL55004 can swing from -12.75V to
+13.4V for VS = ±15V. As the load resistance becomes
lower, the output swing is lower.
Choice of Feedback Resistor and Gain Bandwidth
Product
For applications that require a gain of +1, no feedback
resistor is required. Just short the output pin to the inverting
input pin. For gains greater than +1, the feedback resistor
forms a pole with the parasitic capacitance at the inverting
input. As this pole becomes smaller, the amplifier's phase
margin is reduced. This causes ringing in the time domain
and peaking in the frequency domain. Therefore, RF can't be
very big for optimum performance. If a large value of RF
must be used, a small capacitor in the few Pico Farad range
in parallel with RF can help to reduce the ringing and
peaking at the expense of reducing the bandwidth. For gain
of +1, RF = 0 is optimum. For the gains other than +1,
optimum response is obtained with RF with proper selection
of RF and RG (see Figures15 and 16 for selection).
Video Performance
For good video performance, an amplifier is required to
maintain the same output impedance and the same
frequency response as DC levels are changed at the output.
This is especially difficult when driving a standard video load
of 150Ω, because of the change in output current with DC
level. The dG and dP of this device is about 0.01% and
0.05°, while driving 150Ω at a gain of 2. Driving high
impedance loads would give a similar or better dG and dP
performance.
Driving Capacitive Loads and Cables
The ISL55004 can drive 47pF loads in parallel with 500Ω
with less than 3dB of peaking at gain of +1 and as much as
100pF at a gain of +2 with under 3db of peaking. If less
peaking is desired in applications, a small series resistor
(usually between 5Ω to 50Ω) can be placed in series with the
output to eliminate most peaking. However, this will reduce
8
the gain slightly. If the gain setting is greater than 1, the gain
resistor RG can then be chosen to make up for any gain loss
which may be created by the additional series resistor at the
output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Output Drive Capability
The ISL55004 does not have internal short circuit protection
circuitry. It has a typical short circuit current of 140mA. If the
output is shorted indefinitely, the power dissipation could
easily overheat the die or the current could eventually
compromise metal integrity. Maximum reliability is
maintained if the output current never exceeds ±60mA. This
limit is set by the design of the internal metal interconnect.
Note that in transient applications, the part is robust.
Short circuit protection can be provided externally with a
back match resistor in series with the output placed close as
possible to the output pin. In video applications this would be
a 75Ω resistor and will provide adequate short circuit
protection to the device. Care should still be taken not to
stress the device with a short at the output.
Power Dissipation
With the high output drive capability of the ISL55004, it is
possible to exceed the 150°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for an application to determine if load conditions
or package types need to be modified to assure operation of
the amplifier in a safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX – T AMAX
PD MAX = -------------------------------------------Θ JA
Where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
FN6219.2
July 27, 2006
ISL55004
Application Circuits
For sourcing:
n
V OUTi
∑ ( VS – VOUTi ) × ---------------R Li
PD MAX = V S × I SMAX +
i=1
For sinking:
n
∑ ( VOUTi – VS ) × ILOADi
PD MAX = V S × I SMAX +
i=1
Sallen Key Low Pass Filter
A common and easy to implement filter taking advantage of
the wide bandwidth, low offset and low power demands of
the ISL55004. A derivation of the transfer function is
provided for convenience (See Figure 28).
Sallen Key High Pass Filter
Again this useful filter benefits from the characteristics of the
ISL55004. The transfer function is very similar to the low
pass so only the results are presented (See Figure 29).
Where:
• VS = Supply voltage
• ISMAX = Maximum quiescent supply current
• VOUT = Maximum output voltage of the application
• RLOAD = Load resistance tied to ground
• ILOAD = Load current
• N = number of amplifiers (max = 4)
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOAD to avoid the device
overheat.
Caution: For supply voltages greater then 20V, the
maximum power dissipation at 85°C ambient temperature
could be exceeded. For higher supply voltages the
maximum ambient temperature must be de-rated according
to the Package Power Dissipation curve Figure 27. The
maximum power dissipation is highly dependent upon the
thermal conductivity of the PCB. For lower thermal
conductivity boards use Figure 26.
Power Supply Bypassing Printed Circuit Board
Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possible. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail.
Printed Circuit Board Layout
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
9
FN6219.2
July 27, 2006
ISL55004
K = 1+
V2
5V
1
V1
R2C2s + 1
Vo
V1 − Vi
Vo − Vi
K
1 + − V1 +
=0
1
R1
R2
C1s
K
H(s) =
R1C1R2C2s 2 + ((1 − K )R1C1 + R1C2 + R21C2)s + 1
1
H( jw ) =
2
1 − w R1C1R2C2 + jw ((1 − K )R1C1 + R1C2 + R2C2)
Vo = K
C5
1nF
C1
1nF
R1
R2
1kΩ
V1
1kΩ C2
1nF
+
V+
-
V-
RB
RA
VOUT
R7
1kΩ
RB
Holp = K
1kΩ
RA
1kΩ
1
wo =
C5
R1C1R2C2
1nF
1
Q=
R1C1
R1C2
R2C2
+
+
(1 − K )
R2C2
R2C1
R1C1
V3
5V
Holp = K
FIGURE 28. SALLEN KEY LOW PASS FILTER
Equations simplify if we let all
components be equal R=C
1
wo =
RC
1
Q=
3 −K
V2
5V
Holp = K
C5
1
wo =
R1C1R2C2
1nF
R1C1
R1C2
R2C2
+
+
(1 − K )
R2C2
R2C1
R1C1
1nF
R1
V1
1kΩ
R2
1kΩ C2
1nF
1
Q=
C1
+
V+
-
V-
VOUT
R7
1kΩ
RB
Holp =
1kΩ
RA
1kΩ
C5
wo =
1nF
V3
5V
Q=
K
4 −K
2
RC
Equations simplify if we let
all components be equal R=C
2
4 −K
FIGURE 29. SALLEN KEY HIGH PASS FILTER
10
FN6219.2
July 27, 2006
ISL55004
Differential Output Instrumentation Amplifier
e o3 = – ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 )
The addition of a third amplifier to the conventional three
amplifier instrumentation amplifier introduces the benefits of
differential signal realization, specifically the advantage of
using common-mode rejection to remove coupled noise and
ground potential errors inherent in remote transmission. This
configuration also provides enhanced bandwidth, wider
output swing and faster slew rate than conventional three
amplifier solutions with only the cost of an additional
amplifier and few resistors.
e1
A1
+
-
R3
A3
+
RG
R3
R3
R3
R3
A4
R2
A2
e2
+
e o = – 2 ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 )
2f C1, 2
BW = ----------------A Di
+
R3
A Di = – 2 ( 1 + 2R 2 ⁄ R G )
Strain Gauge
The strain gauge is an ideal application to take advantage of
the moderate bandwidth and high accuracy of the ISL55004.
The operation of the circuit is very straightforward. As the
strain variable component resistor in the balanced bridge is
subjected to increasing strain, its resistance changes,
resulting in an imbalance in the bridge. A voltage variation
from the referenced high accuracy source is generated and
translated to the difference amplifier through the buffer
stage. This voltage difference as a function of the strain is
converted into an output voltage.
R3
R2
e o4 = ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 )
eo3
+
REF
eo
eo4
R3
FIGURE 30. DIFFERENTIAL OUTPUT AMPLIFIER
+V
2
5V
C6
VARIABLE SUBJECT
TO STRAIN
V5 +
0V
-
R15
1kΩ
1kΩ
R16
1kΩ
1nF
R17
1kΩ
R18
1kΩ
1kΩ
+
V+
-
V-
VOUT
RL
(V1+V2+V3+V4)
1kΩ
RF
1kΩ
C12
1nF
+
V4
- 5V
FIGURE 31. STRAIN GAUGE
11
FN6219.2
July 27, 2006
ISL55004
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
SO-8
SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
N
8
14
16
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN6219.2
July 27, 2006
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