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Data
Sheet
December 12, 2012
T
N
1-888-I
ISL99202
FN6758.2
60mW, Capfree, Stereo Headphone
Amplifier
Features
The ISL99202 is a stereo, capfree headphone amplifier. The
wide operating voltage of 2.4V to 5.5V makes it versatile
enough to be used in mobile battery powered applications
powered by 2 AA or Single cell Li-Ion batteries as well as
3.3/5V power supply available notebook computers.
• Ground referenced: No output coupling capacitors
• Supports 16Ω to 600Ω speaker impedance
The ISL99202 has robust RF immunity, which makes it
ideally suited for today’s mobile applications.
• Audiophile quality sound THD of 0.01%, SNR of 102dB
• PSRR < -90dB, no need for LDO
• Wide operating voltage of 2.4V to 5.5V
• < 3mA quiescent current and 0.1µA shutdown current
It has audiophile quality SNR and THD specifications and
Click/Pop suppression.
• State of the art pop and click suppression
• Pb-Free (RoHS Compliant)
The ISL99202 comes with Comprehensive Protection
features, which include undervoltage and short-circuit
protection and thermal shutdown.
Applications
The ISL99202 lowest power consumption in the industry is
achieved by low Iqq and current shutdown.
• MP3 players
• Mobile phones
The product is available in 12 Ld TQFN.
Ordering Information
PART
NUMBER
PART
MARKING
GAIN SETTING
(dB)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL99202IRTAZ (Notes 1, 2)
202A
-1.5V/V
-40 to +85
12 Ld 3x3 TQFN
L12.3x3Z
ISL99202IRTAZ-T (Notes 1, 2)
202A
-1.5V/V
-40 to +85
12 Ld 3x3 TQFN
L12.3x3Z
ISL99202IRTAZ-TK (Notes 1, 2) 202A
-1.5V/V
-40 to +85
12 Ld 3x3 TQFN
L12.3x3Z
ISL99202IRTAEVZ
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-20.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009, 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL99202
Pinouts
10 OUTR
11 OUTL
12 VDD
ISL99202
(12 LD TQFN)
TOP VIEW
CP 1
9 SVSS
THERMAL
PAD
PGND 2
INL 6
SDB 5
7 SGND
PVSS 4
CN 3
8 INR
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1
CP
2
PGND
3
CN
4
PVSS
5
SDB
Active low shutdown input
6
INL
Left channel input
7
SGND
8
INR
9
SVSS
Amplifier negative supply
10
OUTR
Right channel output
11
OUTL
Left channel output
12
VDD
Positive power supply
Charge pump positive terminal
Charge pump Ground
Charge pump negative terminal
Charge pump output
Analog ground
Right channel input
NOTE: Exposed Pad is connected to PGND and SGND
2
FN6758.2
December 12, 2012
ISL99202
Absolute Maximum Ratings (Reference to GND)
Thermal Information
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
INR, INL, CP, SDB . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
ESD Rating
Human Body Model
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
OUTL, OUTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Thermal Resistance (Typical, Notes 3, 4) JA (°C/W)
JC (°C/W)
TQFN Package . . . . . . . . . . . . . . . . . . . .
54
8
Maximum Junction Temperature (Plastic Package) -65°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Dissipation Ratings
Derating Factor
12 LD 3x3 TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . .14.7mW/°C
Power Rating TA
12 Ld 3x3 TQFN
+25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.84W
+70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.12W
+85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.96W
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Supply Voltage (VDD Pin) . . . . . . . . . . . . . . . . . . . . . 5.5V
Operating Supply Voltage (VDD Pin) . . . . . . . . . . . . . . . . 2.4V to 5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For theta JC the “case temp.” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Typical Values are Tested at VDD = 5V, TA = +25°C and RL = 32.
PARAMETER
MIN
(Note 5)
TYP
30
63
mW
70
mW
RL = 1k,VOUT = 1.5VRMS, f = 1kHz
0.003
%
RL = 32,POUT = 50mW, f = 1kHz
0.01
%
RL = 16,POUT = 35mW, f = 1kHz
0.02
%
160
°C
15
°C
200
mA
SYMBOL
TEST CONDITIONS
MAX
(Note 5) UNITS
OUTPUT POWER
Output Power
POUT
RL = 32,THD = 1%
RL = 16
Total Harmonic Distortion + Ratio
THD+N
PROTECTION
Thermal Shutdown
OTP
Thermal Shutdown Hysteresis
Overcurrent Protection
OCP
Undervoltage Shutdown
2.4
V
LOGIC INPUTS (SDB)
Input Voltage High
VINH
Input Voltage Low
VINL
1.4
V
0.9
V
5.5
V
POWER SUPPLY
Supply Voltage Range
VDD
Power Supply Rejection Ratio
PSRR
Quiescent Current
Iqq
Shutdown Current
ISDB
3
2.4
VDD = 2.5V to 5.0V at 217Hz
96
dB
VDD = 2.5V to 5.0V at 1kHz
88
dB
VDD = 2.5V to 5.0V at 20kHz
76
dB
VDD = 5.0V
3
4.6
mA
0.1
1.1
µA
SDB = GND, VDD = 5.0V
FN6758.2
December 12, 2012
ISL99202
Electrical Specifications Typical Values are Tested at VDD = 5V, TA = +25°C and RL = 32. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 5)
TYP
-1.55
-1.50
MAX
(Note 5) UNITS
GAIN CONTROL
Voltage Gain
AV
THD+N
V/V
±0.15
%
RL = 1k,VOUT = 1.5VRMS, f = 1kHz
0.005
%
RL = 32,POUT = 50mW, f = 1kHz
0.01
%
RL = 16,POUT = 35mW, f = 1kHz
0.04
%
RL = 1k, VOUT = 1.5VRMS, BW = 22Hz to 20kHz
102
dB
RL = 1k, VOUT = 1.5VRMS, BW = 22Hz to 20kHz, A-weighted
105
dB
RL = 32, POUT = 35mW, BW = 22Hz to 20kHz
100
dB
RL = 32, POUT = 35mW, BW = 22Hz to 20kHz, A-weighted
113
dB
Ch to Ch Gain Tracking
Total Harmonic Distortion + Ratio
-1.45
NOISE PERFORMANCE
Signal to Noise Ratio
SNR
Slew Rate
SR
0.5
VµS
Capacitve Drive
CL
100
pF
-76
dB
Crosstalk
xtalk
Charge Pump Oscillation
Frequency
fsoc
Click and Pop Level
KCP
RL = 16,POUT = 15mW, f = 10kHz
400
500
600
kHz
RL = 32,Peak voltage, Awtg. 32 sam/sec
-67
dB
217Hz
96
dB
1kHz
88
dB
20kHz
76
dB
VDD = 3.0V
Power Supply Rejection Ratio
PSRR
Quiescent Current
Iqq
Shutdown Current
ISDB
Output Offset Voltage
VOS
SDB = GND
-1
2.4
3.6
mA
0.1
1.1
µA
0.05
1
mV
Output Power at 32Load
RL = 32,THD = 1%
54
mW
Output Power at 16Load
RL = 16,THD = 1%
56
mW
RL = 1k,VOUT = 1.5VRMS, f = 1kHz
0.005
%
RL = 32,POUT = 50mW, f = 1kHz
0.01
%
RL = 16,POUT = 35mW, f = 1kHz
0.02
%
Total Harmonic Distortion + Noise
Ratio
THD+N
NOTE:
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
4
FN6758.2
December 12, 2012
ISL99202
Block Diagram
VDD
SDB
CLICK AND POP
SUPPRESSION
SDB LOGIC
PVSS
POSITIVE VOLTAGE
REGULATOR
BIAS AND REFERENCE
INR
OUTR
AMPR
+
SGND
OVERCURRENT
PROTECTION
SVSS
+
OUTL
AMPL
-
INL
PGND
DYNAMICALLY
ADJUSTED
VOLTAGE
REGULATOR
CLOCK GENERATOR
PVSS
CP
CN
Typical Performance Curves
100
100
10
THD + NOISE RATIO (%)
THD + NOISE RATIO (%)
VDD = 3V
RL = 16
1.0
20Hz
10kHz
0.1
VDD = 3V
RL = 32
10kHz
10
1.0
20Hz
0.1
0.01
0.01
1kHz
1kHz
0.001
1
10
100
OUTPUT POWER (mW)
FIGURE 1. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs OUTPUT POWER
5
0.001
1
10
100
OUTPUT POWER (mW)
FIGURE 2. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs OUTPUT POWER
FN6758.2
December 12, 2012
ISL99202
Typical Performance Curves (Continued)
100
VDD = 3V
RL = 32
10kHz
10
1.0
THD + NOISE RATIO (%)
THD + NOISE RATIO (%)
100
20Hz
0.1
VDD = 5V
RL = 32
10kHz
10
1.0
20Hz
0.1
0.01
0.01
1kHz
0.001
1
10
100
1kHz
0.001
1
10
FIGURE 3. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs OUTPUT POWER
FIGURE 4. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs OUTPUT POWER
10
10
VDD = 5V
RL = 16
THD + NOISE RATIO (%)
THD + NOISE RATIO (%)
VDD = 3V
RL = 16
1.0
POUT = 10mW
0.1
0.01
1.0
POUT = 20mW
0.1
0.01
POUT = 40mW
POUT = 5mW
0.001
10
100
1k
10k
100k
0.001
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs FREQUENCY
FIGURE 6. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs FREQUENCY
10
10
VDD = 3V
RL = 32
VDD = 5V
RL = 32
1.0
THD + NOISE RATIO (%)
THD + NOISE RATIO (%)
100
OUTPUT POWER (mW)
OUTPUT POWER (mW)
0.1
POUT = 15mW
0.01
1.0
0.1
POUT = 50mW
0.01
POUT = 30mW
POUT = 10mW
0.001
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 7. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs FREQUENCY
6
0.001
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 8. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs FREQUENCY
FN6758.2
December 12, 2012
ISL99202
Typical Performance Curves (Continued)
0
-30
RL = 32
-20
CROSSTALK (dB)
-40
-40
PSRR(dB)
VDD = 5V
RL = 16
-60
VDD = 5V
-80
-100
100
1k
RIGHT TO LEFT
-60
-70
VDD = 3V
-120
10
-50
10k
LEFT TO RIGHT
-80
10
100k
100
FIGURE 9. POWER SUPPLY REJECTION RATIO vs
FREQUENCY
FIGURE 10. CROSSTALK vs FREQUENCY
70
90
RL = 32 (STEREO INPUT)
80
POWER DISSIPATION (mW)
60
POWER DISSIPATION (MW)
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
50
40
30
20
10
0
10k
1k
RL = 16 (STEREO INPUT)
70
60
50
40
30
20
10
5
15
25
35
45
55
0
65
5
15
25
OUTPUT POWER (mW)
35
45
55
65
75
85
95
OUTPUT POWER (mW)
FIGURE 11. POWER DISSIPATION vs OUTPUT POWER
FIGURE 12. POWER DISSIPATION vs OUTPUT POWER
90
RL = 32
NO LOAD INPUTS GND
80
OUTPUT POWER (mW)
SHUTDOWN CURRENT (nA)
255
205
155
105
55
5
2.4
THD + N = 10%
fIN = 1kHz
70
THD + N = 1%
60
50
40
2.9
3.4
3.9
4.4
4.9
5.4
SUPPLY VOLTAGE (V)
FIGURE 13. SHUTDOWN CURRENT vs SUPPLY VOLTAGE
7
30
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
FIGURE 14. OUTPUT POWER vs SUPPLY VOLTAGE
FN6758.2
December 12, 2012
ISL99202
Typical Performance Curves (Continued)
100
fIN = 1kHz
THD + N = 10%
80
OUTPUT POWER (W)
OUTPUT POWER (mW)
90
RL = 16
70
THD + N = 1%
60
50
40
30
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.100
0.095
0.090
0.085
0.080
0.075
0.070
0.065
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
10
VDD = 5V
fIN = 1kHz
THD + N = 10%
THD + N = 1%
100
SUPPLY VOLTAGE (V)
THD + N = 10%
FIGURE 16. OUTPUT POWER vs LOAD RESISTANCE
VDD = 3V
fIN = 1kHz
3.6
SUPPLY CURRENT (mA)
OUTPUT POWER (W)
FIGURE 15. OUTPUT POWER vs SUPPLY VOLTAGE
0.080
0.075
0.070
0.065
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
10
1k
LOAD RESISTANCE ()
THD + N = 1%
NO LOAD INPUTS GND
INPUT GND
3.4
3.2
3.0
2.8
2.6
100
LOAD RESISTANCE ()
FIGURE 17. OUTPUT POWER vs. LOAD RESISTANCE
FIGURE 19. CHARGE PUMP RESPONSE FOR SDB GOING
HIGH
8
1k
2.4
2.4
2.9
3.4
3.9
4.4
4.9
5.4
5.9
SUPPLY VOLTAGE (V)
FIGURE 18. SUPPLY CURRENT vs. SUPPLY VOLTAGE
FIGURE 20. CHARGE PUMP RESPONSE FOR SDB GOING
LOW
FN6758.2
December 12, 2012
ISL99202
Typical Application Circuit
ISL99202
INL
LEFT
-
AUDIO INPUT
1µF
OUTL
+
+
INR
RIGHT
OUTR
-
AUDIO INPUT
1µF
9
FN6758.2
December 12, 2012
ISL99202
Detailed Description
RF Immunity
The ISL99202 incorporates a novel proprietary architecture
to eliminate the large output capacitors associated with
single supply headphone amplifiers. Traditional charge
pump based architectures that eliminated the output
capacitors required additional power to operate the charge
pump, which made them ill-suited for portable battery
powered applications. The ISL99202 architecture eliminates
the need for large output capacitors while consuming
industry’s lowest quiescent and shutdown currents.
Most portable applications for ISL99202 are subject to RF
radiation from a myriad of sources, like Wi-Fi networks or
cellular phone networks. Though these signals are not in the
audio band, they can interfere with the audio signals through
complex non-linear mechanisms, aliasing or demodulations
to create audio band noise. The ISL99202 architecture
prevents this coupling into audio band to achieve superior
audio performance.
Capfree Architecture
The ISL99202 has comprehensive protection circuitry, which
protects the part due to undervoltage, over-temperature and
overcurrent. There is hysteresis built into over-temperature
and undervoltage, while the overcurrent is designed to limit
the output current in case of accidental short circuit or low
impedance headphone load connection.
At the core of the Capfree architecture is a dynamically
adjusted negative voltage regulator. By continuously
monitoring the output power requirements, it adjusts the
energy delivery circuitry. The feedback system ensures that
overhead power required to deliver audio at the headphone
speaker is always optimized for lower power dissipation.
Integrated LDO
A high precision LDO integrated into the power path of the
amplifier accounts for a 92dB PSRR. This eliminates the
need for a dedicated LDO used in some systems resulting in
BOM/cost savings.
Protection Circuitry
References
Intersil Technical Brief 389: “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
http://www.intersil.com/data/tb/tb389.pdf
Offset Cancellation Circuitry
The DC offset is a very important parameter. It is a principal
contributor to Click and Pop. In the cast Capfree
architecture, the DC offset can also be a source of DC
current in quiescent state. The ISL99202 is tested and
trimmed to have very low offset voltages (typically 50µV).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN6758.2
December 12, 2012
ISL99202
Package Outline Drawing
L12.3x3Z
12 LEAD THIN QUAD FLAT NO LEAD PLASTIC PACKAGE
FOR ISL99202 USE ONLY WITH REDUCED e-PAD SIZE TO 1.4mm ON LAND PATTERN
Rev 0, 10/08
3.00
0.5
BSC
A
B
6
12
10
PIN #1 INDEX AREA
6
3.00
4X 1.70 REF
PIN 1
INDEX AREA
9
1
7
3
0.10 M C A B
(4X)
0.15
4
6
0.25 +0.07 / -0.05
4
12X 0 . 4 ± 0 .
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 75
C
BASE PLANE
( 2 . 8 TYP )
1.40 )
SEATING PLANE
0.08 C
(
SIDE VIEW
0.6
C
0 . 50
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
0 . 25
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to JEDEC STD MO-229.
3. Unless otherwise specified, tolerance : Decimal ± 0.0
4. Dimension b applies to the metallized terminal and is measured
between 0.20mm and 0.32mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
11
FN6758.2
December 12, 2012
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