The Integration Enabler SONY IMAGE SENSOR BRIDGE Lattice FPGAs offer you the freedom to connect between Sony¹s broad line of CMOS image sensors and various industry standard applications processors (APs) or image signal processors (ISPs), thus giving you the ability to design your next camera-based sub-systems without compromise. You get the needed flexibility without busting your space, power or cost constraints. Don’t get caught between emerging standards and fixed interface protocols. sub-LVDS to CSI-2 Bridge CMOS Image Sensor sub-LVDS TX sub-LVDS RX CSI-2 RX MIPI CSI-2 TX ■ sub-LVDS ■ 1 clock with 4 to 10 lanes ■ Up to 900 Mbps/lane Applications Processors or ISP ■ CSI-2 ■ 4 to 10 lanes capable ■ Up to 800 Mbps/lane Sony sub-LVDS Image Sensor Bridge Interfaces already available in multiple configurations Sony CIS Bridge Examples Sony sub-LVDS Interface Sony IMX Example AP/ISP Interface 4 data IMX136 Parallel IMX172 CSI-2 IMX236 CSI-2 8 data IMX178 10 data IMX226 4 data Max AP/ISP Data Bit Bus Speed Smallest Package Size 12 bits 162 Mhz 49 wlcsp 4 data lanes 900 Mbps 49 wlcsp 4 data lanes 900 Mbps 49 wlcsp CSI-2 4 data lanes 900 Mbps 81 wlcsp CSI-2 4 - 8 data lanes 900 Mbps 121 fcBGA AP/ISP Max Bus Width Lattice’s low power, low cost XO2, XO3L and ECP5 offered in amazingly small packages! (see reverse for details) 49 WLCSP 81 WLCSP 121 fcBGA 132 csBGA 3.2 x 3.2 mm 0.4 mm pitch 3.8 x 3.7 mm 0.4 mm pitch 6.0 x 6.0 mm 0.5 mm pitch 8.0 x 8.0 mm 0.5 mm pitch ENABLER Integration SONY IMAGE SENSOR BRIDGE The A variety of bridging possibilities available! Dual Image Sensor Bridge Dual CSI-2 Bridge CSI-2 1-4 Data Lanes CSI- 2 Dual Image Sensors CSI-2 1-4 Data Lanes 2 CSI- Image Sensor Extender Sensor Extender Tx 3D Stereoscopic Image Image Sensor CSI-2 Parallel HiSPI ■ CSI-2 for ISP/AP CSI-2, HiSPI, sub-LVDS, etc. Serial LVDS CAT 5E/6 cable Output frame arrangement Sensor Extender Rx ■ Side by side ■ Top and bottom CSI-2, HiSPI, sub-LVDS, etc. Serial LVDS ■ Parallel for ISP/USB 3.0 ■ HiSPi for ISP Applications Processor/ISP Choose from Lattice’s array of integration solutions and speed your design to market. XO2 Series 49 WLCSP 132 csBGA 256 csBGA (3.2 x 3.2 mm) 0.4 mm pitch (8 x 8 mm) 0.5 mm pitch (14 x 14 mm) 0.8 mm pitch LUTs 2000 4000 7000 D-Phy speed/lane (Mbps) 420 750 750 (smallest package option only shown) D-PHY interfaces Rx/Tx MachXO2 1/1 2/1 2/2 XO2-2000ZE XO2-4000 XO2-7000 (3.2 x 3.1 mm) 0.4 mm pitch (3.7 x 3.8 mm) 0.4 mm pitch 81 WLCSP 121 csfBGA 121 csfBGA 256 csfBGA LUTs 2100 4300 1300 2100 6900 D-Phy speed/lane (Mbps) 900 900 900 900 900 D-PHY interfaces Rx/Tx 1/1 2/2 2/1 2/2 2/2 XO3L-2100 XO3L-4300 XO3L-1300 XO3L-2100 XO3L-6900 XO3L Series (smallest package option only shown) MachXO3L ECP5 Series 49 WLCSP 285 csfBGA (6 x 6 mm) 0.5 mm pitch 285 csfBGA (6 x 6 mm) 0.5 mm pitch (9 x 9 mm) 0.5 mm pitch 285 csfBGA (10x10 mm) 0.5 mm pitch (10x10 mm) 0.5 mm pitch (10x10 mm) 0.5 mm pitch 24000 45000 84000 D-Phy speed/lane (Mbps) 800 800 800 D-PHY interfaces Rx/Tx 2/2 2/2 2/2 LFE5U-25* LFE5U-45* LFE5U-85* (smallest package option only shown) LUTs ECP5 * Available in mass production in early 2015 Get more information at: www.latticesemi.com/sonysublvds Applications Support [email protected] Copyright © 2015 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), MachXO2TM, MachO3LTM and ECP5TM are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. September 2015 Order #: I0244 Rev. 2 LATTICESEMI.COM