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January 17, 2002
NO t oData
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8-INT
1-88
EL5283
®
Window 8ns High-Speed Comparator
Features
The EL5283 comparator is designed
for operation in single supply and dual
supply applications with 5V to 12V
between VS+ and VS-. For single supplies, the inputs can
operate from 0.1V below ground for use in ground-sensing
applications.
• 8ns typ. propagation delay
FN7189
• 5V to 12V input supply
• +2.7V to +5V output supply
• True-to-ground input
• Rail-to-rail outputs
The output side of the comparators can be supplied from a
single supply of 2.7V to 5V. The rail-to-rail output swing
enables direct connection of the comparator to both CMOS
and TTL logic circuits.
The latch input of the EL5283 can be used to hold the
comparator output value by applying a low logic level to the
pin.
The EL5283 is a window comparator. A single input is
compared with a high reference and a low. When the output
goes beyond one of these reference signals, the relevant
output goes low.
The EL5283 is available in the 10-pin MSOP package and is
specified for operation over the full -40°C to +85°C
temperature range. Also available are a single (EL5181) and
quad versions (EL5481 and EL5482).
• Active low latch
• Single available (EL5181)
• Dual available (EL5281)
• Quad available (EL5481 & EL5482)
• Pin-compatible 4ns family available (EL5x85, EL5287 &
EL5486)
Applications
• Threshold detection
• High speed sampling circuits
• High speed triggers
• Line receivers
• PWM circuits
Pinout
• High speed V/F converters
EL5283
(10-PIN MSOP)
TOP VIEW
Ordering Information
PART NUMBER
VS+
VREFH
1
2
PACKAGE
TAPE & REEL
PKG. NO.
EL5283CY
10-Pin MSOP
-
MDP0043
EL5283CY-T13
10-Pin MSOP
13”
MDP0043
10 VSD
+
9
OUTH
8
LATCH
7
OUTL
6
GND
IN
3
+
VREFL
4
VS-
5
-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL5283
Absolute Maximum Ratings (TA = 25°C)
Analog Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . +12.6V
Digital Supply Voltage (VSD to GND) . . . . . . . . . . . . . . . . . . . . .+7V
Differential Input Voltage . . . . . . . . . . .[(VS-) -0.2V] to [(VS+) +0.2V]
Common-mode Input Voltage . . . . . . .[(VS-) -0.2V] to [(VS+) +0.2V]
Latch Input Voltage . . . . . . . . . . . . . . . . . . . . -0.2V to [(VSD) +0.2V]
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS = ±5V, VSD = 5V, RL = 2.3kΩ, TA = 25°C, unless otherwise specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
1
4
mV
INPUT
VOS
Input Offset Voltage
IB
Input Bias Current
CIN
Input Capacitance
VCM
Input Voltage Range
CMRR
Common-mode Rejection Ratio
-5.1V < VCM < +2.75V
VOH
Output High Voltage
VIN > 250mV
VOL
Output Low Voltage
VIN > 250mV
VCM = 0V, VO = 2.5V
-6
-3.5
µA
5
pF
(VS-) - 0.1
(VS+) - 2.25
V
65
90
dB
VSD - 0.6
VSD - 0.4
V
OUTPUT
GND + 0.25
GND + 0.5
V
DYNAMIC PERFORMANCE
tPD+
Positive Going Delay Time
VIN = 1VP-P, VOD = 50mV
8
12
ns
tPD-
Negative Going Delay Time
VIN = 1VP-P, VOD = 50mV
8
12
ns
IS+
Positive Analog Supply Current
Per comparator
7
8.2
mA
IS-
Negative Analog Supply Current
Per comparator
5
6.5
mA
ISD
Digital Supply Current at No Load
Per comparator, output high
4
5
mA
Per comparator, output low
0.75
1
mA
SUPPLY
PSRR
Power Supply Rejection Ratio
60
80
dB
LATCH
VLH
Latch Input Voltage High
VLL
Latch Input Voltage Low
ILH
Latch Input Current High
VLH = 3.0V
-50
-30
µA
ILL
Latch Input Current Low
VLL = 0.3V
-50
-40
µA
tD+
Latch Disable to High Delay
6
ns
tD-
Latch Disable to Low Delay
6
ns
tS
Minimum Setup Time
2
ns
tH
Minimum Hold Time
1
ns
tPW(D)
Minimum Latch Disable Pulse Width
10
ns
2
2.0
0.8
V
V
EL5283
Typical Performance Curves
Positive Supply Current vs Temperature
(per comparator)
Negative Supply Current vs Temperature
(per comparator)
7.15
-4.5
Output Low
7.1
-4.6
7.05
-4.7
IS- (mA)
IS+ (mA)
7
6.95
6.9
6.85
-4.8
-4.9
-5
6.8
-5.1
6.75
-5.2
6.7
-50
-30
-10
10
30
50
70
-5.3
-50
90
-30
-10
Temperature (°C)
10
30
50
70
90
50
70
90
Temperature (°C)
Supply Current vs Supply Voltage
(per comparator)
Input Bias Current vs Temperature
6
8
VS+=VSD
VOUT=low
7
5
6
4
IS+
IB (µA)
IS (mA)
5
IS-
4
3
3
2
2
1
1
0
-50
0
0
1
2
3
4
5
6
7
-30
-10
1.6
10
1.5
9.5
1.4
9
1.3
8.5
Delay Time (ns)
VOS (mV)
Offset Voltage vs Temperature
1.2
1.1
1
0.9
30
Temperature (°C)
3
50
70
90
TPD+
7
5.5
10
VS=±5V
VSD=5V
VIN=1V Step
RL=2.2kΩ
6.5
0.7
-10
Propagation Delay vs Overdrive
VIN=1V Step
8
6
-30
30
7.5
0.8
0.6
-50
10
Temperature (°C)
±VS (V)
5
0
TPD-
100
200
300
VOD (mV)
400
500
600
EL5283
Typical Performance Curves
Propagation Delay vs Load Capacitance
VIN=1V Step
VS=±5V
VSD=5V
RL=2.2kΩ
VIN=1V Step
VOD=50mV
Delay Time (ns)
11
10
10.5
Propagation Delay vs Supply Voltage
VIN=1V Step
VSD=VS+
VIN=1V Step
VOD=50mV
RL=2.2kΩ
10
9.5
Delay Time (ns)
12
(Continued)
TPD+
9
8
TPD-
9
8.5
TPD+
8
7.5
7
TPD-
6.5
7
6
6
0
20
40
60
80
100
5.5
4
120
4.5
5
CLOAD (pF)
10
Propagation Delay vs Overdrive
VIN=3VP-P Step
11
9.5
TPD+
Delay Time (ns)
Delay Time (ns)
VS=±5V
VSD=5V
RL=2.2kΩ
VIN=5V Step
10
8.5
8
7.5
7
6.5
6
0
TPD-
VS=±5V
VSD=5V
VIN=1V Step
RL=2.2kΩ
0.2
0.4
0.6
TPD+
9.5
9
TPD-
8.5
8
7.5
0.8
1
1.2
1.4
1.6
1.8
7
0
2
0.5
1
1.5
VOD (V)
Propagation Delay vs Source Resistance
VIN=1V Step
18
Delay Time (ns)
16
14
VS=±5V
VSD=5V
RL=2.2kΩ
VIN=1V Step
VOD=50mV
3
0.33
TPD+
10
TPD-
TA=85°C
0.29
TA=25°C
0.25
TA=-40°C
0.21
VS=±5V
VSD=5V
VIN=-50mV
6
4
0
2.5
Output Low Voltage vs Load Current
12
8
2
VOD (V)
Output Low Voltage (V)
20
6
Propagation Delay vs Overdrive
VIN=5VP-P Step
10.5
9
5.5
±VS (V)
0.17
0.2
0.4
0.6
0.8
1
1.2
Source Resistance (kΩ)
4
1.4
1.6
0
2
4
6
Load Current (mA)
8
10
EL5283
Typical Performance Curves
(Continued)
Output High Voltage vs Load Current
Digital Supply Current vs Input Switching
Frequency
4.8
30
25
4.65
20
ISD (mA)
Output High Voltage (V)
TA=-40°C
4.7
VS=±5V
VS=±5V
VSD=5V
VIN=50mV
4.75
TA=25°C
4.6
4.55
TA=85°C
4.5
VSD=5V
15
10
VSD=3V
4.45
5
4.4
4.35
0
0
2
4
6
8
10
0
5
10
Package Power Dissipation vs Ambient Temperature
JEDEC JESD51-3 Low Effective Thermal Conductivity
Test Board
20
25
30
35
40
45
50
Package Power Dissipation vs Ambient Temperature
JEDEC JESD51-7 High Effective Thermal Conductivity Test
Board
0.6
1
0.4
Power Dissipation (W)
486mW
0.5
Power Dissipation (W)
15
Frequency (MHz)
Load Current (mA)
M
SO
P1
20
0
6°
C/
W
0.3
0.2
0.1
0
870mW
0.8
M
S
11 OP1
5°
0
C/
W
0.6
0.4
0.2
0
0
25
50
75 85 100
Ambient Temperature (°C)
125
0
VS=±5V
VSD=5V
100
VIN=3VP-P
FIN=30MH
VO
VO
VIN
VIN
5
75 85
Output with 30MHz Input
VIN=3VP-P
VIN=1VP-P
FIN=30MH
2V
50
Ambient Temperature (°C)
Output with 30MHz Input
VIN=1VP-P
1V
25
20ns
2V
2V
20ns
VS=±5V
VSD=5V
125
EL5283
Timing Diagram
Compare
Compare
Latch
Enable
Input
1.4V
Latch
Latch
Differenti
al Input
Voltage
tS
tH
Latch
tPW(D
VIN
VOS
VDD
tPD-
tD+(D)
Comparator
Output
2.4V
Definition of Terms
TERMS
DEFINITION
VOS
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
VIN
Input Voltage Pulse Amplitude - Usually set to 100mV for comparator specifications
VOD
Input Voltage Overdrive - Usually set to 5mV and in opposite polarity to VIN for comparator specifications
tPD+
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the
CMOS logic threshold of an output low to high transition
tPD-
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the
CMOS logic threshold of an output high to low transition
tD+
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low
to high transition to the point of the output crossing CMOS threshold in a low to high transition
tD -
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low
to high transition to the point of the output crossing CMOS threshold in a high to low transition
tS
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be
present in order to be acquired and held at the outputs
tH
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged
in order to be acquired and held at the output
tPW (D)
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an
input signal change
6
EL5283
Pin Descriptions
PIN NUMBER
PIN NAME
FUNCTION
1
VS+
Positive supply voltage
2
VREFH
Upper voltage reference
EQUIVALENT CIRCUIT
VS+
VREF
IN
VSCircuit 1
3
IN
Input
(Reference Circuit 1)
4
VREFL
Lower voltage reference
(Reference Circuit 1)
5
VS-
Negative supply voltage
6
GDN
Digital ground
7
OUTL
Low output
VSD
VS+
OUT
VSCircuit 2
8
LATCH
Latch
VS+ VSD
VSD
LATCH
VSCircuit 3
9
OUTH
10
VSD
High output
(Reference Circuit 2)
Digital supply voltage
Applications Information
Power Supplies and Circuit Layout
The EL5283 comparator operates with single and dual
supply with 5V to 12V between VS+ and VS-. The output
side of the comparators is supplied by a single supply from
2.7V to 5V. The rail to rail output swing enables direct
connection of the comparator to both CMOS and TTL logic
circuits. As with many high speed devices, the supplies must
be well bypassed. Elantec recommends a 4.7µF tantalum in
parallel with a 0.1µF ceramic. These should be placed as
close as possible to the supply pins. Keep all leads short to
reduce stray capacitance and lead inductance. This will also
minimize unwanted parasitic feedback around the
comparator. The device should be soldered directly to the
PC board instead of using a socket. Use a PC board with a
good, unbroken low inductance ground plane. Good ground
7
plane construction techniques enhance stability of the
comparators.
Input Voltage Considerations
The EL5283 input range is specified from 0.1V below VS- to
2.25V below VS+. The criterion for the input limit is that the
output still responds correctly to a small differential input
signal. The differential input stage is a pair of PNP
transistors, therefore, the input bias current flows out of the
device. When either input signal falls below the negative
input voltage limit, the parasitic PN junction formed by the
substrate and the base of the PNP will turn on, resulting in a
significant increase of input bias current. If one of the inputs
goes above the positive input voltage limit, the output will still
maintain the correct logic level as long as the other input
stays within the input range. However, the propagation delay
will increase. When both inputs are outside the input voltage
range, the output becomes unpredictable. Large differential
EL5283
voltages greater than the supply voltage should be avoided
to prevent damages to the input stage.
Input Slew Rate
Most high speed comparators oscillate when the voltage of
one of the inputs is close to or equal to the voltage on the
other input due to noise or undesirable feedback. For clean
output waveform, the input must meet certain minimum slew
rate requirements. In some applications, it may be helpful to
apply some positive feedback (hysteresis) between the
output and the positive input. The hysteresis effectively
causes one comparator's input voltage to move quickly past
the other, thus taking the input out of the region where
oscillation occurs. For the EL5283, the propagation delay
increases when the input slew rate increases for low
overdrive voltages. With high overdrive voltages, the
propagation delay does not change much with the input slew
rate.
Latch Pin Dynamics
The EL5283 contains a “transparent” latch for each channel.
The latch pin is designed to be driven with either a TTL or
CMOS output. When the latch is connected to a logic high
level or left floating, the comparator is transparent and
immediately responds to the changes at the input terminals.
When the latch is switched to a logic low level, the
comparator output latches remains latched to its value just
before the latch high-to-low transition. To guarantee data
retention, the input signal must remain the same state at
least 1ns (hold time) after the latch goes low and at least 2ns
(setup time) before the latch goes low. When the latch goes
high, the new data will appear at the output in approximately
6ns (latch propagation delay).
where:
VS is the analog supply voltage from VS+ to VSIS is the analog quiescent supply current per comparator
VSD is the digital supply voltage from VSD to ground
ISD is the digital supply current per comparator
N is the number of comparators in the package
ISD strongly depends on the input switching frequency.
Please refer to the performance curve to choose the input
driving frequency. Having obtained the power dissipation,
the maximum junction temperature can be determined as
follows:
T JMAX = T MAX + Θ JA × P DISS
where:
TMAX is the maximum ambient temperature
θJA is the thermal resistance of the package
Window Detector
If VIN is in the range of VREFL < VIN < VREFH, both outputs
go high and the input in range is high. If VIN is out of the
range set by VREFH and VREFL, the input in range is low.
VREFH
+
-
Input In
Range
VIN
VREFL
OUTH
+
-
OUTL
Power Dissipation
When switching at high speeds, the comparator's drive
capability is limited by the rise in junction temperature
caused by the internal power dissipation. For reliable
operation, the junction temperature must be kept below
TJMAX (125°C).
An approximate equation for the device power dissipation is
as follows. Assume the power dissipation in the load is very
small:
P DISS = ( V S × I S + V SD × I SD ) × N
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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