DATASHEET

®
UCT
NT
ROD ACEME at
P
E
r
T
L
E
P
t
L
E
n
e e
O
R
OBS ENDED upport C om/tsc
c
.
l
MM nical S
tersi
ECO TSheet
ech www.in
NO R Data
r
u
r
o
o
IL
act
cont -INTERS
8
8
8
1-
EL5485, EL5486
January 18, 2002
Quad 4ns High Speed Comparators
Features
The EL5485 and EL5486 comparators
are designed for operation in single
supply and dual supply applications
with 5V to 12V between VS+ and VS-. For single supplies,
the inputs can operate from 0.1V below ground for use in
ground sensing applications.
• 4ns typ. propagation delay
FN7200
• 5V to 12V input supply
• +2.7V to +5V output supply
• True-to-ground input
• Rail-to-rail outputs
The output side of the comparators can be supplied from a
single supply of 2.7V to 5V. The rail-to-rail output swing
enables direct connection of the comparator to both CMOS
and TTL logic circuits.
The latch input of the EL5486 can be used to hold the
comparator output value by applying a low logic level to the
pin.
The EL5485 is available in the 16-pin SO (0.150") package
and the EL5486 in the 24-pin QSOP package. Both are
specified for operation over the full -40°C to +85°C
temperature range. Also available are single (EL5185), dual
(EL5285), and window comparator (EL5287) versions.
• Active low latch
• Single (EL5185) available
• Dual (EL5285) available
• Window available (EL5287)
• Pin-compatible 8ns family available (EL5x81, EL5283 &
EL5482)
Applications
• Threshold detection
• High speed sampling circuits
• High speed triggers
Pinouts
EL5485
[16-PIN SO (0.150")]
TOP VIEW
EL5486
(24-PIN QSOP)
TOP VIEW
INA- 1
16 IND-
INA- 1
24 IND-
INA+ 2
15 IND+
INA+ 2
23 IND+
+ -
• PWM circuits
• High speed V/F converters
Ordering Information
PACKAGE
TAPE &
REEL
PKG. NO.
- +
GND 3
NC 3
14 VS+
22 NC
+ -
OUTA 4
13 OUTD
GND 4
OUTB 5
12 OUTC
LATCHA 5
PART NUMBER
- +
21 VS+
EL5485CS
16-Pin SO (0.150")
-
MDP0027
20 LATCHD
EL5485CS-T7
16-Pin SO (0.150")
7”
MDP0027
EL5485CS-T13
16-Pin SO (0.150")
13”
MDP0027
EL5486CU
24-Pin QSOP
-
MDP0040
EL5486CU-T13
24-Pin QSOP
13”
MDP0040
11 VSD
OUTA 6
19 OUTD
INB+ 7
10 INC+
OUTB 7
18 OUTC
INB- 8
9 INC-
LATCHB 8
VS- 6
+ -
• Line receivers
- +
17 LATCHC
VS- 9
16 VSD
+ -
NC 10
1
- +
15 NC
INB+ 11
14 INC+
INB- 12
13 INC-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL5485, EL5486
Absolute Maximum Ratings (TA = 25°C)
Analog Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . +12.6V
Digital Supply Voltage (VSD to GND). . . . . . . . . . . . . . . . . . . . . .+7V
Differential Input Voltage . . . . . . . . . . .[(VS-) -0.2V] to [(VS+) +0.2V]
Common-Mode Input Voltage . . . . . . .[(VS-) -0.2V] to [(VS+) +0.2V]
Latch Input Voltage . . . . . . . . . . . . . . . . . . . . -0.2V to [(VSD) +0.2V]
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS = ±5V, VSD = 5V, RL = 2.3kΩ, TA = 25°C, unless otherwise specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
1
4
mV
INPUT
VOS
Input Offset Voltage
IB
Input Bias Current
CIN
Input Capacitance
IOS
Input Offset Current
VCM
Input Voltage Range
CMRR
Common-mode Rejection Ratio
-5.1V < VCM < +2.75V, VO = 2.5V
VOH
Output High Voltage
VIN > 250mV
VOL
Output Low Voltage
VIN > 250mV
VCM = 0V, VO = 2.5V
-10
VCM = 0V, VO = 2.5V
-2.5
-5
µA
5
pF
0.5
(VS-) -0.1
2.5
µA
(VS+) -2.25
V
65
90
dB
VSD -0.6
VSD -0.4
V
OUTPUT
GND +0.25
GND +0.5
V
DYNAMIC PERFORMANCE
tpd+
Latch Disable to High Delay
VIN = 1VP-P, VOD = 50mV
4
6
ns
tpd-
Latch Disable to Low Delay
VIN = 1VP-P, VOD = 50mV
4
6
ns
IS+
Positive Analog Supply Current
Per comparator
12
13.5
mA
IS-
Negative Analog Supply Current
Per comparator
7.5
8.5
mA
ISD
Digital Supply Current at No Load
Per comparator, output high
5.5
6.5
mA
Per comparator, output low
0.9
1.2
mA
SUPPLY
PSRR
Power Supply Rejection Ratio
55
80
dB
LATCH
VLH
Latch Input Voltage High
VLL
Latch Input Voltage Low
ILH
Latch Input Current High
VLH = 3.0V
-30
-18
µA
ILL
Latch Input Current Low
VLL = 0.3V
-30
-24
µA
td +
Positive Going Delay Time
VOD = 5mV, CL = 15pF, IO = 2mA
4
ns
td -
Negative Going Delay Time
VOD = 5mV, CL = 15pF, IO = 2mA
4
ns
ts
Minimum Setup Time
2
ns
th
Minimum Hold Time
1
ns
tpw(D)
Minimum Latch Disable Pulse Width
5
ns
2
2.0
0.8
V
V
EL5485, EL5486
Typical Performance Curves
Output High Voltage vs Temperature
Supply Current vs Supply Voltage
5
14
VIN=-50mV
RL=2.3kΩ
12
4.8
IS+
8
VOH (V)
IS (mA)
10
IS-
6
4.6
4.4
4
4.2
2
4
-50
0
0
1
2
3
4
5
6
-30
-10
10
30
50
70
90
50
70
90
70
90
Temperature (°C)
±VS (V)
Input Bias Current vs Temperature
Offset Voltage vs Temperature
2.5
9
8
2
7
6
IB (µA)
VOS (mV)
1.5
1
5
4
0.5
3
0
2
-0.5
-50
-30
-10
10
30
50
70
1
-50
90
-30
-10
Temperature (°C)
10
30
Temperature (°C)
Output Low Voltage vs Temperature
Supply Current vs Temperature (per comparator)
0.4
14
12
Supply Current (mA)
IS+
VOL (V)
0.3
0.2
10
8
IS-
6
4
2
0.1
-50
-30
-10
10
30
Temperature (°C)
3
50
70
90
0
-50
-30
-10
10
30
Temperature (°C)
50
EL5485, EL5486
Typical Performance Curves
(Continued)
Propagation Delay vs Overdrive
VIN=1VSTEP
Propagation Delay vs Supply Voltage
4.2
4.5
VS=±5V
VSD=5V
RL=2.3kΩ
4.1
4.3
4.2
TPD+
Delay Time (ns)
Delay Time (ns)
4
3.9
3.8
TPD-
3.7
VSD=VS+
VOD=50mV
RL=2.2kΩ
4.4
TPD+
4.1
4
TPD-
3.9
3.8
3.7
3.6
3.6
3.5
50
3.5
100 150 200 250 300 350 400 450 500 550 600
4
4.2
4.4
4.6
4.8
VOD (mV)
Propagation Delay vs Overdrive
VIN=3VSTEP
5.2
5.4
5.6
5.8
6
Digital Supply Current vs Switching Frequency
(per comparator)
6.8
25
VS=±5V
VSD=5V
RL=2.3kΩ
6.6
6.4
VS=±5V
TA=25°C
RL=2.3kΩ
20
6.2
TPD+
6
ISD (mA)
Delay Time (ns)
5
±VS (V)
5.8
15
VSD=5V
10
VSD=3V
TPD-
5.6
5.4
5
5.2
5
0.2
0
0.6
0.4
0.8
1
1.2
1.4
1.8
1.6
0
2
10
20
VOD (V)
30
40
50
Frequency (MHz)
Propagation Delay vs Overdrive
VIN=5VSTEP
Propagation Delay vs Source Resistance
VIN=1VSTEP
7.2
16
7
VS=±5V
VSD=5V
RL=2.3kΩ
TPD+
VS=±5V
VSD=5mV
VOD=50mV
RL=2.3kΩ
14
Delay Time (ns)
Delay Time (ns)
6.8
TPD-
6.6
6.4
TPD+
12
10
TPD-
8
6.2
6
6
5.8
0.2
4
0.4
0.6
0.8
1
1.2
1.4
1.6
VOD (V)
4
1.8
2
2.2
2.4
2.6
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Source Resistance (kΩ)
1.6
1.8
2
EL5485, EL5486
Typical Performance Curves
(Continued)
Propagation Delay vs Load Capacitance
VIN=1VSTEP
Power Dissipation vs Ambient Temperature
JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board
1.4
7.5
VS=±5V
VSD=5V
VOD=50mV
RL=2.3kΩ
1.2
Power Dissipation (W)
7
Delay Time (ns)
6.5
TPD+
6
TPD-
5.5
5
4.5
1
909mW
0.8
0.6
OP
24
870mW
SO
16
θ
=1
15
JA
=
°C
/
W
0.4
11
0°
C/
W
0.2
4
0
0
20
10
30
50
40
60
70
80
90
100
0
CLOAD (pF)
1.250W
1.2
16
SO
1.136W
.
(0
SO
P2
4=
88
°C
/
Output
(5ns/div,
2V/div)
/W
0.6
°C
80
)=
0”
15
Q
0.8
W
0.4
Input
(5ns/div,
0.5V/div)
0.2
0
0
25
50
75 85
100
Ambient Temperature (°C)
Output with 50MHz Input
VIN=3VP-P
Output
(5ns/div,
2V/div)
Input
(5ns/div,
2V/div)
5
50
Output with 50MHz Input
VIN=1VP-P
1.4
1
25
75 85
100
Ambient Temperature (°C)
Power Dissipation vs Ambient Temperature
JEDEC JESD51-7 High Effective Thermal Conductivity Test Board
Power Dissipation (W)
QS
125
150
125
150
EL5485, EL5486
Timing Diagram
Compare
Compare
Latch
Enable
Input
1.4V
Latch
Latch
ts
Differential
Input
Voltage
Latch
th
tpw(D)
VIN
VOS
VOD
tpd-
td+
Comparator
Output
2.4V
Definition of Terms
TERM
DEFINITION
VOS
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
VIN
Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications
VOD
Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications
tpd+
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to
the CMOS logic threshold of an output low to high transition
tpd-
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to
the CMOS logic threshold of an output high to low transition
td+
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in
a low to high transition to the point of the output crossing CMOS threshold in a low to high transition
td -
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a
low to high transition to the point of the output crossing CMOS threshold in a high to low transition
ts
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must
be present in order to be acquired and held at the outputs
th
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain
unchanged in order to be acquired and held at the output
tpw (D)
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an
input signal change
6
EL5485, EL5486
Pin Descriptions
24-PIN
QSOP
16-PIN SO
(0.150")
PIN NAME
1
1
INA-
FUNCTION
EQUIVALENT CIRCUIT
Negative input, channel A
VS+
IN-
IN+
VSCircuit 1
2
2
3,10,15,22
4
3
5
INA+
Positive input, channel A
NC
Not Connected
GND
Digital ground
LATCHA
(Reference circuit 1)
Latch input, channel A
VS+ VSD
VSD
LATCH
VSCircuit 2
6
4
OUTA
Output, channel A
VSD
VS+
OUT
VSCircuit 3
7
5
8
OUTB
LATCHB
Output, channel B
(Reference circuit 3)
Latch input, channel B
(Reference circuit 2)
9
6
VS-
Negative supply voltage
11
7
INB+
Positive input, channel B
(Reference circuit 1)
12
8
INB-
Negative input, channel B
(Reference circuit 1)
13
9
INC-
Negative input, channel C
(Reference circuit 1)
14
10
INC+
Positive input, channel C
(Reference circuit 1)
16
11
VSD
Digital supply voltage
LATCHC
Latch input, channel C
(Reference circuit 2)
17
18
12
OUTC
Output, channel C
(Reference circuit 3)
19
13
OUTD
Output, channel D
(Reference circuit 3)
LATCHD
Latch input, channel D
(Reference circuit 2)
20
21
14
VS+
Positive supply voltage
23
15
IND+
Positive input, channel D
(Reference circuit 1)
24
16
IND-
Negative input, channel D
(Reference circuit 1)
7
EL5485, EL5486
Applications Information
Power Supplies and Circuit Layout
The EL5485 and EL5486 comparators operate with single
and dual supply with 5V to 12V between VS+ and VS-. The
output side of the comparator is supplied by a single supply
from 2.7V to 5V. The rail to rail output swing enables direct
connection of the comparator to both CMOS and TTL logic
circuits. As with many high speed devices, the supplies must
be well bypassed. Elantec recommends a 4.7µF tantalum in
parallel with a 0.1µF ceramic. These should be placed as
close as possible to the supply pins. Keep all leads short to
reduce stray capacitance and lead inductance. This will also
minimize unwanted parasitic feedback around the
comparator. The device should be soldered directly to the
PC board instead of using a socket. Use a PC board with a
good, unbroken low inductance ground plane. Good ground
plane construction techniques enhance stability of the
comparators.
increases for low overdrive voltages. With high overdrive
voltages, the propagation delay does not change much with
the input slew rate.
Latch Pin Dynamics
The EL5486 contains a “transparent” latch for each channel.
The latch pin is designed to be driven with either a TTL or
CMOS output. When the latch is connected to a logic high
level or left floating, the comparator is transparent and
immediately responds to the changes at the input terminals.
When the latch is switched to a logic low level, the
comparator output remains latched to its value just before
the latch’s high-to-low transition. To guarantee data
retention, the input signal must remain the same state at
least 1ns (hold time) after the latch goes low and at least 2ns
(setup time) before the latch goes low. When the latch goes
high, the new data will appear at the output in approximately
4ns (latch propagation delay). The EL5485 does not have
latch inputs.
Input Voltage Considerations
Hysteresis
The EL5485 and EL5486’s input range is specified from 0.1V
below VS- to 2.25V below VS+. The criterion for the input
limit is that the output still responds correctly to a small
differential input signal. The differential input stage is a pair
of PNP transistors, therefore, the input bias current flows out
of the device. When either input signal falls below the
negative input voltage limit, the parasitic PN junction formed
by the substrate and the base of the PNP will turn on,
resulting in a significant increase of input bias current. If one
of the inputs goes above the positive input voltage limit, the
output will still maintain the correct logic level as long as the
other input stays within the input range. However, the
propagation delay will increase. When both inputs are
outside the input voltage range, the output becomes
unpredictable. Large differential voltages greater than the
supply voltage should be avoided to prevent damages to the
input stage. Inputs of unused channels should not be left
floating. They should be driven to a known state. For
example, one input can be tied to ground and the other input
can be connected to some voltage reference (like ±100mV)
to avoid oscillation in the output due to unwanted output to
input feedback.
Hysteresis can be added externally. The following two
methods can be used to add hysteresis.
Inverting comparator with hysteresis:
VREF
R3
R2
R1
VIN
+
-
R3 adds a portion of the output to the threshold set by R1
and R2. The calculation of the resistor values are as follows:
Select the threshold voltage VTH and calculate R1 and R2.
The current through R1/R2 bias string must be many times
greater than the input bias current of the comparator:
R1
V TH = V REF × --------------------R +R
1
2
Let the hysteresis be VH, and calculate R3:
VO
R 3 = -------- × ( R 1 || R 2 )
VH
where:
Input Slew Rate
Most high speed comparators oscillate when the voltage of
one of the inputs is close to or equal to the voltage on the
other input due to noise or undesirable feedback. For clean
output waveform, the input must meet certain minimum slew
rate requirements. In some applications, it may be helpful to
apply some positive feedback (hysteresis) between the
output and the positive input. The hysteresis effectively
causes one comparator's input voltage to move quickly past
the other, thus taking the input out of the region where
oscillation occurs. For the EL5485 and EL5486, the
propagation delay increases when the input slew rate
8
VO=VSD-0.8V (swing of the output)
Recalculate R2 to maintain the same value of VTH:
 V TH V TH – 0.5V SD 
R 2 1 = ( V REF – V TH ) ÷  ----------- + -------------------------------------- 
R3
 R1

Non inverting comparator with hysteresis:
R3
VIN
R1
VREF
+
-
EL5485, EL5486
R3 adds a portion of the output to the positive input. Note
that the current through R3 should be much greater than the
input bias current in order to minimize errors. The calculation
of the resistor values as follows:
maximum junction temperature can be determined as
follows:
Pick the value of R1. R1 should be small (less than 1kΩ) in
order to minimize the propagation delay time.
where:
Choose the hysteresis VH and calculate R3:
R1
R 3 = ( V SD – 0.8 ) × -------V
H
Check the current through R3 and make sure that it is much
greater than the input bias current as follows:
0.5V SD – V REF
I = ----------------------------------------R3
The above two methods will generate hysteresis of up to a
few hundred millivolts. Beyond that, the impedance of R3 is
low enough to affect the bias string and adjustment of R1
may be required.
Power Dissipation
When switching at high speeds, the comparator's drive
capability is limited by the rise in junction temperature
caused by the internal power dissipation. For reliable
operation, the junction temperature must be kept below
TJMAX (125°C).
An approximate equation for the device power dissipation is
as follows. Assume the power dissipation in the load is very
small:
P DISS = ( V S × I S + V SD × I SD ) × N
where:
VS is the analog supply voltage from VS+ to VSIS is the analog quiescent supply current per comparator
T JMAX = T MAX + Θ JA × P DISS
TMAX is the maximum ambient temperature
θJA is the thermal resistance of the package
Threshold Detector
The inverting input is connected to a reference voltage and
the non-inverting input is connected to the input. As the input
passes the VREF threshold, the comparator's output
changes state. The non-inverting and inverting inputs may
be reversed.
A simple crystal oscillator using one comparator of an
EL5485 and EL5486 is shown below. The resistors R1 and
R2 set the bias point at the comparator's non-inverting input.
Resistors R3, R4, and C1 set the inverting input node at an
appropriate DC average voltage based on the output. The
crystal's path provides resonant positive feedback and stable
oscillation occurs. Although the EL5485 and EL5486 will give
the correct logic output when an input is outside the common
mode range, additional delays may occur when it is so
operated. Therefore, the DC bias voltages at the inputs are
set about 500mV below the center of the common mode
range and the 200Ω resistor attenuates the feedback to the
non-inverting input. The circuit will operate with most AT-cut
crystal from 1MHz to 8MHz over a 2V to 7V supply range.
The output duty cycle for this circuit is roughly 50% at 5V
VCC, but it is affected by the tolerances of the resistors. The
duty cycle can be adjusted by changing VCC value.
5V
200Ω
R1
5kΩ
R2
1.5kΩ
N is the number of comparators in the package
ISD strongly depends on the input switching frequency.
Please refer to the performance curve to choose the input
driving frequency. Having obtained the power dissipation, the
VOUT
Crystal Oscillator
VSD is the digital supply voltage from VSD to ground
ISD is the digital supply current per comparator
+
-
VIN
VREF
1MHz to
8MHz
+
VOUT
R3
C1
R4
0.01µF
2kΩ
2kΩ
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
Similar pages