DATASHEET

ISL28196, ISL28197
®
Data Sheet
September 29, 2008
Ultra-Small, 800nA and 2.5µA Single
Supply, Rail-to-Rail Input/Output (RRIO)
Comparators
The ISL28196 and ISL28197 are micropower comparators
optimized for low-power applications. The parts are
designed for single-supply operation from 1.8V to 5.5V. The
ISL28197 typically consumes 800nA of supply current and
the ISL28196 typically consumes 2.5µA of supply current.
Both parts feature rail-to-rail input and output swing (RRIO),
allowing for maximum battery usage. The ISL28196 features
a propagation delay of 150µs and the ISL28197 features a
propagation delay of 0.6ms.
FN6152.4
Features
• Typical Supply Current 800nA (ISL28197)
• Typical Supply Current 2.5µA (ISL28196)
• Ultra-Low Single-Supply Operation Down to +1.8V
• Rail-to-Rail Input/Output Voltage Range (RRIO)
• 150µs Typical Propagation Delay (ISL28196)
• 0.6ms Typical Propagation Delay (ISL28197)
• ENABLE Pin Feature
• Push-Pull Output
Equipped with an ENABLE pin (EN), both parts draw
typically 2nA when off. The combination of small footprint,
low power, single supply, and rail-to-rail operation makes
them ideally suited for all battery operated devices.
• -40°C to +125°C Operation
Pinouts
• 2-Cell Alkaline Battery-Powered/Portable Systems
ISL28196, ISL28197
(6 LD SOT-23)
TOP VIEW
OUT 1
GND 2
6 V+
+ -
IN+ 3
5 EN
4 IN-
ISL28196, ISL28197
(6 LD 1.6X1.6X0.5 µTDFN)
TOP VIEW
6 V+
GND 2
5 EN
+ -
IN- 1
IN+ 3
4 OUT
• Pb-Free (RoHS Compliant)
Applications
• Window Comparators
• Threshold Detectors/Discriminators
Ordering Information
PART
NUMBER
ISL28196FHZ-T7*
(Note 1)
PART
MARKING
GABM
PACKAGE
Tape & Reel
(Pb-Free)
6 Ld SOT-23
PKG.
DWG. #
MDP0038
ISL28196FRUZ-T7* M5
(Note 2)
6 Ld 1.6x1.6x0.5 µTDFN L6.1.6x1.6A
ISL28197FHZ-T7*
(Note 1)
6 Ld SOT-23
GABN
ISL28197FRUZ-T7* M6
(Note 2)
MDP0038
6 Ld 1.6x1.6x0.5 µTDFN L6.1.6x1.6A
*Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
2. These Intersil Pb-free plastic packaged products employ special Pbfree material sets; molding compounds/die attach materials and
NiPdAu plate - e4 termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020..
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL28196, ISL28197
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (V+, V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V
Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/µs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . .
230
6 Ld µTDFN Package . . . . . . . . . . . . . . . . . . . . . . .
117.52
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite
Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at
the specified temperature and are pulsed tests, Therefore TJ = TC = TA
Electrical Specifications
V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, unless otherwise specified. Boldface limits apply over -40°C to
+125°C.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4)
UNIT
VOS
Input Offset Voltage
-2
-2.5
-0.1
2
2.5
mV
IOS
Input Offset Current
-60
-100
10
60
100
pA
IB
Input Bias Current
-80
-150
15
80
150
pA
CMIR
Common Mode Input Range
Established by CMRR test
0
5
V
CMRR
Common-Mode Rejection Ratio
VCM = 0.5V to 3.5V
70
70
VCM = 0V to 5V
60
70
70
100
dB
dB
PSRR
Power Supply Rejection Ratio
V+ = 1.8V to 5.5V
VOUT
Maximum Output Voltage Swing
RL terminated to V+/2
Output low, RL = 10kΩ
Supply Current, Enabled
ISL28196
2.5
4.0
4.5
µA
ISL28197
0.8
1.6
2.0
µA
EN = 0.4V
2
20
50
nA
5.5
V
IS,ON
IS,OFF
Supply Current, Disabled
VSUPPLY
Supply Voltage Range
CIN
Input Capacitance
Output high, RL = 10kΩ
100
35
4.930
dB
70
4.950
1.8
mV
V
5
pF
ENABLE INPUT
VINH
Enable Pin High Level
VINL
Enable Pin Low Level
IENH
Enable Pin Input Current
VEN = 5V
IENL
Enable Pin Input Current
VEN = 0V
2
(V+)x(0.8)
V
0.4
V
30
150
200
nA
30
150
200
nA
FN6152.4
September 29, 2008
ISL28196, ISL28197
Electrical Specifications
V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, unless otherwise specified. Boldface limits apply over -40°C to
+125°C. (Continued)
PARAMETER
DESCRIPTION
MIN
(Note 4)
CONDITIONS
TYP
MAX
(Note 4)
UNIT
TIMING
tPD±
ISL28196 Propagation Delay Low to High and High to Low CL = 10pF, 20mV Overdrive
150
300
µs
tPD±
ISL28197 Propagation Delay Low to High and High to Low CL = 10pF, 1.5V Overdrive
0.625
1.3
ms
tR/tF
ISL28196 Rise/Fall Time
CL = 10pF
9
18
μs
ISL28197 Rise/Fall Time
CL = 10pF
35
70
μs
NOTE:
4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified.
730
164
162
RL = INF
RL = INF
SUPPLY CURRENT (nA)
SUPPLY CURRENT (nA)
720
160
158
156
154
152
150
710
700
690
680
148
146
1.5
2.0
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
4.5
670
1.5
5.0
FIGURE 1. ISL28196 SUPPLY CURRENT vs SUPPLY VOLTAGE
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
4.5
5.0
FIGURE 2. ISL28197 SUPPLY CURRENT vs SUPPLY VOLTAGE
400
350
2.0
1200
RL TO GND
RL = 10kΩ
RL TO GND
RL = 10kΩ
1000
250
200
RL TO V+
OD = 20mV
RL TO GND
150
DELAY (µs)
DELAY (µs)
300
800
OD = 20mV
600
400
100
50
0
1.5
OD = 100mV
OD = 100mV
200
RL TO V+
RL TO V+
RL TO GND
RL TO V+
0
2.0
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
4.5
5.0
FIGURE 3. ISL28196 PROP DELAY vs SUPPLY VOLTAGE
(RISING EDGE)
3
1.5
2.0
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
4.5
5.0
FIGURE 4. ISL28197 PROP DELAY vs SUPPLY VOLTAGE
(RISING EDGE)
FN6152.4
September 29, 2008
ISL28196, ISL28197
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified.
350
1200
RL TO V+
RL = 10kΩ
RL TO V+
RL = 10kΩ
300
RL TO GND
OD = 20mV
200
RL TO V+
150
100
DELAY (µs)
1000
250
DELAY (µs)
(Continued)
800
OD = 20mV
RL TO GND
RL TO V+
600
400
RL TO GND
RL TO GND
50
200
OD = 100mV
0
1.5
2.0
OD = 100mV
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
4.5
0
1.5
5.0
FIGURE 5. ISL28196 PROP DELAY vs SUPPLY VOLTAGE
(FALLING EDGE)
2.0
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
4.5
5.0
FIGURE 6. ISL28197 PROP DELAY vs SUPPLY VOLTAGE
(FALLING EDGE)
900
3500
RL = 10kΩ
V+ = 5V
800
RL = 10kΩ
V+ = 5V
3000
700
2500
500
DELAY (µs)
DELAY (µs)
600
RL TO GND
400
RL TO V+
V+ = 2V
300
2000
1500
RL TO GND
RL TO V+
V+ = 2V
1000
200
500
100
0
0
1
10
100
1000
1
10
100
OVERDRIVE (mV)
OVERDRIVE (mV)
FIGURE 7. ISL28196 PROP DELAY vs OVERDRIVE
(RISING EDGE)
1000
FIGURE 8. ISL28197 PROP DELAY vs OVERDRIVE
(RISING EDGE)
3000
900
RL = 10kΩ
V+ = 5V
800
RL = 10kΩ
V+ = 5V
2500
700
500
DELAY (μs)
DELAY (μs)
600
RL TO GND
400
RL TO V+
2000
RL TO GND
V+ = 2V
RL TO V+
1500
1000
300
200
500
100
V+ = 2V
0
0
1
10
100
OVERDRIVE (mV)
FIGURE 9. ISL28196 PROP DELAY vs OVERDRIVE
(FALLING EDGE)
4
1000
1
10
100
1000
OVERDRIVE (mV)
FIGURE 10. ISL28197 PROP DELAY vs OVERDRIVE
(FALLING EDGE)
FN6152.4
September 29, 2008
ISL28196, ISL28197
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified.
25
25
RL = 10Ω
20
SINKING
15
SOURCING
10
5
0
1.0
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
RL = 10Ω
20
SINKING
15
SOURCING
10
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1.0
5.5
1.5
3.0
3.0
2.8
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
3.5
4.0
4.5
5.0
5.5
2.6
2.4
2.2
2.0
1.8
1.6
1.4
2.0
2.5
3.0
3.5
4.0
4.5
1.0
1.5
5.0
2.0
SUPPLY VOLTAGE (V)
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
FIGURE 13. ISL28196 ENABLE THRESHOLD VOLTAGE vs
SUPPLY VOLTAGE
FIGURE 14. ISL28197 ENABLE THRESHOLD VOLTAGE vs
SUPPLY VOLTAGE
80
ENABLE TO OUTPUT DELAY (ms)
100
ENABLE TO OUTPUT DELAY (ms)
3.0
1.2
1.2
90
80
70
60
50
40
30
20
10
1.5
2.5
FIGURE 12. ISL28197 SHORT CIRCUIT CURRENT vs SUPPLY
VOLTAGE
ENABLE THRESHOLD (V)
ENABLE THRESHOLD (V)
FIGURE 11. ISL28196 SHORT CIRCUIT CURRENT vs SUPPLY
VOLTAGE
1.0
1.5
2.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
0
(Continued)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
FIGURE 15. ISL28196 ENABLE TO OUTPUT DELAY TIME vs
SUPPLY VOLTAGE
5
70
60
50
40
30
20
10
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
FIGURE 16. ISL28197 ENABLE TO OUTPUT DELAY TIME vs
SUPPLY VOLTAGE
FN6152.4
September 29, 2008
ISL28196, ISL28197
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified.
1500
DISABLE TO OUTPUT DELAY (ns)
DISABLE TO OUTPUT DELAY (ns)
1000
950
900
850
800
750
700
650
600
1.5
1400
1300
1200
1100
1000
900
800
700
600
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1.5
2.0
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 17. ISL28196 ENABLE LOW TO OUTPUT TURN-OFF
TIME vs SUPPLY VOLTAGE
1.8
N = 1000
MAX
SUPPLY CURRENT (µA)
4.0
3.0
MEDIAN
2.0
1.5
MIN
1.0
0.5
MAX
N = 1000
1.4
1.2
1.0
MEDIAN
0.8
0.6
0.4
MIN
0.2
-40
-20
0
20
40
60
80
100
0
-40
120
-20
0
TEMPERATURE (°C)
FIGURE 19. ISL28196 SUPPLY CURRENT vs TEMPERATURE,
V+, V- = ±2.5V
90
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 20. ISL28197 SUPPLY CURRENT vs TEMPERATURE,
V+, V- = ±2.5V
100
N = 1000
80
N = 1000
80
70
MAX
60
MEDIAN
60
IBIAS+ (pA)
IBIAS+ (pA)
5.0
1.6
3.5
2.5
4.5
FIGURE 18. ISL28197 ENABLE LOW TO OUTPUT TURN-OFF
TIME vs SUPPLY VOLTAGE
SUPPLY CURRENT (µA)
4.5
(Continued)
50
40
30
MEDIAN
MAX
40
20
MIN
20
0
10
0
-40
MIN
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 21. ISL28196 IBIAS+ vs TEMPERATURE, V+, V- = ±2.5V
6
-20
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 22. ISL28197 IBIAS+ vs TEMPERATURE, V+, V- = ±2.5V
FN6152.4
September 29, 2008
ISL28196, ISL28197
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified.
(Continued)
120
120
N = 1000
N = 1000
100
100
80
80
IBIAS- (pA)
IBIAS- (pA)
MAX
MAX
60
MEDIAN
40
20
MEDIAN
60
40
MIN
20
MIN
0
-40
-20
0
20
40
60
80
100
0
-40
120
-20
0
FIGURE 23. ISL28196 IBIAS- vs TEMPERATURE,
V+, V- = ±2.5V
100
120
40
MAX
50
35
IOS (pA)
IOS (pA)
80
N = 1000
45
60
40
30
30
MAX
25
20
15
20
MEDIAN
5
MIN
0
-40
-20
0
MEDIAN
10
10
20
40
60
80
100
MIN
0
-40
120
-20
0
TEMPERATURE (°C)
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 25. ISL28196 IOS vs TEMPERATURE, V+, V- = ±2.5V
FIGURE 26. ISL28197 IOS vs TEMPERATURE, V+, V- = ±2.5V
3
N = 1000
2
N = 1000
2
MAX
MAX
1
1
VOS (µV)
VOS (µV)
60
50
N = 1000
0
MEDIAN
-1
0
MEDIAN
-1
-2
-2
MIN
-3
-40
40
FIGURE 24. ISL28197 IBIAS- vs TEMPERATURE,
V+, V- = ±2.5V
70
3
20
TEMPERATURE (°C)
TEMPERATURE (°C)
-20
0
20
40
MIN
60
80
100
120
TEMPERATURE (°C)
FIGURE 27. ISL28196 VOS vs TEMPERATURE, V+, V- = ±2.5V
VIN = 2.5V
7
-3
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 28. ISL28197 VOS vs TEMPERATURE, V+, V- = ±2.5V
VIN = 2.5V
FN6152.4
September 29, 2008
ISL28196, ISL28197
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified.
105
N = 1000
MAX
100
100
95
95
CMRR (dB)
CMRR (dB)
105
MEDIAN
90
85
MIN
N = 1000
(Continued)
MAX
MEDIAN
90
85
80
80
75
75
MIN
70
-40
-20
0
20
40
60
80
100
70
-40
120
-20
0
FIGURE 29. ISL28196 CMRR vs TEMPERATURE,
VCM = 0.5V TO 3.5, V+, V- = ±2.5V
110
110
N = 1000
100
95
95
PSRR (dB)
PSRR (dB)
80
100
120
N = 1000
MAX
90
MEDIAN
85
MAX
90
MEDIAN
85
80
80
MIN
75
70
-40
-20
0
20
40
MIN
75
60
80
100
70
-40
120
-20
0
TEMPERATURE (°C)
FIGURE 31. ISL28196 PSRR vs TEMPERATURE,
V+, V- = ±0.9V TO ±2.5V
4.955
4.954
MAX
VOUT (V)
MIN
4.946
MEDIAN
4.944
4.950
4.948
4.947
4.938
4.946
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 33. ISL28196 VOUT HIGH vs TEMPERATURE,
V+, V- = ±2.5V, RL = 10k
8
120
MEDIAN
4.949
4.940
0
MAX
4.951
4.942
-20
120
N = 1000
4.952
4.948
100
4.953
4.950
4.936
-40
20
40
60
80
TEMPERATURE (°C)
FIGURE 32. ISL28197 PSRR vs TEMPERATURE,
V+, V- = ±0.9V TO ±2.5V
N = 1000
4.952
VOUT (V)
60
105
100
4.954
40
FIGURE 30. ISL28197 CMRR vs TEMPERATURE,
VCM = 0.5V TO 3.5, V+, V- = ±2.5V
105
4.956
20
TEMPERATURE (°C)
TEMPERATURE (°C)
4.945
-40
MIN
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 34. ISL28197 VOUT HIGH vs TEMPERATURE,
V+, V- = ±2.5V, RL = 10k
FN6152.4
September 29, 2008
ISL28196, ISL28197
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified.
50
(Continued)
39
N = 1000
N = 1000
45
37
40
35
MAX
VOUT (mV)
VOUT (mV)
MAX
35
30
MEDIAN
25
33
31
MEDIAN
29
20
27
MIN
15
-40
-20
0
MIN
20
40
60
80
TEMPERATURE (°C)
100
25
-40
120
FIGURE 35. ISL28196 VOUT LOW vs TEMPERATURE,
V+, V- = ±2.5V, RL = 10k
1750
120
MAX
MAX
+ PROP DELAY (µs)
+ PROP DELAY (µs)
100
1550
250
230
210
MEDIAN
190
170
MIN
-20
0
20
40
60
80
TEMPERATURE (°C)
1350
1150
950
MEDIAN
750
550
350
100
MIN
150
-40
120
FIGURE 37. ISL28196 POSITIVE PROP DELAY vs
TEMPERATURE 50% TO 20%, V+ = 5V
1700
N = 1000
- PROP DELAY (µs)
MAX
180
160
MEDIAN
120
100
120
N = 1000
1300
MAX
1100
900
700
20
40
60
80
TEMPERATURE (°C)
MIN
100
FIGURE 39. ISL28196 NEGATIVE PROP DELAY vs
TEMPERATURE 50% TO 20%, V+ = 5V
9
MEDIAN
500
100
0
20
40
60
80
TEMPERATURE (°C)
300
MIN
-20
0
1500
200
140
-20
FIGURE 38. ISL28197 POSITIVE PROP DELAY vs
TEMPERATURE 50% TO 20%, V+ = 5V
220
- PROP DELAY (µs)
20
40
60
80
TEMPERATURE (°C)
N = 1000
N = 1000
100
-40
0
FIGURE 36. ISL28197 VOUT LOW vs TEMPERATURE,
V+, V- = ±2.5V, RL = 10k
270
150
-40
-20
120
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 40. ISL28197 NEGATIVE PROP DELAY vs
TEMPERATURE 50% TO 20%, V+ = 5V
FN6152.4
September 29, 2008
ISL28196, ISL28197
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified.
54.5
8.0
N = 1000
N = 1000
49.5
7.5
MAX
44.5
+ PROP DELAY (µs)
+ PROP DELAY (µs)
(Continued)
7.0
6.5
6.0
MEDIAN
5.5
39.5
MAX
34.5
29.5
24.5
MEDIAN
19.5
14.5
5.0
4.5
-40
-20
0
MIN
9.5
MIN
20
40
60
80
TEMPERATURE (°C)
100
4.5
-40
120
FIGURE 41. ISL28196 FALL TIME vs TEMPERATURE 20% TO
80%, V+ = 5V
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 42. ISL28197 FALL TIME vs TEMPERATURE 20% TO
80%, V+ = 5V
Pin Descriptions
ISL28196,
ISL28196,
ISL28197
ISL28197
(6 LD SOT-23) (6 LD µTDFN)
PIN NAME
EQUIVALENT
CIRCUIT
DESCRIPTION
1
4
OUT
Circuit 3
Comparator output
2
2
GND
Circuit 4
GROUND terminal
3
3
IN+
Circuit 1
Comparator non-inverting input
4
1
IN-
Circuit 1
Comparator inverting input
5
5
EN
Circuit 2
Comparator enable pin; Logic “1” selects the enabled state: Logic “0” selects the
disabled state
6
6
V+
Circuit 4
Positive power supply
V+
V+
V+
IN-
V+
100Ω
IN+
LOGIC
PIN
V-
V-
V-
CIRCUIT 1
CIRCUIT 2
Applications Information
Introduction
The ISL28196 and ISL28197 are CMOS rail-to-rail input and
output (RRIO) micropower comparators. These devices are
designed to operate from single supply (1.8V to 5.5V) and
have an input common mode range that extends to the
positive rail and to the negative supply rail for true rail-to-rail
performance. The CMOS output can swing within tens of
millivolts to the rails. Featuring worst case maximum supply
currents of only 4.5µA and 2µA for the ISL28196 and
ISL28197 respectively, these comparators are ideally suited
for solar and battery powered applications.
10
CAPACITIVELY
COUPLED
ESD CLAMP
OUT
VCIRCUIT 3
CIRCUIT 4
Input Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. Both the ISL28196
and ISL28197 have a maximum input differential voltage that
extends beyond the rails (+V + 0.5V to -V - 0.5V).
Rail-to-Rail Output
A pair of complementary MOSFET devices are used to
achieve the rail-to-rail output swing. The NMOS sinks
current to swing the output in the negative direction. The
PMOS sources current to swing the output in the positive
direction. The ISL28196 and ISL28197 with a 100kΩ load
will swing to within 6mV of the positive supply rail and within
3mV of ground.
FN6152.4
September 29, 2008
ISL28196, ISL28197
Break-Before-Make Operation of the Output
The output circuit has a break-before-make response. This
means that the P-Channel turns off before the N-Channel
turns on during a high to low transition of the output
(reference Figure 43). Likewise, the N-Channel turns off
before the P-Channel turns on during a low to high transition.
This results in different propagation delay times depending
upon where the output load resistor is tied to. If the load
resistor is tied to ground, (Figure 44A) then the propagation
delay is controlled by the P-Channel. For a high to low
transition the propagation delay does not include the
additional break-before-make time because the load resistor
will pull the output low once the P-Channel has turned off.
v+
P-CH ON
P-CH OFF
ISL28196 AND ISL28197
OUTPUT STAGE
P-CHANNEL
N-CH OFF
N-CH ON
N-CH OFF
P-CH ON
BREAK-BEFORE-MAKE
VOUT
If the load resistor is tied to V+ (Figure 44B) then the
propagation delay is controlled by the N-Channel. For this
condition, the additional delay time is added to the high to
low transition because the output won’t pull low until the
N-Channel turns on. Figures 3 through 10 show the
differences in propagation delay depending upon where the
load is tied.
Propagation Delay
The input to output propagation delay has a dependency on
power supply voltage, overdrive and whether the output is
sourcing or sinking current. Figures 3 and 5 show a
decreasing time propagation delay vs supply voltage for the
ISL28196 and Figure 4 shows a similar behavior for the
ISL28197. The output break-before-make mechanism
results in a difference in propagation delay, depending on
whether the output stage NMOS and PMOS are sourcing or
sinking current. This delay difference is shown in the figures
as a function of where the load is terminated (+V or -V) and
also as a function of supply voltage. The dependence of
propagation delay as a function of power supply voltage and
input overdrive (from 5mV to 1V) is shown in Figures 7 and 9
for the ISL28196, and Figures 8 and 10 for the ISL28197.
Enable Feature
N-CHANNEL
FIGURE 43. MAKE-BEFORE-BREAK ACTION OF THE
OUTPUT STAGE
During the low to high transition, however, if the load resistor
is tied to ground, then the additional break-before-make time
is added to the propagation delay time because the output
won’t pull high until the P-Channel turns on.
V+
+
-
VOUT
RL
FIGURE 44A. RL TO GND
V+
Both parts offer an EN pin, which enables the device when
pulled high. The enable threshold is referenced to the -V
terminal and has a level proportional to the total supply
voltage (reference Figures 13 and 14 for EN Threshold vs
Supply Voltage). The enable circuit has a delay time that
changes as a function of supply voltage. Figures 23 through
26 show the effect of supply voltage on the enable and
disable times. For supply voltages less than 3V, it is
recommended that the user account for the increase
enable/disable delay time.
In the disabled state (output in a high impedance state), the
supply current is reduced to a typical of only 2nA. By
disabling the devices, multiple parts can be connected
together as a MUX. In this configuration, the outputs are tied
together in parallel and a channel can be selected by the EN
pin. The EN pin should never be left floating. The EN pin
should be connnected directly to the V+ supply when not in
use.
Proper Layout Maximizes Performance
+
-
RL
VOUT
FIGURE 44B. RL TO V+
FIGURE 44. CONNECTION OF RL TO GND AND V+
11
To achieve the maximum performance of the high input
impedance, care should be taken in the circuit board layout.
The PC board surface must remain clean and free of
moisture to avoid leakage currents between adjacent traces.
Surface coating of the circuit board will reduce surface
moisture and provide a humidity barrier, reducing parasitic
resistance on the board. When input leakage current is a
concern, the use of guard rings around the comparator
inputs will further reduce leakage currents.
FN6152.4
September 29, 2008
ISL28196, ISL28197
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power-supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all applications
to determine if power supply voltages, load conditions, or
package type need to be modified to remain in the safe
operating area. These parameters are related in Equation 1:
T JMAX = T MAX + ( θ JA xPD MAXTOTAL )
(EQ. 1)
where:
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
• PDMAX for each amplifier can be calculated as shown in
Equation 2:
V OUTMAX
PD MAX = 2*V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------RL
(EQ. 2)
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Supply voltage (Magnitude of V+ and V-)
• IMAX = Maximum supply current of 1 amplifier
• VOUTMAX = Maximum output voltage swing of the
application
• RL = Load resistance
12
FN6152.4
September 29, 2008
ISL28196, ISL28197
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
A
A
E
6
B
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
4
MILLIMETERS
D
PIN 1
REFERENCE
2X
0.15 C
1
2X
L6.1.6x1.6A
3
MIN
NOMINAL
MAX
NOTES
A
0.45
0.50
0.55
-
A1
-
-
0.05
-
0.127 REF
A3
0.15 C
A1
TOP VIEW
e
1.00 REF
4
6
L
CO.2
D2
SYMBOL
b
0.15
0.20
0.25
-
D
1.55
1.60
1.65
4
D2
0.40
0.45
0.50
-
E
1.55
1.60
1.65
4
E2
0.95
1.00
1.05
-
0.50 BSC
e
DAP SIZE 1.30 x 0.76
L
3
1
b 6X
0.10 M C A B
E2
-
0.25
0.30
0.35
Rev. 1 6/06
NOTES:
1. Dimensions are in mm. Angles in degrees.
BOTTOM VIEW
2. Coplanarity applies to the exposed pad as well as the terminals.
Coplanarity shall not exceed 0.08mm.
DETAIL A
6X
0.10 C
3. Warpage shall not exceed 0.10mm.
0.08 C
4. Package length/package width are considered as special
characteristics.
5. JEDEC Reference MO-229.
A3
SIDE VIEW
C
SEATING
PLANE
6. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
0.127±0.008
0.127 +0.058
-0.008
TERMINAL THICKNESS
A1
DETAIL A
0.25
0.50
1.00
0.45
1.00
2.00
0.30
1.25
LAND PATTERN
13
6
FN6152.4
September 29, 2008
ISL28196, ISL28197
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
1
2X
2
3
0.20 C
5
2X
e
0.20 M C A-B D
B
b
NX
0.15 C A-B
1
3
SOT23-5
SOT23-6
TOLERANCE
A
1.45
1.45
MAX
A1
0.10
0.10
±0.05
A2
1.14
1.14
±0.15
b
0.40
0.40
±0.05
c
0.14
0.14
±0.06
D
2.90
2.90
Basic
E
2.80
2.80
Basic
E1
1.60
1.60
Basic
e
0.95
0.95
Basic
e1
1.90
1.90
Basic
L
0.45
0.45
±0.10
L1
0.60
0.60
Reference
N
5
6
Reference
D
2X
Rev. F 2/07
NOTES:
C
A2
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
SEATING
PLANE
A1
0.10 C
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
NX
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
(L1)
6. SOT23-5 version has no center lead (shown as a dashed line).
H
A
GAUGE
PLANE
c
L
0.25
0° +3°
-0°
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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14
FN6152.4
September 29, 2008
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