DATASHEET

Nano Power, Push/Pull Output Comparator
ISL28915
Features
The ISL28915 is a nano power comparator optimized for
low-power applications. This device is designed for
single-supply operation from 1.8V to 5.5V and typically
consumes 500nA of supply current. These devices also feature
a push/pull output stage with rail-to-rail input and output
swing (RRIO), allowing for maximum battery usage.
• Low Active Current . . . . . . . . . . . . . . . . . . . . . . . . . . 600nA Max
The combination of small footprint, low power, single supply,
and rail-to-rail operation makes them ideally suited for all
battery operated devices.
• Operating Temperature Range. . . . . . . . . . .-40°C to +125°C
The ISL28915 features an enable pin and is offered in the
6 Ld SOT-23 package. The device operates over the -40°C to
+125°C temperature range.
• Low Disable Current. . . . . . . . . . . . . . . . . . . . . . . . . . 20nA Max
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150µs
• Rail-to-Rail Input/Output Voltage Range (RRIO)
• Wide Supply Range . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V
Applications
•
•
•
•
•
•
Battery-Powered/Portable Systems
Telemetry and Remote Systems
Alarm and Monitoring Systems
Oscillator Circuits
Window Comparators
Threshold Detectors/Discriminators
520
VREF
C1
IN+
RL = ∞
500
V+
ISL28915
GND
+
2kΩ
RL
10µF
SUPPLY CURRENT (nA)
IN-
5V
480
460
440
420
400
380
AUDIO SIGNAL PEAK DETECTOR
FIGURE 1. TYPICAL APPLICATION CIRCUIT
July 12, 2012
FN8343.0
1
360
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
FIGURE 2. SUPPLY CURRENT vs SUPPLY VOLTAGE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL28915
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL28915FH6Z-T7
PACKAGE
TAPE & REEL
(Pb-Free)
TEMP RANGE
(°C)
BENA
-40°C to +125°C
SOT23-6
PKG.
DWG. #
P6.064A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28915. For more information on MSL please see techbrief TB363.
Pin Configuration
ISL28915FH6Z
(6 LD SOT-23)
TOP VIEW
OUT 1
6 V+
GND 2
+ -
IN+ 3
5 EN
4 IN-
Pin Descriptions
ISL28915FH6Z
(6 LD SOT-23)
PIN NAME
EQUIVALENT
CIRCUIT
1
OUT
Circuit 3
Comparator output
2
GND
Circuit 4
GROUND terminal
3
IN+
Circuit 1
Comparator non-inverting input
4
IN-
Circuit 1
Comparator inverting input
5
EN
Circuit 2
Comparator enable pin; Logic “1” selects the enabled state: Logic “0” selects the disabled
state
6
V+
Circuit 4
Positive power supply
DESCRIPTION
V+
V+
V+
IN-
IN+
LOGIC
PIN
GND
GND
CIRCUIT 2
2
CAPACITIVELY
COUPLED
ESD CLAMP
OUT
GND
CIRCUIT 1
V+
GND
CIRCUIT 3
CIRCUIT 4
July 12, 2012
FN8343.0
ISL28915
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V
Supply Turn-On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Maximum Differential Input Voltage . . . . . . . . . . . GND - 0.5V to V+ + 0.5V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to V+ + 0.5V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite
ESD Tolerance
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . . 150V
Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . . 1kV
Latch-up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . . at +125°C
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
6 Ld SOT-23 Package (Notes 4, 5) . . . . . . .
239
108
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications
-40°C to +125°C.
PARAMETER
VOS
V+ = 5V, GND = 0V, VCM = 2.5V, TA = +25°C, unless otherwise specified. Boldface limits apply over
DESCRIPTION
CONDITIONS
Input Offset Voltage
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
-2
-0.2
2
mV
2.5
mV
25
pA
67
pA
31
pA
-100
100
pA
5
V
-2.5
IOS
Input Offset Current
-25
-3
-67
IB
Input Bias Current
-31
CMIR
Common Mode Input Range
Established by CMRR test
0
CMRR
Common-Mode Rejection Ratio
VCM = 0.5V to 3.5V
72
PSRR
Power Supply Rejection Ratio
1.2
98
dB
70
dB
VCM = 0V to 5V
60
dB
V+ = 1.8V to 5.5V
77
100
dB
70
VOUT
IS,ON
IS,OFF
Maximum Output Voltage Swing
RL terminated to V+/2
Supply Current, Enabled
Supply Current, Disabled
VSUPPLY
Supply Voltage Range
CIN
Input Capacitance
Output low, RL = 10kΩ
Output high, RL = 10kΩ
dB
35
4.930
VEN = V+ - 0.3V
mV
4.990
500
VEN = GND + 0.3V
70
0.25
1.8
V
600
nA
900
nA
20
nA
50
nA
5.5
V
6
pF
ENABLE INPUT
VENH
Enable Pin High Level
VENL
Enable Pin Low Level
IEN-H,L
Enable Pin Input Current
V+ - 0.3
VEN = 0V, 5V
-80
-200
3
V
2.2
GND + 0.3
V
80
nA
200
nA
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ISL28915
Electrical Specifications
-40°C to +125°C. (Continued)
PARAMETER
V+ = 5V, GND = 0V, VCM = 2.5V, TA = +25°C, unless otherwise specified. Boldface limits apply over
DESCRIPTION
MIN
(Note 6)
CONDITIONS
TYP
MAX
(Note 6)
UNIT
150
260
µs
11
20
µs
TIMING
tPD±
Propagation Delay Low to High and High to
Low
CL = 10pF, 20mV Overdrive
tR/tF
Output Rise/Fall Time
CL = 10pF
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Typical Performance Curves
520
250
RL = ∞
+PROPAGATION DELAY (µs)
SUPPLY CURRENT (nA)
500
480
460
440
420
400
380
360
1.5
2.0
2.5
3.0
3.5
4.0
4.5
RL = 10kΩ
RL TO GND
200
OVERDRIVE = 20mV
150
100
RL TO V+
50
OVERDRIVE = 100mV
0
1.5
5.0
2.0
FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE
RL = 10kΩ
160
RL TO V+
4.0
4.5
5.0
100
RL TO V+
80
60
RL TO GND
OVERDRIVE = 100mV
RL = 10kΩ
V+ = 5V
OVERDRIVE = 20mV
40
3.5
600
RL TO GND
140
120
3.0
FIGURE 4. PROPAGATION DELAY vs SUPPLY VOLTAGE (RISING EDGE)
+PROPAGATION DELAY (µs)
-PROPAGATION DELAY (µs)
180
2.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
20
500
400
RL TO GND
300
V+ = 2V
RL TO V+
200
100
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
FIGURE 5. PROPAGATION DELAY vs SUPPLY VOLTAGE (FALLING EDGE)
4
0
1
10
100
1000
OVERDRIVE (mV)
FIGURE 6. PROPAGATION DELAY vs OVERDRIVE (RISING EDGE)
July 12, 2012
FN8343.0
ISL28915
Typical Performance Curves
(Continued)
30
400
RL = 10kΩ
V+ = 5V
300
OUTPUT CURRENT (mA)
-PROPAGATION DELAY (µs)
350
250
V+ = 2V
200
RL TO V+
150
100
25
SINKING
20
SOURCING
15
10
RL TO GND
50
0
RL = 10Ω
1
10
100
5
1.5
1000
2.0
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
OVERDRIVE (mV)
2.5
900
2.3
880
2.1
1.9
1.7
1.5
1.3
1.5
2.0
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
4.5
860
840
820
800
760
1.5
5.0
FIGURE 9. ENABLE THRESHOLD VOLTAGE vs SUPPLY VOLTAGE
9
650
8
600
7
6
5
4
3
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
4.5
5.0
RL = ∞
550
500
450
400
350
2
1
1.5
2.0
FIGURE 10. ENABLE TO OUTPUT DELAY TIME vs SUPPLY VOLTAGE
SUPPLY CURRENT (nA)
DISABLE TIME (µs)
5.5
780
1.1
0.9
5.0
FIGURE 8. SHORT CIRCUIT CURRENT vs SUPPLY VOLTAGE
ENABLE TIME (µs)
ENABLE THRESHOLD (V)
FIGURE 7. PROPAGATION DELAY vs OVERDRIVE (FALLING EDGE)
4.5
2.0
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
4.5
5.0
FIGURE 11. ENABLE LOW TO OUTPUT TURN-OFF TIME vs SUPPLY
VOLTAGE
5
300
-60
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
FIGURE 12. SUPPLY CURRENT vs TEMPERATURE, V+, GND = ±2.5V
July 12, 2012
FN8343.0
ISL28915
(Continued)
4
6
3
5
2
4
IBIAS- (pA)
IBIAS+ (pA)
Typical Performance Curves
1
3
0
2
-1
1
-2
-60
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
0
-60
140
FIGURE 13. IBIAS+ vs TEMPERATURE, V+, GND = ±2.5V
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
250
230
OFFSET VOLTAGE (µV)
3.5
OFFSET CURRENT (pA)
-20
FIGURE 14. IBIAS- vs TEMPERATURE, V+, GND = ±2.5V
4.0
3.0
2.5
2.0
1.5
1.0
210
190
170
150
130
110
90
70
0.5
0
-60
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
50
-60
140
110
5.000
105
4.998
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
4.996
100
4.994
VOUT (V)
95
90
85
4.992
4.990
4.988
4.986
80
4.984
75
70
-60
-40
FIGURE 16. VOS vs TEMPERATURE, V+, GND = ±2.5V, VCM = 0V
FIGURE 15. IOS vs TEMPERATURE, V+, GND = ±2.5V
CMRR (dB)
-40
4.982
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 17. CMRR vs TEMPERATURE,
VCM = 0.5V TO 3.5, V+, GND = ±2.5V
6
100
120
140
4.980
-60
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
FIGURE 18. VOUT HIGH vs TEMPERATURE,
V+, GND = ±2.5V, RL = 10k
July 12, 2012
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ISL28915
Typical Performance Curves
(Continued)
10
180
9
7
VOUT (mV)
170
+PROPAGATION DELAY (µs)
8
6
5
4
3
2
160
150
140
130
120
110
1
0
-60
-40
-20
0
20
40
60
80
100
120
100
-60
140
-40
-20
0
20
12.5
170
12.0
160
11.5
RISE DELAY (µs)
150
140
130
120
40
140
9.5
8.5
20
120
10.0
100
0
100
10.5
9.0
-20
80
11.0
110
-40
60
FIGURE 20. POSITIVE PROPAGATION DELAY vs TEMPERATURE 50%
TO 50%, V+ = 5V
180
60
80
100
120
8.0
-60
140
-40
-20
TEMPERATURE (°C)
FIGURE 21. NEGATIVE PROPAGATION DELAY vs TEMPERATURE 50%
TO 50%, V+ = 5V
0
20
40
60
TEMPERATURE (°C)
80
100
120
140
FIGURE 22. RISE TIME vs TEMPERATURE 20% TO 80%, V+ = 5V
13
12
FALL DELAY (µs)
-PROPAGATION DELAY (µs)
FIGURE 19. VOUT LOW vs TEMPERATURE,
V+, GND = ±2.5V, RL = 10k
90
-60
40
TEMPERATURE (°C)
TEMPERATURE (°C)
11
10
9
8
7
-60
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
FIGURE 23. FALL TIME vs TEMPERATURE 20% TO 80%, V+ = 5V
7
July 12, 2012
FN8343.0
ISL28915
Applications Information
Introduction
The ISL28915 is a CMOS rail-to-rail input and output (RRIO)
nanopower comparator. This device is designed to operate from
single supply (1.8V to 5.5V) and have an input common mode
range that extends to the positive rail and to the negative supply
rail for true rail-to-rail performance. The CMOS output can swing
within tens of millivolts to the rails. Featuring worst case
maximum supply current of only 900nA, this comparator is
ideally suited for solar and battery powered applications.
Input Protection
During the low to high transition, however, if the load resistor is
tied to ground, then the additional break-before-make time is
added to the propagation delay time because the output won’t
pull high until the P-Channel turns on.
V+
+
-
FIGURE 25A. RL TO GND
V+
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. The ISL28915 has a
maximum input differential voltage that extends beyond the rails
(V+ + 0.5V to GND - 0.5V).
+
-
Rail-to-Rail Output
Break-Before-Make Operation of the Output
The output circuit has a break-before-make response. This
means that the P-Channel turns off before the N-Channel turns
on during a high to low transition of the output (reference
Figure 24). Likewise, the N-Channel turns off before the
P-Channel turns on during a low to high transition. This results in
different propagation delay times depending upon where the
output load resistor is tied to. If the load resistor is tied to ground
(Figure 25A), then the propagation delay is controlled by the
P-Channel. For a high to low transition, the propagation delay
does not include the additional break-before-make time because
the load resistor will pull the output low once the P-Channel has
turned off.
ISL28915
OUTPUT STAGE
P-CH ON
V+
N-CH OFF
N-CH ON
P-CH OFF
BREAK-BEFORE-MAKE
P-CH ON
RL
VOUT
FIGURE 25B. RL TO V+
A pair of complementary MOSFET devices are used to achieve
the rail-to-rail output swing. The NMOS sinks current to swing the
output in the negative direction. The PMOS sources current to
swing the output in the positive direction. The ISL28915 with a
10kΩ load will typically swing to within 10mV of the positive
supply rail and within 35mV of ground.
N-CH OFF
VOUT
RL
P-CHANNEL
VOUT
N-CHANNEL
FIGURE 24. MAKE-BEFORE-BREAK ACTION OF THE OUTPUT STAGE
8
FIGURE 25. CONNECTION OF RL TO GND AND V+
If the load resistor is tied to V+ (Figure 25B), then the
propagation delay is controlled by the N-Channel. For this
condition, the additional delay time is added to the high to low
transition because the output won’t pull low until the N-Channel
turns on. Figures 4 through 7 show the differences in
propagation delay depending upon where the load is tied.
Propagation Delay
The input to output propagation delay has a dependency on
power supply voltage, overdrive and whether the output is
sourcing or sinking current. Figures 4 and 5 show a decreasing
time propagation delay vs supply voltage for the ISL28915. The
output break-before-make mechanism results in a difference in
propagation delay, depending on whether the output stage
NMOS and PMOS are sourcing or sinking current. This delay
difference is shown in the figures as a function of where the load
is terminated (V+ or GND) and also as a function of supply
voltage. The dependence of propagation delay as a function of
power supply voltage and input overdrive (from 5mV to 1V) is
shown in Figures 6 and 7. Propagation delay is measured from
the time the input signal reached 50% of its final value to the
time the output reaches 50% of its final value. Rise and fall times
are measured from the time the signal is at 20% of its final value
to the time it reaches 80% of the final value.
Enable Feature
The ISL28915 in the 6 Ld SOT-23 package offers an EN pin that
enables the device when pulled high. The enable threshold is
referenced to the GND terminal and has a level proportional to the
total supply voltage (reference Figure 9 for EN Threshold vs Supply
Voltage). The enable circuit has a delay time that changes as a
function of supply voltage. Figures 10 and 11 show the effect of
supply voltage on the enable and disable times. The enable and
disable delay is measured from the time the signal crosses the
enable threshold to the time the output reaches 20% of its final
value. For supply voltages less than 3V, it is recommended that the
user account for the increased enable/disable delay time.
July 12, 2012
FN8343.0
ISL28915
In the disabled state (output in a high impedance state), the
supply current is reduced to a typical of only 0.25nA. By disabling
the devices, multiple parts can be connected together as a MUX.
In this configuration, the outputs are tied together in parallel and
a channel can be selected by the EN pin. The EN pin should never
be left floating. The EN pin should be connected directly to the V+
supply when not in use.
Proper Layout Maximizes Performance
To achieve the maximum performance of the high input
impedance, care should be taken in the circuit board layout. The
PC board surface must remain clean and free of moisture to
avoid leakage currents between adjacent traces. Surface coating
of the circuit board will reduce surface moisture and provide a
humidity barrier, reducing parasitic resistance on the board.
When input leakage current is a concern, the use of guard rings
around the comparator inputs will further reduce leakage
currents.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
July 16, 2012
FN8343.0
CHANGE
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL28915
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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9
July 12, 2012
FN8343.0
ISL28915
Package Outline Drawing
P6.064A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
0.95
D
0.08-0.20
A
5
6
4
PIN 1
INDEX AREA
2.80
3
1.60
3
0.15 C D
2x
1
(0.60)
3
2
0.20 C
2x
0.40 ±0.05
B
5
SEE DETAIL X
3
0.20 M C A-B
D
TOP VIEW
2.90
5
END VIEW
10° TYP
(2 PLCS)
0.15 C A-B
2x
H
1.14 ±0.15
C
SIDE VIEW
0.10 C
0.05-0.15
1.45 MAX
SEATING PLANE
DETAIL "X"
(0.25) GAUGE
PLANE
0.45±0.1
4
(0.60)
(1.20)
NOTES:
(2.40)
(0.95)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
This dimension is measured at Datum “H”.
6.
Package conforms to JEDEC MO-178AA.
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
10
July 12, 2012
FN8343.0
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