DATASHEET

ISL55141, ISL55142, ISL55143
Data Sheet
August 13, 2015
High-Speed 18V CMOS Comparators
Features
ISL55141, ISL55142, ISL55143 integrated circuits are
high-speed, wide input common-mode range comparators.
They provide three-state window comparators in a high
voltage CMOS process (18V). Each comparator has dual
receive thresholds, CVA and CVB, for establishing
minimum 1-VIH and maximum 0-VIL voltage levels. These
devices can accept inputs from a number of logic families,
such as TTL, ECL, CMOS, LVCMOS, LVDS and CML. Two
bits of output per comparator provide the test controller with
qualification of a comparator input into three states. The two
output bits work with a separate user supply to establish
VOH, VOL levels compatibility with the system’s controller
logic levels.
• 18V I/O Range
Fast propagation delay (9.5ns typical at ±50mV overdrive)
makes this family compatible with high-speed digital test
systems. The 18V range enables the comparator input to
operate over a wide input range. Two references per input
enable and three state digitalization of input with voltage
swings of up to 13V common mode. The operating
frequency of these devices is typically 65MHz.
Applications
FN6230.4
• 65MHz Operation
• 9.5ns Typical Propagation Delay
• Programmable Input Thresholds
• User Defined Comparator OutputLlevels
• Common-Mode Range Includes Negative Rails
• Small Footprints in QFN Packages
• Power-Down Current <10µA
• Pb-Free (RoHS compliant)
• Burn in ATE
• Low Cost ATE
• Fast Supervisory Power Control
• Instrumentation
High voltage CMOS process makes these devices ideal for
large voltage swing applications, such as special test
voltages levels associated with Flash devices or power
supervision applications and may avoid the need for test bus
isolation relay(s).
DUAL LEVEL COMPARATOR - RECEIVERS
VOH
VCC
QAX
CVAX
VOL
VEE
VOH
VCC
VINPX
QBX
CVBX
VOL
VEE
Note: x denotes 1, 2 or 4 channels for ISL55141, ISL55142 and
ISL55143, respectively
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2008, 2011, 2013, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL55141, ISL55142, ISL55143
Pinouts
QA
3
10 VINP
QB
4
9
6
7
8
CVA
CVB0
CVB1
18
17
16
PD
1
15 VINP1
VEE
2
14 CVA1
VCC
3
13 VCC
VOH
4
12 VEE
VOL
5
11
6
QA0
5
CVB
19
7
8
9
10
ISL55142
(20 LD TSSOP)
TOP VIEW
ISL55141
(14 LD TSSOP)
TOP VIEW
VEE
1
14 PD
CVB0
1
20 CVB1
NC
2
13 NC
VINP0
2
19 VINP1
NC
3
12 CVB
CVA0
3
18 CVA1
4
17 NC
QA
4
11 VINP
PD
QB
5
10 CVA
VEE
5
16 VCC
VOL
6
9 VCC
VCC
6
15 VEE
8 VEE
VOH
7
14 NC
VOL
8
13 NC
QA0
9
12 QB1
QB0 10
11 QA1
7
2
NC
NC
VCC
VEE
VCC
VEE
NC
NC
PD
ISL55143 QUAD DEVICE
(36 LD 6X6 TQFN)
TOP VIEW
36
35
34
33
32
31
30
29
28
25 CVA0
QA1
4
24 CVB1
QB1
5
23 VINP1
QA2
6
22 CVA1
QB2
7
21 CVB2
QA3
8
20 VINP2
QB3
9
19 CVA2
10
11
12
13
14
15
16
17
18
CVB3
3
VINP3
QB0
CVA3
26 VINP0
VCC
2
VEE
QA0
VOL
27 CVB0
VOH
1
VOL
NC
VOH
VOH
NC
NC
11
20
QB1
2
VCC
NC
VEE
12 NC
VOH
1
VOL
NC
VINP0
PD
13
QA1
NC
14
CVA0
VEE
15
QB0
NC
16
NC
ISL55142 SINGLE DEVICE
(20 LD 5X5 QFN)
TOP VIEW
ISL55141 SINGLE DEVICE
(16 LD 4X4 QFN)
TOP VIEW
FN6230.4
August 13, 2015
ISL55141, ISL55142, ISL55143
Pin Descriptions
PIN
FUNCTION
VEE
Negative supply input
QAX
Channel A, CVAX reference driven. Comparator output.
QBX
Channel B, CVBX reference driven. Comparator output.
VOL
Comparator output logic low supply. Unbuffered analog input that sets all QAX, QBX “low” voltage level.
VOH
Comparator output logic high supply. Unbuffered analog input that sets all QAX, QBX “high” voltage level.
VCC
Positive supply input.
CVAX
Channel A comparator reference analog input.
VINPX
Window comparator input. Common to both Channel Ax and Channel Bx.
CVBX
Channel B comparator reference analog input.
PD
Power-down logic input (connect to VEE if not used for power-down).
NC
No internal connection.
TABLE 1. CVA-QA AND CVB-QB BASIC COMPARATOR TRUTH TABLE
INPUT
OUTPUTS*
VINPX
QAX
QBX
<CVAX
<CVBX
0
0
<CVAX
>CVBX
0
1
>CVAX
<CVBX
1
0
>CVAX
>CVBX
1
1
* When QAX/QBX = 1, Output is connect to VOH
* When QAX/QBX = 0, Output is connect to VOL
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
PACKAGE
(Pb-Free)
TEMP. RANGE (°C)
PKG. DWG. #
ISL55141IRZ (No longer
available or supported)
55 141IRZ
-40 to +85
16 Ld QFN
L16.4X4A
ISL55141IVZ (No longer
available or supported)
55141 IVZ
-40 to +85
14 Ld TSSOP
M14.173
ISL55142IRZ (No longer
available or supported)
55142 IRZ
-40 to +85
20 Ld QFN
L20.5x5
ISL55142IVZ (No longer
available or supported)
55142 IVZ
-40 to +85
20 Ld TSSOP
M20.173
ISL55143IRZ
55143 IRZ
-40 to +85
36 Ld TQFN
L36.6X6
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL55141, ISL55142, ISL55143. For more information on MSL
please see techbrief TB363.
3
FN6230.4
August 13, 2015
ISL55141, ISL55142, ISL55143
Absolute Maximum Ratings
Thermal Information
VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 19V
Input Voltages
PD, CVAX, CVBX, VINPX, VOH, VOL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VEE -0.5V) to (VCC +0.5V)
Output Voltage
QAX, QBX . . . . . . . . . . . . . . . . . . . . . (VOL -0.5V) to (VOH +0.5V)
Thermal Resistance (Typical, Note 8)
JA (°C/W)
JC (°C/W)
16 Ld QFN Package (Notes 6, 7). . . . .
40
3
14 Ld TSSOP Package (Notes 4, 5) . .
100
31
20 Ld QFN Package (Notes 6, 7). . . . .
31
1.4
20 Ld TSSOP Package (Notes 4, 5) . .
76
25
36 Ld TQFN Package (Notes 6, 7). . . .
29
0.75
Maximum Junction Temperature (Plastic Plackage) . .
150°
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For JC, the “case temp” location is taken at the package top center.
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
8. Device temperature is closely tied to data-rates, driver loads and overall pin activity. Review “Power Dissipation Considerations” on page 6 for
more information.
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
VCC-VEE
10
15
18
V
Comparator Output High Rail
VOH
VEE+1
VCC-0.5
V
Comparator Output Low Rail
VOL
VEE+0.5
VEE+6
V
Common Mode Input Voltage Range
VCM
VEE
VCC-5
V
Ambient Temperature
TA
-40
+85
°C
Junction Temperature
TJ
+125
°C
Device Power
Electrical Specifications
27
Test Conditions: VCC = 12V, VEE = -3V, VOH = 5V, VOL = 0V, PD = VEE, CLOAD = 15pF, TA = 25°C, unless
otherwise specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 13)
TYP
MAX
(Note 13)
UNITS
50
mV
DC CHARACTERISTICS
Input Offset Voltage
VOS
CVAX = CVBX = 1.5V
Input Bias Current
IBIAS
VINPX - CV(A/B)X = ±5V
10
25
nA
Power-down Current
IPD
PD = VCC
8
25
µA
Power-down Time (Note 11)
tPD
10
µs
Power-up Time (Note 11)
tPU
15
µs
-50
TIMING CHARACTERISTICS
Propagation Delay
4.0
tpd
9.5
15
ns
Rise Time (Note 11)
tr
1.4
ns
Fall Time (Note 11)
tf
1.5
ns
tpd
Propagation Delay Mismatch
Maximum Operating Frequency
FMAXR
Min Pulse Width
tWIDR
0.5
Symmetry 50%
2
ns
65
MHz
7.7
ns
COMPARATOR INPUT
Input Current
IIN
4
VINPX = VCC or VEE
-100
0
100
nA
FN6230.4
August 13, 2015
ISL55141, ISL55142, ISL55143
Electrical Specifications
Test Conditions: VCC = 12V, VEE = -3V, VOH = 5V, VOL = 0V, PD = VEE, CLOAD = 15pF, TA = 25°C, unless
otherwise specified. (Continued)
PARAMETER
SYMBOL
Input Capacitance (Note 11)
MIN
(Note 13)
TEST CONDITIONS
CIN
MAX
(Note 13)
TYP
2.5
UNITS
pF
DIGITAL OUTPUTS QAX, QBX
Output Resistance
RoutR
18
27
37

Output Logic High Voltage
VOH
VOH = 5V, ISOURCE = 1mA
4.9
4.95
5.0
V
Output Logic Low Voltage
VOL
VOL = 0V, ISINK = 1mA
0.00
0.05
0.1
V
ICC
No input data
+8.25
12.5
mA
IEE
No input data
POWER SUPPLIES, STATIC CONDITIONS
Positive Supply DC Current/Comparator
Negative Supply Current/Comparator
Total Power Dissipation/Comparator
-12.5
P (Note 12) Input data at 40MHz
-8.25
mA
670
mW
NOTES:
9. Lab characterization, room temperature, timing parameters matched stimulus/loads, channel-to-channel skew < 500ps, 1ns maximum by design
10. Note about ICC measurement input can approach 140mA (single comparator) at maximum pattern rates
11. Limits should be considered typical and are not production tested.
12. Total Power dissipation per comparator can be approximately calculated from the following:
P = (VCC-VEE)*8.25mW + 90pF*(VCC-VEE)^2*f + CL*(VCC-VEE)^2*f, where f is the operating frequency and CL is the load capacitance.
Because the ISL55142 has two comparators, the power dissipation would be twice of P calculated from this equation. The ISL55143 would be
four times P.
13. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Test Circuits and Waveforms
DATA = 1
DATA = 0
400mV
VINPX
0V
tPDLH
tPDHL
VOH (VH)
50%
QAX, QBX
50%
VOL (VL)
tR
tF
FIGURE 2. COMPARATOR PROPAGATION DELAY AND TRANSITION TIME MEASUREMENT POINTS
CVA 2.4V
+
-
VCC
QA
VINP
CVB 0.4V
+
-
VEE
Although there is no electrical difference between the CVA
and CVB Inputs, if one defines CVA as being the high
threshold and CVB being the low threshold, it becomes
easier to understand the utilization of a dual threshold
comparator. Essentially this enables the qualification of an
incoming signal into three states. In Figure 3, the three
states are Valid Low <0.4V, No-man’s-land (between 0.4
and 2.4V), Valid High >2.4V. Table 2 shows how the QA/QB
truth table would be utilized in the real world.
TABLE 2. QA/QB TRUTH TABLE
QB
QA
QB
<0.4V
0
0
Valid 0
>0.4 and <2.4V
0
1
Invalid
>2.4V
1
1
Valid 1
VINP
COMMENT
FIGURE 3. THREE-STATE WINDOW COMPARATOR FUNDAMENTALS
5
FN6230.4
August 13, 2015
ISL55141, ISL55142, ISL55143
Test Circuits and Waveforms (Continued)
CVA = CVB = 1.5V
+11 VCC
CVA 1.5V
50mV
+
+5V-VOH
VINP
QA
VINP
1.5V
-50mV
tPDLH
VOL
CVB 1.5V
1.5V
tPDHL
VOH (5V)
+
-
QB
QX
50%
50%
VOL (0V)
-3 VEE
FIGURE 4. tPD RECEIVER SWITCHING TEST CIRCUIT
Application Information
The ISL55141, ISL55142, ISL55143 provide 1, 2 and 4 dual
threshold, three-state window comparator(s) in TSSOP or
QFN footprints. They offer a combination of speed (10ns Tpd
and wide voltage range (18V). This product directly
addresses the need for unique common-mode
characteristics while supplying a power-down feature.
Figures 4 and 5 show the stimulus setup and measurement
points for an example propagation delay measurement.
Typical room temperature results are displayed in Figure 12.
FIGURE 5. tPD RECEIVER PROPAGATION DELAY
MEASUREMENT POINTS
The truth table for the receivers is given in Table 1. Receiver
outputs are not tri-statable, and do not incorporate any on-chip
short circuit current protection. Momentary short circuits to
GND, or any supply voltage, will not cause permanent
damage, but care must be taken to avoid longer duration short
circuits. If tolerable to the application, current limiting resistors
can be inserted in series with the QAX and QBX outputs to
protect the receiver outputs from damage due to overcurrent
conditions.
Power-down Features
Figure 5 shows a VINP range of 50mV. In Figure 12 the
offset is increased in the horizontal axis from 50mV above
and below the reference (1.5V) up to 2.5V above and below
the 1.5V reference.
The ISL55141, ISL55142, ISL55143 PD pin provides a
means of reducing current consumption when the device is
not in use. Supply currents fall from ~7mA to less than 10µA
in the power-down mode. The device requires approximately
10µs to power-down and 15µs to power-up.
Two lines are displayed in Figure 12. One represents the
rising-to-rising delay (tPDLH) and the other the
falling-to-falling delay (tPDHL).
Power Supply Bypassing and Printed Circuit
Board Layout
Comparator Features
These three-state window comparators feature high output
current capability, and user defined high and low output levels
to interface with a wide variety of logic families. Each receiver
comprises two comparators and each comparator has an
independent threshold level input, making it easy to
implement (Minimum1-VIH)/(Maximum 0-VIL) logic level
comparator functions. The CVAX and CVBX pins set the
threshold levels of the A and B comparators respectively. VOH
and VOL set all the comparator output levels, and VOH must
be more positive than VOL. These two inputs are unbuffered
supply pins, so the sources driving these pins must provide
adequate current for the expected load. VOH and VOL
typically connect to the power supplies of the logic device
driven by the comparator outputs.
6
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended, lead lengths
should be as short as possible, and the power supply pins
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the VEE pin is
connected to ground, one 0.1µF ceramic capacitor should be
placed from the VCC pin to ground. A 4.7µF tantalum
capacitor should then be connected from the VCC pin to
ground. This same capacitor combination should be placed
at each supply pin to ground if split supplies are to be used.
Power Dissipation Considerations
Specifying continuous data rates, driver loads and driver
level amplitudes are key in determining power supply
requirements as well as dissipation/cooling necessities.
Driver output patterns also impact these needs. The faster
the pin activity, the greater the need to supply current and
remove heat.
FN6230.4
August 13, 2015
ISL55141, ISL55142, ISL55143
The maximum power dissipation allowed in a package is
determined according to Equation 1.
T JMAX - T AMAX
P DMAX = -------------------------------------------- JA
Power Supply Information
OPTIONAL PROTECTION
DIODE
(EQ. 1)
VCC
where:
• TJMAX = Maximum junction temperature
VOH
CVA
• TAMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
QA
VINP
• PDMAX = Maximum power dissipation in the package
Approximate Power Dissipation
(Typ) P = N*[(VCC-VEE)*8.25mW + 90pF*(VCC-VEE)^2*f +
CL*(VOH-VOL)^2*f]
where:
N is the number of comparators in the chip
(1 for ISL55141, 2 for ISL55142 and 4 for ISL55143).
(f) is the operating frequency.
CL is the load capacitor.
QB
CVB
VOL
VEE
OPTIONAL PROTECTION
DIODE
The power dissipation calculated from the above formula
may have an error of ±20 to 25%.
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads.
Power also depends on the number of channels changing
state and frequency of operation. The extent of continuous
active pattern generation/reception will greatly affect
dissipation requirements.
The user should evaluate various heat sink/cooling options
in order to control the ambient temperature part of the
equation. This is especially true if the user’s applications
require continuous, high-speed operation.
Note: The reader is cautioned against assuming the same
level of thermal performance in actual applications. A careful
inspection of conditions in your application should be
conducted.
7
Circuit design must always take into account the internal
EOS/ESD protection structure of the device.
Important Note: The QFN package metal plane is used for
heat sinking of the device. It is electrically connected to the
negative supply potential (VEE). If VEE is tied to ground, the
thermal pad can be connected to ground. Otherwise, the
thermal pad (VEE) must be isolated from other power
planes.
Power Supply Sequencing
The ISL55141, ISL55142, ISL55143 reference every supply
with respect to VEE. Therefore, apply VEE, VOL then VCC
followed by the CVA and CVB supplies. The comparator
VINP pin should not exceed VEE or VCC during power-up.
In cases where inputs may exceed voltage rails during
power-up, series resistance should be employed to
safeguard EOS to the ESD protection diodes.
FN6230.4
August 13, 2015
ISL55141, ISL55142, ISL55143
Typical Performance Curves
Device installed on Intersil ISL55141, ISL55142, ISL55143 Evaluation Boards.
60
30.0
54
27.0
48
ISL55143
21.0
42
18.0
36
ICC (mA)
ICC (mA)
24.0
15.0
ISL55142
12.0
VCC = 18V
VCC = 14V
30
24
18
09.0
06.0
12
ISL55141
03.0
6
00.0
0
10
12
14
16
18
VCC = 10V
3200
1600
80
100
50
160
56
ICC (mA)
40
32
24
4 CHANNELS
140
2 CHANNELS
48
1 CHANNEL
120
3 CHANNEL
100
2 CHANNEL
80
60
16
40
8
20
1600
800
400
200
100
50
0
3200
25
VINP SQUARE WAVE PERIOD IN ns
1 CHANNEL
1600
800
400
200
100
50
25
VINP SQUARE WAVE PERIOD IN ns
FIGURE 8. ISL55142 ICC 1 AND 2 CHANNELS ACTIVE
FIGURE 9. ISL55143 ICC 1, 2, 3, 4 CHANNELS ACTIVE
100
250
90
225
80
VCC = 18V
200
VCC = 18V
70
175
60
ICC (mA)
VCC = 14V
50
40
150
100
75
20
50
10
25
VCC = 10V
1600
800
400
200
100
50
25
VINP SQUARE WAVE PERIOD IN ns
FIGURE 10. ISL55142 2-CHANNEL ICC @ 10V, 14V, AND 18V
8
VCC = 14V
125
30
0
3200
25
180
64
ICC (mA)
200
200
72
ICC (mA)
400
FIGURE 7. ISL55141 ICC vs FREQUENCY @ 10V, 14V, AND
18V
FIGURE 6. ISL55141, ISL55142, ISL55143 QUIESCENT
CURRENT
0
3200
800
VINP SQUARE WAVE PERIOD IN ns
VCC - VEE VOLTAGE
0
3200
VCC = 10V
1600
800
400
200
100
50
25
VINP SQUARE WAVE PERIOD IN ns
FIGURE 11. ISL55143 4-CHANNEL ICC @ 10V, 14V, AND 18V
FN6230.4
August 13, 2015
ISL55141, ISL55142, ISL55143
Typical Performance Curves
Device installed on Intersil ISL55141, ISL55142, ISL55143 Evaluation Boards. (Continued)
15.0
13.5
+tpd DELAY
tPDLH
DELAY (ns)
10.5
9.0
7.5
VCC 15.0
VEE - 3.0
0.5V/DIV
12.0
-tpd DELAY
tPDHL
6.0
4.5
0
3.0
0
0.05 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
VINP INPUT OFFSET ±1.5 VOLT REFERENCE
FIGURE 12. PROPAGATION DELAY @ 14V VCC-VEE
1.0V/DIV
1.5
0
10ns/DIV
FIGURE 13. MINIMUM PULSE WIDTH RESPONSE
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
August 13, 2015
FN6230.4
Moved Ordering Information to page 3 and fixed page 1 layout.
Updated Ordering Information table on page 3.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing (POD) L16.4X4A to the latest revision changes are as follows:
Updated to new POD format by removing table listing dimensions and moving dimensions onto drawing.
Added Typical Recommended Land Pattern. Removed package option.
About Intersil
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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9
FN6230.4
August 13, 2015
ISL55141, ISL55142, ISL55143
Package Outline Drawing
L16.4x4A
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 03/15
2.40
4.00
A
4X 1.50
B
6
13
PIN #1
INDEX AREA
16
6
PIN 1
INDEX AREA
12
1
4.00
12X 0.50
2.40
4
9
0.15
(4X)
5
8
TOP VIEW
0.10 M C A B
4 0.25 +0.05
-0.07
16x 0.40±0.01
BOTTOM VIEW
SEE
DETAIL "X"
0.90±0.10
0.10 C
SEATING
PLANE
C
0.08 C
SIDE VIEW
(3.8 TYP)
(
2.40)
(12x 0.50)
C
(16x 0.25)
(16x 0.60)
0.20 REF
5
+0.03/-0.02
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be either
a mold or mark feature.
10
FN6230.4
August 13, 2015
ISL55141, ISL55142, ISL55143
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
8
14
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
0.20 C B A
7
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06
0.10 C
0.10
GAUGE
PLANE
0.25
5
0°-8°
0.05 MIN
0.15 MAX
CBA
SIDE VIEW
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
11
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation AB-1.
FN6230.4
August 13, 2015
ISL55141, ISL55142, ISL55143
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L20.5x5
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
0.02
0.05
-
A2
-
0.65
1.00
9
0.38
5, 8
A3
b
0.20 REF
0.23
0.30
9
D
5.00 BSC
-
D1
4.75 BSC
9
D2
2.95
E
E1
E2
3.10
3.25
7, 8
5.00 BSC
-
4.75 BSC
2.95
e
3.10
9
3.25
7, 8
0.65 BSC
-
k
0.20
-
-
-
L
0.35
0.60
0.75
8
N
20
2
Nd
5
3
Ne
5
3
P
-
-
0.60
9

-
-
12
9
Rev. 4 11/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P &  are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220VHHC Issue I except for the "b"
dimension.
12
FN6230.4
August 13, 2015
ISL55141, ISL55142, ISL55143
Package Outline Drawing
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
6.50 ±0.10
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
SEE DETAIL "X"
10
20
3
0.20 C B A
1
9
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
H
- 0.05
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25 +0.05/-0.06 5
0.10 M C B A
0.10 C
0°-8°
0.05 MIN
0.15 MAX
SIDE VIEW
0.25
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
13
FN6230.4
August 13, 2015
ISL55141, ISL55142, ISL55143
Package Outline Drawing
L36.6x6
36 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 08/08
6.00
A
36
28
6
27
PIN 1
INDEX AREA
1
4.15 +0.10/-0.15
6.00
4X 4.00
9
19
(4X)
6
PIN #1 INDEX AREA
32 x 0.50
B
0.15
10
18
TOP VIEW
36 X 0.55 ± 0.10
36 X 0.25 +0.05/-.07 4
0.10 M C A B
BOTTOM VIEW
( 5.65 )
( 4.15)
Exp. Dap.
SEE DETAIL "X"
( 5.65 )
( 32 x 0.50)
0.10 C
Max 0.80
C
0.08C
( 4.15)
Exp. Dap.
SIDE VIEW
(36 X .25)
0.2 REF
5
0.00 MIN.
0.05 MAX.
( 4 X 4.00)
(36X 0.75)
TYPICAL RECOMMENDED LAND PATTERN
C
DETAIL "X"
1. Dimensions are in millimeters.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
14
FN6230.4
August 13, 2015
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