an1217

ISL55100A/BEVAL3/3Z Evaluation Board User’s
Guide
®
Application Note
September 12, 2008
AN1217.1
ISL55100 Device Application Overview
The ISL55100 is a Quad Driver/Receiver device that is
typically utilized in bi-directional testing applications where
formatted timing sets “write data to” and “read data back”
from digital devices.
Examples of bi-directional bus based devices are UARTs,
Real Time Clocks, Interrupt Controllers, Parallel I/O devices,
FPGA's and others. Memory devices are also bi-directional
in that data can be stored in them and then retrieved at a
later time.
The ISL55100 provides four driver/receiver pairs
(DOUT0-3/VINP0-3) that are usually tied together in order to
support bi-directional communications (bus cycle emulation).
HIZ control of the drivers enables this configuration.
50
46
42
38
53
49
45
41
23
30
33
35
21
28
31
34
VH0
VH1
VH2
VH3
CVB0
CVB1
CVB2
CVB3
CVA0
CVA1
CVA2
CVA3
LOW
DRIVER
HIGH
RAILS
MINI DOUT0
MAX0
52
RCVR THRESHOLDS
22
VINP0
The ISL55100A/BEVAL3/3Z Evaluation Board enables easy
access to the various ISL55100 connections. All inputs and outputs
are matched for signal path length.
.
QUAD - WIDE RANGE, LOW ROUT, TRI-STATABLE - DRIVERS
DOUT1 48
VH(0-3)
VINP1 29
ISL55100
DATA+(0-3)
DOUT2 44
VINP2 32
VCC 27, 59, 61, 67
VEE 26, 60, 62, 68
DOUT3 40
VINP3 36
VL(0-3)
DRV_EN+(0-3)
DRV_EN-(0-3)
+
-
VCC
VEE
COMP HIGH
VCC
QA(0-3)
27
VEXT
COMP OUT LOW RAIL
26
70 QA0
69
QB0
3
4 QA1
QB1
9
10 QA2
QB2
15
16 QA3
QB3
24 COMP OUT HIGH RAIL
25
DATA-(0-3)
DOUT(0-3)
+
-
QUAD - DUAL LEVEL COMPARATOR - RECEIVERS
COMPARATOR OUTPUTS
BITS 0- 3
/LOWSWING
54
37
VL0
VL1
VL2
VL3
1
2 DATA+0
DATA-0
72
71 /DRV EN+0
/DRV EN-0
7
8 DATA+1
DATA-1
5
/DRV
EN+1
6
/DRV EN-1
13
14 DATA+2
DATA-2
11
12 /DRV EN+2
/DRV EN-2
19
20 DATA+3
DATA-3
17
18 /DRV EN+3
/DRV EN-3
FIGURE 2. DEVICE AREA, ISL55100A/BEVAL3/3Z
EVALUATION BOARD
CVA(0-3)
COMP LOW
VEE
FIGURE 1. FUNCTIONAL ISL55100A/BEVAL3/3Z PINOUT
COMP HIGH
The ISL55100 provides the means of “translating” the DUT's
bus levels for a test system (Figure 3). Level translation on
“Write Operations” is accomplished with the drivers. “Read
Operation” level translation is done via the
receiver/comparators. Comparator QA/QB outputs adjust
their levels to the tester side logic levels by way of the
COMP-HIGH and COMP-LOW levels. Comparators in the
receivers set the DUT side level thresholds. Further the
Window Comparators (Dual Threshold Receivers) enable
received data to be verified for proper levels (Valid1, Valid 0).
Level translation enables the Pin Electronics Pattern
Devices to write data to and read data back from different
types of logic families.
1
VCC
VINP(0-3)
QB(0-3)
COMP LOW
CVB(0-3)
VEE
FIGURE 3. DIAGRAM OF ISL55100A/BEVAL3/3Z DRIVERS
AND RECEIVERS
The ISL55100A/BEVAL3/3Z is made up of four drivers and four dual
level receivers. Drivers provide voltage level translation for “Write”
operations while the Dual Level Comparators translate voltage
levels for “Read” operations.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1217
ISL55100A/BEVAL3/3Z Evaluation Board
Basic Design Fundamentals Include:
The ISL55100A/BEVAL3/3Z Evaluation board provides the
means to experiment with an Intersil ISL55100A/BEVAL3/3Z
Quad Driver Receiver. Experiments typically include Driver
Waveform analysis based on the user's load. Driver analysis
may also include waveforms at various voltage rails and also
include data propagation and HIZ transition timing.
• Matched circuit lengths on DATA inputs, Driver Outputs
and Comparator measurement points.
The user can also collect information related to receiver
comparator characteristics, device dynamic power
consumption and the timing of comparator outputs. In
addition, the evaluation board accommodates loop-back
testing and exercising of the LowSwing and VEXT modes of
operation.
• Banana jack terminals used for low frequency
connections. (Power supplies, VDIGC/D Bias Busses)
• BNC connectors for high frequency connections. (Driver
data and enable inputs, driver outputs, receiver inputs,
comparator outputs)
• Jumpers for static mode selections. (LowSwing,
Differential Biasing, VEXT)
• All DATA, DRV_EN and VINP signals have 50Ω loads to
ground and may be jumpered to test busses via jumpers.
The DOUT_LOAD and VDIGC/D busses on the
ISL55100A/BEVAL3/3Z Evaluation board provide the user
with flexibility to initiate special analysis. This document sets
up the ISL55100A/BEVAL3/3Z in a typical
usage/configuration. As the user progresses in knowledge,
the concept behind the analysis capability of the
DOUT_LOAD, VDIGC and VDIGD should become evident.
FIGURE 5. HIGH SPEED, TESTER SIDE, DRIVER
CONNECTIONS
There are six high speed BNC tester side connections for each of
the four channels: DATA± control the high/low activity. DRV_EN±
enable/disable the driver outputs and QA/QB are receiver/window
comparator outputs.
FIGURE 6. LOW FREQUENCY CONNECTORS
FIGURE 4. ISL55100A/BEVAL3/3Z EVALUATION BOARD
BNC’s are used for high frequency connections. Banana plugs
and jumpers are used for low frequency/power supply
connections.
2
COMP_HIGH and LOW, CVA, CVB, VEE, VCC, GND and
VDIGC/D are low frequency power supply banana jack
connections.
AN1217.1
September 12, 2008
Application Note 1217
Driver Data and Driver Enable Differential Inputs
Overview
DATA+0
DATA+0
DATA-0
DATA-0
DATA+0
DATA+0
R17
R17
49.9
49.9
0
0
JP13
JP13
DATA-0
DATA-0
R18
R18
49.9
49.9
JP14
JP14
VDIGD
VDIGD
0
0
DRVEN+0
DRVEN+0
DRVEN-0
DRVEN-0
DRV_EN+0
R36
R36
49.9
49.9
0
0
JP27
JP27
DRV_EN-0
DRVEN-0
R35
R35
49.9
49.9
JP28
JP28
VDIGD
VDIGD
0
0
FIGURE 7. EACH DRIVER HAS FOUR INPUT CONTROL LINES
The user may wish to remove the 49.9Ω resistors and terminate
the inputs differently to ground. For series termination, all
resistors and jumpers would be removed. The user can then
install resistors across the differential inputs by connecting a
resistor from the signal side of JP13/JP27 (+ inputs) to the signal
side of JP14/JP28 (- inputs).
SINGLE-ENDED CONTROL
An important note to remember is the user must NOT tie one
of the inputs to ground. Often this is mistakenly done to
enable “Single-Ended” control. However, connecting one
input to ground and toggling the other input usually results in
both inputs being at the same voltage level (Ground) when
the driven signal is low.
The proper remedy to obtain Single-Ended control is to bias
one of the inputs to the “mid-level” of the other inputs
planned voltage swing. Example; a TTL driver is 2.8V when
high and 0.4V when low. The preferred bias level of the
paired differential input will be 1.4V.
Preparation for Power-up
JUMPER DISCUSSION
Note: A Jumper Placement Summary is located on page
page 4.
The ISL55100 Evaluation board enables single-ended input
via two design attributes. First, jumpers are provided on all
DATA+(0-3), DATA-(0-3), DRV_EN+(0-3), DRV_EN-(0-3)
inputs. These jumpers enable the selected inputs to be
connected to a Bias Bus on the Evaluation board. Second,
this bias bus VDIGD is connected to a banana jack for
connection to a DC bias voltage. The ISL55100 Evaluation
board is typically shipped with the jumpers set to connect
DATA-(0-3) and DRV_EN-(0-3) to the bias bus VDIGD.
DIFFERENTIAL INPUTS
DATA± and DRV_EN± are differential inputs. For each of the
four drivers, there are four input signals. DATA+, DATA- and
DRV_EN+, DRV_EN-. The DATA+ and DATA- inputs will
control if the Driver Output is driven to the High Driver Rail
(VH) or the Low Driver Rail (VL). The DRV_EN+ and
DRV_EN-inputs enable or disable the Driver Output. When
enabled, the Driver Output will be driven either to the Driver
High Rail or the Driver Low Rail. When disabled, the Driver
Output floats to a High Impedance condition (HIZ). The
ability to “Float” the Drivers enables bi-directional operations,
or shared bus line utilization.
Caution: These paired inputs: DATA+, DATA- and
DRV_EN+, DRV_EN- must NOT be driven to the same
voltage level. DATA+ and DATA- must be at least 200mV
apart in voltage level. DRV_EN+ and DRV_EN- must also be
at least 200mV apart in voltage level. The differential
receivers within the ISL55100 can exhibit high speed chatter
if their inputs are at the same voltage level. The user will
notice an increase in ISL55100's ICC if the chatter condition
exists.
The differential inputs need to transition quickly (<5ns) with
respect to each other. When DATA+ is 200mV (or more)
higher than DATA-, the associated driver output will be
driven to the High Driver Rail/Supply (VH). When DATA+ is
lower than DATA- by 200mV or more, the associated driver
output will be driven to the Low Driver Rail/Supply (VL).
3
During initial setup of the board, it is recommended the
VDIGD Banana Jack be connected to a 0.5V DC supply. The
reason for the low voltage level relates to the 50Ω load
resistors on all inputs. Keeping the bias low reduces the
current requirements of the bias supply. This enables the
user to become familiar with the ISL55100 until such time as
experiments possibly lead to the removal of the 50Ω
resistors and the addition of series termination across the +
and - differential inputs.
As a result, in the early experiment stages, it is
recommended that Jumpers 14, 28, 01, 03, 10, 07, 08 and
25 be installed. Jumpers 13, 27, 02, 04, 09, 05, 06, 26
should be removed. In this configuration, VDIGD banana
jack will need to be connected to a 0.5V DC Power Supply at
the proper time in the power-up sequence (see Table 1).
/Lowswing and VEXT Mode Jumpers
There are two mode jumpers on the ISL55100 Eval board.
First, the /LowSwing (Pin 37 of the 55100) JP30 should be
placed in the VCC position. Second, the V5V banana jack
(Pin 54 of the ISL55100) JP29 should be placed in the VEE
position.
Comparator Threshold Jumpers
Both CVA Input - JP12 and CVB Input - JP15 should be
removed.
AN1217.1
September 12, 2008
Application Note 1217
Receiver Input Bias Jumpers
VEXT not in use.............JP29 in VEE Position
The four receivers (VINP0-3) should have the bias Jumpers
removed. JP21, 11, 22, 23 should not be installed. These
jumpers enable the connection of the four receivers to a bias
bus “VDIGC” on the ISL55100A/BEVAL3/3Z Evaluation
Board. This feature will not be used during early experiments
with the ISL55100 but may be of use to the user in later
experiments.
JUMPER SETUP SUMMARY
Note: Detailed discussion on Jumper Placement is given on
page 3.
Jumpers Installed
Negative Differential Input connections to the VDIGD (0.5V)
Bias Bus.
• DATA-0 JP14
• DATA-1 JP01
• DATA-2 JP10
• DATA-3 JP08
• DRV_EN-0 JP28
FIGURE 8. EVALUATION BOARD JUMPERS AND LOADS
• DRV_EN-1 JP03
Jumpers are placed in a circle around the ISL55100. Please note
that all inputs have 50Ω resistors to ground. Configuring the
jumpers as shown will place the drivers in “driven - low” output,
enabled, and compatible with single ended operation.
• DRV_EN-2 JP07
• DRV_EN-3 JP25
Jumpers Removed
Positive Differential Inputs, No VDIGD bias connection
• DATA+0 JP13
• DATA+1 JP02
• DATA+2 JP09
• DATA+3 JP06
• DRV_EN+0 JP27
• DRV_EN+1 JP04
• DRV_EN+2 JP05
• DRV_EN+3 JP26
CVA Input - JP12 and CVB Input - JP15
VINP, no bias (VDIGC not connected)
• VINP0 JP21
• VINP1 JP11
• VINP2 JP22
• VINP3 JP23
Jumpers Positioned
/LowSwing Mode Off..... JP30 in VCC Position
4
AN1217.1
September 12, 2008
Application Note 1217
Power Supply Connections
Power Supply Sequence, Quick Overview
TABLE 1. ISL55100A/BEVAL3/3Z POWER SUPPLY SEQUENCE/SETUP OVERVIEW
SEQ#
BANANA1
LABEL
SUPPLY DESC
BANANA2
LABEL
VOLTAGE
NOTE
1
VEE - Device Power
VEE
GND
-3.0
70mA quiescent to 450mA
2
VCC - Device Power
VCC
GND
12.0
70mA quiescent to 450mA
3
Vbias - Single Ended
VDIGD
GND
0.5
4
COMP-HIGH and
COMP-LOW
COMP-HIGH
COMP-LOW,
GND
3.0
COMP-HIGH must be > COMP-LOW
5
Rcvr Threshold #1
CVA
GND
2.0
If missing, Comparator Outputs may chatter*
6
Rcvr Threshold #2
CVB
GND
1.0
If missing, Comparator Outputs may chatter*
7
Driver High Rail
VH
GND
3.0
10-800mA
8
Driver Low Rail
VL
GND
-1.0
10-800mA
80mA
If missing, drivers will
chatter*
Determined by driver load,
driver rails and frequency
Seq 1 to 6 should be applied in as little time as possible. Remove in reverse order. If supply current exceeds quiescent values, power-down
immediately. Supply 7 to 8 can be applied at leisure.
No supply should exceed VEE on the negative side or VCC on the positive side.
* Chatter - Condition where driver or receiver is in an indeterminate state, toggling between high and low. Chatter can cause excessive current
drain and possible damage to the ISL55100.
POWER SUPPLY DISCUSSION
All power supplies should be referenced to the “GND”
Ground Banana Jack at the corner of the board. Please
consult the data sheet for recommended and max voltages
used with the ISL55100A/B. In this document we will supply
“typical” settings as a starting point for the user.
An ideal quantity of power supplies would be 8 supplies, all
with voltage/current displays. In addition, two variable DC
sources will be used for various experiments. Another
5.5V/100mA supply will be needed if you with to try the
VEXT mode. The supplies operate in the 1V to 20V range
and should be rated for ~1A.
At no time should any of the other supplies exceed the VCC
voltage or be less than the VEE voltage. Note that internal
protection circuits assume VH > VL and COMP_HIGH >
COMP_LOW.
These are the three main supplies that need to come up
quickly for the ISL55100 to work properly. Check the current
drains of VEE/VCC to see if they are ~70mA. (DATA±,
DRV_EN± at static levels, no toggling). If the currents are not
in this range, power down the board and check the
differential bias connections.
Next power-up the Comparator Output Rails (COMP_HIGH
and COMP_LOW) and the Comparator Threshold Inputs
CVA’s and CVB’s.
Comparator Output Rails
Connect +3.0V across the COMP_HIGH and COMP_LOW
banana jacks. Also, connect the COMP_LOW banana jack
to the GND banana jack on the board. Current will be
<20mA.
Comparator Thresholds
Connect CVA to +2.0V, Reference to ground (GND)
Main Device Power
For a typical setup the main supplies are:
Device Logic VEE -3.0V to ground (GND), 70mA with the
drivers/receivers in a static condition, to up to 450mA at high
frequency.
Connect CVB to +1.0V, Reference to ground (GND)
Current on the CVA and CVB inputs <20mA
Driver Rails
Connect VH to +3.0V, current will be <10mA*
Device Logic VCC +12.0V to ground (GND), 70mA with the
drivers/receivers in a static condition, to up to 450mA at high
frequency.
Connect VL to -1.0V, current will be <10mA*. Wire this
supply as a negative supply.
VDIGD Bias Bus should be set to + 0.5V to ground (GND),
80mA (Due to 50Ω loads on differential inputs).
* VH/VL Current depends on the User's Driver Load
(C33 to 36) and frequency of operation. The <10mA current
is based on quiescent operating conditions and no resistive
load on the driver outputs.
5
AN1217.1
September 12, 2008
Application Note 1217
Note: If supplies are limited, CVA/CVB can be tied to the
same supply. Do not leave either one floating or connected
to ground as this will cause the comparator output to chatter.
Chattering occurs if the input to a comparator is equal to the
threshold voltage. If the receiver input is connected to
ground via the 50Ω resistor and 0.0V is applied to CVA or
CVB then both the input and the threshold will be at 0.0V.
Any noise coupling will cause the comparator outputs
QA/QB to “Chatter” high and low with the system noise.
COMPARATOR DISCUSSION
Most computer busses deal with one of two states during
active bus transactions. They are high, usually considered a
digital 1, or low, usually considered a digital 0.
But digital 1’s and 0’s must operate in an analog world so a
tolerance is assigned. The minimum voltage a digital pin can
be and still be considered a valid 1 is the VIH level. Likewise,
the maximum voltage a digital pin can be and still be
considered a valid 0 is the VIL level.
VOH/VOL AND VIH/VIL DISCUSSION
TTL logic levels are assigned these levels:
(VOH, VOL define the Driver Output Rails (VH/VL))
• VOH: A driver driving a digital 1 must assert a minimum of
2.8V to be valid.
• VOL: A driver driving a digital 0 must assert a maximum of
0.4V to be valid.
These voltages are specified at the Driver (High 2.8V, Low
0.4V). However there is an allowance between drive levels
and receive thresholds. This allowance is for loss through
the circuit paths. A TTL Digital Receiver must be designed
such that:
(VIH, VIL define the Receiver Comparator Thresholds)
CVB would be set to 0.8V. CVB comparator drives the QB
Outputs.
Here are examples of QA/QB levels based on various VINP
voltages. (Examples include 50mV Offset per ISL55100
Data Sheet)
1. If VINP = 0.0V then QA = 0, QB = 0
VINP is less than both thresholds, a valid digital 0.
2. If VINP = 0.75V then QA = 0, QB = 0
VINP is still less than both thresholds and still a valid
digital 0.
3. If VINP = 0.85V then QA = 0, QB = 1
VINP is > CVB threshold of.8V but less than the CVA
threshold of 2.4V.
4. If VINP = 2.35V then QA = 0, QB = 1
VINP is > CVB threshold of.8V but less than the CVA
threshold of 2.4V.
5. If VINP = 2.45V then QA = 1, QB = 1
VINP is > both CVA and CVB thresholds, A valid digital 1.
6. If VINP = 2.80V then QA = 1, QB = 1
VINP is > both CVA and CVB thresholds, Still valid digital 1.
Window Comparators Bring Real World Benefits in
the Test World
First, the dual thresholds normally detect “slow” pins.
Therefore, they provide insight into weak devices. Window
comparators detect the fact that the pin is changing, just not
quickly enough.
WINDOW COMPARATOR UTILIZATION
COMP HIGH
VCC
MINIMUM VALID 1
QA
• VIL: Any received voltage of <0.8V is considered a valid
digital 0.
COMP LOW
• VIH: Any received voltage of >2.4V is considered a valid
digital 1.
COMP HIGH
CVA 2.4V
VEE
VINP
VCC
QB
Window Comparators go beyond the ability to merely detect
1 and 0 voltage levels. Window Comparators can detect
indeterminate pin states (often slow transition pins in the real
world).
Window comparators have 2 bits of information for each
digital receiver under test. With 2 bits, the tester side logic
can determine if the pin under test is a valid digital 1/0 or an
illegal voltage level.
In our example, TTL Test Application, we will use the CVA
voltage to set the Min1 (VIH) Threshold and the CVB voltage
to set the Max1 (VIL) Threshold.
CVA would be set to 2.4V. CVA comparator drives the QA
Outputs.
6
COMP LOW
CVB 0.8V
VEE
MAXIMUM VALID 0
FIGURE 9. WINDOW COMPARATOR USING TTL THRESHOLDS
TABLE 2. WINDOW COMPARATOR TRUTH TABLE
CVA
CVB
VINP
QA
QB
2.4V
0.8V
<0.75V
0
0
2.4V
0.8V
0.85V to 2.35V
0
1
2.4V
0.8V
>2.45V
1
1
Secondly, since the user is testing unknowns, verifying pin
activity during write cycles detects shorts in the device under
AN1217.1
September 12, 2008
Application Note 1217
test. Often these are high-impedance shorts. Detecting
these types of failures helps in reducing troubleshooting
time. This is one reason why all drivers should be
looped-back to receivers even when the pin is being used in
a driver only situation (typical example is the Address bus).
Looping drivers back for verification is a good test
design/development practice.
TABLE 3. BASIC EXAMPLES OF VIH, VIL VOLTAGE LEVELS
LOGIC
FAMILY
SUB FAMILIES
VIL VOLTS
VIH VOLTS
CMOS
AC-HC-AHC-C
1.30
3.70
TTL/CMOS
ACT-HCT-AHCT-FCT
0.8
2.40
TTL
F-S-AS-LS-ALS
0.8
2.40
NOTE: Window comparators are used to verify receiver inputs meet
VIL, VIH requirements.
SLOW SPEED COMPARATOR OBSERVATIONS
With the board powered up as detailed in Table 1 and
jumpers set as previously defined, connect a DC source to
the VINP0 BNC. Keep the voltage low, as there is a 50Ω
load resistor to ground (R29). Place a scope or a couple of
voltmeters on QA0 and QB0. Assuming CVA is set to 2.4V
and CVB is set to 0.8V, slowly vary the power supply up and
down. You should be able to verify Table 2.
As long as the input voltage is <0.8V, both QA and QB will be
at low levels. Once you move the supply above 0.8V QB will
become a 1 but QA will remain a 0 until the volt exceeds
2.4V at which point the QA comparator will switch to a one
and both QA and QB will be a high.
QA0
QA0
P2
0
P1
R12
DNP
R11
DNP
QB0
QB0
FIGURE 10. QA/QB BNC COMPARATOR OUTPUTS
There are locations on the evaluation board for load resistors on
the comparator outputs. However, they are not populated.
(DNP = Do not populate.)
The QA/QB high and low voltage levels are determined by
the COMP supply. The comparators will drive the QA/QB to
the COMP-HIGH level whenever VINP exceeds the CVA
/CVB threshold levels. When VINP is less than the CVA/CVB
levels, the comparators drive the QA/QB signals to the
COMP-LOW signal. The voltage you connect across
COMP-HIGH and COMP-LOW determines the amount of
voltage swing the Comparator Outputs QA/QB will put out.
7
There is only one COMP_HIGH/COMP_LOW connection for
all four receivers.
SLOW SPEED DRIVER DATA OBSERVATIONS
Data Control (Digital 1, Digital 0)
With the board powered up as detailed in Table 1 and
jumpers set as previously defined, place a scope on DOUT0
BNC. The DOUT0 should be sitting at VL voltage. Connect a
power supply to the DATA+0 BNC. Set the voltage to 1.0V.
The DOUT pin should transition to the VH voltage. Moving
the supply >200mV above and below the 0.5 bias voltage
will cause the output to toggle between VH and VL.
SLOW SPEED DRIVER HIZ OBSERVATIONS
Driver Enable Control (Enabled, HIZ)
With the 1.0V still applied to DATA+0 BNC (DOUT should be
at VH Voltage), use another jumper and connect the 1.0V to
the DRV_EN+0 BNC. This “disables” the DOUT0 Output.
The Output will float slowly downward. Connect the DOUT
Pin to ground through a 1kΩ resistor. When DRV_EN+0 is
set high the DOUT 0 will be pulled to ground.
Remove the DRV_EN+0 jumper. Set the VL voltage to -3V.
Verify that DOUT now transitions from +3 to -3V as you
toggle the DATA+0 BNC between ground and 1.0V. You can
verify that the driver is always enabled because the DOUT is
either +3 to -3V.
Re-apply the 1.0V to the DRV_EN +0 BNC. Notice the
DOUT floats down to 0V because of the 1k DOUT load. This
verifies the driver is not connected to either VH or VL rail.
The driver output is in a HIZ state. In this state other devices
can now drive the DOUT pin and not conflict with the
ISL55100 Driver.
With the driver disabled, the DOUT bus connection can be
driven by another device. The HIZ function enables
computer busses to multiplex common bus pins among
several computer subsystems.
DYNAMIC DRIVER OBSERVATIONS
Connect the DATA+ inputs to a pattern or pulse generator.
Start by setting up a 10MHz square wave into DATA+0 and
place a scope on DOUT0. Remember, the generator will be
driving a 50Ω load and must be of sufficient amplitude to go
> 200mV above the 0.5V bias when high and 200mV below
the 0.5V bias when low. Since DRV_EN+0 is low, DOUT0
should be enabled and should be following the generators
output. Propagation delay will be about 10ns. Therefore,
10nsec after the generator rises above 0.5V, the DOUT
should rise to the VH-Rail value of 3.0V. Likewise it should
fall back to VL volts when the generator output falls below
0.5V.
DYNAMIC POWER OBSERVATIONS
As you increase and decrease the frequency of the
generator, the ICC current of the VCC and VEE will rise and
AN1217.1
September 12, 2008
Application Note 1217
fall with the pin activity. Remember to keep an eye on the
ISL55100 Device Temperature. It is possible to damage the
device if it is run at high frequency without proper cooling.
Remember also, as you add more channels the power
consumption will go up accordingly.
DRIVER LOAD OBSERVATIONS
C33, C34, C35, C36 provide load locations for DOUT 0, 1, 2
and 3.
VCC 12.0 VH 6.0
VEE - 3.0 VL 0.0
DATA IN
2V/DIV
2V/DIV
DATA IN
0
DRIVER OUT
VCC 12.0 VH 6.0
VEE - 3.0 VL 0.0
20ns/DIV
FIGURE 12. DATA AND DRVEN CONTROL OF DRIVER OUT
With HIZ control, driver outputs are only enabled when DRV_EN
is in the proper state. If disabled, the DOUT floats. There is ~20ns
of propagation delay on the DRV_EN control and ~10ns on the
DATA control.
In the above example, the Driver output is tied to a current limited
3.0 voltage source with Drive High Rail of 6.0V and a Low Rail of
0.0V. Your HIZ experiments should include your drive rail voltage
values and driver loads
680pF
1K/100pF
2200pF
0
DRV_EN
0
0
During these experiments you should check out C33 on the
evaluation board. In most cases it will be empty when
shipped, unless you have requested a specific load installed
prior to shipment from the factory. C33 is the location where
you can add capacitance and resistors to simulate your
desired load.
0
HIZ OBSERVATIONS
1000pF
10ns/DIV
FIGURE 11. DRIVER WAVEFORMS UNDER VARIOUS LOADS
C33-C36 are surface mount locations where user defined
driver loads can be installed.
DOUT_LOAD BUS
There is a DOUT_LOAD Banana jack. This bus connects to
the DOUT(s) via R13, R14, R15, and R16, which are located
on the bottom of the board. This bus enables you to “Bias”
the drivers via user selectable resistors so you can either
load them to ground or apply a voltage. Normally these load
locations (R13 to R16) are not populated when shipped from
the factory.
Setting your drive rails to +3 and -3V improves observation
of the HIZ operation of the driver. Connect a 1k resistor from
DOUT0 to ground. Observe the waveform on DOUT0 with
the Generator connected to DATA+0. The DOUT signal
should be transitioning from +3 to -3V. This means the driver
is always enabled.
Now apply another synchronized pulse to DRV_EN+0.
Whenever DRV_EN+0 is low the driver is enabled, and
active for either at +3 or -3V. However, when DRV_EN+0 is
driven high, the DOUT0 signal goes to HIZ and the 1k DOUT
load resistor will pull the output to ground. A 1k load will work
when running slow, but as speed increases you have to
decrease the value of the load resistor from DOUT0 to
ground.
Experiment with the timing of the DATA+0 and DRV_EN+0
while watching the output. Essentially there is ~10ns of
propagation delay on the DATA+0 signal, while DRV_EN+0
(HIZ control) takes ~20ns to change the DOUT output. You
will also notice that measuring the time to HIZ is a little
difficult in that the DOUT floats when in HIZ so the output is
slow to reveal that the DOUT drivers are no longer driving
the DOUT signal.
ADVANCED HIZ
With the HIZ control you can tie two drivers together. This is
often done in memory applications where dual banks are
used. Effectively the data is being driven from one driver
while the other driver's data is being updated. This enables
two drivers/banks of drivers to ping-pong back and forth via
the HIZ control. Receivers can also be ganged so the data
on one set of receivers is latched and being evaluated while
8
AN1217.1
September 12, 2008
Application Note 1217
the other receivers are following the inputs waiting for a
secondary latching.
ISL55100 UNIQUE FEATURES
The down side of pin muxing is the added capacitance of
connecting two drivers together. Added capacitance slows
rise and fall times and reduces throughput/bandwidth of the
test bus.
The Lowswing signal improves driver waveforms at low
voltages. /Lowswing is available when VH (Driver High Rail)
is <5.75V above VEE. You can watch the part automatically
change modes as you move the VH voltage above and
below 5.75V above VEE. Therefore, connecting /Lowswing to
VEE only enables /Lowswing if VH is kept < 5.75V above
VEE.
Essentially you will see the pulse generator signal propagate
through to the QA, QB outputs. By changing the amplitude of
the pulse generator and the DC Levels on CVA and CVB you
can measure the propagation delay through the
comparators.
An interesting note is that you can measure rise/fall time with
window comparators. Start by setting the pulse generator for
0V to 5V amplitude. You then set the CVB voltage at 0.5V
and the CVA voltage at 4.5V. These represent the 10% and
90% amplitude of the 5V pulse.
ISL55100 LOWSWING DRIVER MODE
VCC 12.0 VH 2.0
VEE - 3.0 VL 0.0
0.5V/DIV
To observe the receivers at speed, connect a pulse
generator directly to the VINP BNCs. Remember there is a
50Ω resistor to ground. R29, R32, R33, and R34 are located
on the top of the board between the VINP BNC’s and the
ISL55100.
/LOWSWING OFF
0
0.5V/DIV
DYNAMIC RECEIVER OBSERVATIONS
/Lowswing Driver Mode
/LOWSWING ON
0
10ns/DIV
With QB firing at the 0.5 voltage level and QA firing at the 4.5
voltage level, the difference in the two edges of QA/QB is
equal to the 10% to 90% rise/fall time of the pulse.
VDIGC RECEIVER TEST BUS
By using the VDIGC bus you can connect a single source to
all four inputs. The VDIGC bus helps with measurements
regarding timing and threshold levels. The differences from
receiver to receiver can be compared in the configuration.
The jumpers that couple the 4 VINP(0 to 3)s to the VDIGC
bus are J21, J11, J22 and J23. You can then run a DC level
or pulse into the VDIGC banana jack for comparison
measurements. When using the VDIGC bus, remember
each receiver has a 50Ω load to ground.
Driver to Receiver Loop Back Testing
On most pin electronics designs, there is a user defined
series resistor (10Ω to 50Ω) installed between the driver
output and the receiver input. This series resistor would be
placed between a DOUT BNC and a VINP BNC.You may
wish to use various length BNC to BNC cables to provide the
loop-back.
Once you’ve connected a driver to a receiver, you can
change the amplitude of the receiver Inputs by changing the
VH/VL voltages of the drivers. Remember the 50Ω resistors
on the receiver (VINP pins) inputs. You may wish to remove
them if you want to run the drivers at higher voltages or with
higher load impedance.
FIGURE 13. LOWSWING CAN BE USEFUL IN SOME
APPLICATIONS
/VEXT (V5V Banana Jack) Power Mode
The pin is normally tied to VEE by way of JP29. In this mode,
the ISL55100 manufacturers its own internal 5V supply.
However, as speed requirements increase, heat dissipation
becomes a problem. Utilizing the VEXT option helps reduce
heat dissipation of the ISL55100.
To use the VEXT option, remove JP29 and connect a 5.5V
power supply from VEE to V5V banana jack on the
evaluation board.
Caution: Do not reference the VEXT power supply to
ground. The negative terminal of the external 5.5V supply
needs to be connected to VEE so the voltage on VEXT is
5.5V above VEE.
VEXT will require ~25mA quiescent current per ISL55100.
However, this requirement will approach 100mA for each
device during high frequency operation.
Note: When not using VEXT, the minimum voltage from VCC
to VEE is 12V. However this drops to 9V when using the
VEXT option. Operating at 9.0V reduces power consumption
and heat dissipation requirements. But, this also limits the
VH drive high rail to the lower VCC potential.
Device Power Observations: VEXT Mode
With a pulse generator connected to DATA+X and the
drivers enabled, you will see an increase in power
9
AN1217.1
September 12, 2008
Application Note 1217
consumption on the VEXT supply along with VCC and VEE.
The increase in power will coincide with an increase in
frequency. Still, there is an overall heat dissipation savings
when using VEXT.
ISL55100A/BEVAL3/3Z Miscellaneous
Notes
A complete schematic of the ISL55100A/BEVAL3/3Z
Evaluation board is included on the final page of this
document.
On the ISL55100A/BEVAL3/3Z Evaluation Board, four
voltage busses have been tied across all channels for ease
of use.
VH(0 to 3), VL(0 to 3), CVA(0 to 3), CVB(0 to 3) signals are
all common within themselves. A review of Figure 1 reveals
that each channel has separate pin connections for the VH,
VL, CVA, CVB functions.
Summary
A typical application for the ISL55100A/BEVAL3/3Z is testing
bi-directional bussed based digital devices.
Driver waveforms under user specified loads is one of the
first evaluations to be made.
Propagation Delay through the Drivers and Receivers and
Time to HIZ are critical timing requirements.
Channel-to-channel matching of propagation time is also
important.
Power consumption measurements and waveform integrity
as Frequency of Operation increases are key in most
applications.
The ISL55100A/BEVAL3/3Z Evaluation Board enables the
user to view these and other attributes before designing your
first ISL55100A/BEVAL3/3Z Pin Electronics Card.
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
AN1217.1
September 12, 2008
TP2
COMP LOW
QB0
QA0
R27
49.9
R26
49.9
R21
49.9
R17
49.9
D1
QB0
R11
DNP
QA0
P1
R26
49.9
JP10
R28
49.9
VEE
F2
VCC
F1
DRV_EN-3
QB1
QA1
P4
P3
C13
0.1µF
C12
0.1µF
FUSE 250mA
QA1
R30
49.9
0
R23
49.9
R19
49.9
R36
49.9
R10
DNP
QB1
R09
DNP
DRV_EN+3
DRV_EN-2
DRV_EN+2
DRV_EN-1
DRV_EN+1
DRV_EN-0
FUSE 250mA
JP08
DATA+3
DATA-3
VDIGD
JP06
JP01
DATA+2
DATA-2
VDIGD
JP09
R12
DNP
R22
49.9
DATA+1
DATA-1
VDIGD
JP02
P2
D2
R18
49.9
JP14
DATA-0
DRV_EN+0
R35
49.9
R20
49.9
R24
49.9
R31
49.9
QB2
QA2
COMP-
COMP+
VDIGD
JP26
JP03
JP07
P6
P5
D10
D9
C62
0.1µF
C39
0.1µF
C63
0.1µF
C40
0.1µF
R06
DNP
QB2
R05
DNP
QA2
QB3
QA3
P8
P7
C32
.1µF
QB3
R08
DNP
1 Data+0
2 Data-0
72 /Drv En+0
71 /Drv En-0
7 Data+1
8 Data-1
5 /Drv En+1
6 /Drv En-1
13 Data+2
14 Data-2
11 /Drv En+2
12 /Drv En-2
19 Data+3
20 Data-3
17 /Drv En+3
18 /Drv En-3
VEE
D7
C65
0.1µF
D6
VCC
QA3
QB3
QA2
QB2
QA1
QB1
QA0
QB0
D15
D13
MAX0
VDIGC
MIN1
VDIGC
VINP3
DOUT3
C5
.1µF
D1
36
40
32
44
29
48
JP23
R29
49.9
VDIGC
VEE
JP29
VCC
R34
49.9
J15
J12
ISL55100A/BEVAL3Z
C21
0.1µF
V5V
Comparator Outputs
Bits 0-3
VCC 27, 59, 61, 67
VEE 26, 60, 62, 68
VINP2
DOUT2
VINP1
DOUT1
Min1
Max0
52
Rcvr Thresholds DOUT0
22
VINP0
ISL55100 Pin Driver
U1
D14
CVB
CVA
D12
VCC
VEE
QAX [ > Min1 = COMP_HIGH] | [ < Min1 = COMP_LOW]
QBX [ > Max0 = COMP_HIGH] | [ < Max0 = COMP_LOW]
Comparator Operation
VL
VH
Low High
Driver Rails
37 /LowSwing
COMP+ 24
Out High Rail
COMP- 25 Comp
Comp Out Low Rail
DR_EN+3
DR_EN-3
Data+3
Data-3
D3
C64
0.1µF
C42
0.1µF
R07 DNP = Not Populated
DNP
QA3
To Enable "LowSwing" Mode
Jumper /LowSwing to VEE if
VH-VEE <= 5.0 Volts
J30
VCC
Pos1
/LowSwing
Pos2
VEE
Pos3
C24
.1µF
DR_EN+2
DR_EN-2
Data+2
Data-2
DR_EN+1
DR_EN-1
Data+1
Data-1
DR_EN+0
DR_EN-0
Data+0
Data-0
Note1: DL Supply needs sink current even if
positive voltage. If Driver Low does not look
correct, make sure your DL supply connection
method enables it to sink rather than source.
Power Up Sequence : Example Voltages
VEE ... -3.0
VCC ...+12.0
VDIGD.. +0.5 Bias for Diff to Single Ended
Comp+-.. +3.0 Rcvr Comparators Output Level
VH ... +2.8
Drive High Voltage
VL ... +0.0
Drive Low Voltage: Note 1
CVA ... +2.4
Rcvr Min Logic 1 (VIH)
CVB ... +0.6
Rcvr Max Logic 0 (VIL)
C33,34,35,36 = Not Populated
DATA and DRVEN Input
Jumpers set for Single Ended
D11
VDIGD VDIGC
D8
D4
FIGURE 14. ISL55100A/BEVAL3/3Z EVALUATION BOARD SCHEMATIC
JP25
DR_EN+3
DR_EN-3
VDIGD
JP05
JP28
DR_EN+2
DR_EN-2
VDIGD
JP04
C33
0.1µF
DR_EN+1
DR_EN-1
VDIGD
JP27
DR_EN-0
C55
0.1µF
C61
0.1µF
TP2
C54
0.1µF
DR_EN+0
C34
0.1µF
C35
0.1µF
C8
0.1µF
C1
0.1µF
DATA+0
C60
0.1µF
C59
0.1µF
C58
0.1µF
C53
0.1µF
C57
0.1µF
VDIGD
JP13
C2
10µF
C56
0.1µF
QA/QB Comparator
Input Supply
COMP HIGH
DATA-3
DATA+3
DATA-2
DATA+2
DATA-1
DATA+1
DATA-0
DATA+0
VEE
TP1
GND
C52
0.1uF
50
46
42
38
VL0
VL1
VL2
VL3
70 QA0
69 QB0
C9
0.1µF
53
49
45
41
VH0
VH1
VH2
VH3
QA1
QB1
3
4
C3
0.1µF
23
30
33
35
CVB0
CVB1
CVB2
CVB3
9 QA2
10 QB2
15 QA3
16 QB3
+ C4
10µF
21
28
31
34
CVA0
CVA1
CVA2
CVA3
11
54 V5V
VEE 26
VEE
27 VCC
+
VCC
DLoad
R33
49.9
DLoad
VDIGC
JP21
DLoad
DLoad
R13
J11
DNP
R14
DNP
C34
DNP
C33
DNP
R16
C48 DNP
DNP
VDIGC
BNC
VINP3
DOUT3
VINP2
BNC
BNC
DOUT2
VINP1
DOUT1
VINP0
DOUT0
BNC
BNC
BNC
BNC
BNC
DOUT_LOAD
C36
DNP
C35
DNP
C43 DNP
DNP
R15
VDIGC
JP22
R32
49.9
C46
DNP
C45
DNP
DLoad
Application Note 1217
AN1217.1
September 12, 2008
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