DATASHEET

DATASHEET
Quad 18V Pin Electronics Driver/Window Comparator
ISL55100B
Features
The ISL55100B is a Quad pin driver and window comparator
fabricated in a wide voltage CMOS process. It is designed
specifically for Test During Burn-In (TDBI) applications, where
cost, functional density and power are all at a premium.
• Low driver output resistance
- ROUT typical: 9.0Ω
• 18V I/O range
• 50MHz operation
This IC incorporates four channels of programmable drivers
and window comparators into a small 72 Ld QFN package.
Each channel has independent driver levels, data and high
impedance control. Each receiver has dual comparators, which
provide high and low threshold levels.
• 4 Channel driver/receiver pairs with per pin flexibility
• Dual level - per pin - input thresholds
• Differential or single-ended digital inputs
• User defined comparator output levels
The ISL55100B uses differential mode digital inputs and can
therefore mate directly with LVDS or CML outputs.
Single-ended logic families are handled by connecting one of
the digital input pins to an appropriate threshold voltage (e.g.,
1.4V for TTL compatibility). The comparator outputs are
single-ended and the output levels are user defined to mate
directly with any digital technology.
• Low channel-to-channel timing skew
• Small footprint (72 Ld QFN)
• Pb-free (RoHS compliant)
Applications
• Burn in ATE
The 18V driver output and receiver input ranges allow this
device to interface directly with TTL, ECL, CMOS (3V, 5V and
7V), LVCMOS and custom level circuitry, as well as the high
voltage (super voltage) level required for many special test
modes for Flash Devices.
• Wafer level flash memory test
• LCD panel test
• Low cost ATE
• Instrumentation
• Emulation
• Device programmers
Functional Block Diagram
QUAD - WIDE RANGE, LOW ROUT, TRI-STATEABLE - DRIVERS
VH(0-3)
DATA+(0-3)
DATA-(0-3)
DOUT(0-3)
+
-
VL(0-3)
DRVEN+(0-3)
DRVEN-(0-3)
+
-
QUAD - DUAL LEVEL COMPARATOR - RECEIVERS
COMP HIGH
VCC
QA(0-3)
COMP LOW
COMP HIGH
CVA(0-3)
VEE
VCC
VINP(0-3)
QB(0-3)
COMP LOW
December 4, 2014
FN6229.2
1
CVB(0-3)
VEE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2006, 2008, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL55100B
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL55100BIRZ
TEMP. RANGE
(°C)
ISL55100 BIRZ
PACKAGE
(RoHS Compliant)
-40 to +85
72 Ld QFN
PKG.
DWG. #
L72.10x10
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL55100B For more information on MSL, please see tech brief TB363.
Pin Configuration
QA 0
QB 0
VEE
VCC
NC
NC
NC
NC
VEE
VCC
VEE
VCC
NC
NC
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
NC
DRV EN- 0
72
NC
DRV EN+ 0
ISL55100B
(72 LD QFN)
TOP VIEW
55
DATA+ 0
1
54 VEXT
DATA- 0
2
53 VH 0
QA 1
3
52 DOUT 0
QB 1
4
51 NC
DRV EN+ 1
5
50 VL 0
DRV EN- 1
6
49 VH 1
DATA+ 1
7
48 DOUT 1
DATA- 1
8
47 NC
QA 2
9
QB 2
10
45 VH 2
DRV EN+ 2
11
44 DOUT 2
DRV EN- 2
12
43 NC
DATA+ 2
13
42 VL 2
DATA- 2
14
41 VH 3
QA 3
15
40 DOUT 3
QB 3
16
39 NC
DRV EN+ 3
17
38 VL 3
DRV EN- 3
18
37 LOWSWING
26
27
28
29
30
CVA 0
VINP 0
CVB 0
COMP HIGH
COMP LOW
VEE
VCC
CVA 1
VINP 1
CVB 1
2
31
32
33
34
35
36
VINP 3
25
CVB 3
24
CVA 3
23
CVB 2
22
VINP 2
21
CVA 2
20
DATA- 3
DATA+ 3
19
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FN6229.2
December 4, 2014
ISL55100B
Pin Descriptions
PIN NAME
FUNCTION
DATA+(0:3)
Positive differential digital input that determines the driver output state when it is enabled.
DATA-(0:3)
Negative differential digital input that determines the driver output state when it is enabled.
DRV EN+(0:3)
Positive differential digital input that enables or disables the corresponding driver.
DRV EN-(0:3)
Negative differential digital input that enables or disables the corresponding driver.
QA (0:3)
Comparator digital outputs. QA(X) is high when VINP(X) exceeds CVA(X).
QB (0:3)
Comparator digital outputs. QB(X) is high when VINP(X) exceeds CVB(X).
DOUT (0:3)
Driver outputs.
VINP (0:3)
Comparator inputs.
VH (0:3)
Unbuffered analog inputs that set each individual driver’s “high” voltage level.
VL (0:3)
Unbuffered analog inputs that set each individual driver’s “low” voltage level. VL must be a lower voltage than VH.
NC
No internal connection.
CVA (0:3)
Analog inputs that set the threshold for the corresponding Channel A comparators.
CVB (0:3)
Analog inputs that set the threshold for the corresponding Channel B comparators.
COMP HI
Supply voltage, unbuffered input that sets the high output level of all comparators. Must be greater than COMP LO.
COMP LO
Supply voltage, unbuffered input that sets the low output level of all comparators. Must be less than COMP HI.
VCC
Positive power supply (5% tolerance).
VEE
Negative power supply (5% tolerance). This is also the potential of the exposed thermal pad on the package bottom.
VEXT
External 5.5VDC power supply (5.5VDC to 6.0VDC as referenced to VEE, NOT GND. Recommended VEXT = 5.5V) for internal logic.
Connect pin to VEE when not using an external supply.
LOWSWING
EP
Input that selects driver output configurations optimized to yield minimum overshoots for low level swings (VH < VEE +5V), or
optimized for large output swings. Connect LOWSWING to VEE to select low swing circuitry, or connect it to VCC to select high swing
circuitry.
QFN package exposed thermal pad; connect to VEE.
Truth Tables
RECEIVERS
INPUT
DRIVERS
INPUTS
OUTPUTS
VINP
OUTPUT
QA
QB
DATA
DRV EN
DOUT
<CVA
<CVB
0
0
X
+>-
Hi - Z
<CVA
>CVB
0
1
<CVB
1
0
>CVB
1
1
+>-
+<-
VH
>CVA
+<-
+<-
VL
>CVA
X = DON’T CARE
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FN6229.2
December 4, 2014
ISL55100B
Absolute Maximum Ratings
Thermal Information
VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 19V
VEXT to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Input Voltages
DATA, DRV EN, CVX, VH, VL, VINP, COMPX, LOWSWING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VEE - 0.5V) to (VCC + 0.5V)
Output Voltages
DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VEE - 0.5V) to (VCC + 0.5V)
QX . . . . . . . . . . . . . . . . . . . . . (COMP LOW - 0.5V) to (COMP HIGH + 0.5V)
Thermal Resistance (Typical, Notes 4, 5)
JA (°C/W) JC (°C/W)
72 Ld QFN Package . . . . . . . . . . . . . . . . . . .
23
2.0
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on high effective thermal conductivity test board with “direct attach” features. See Tech Brief
TB379 and Tech Brief TB389 for details. Device temperature is closely tied to data-rates, driver loads and overall pin activity. Review “Power
Dissipation Considerations” on page 9 for more information.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Recommended Operating Conditions
SYMBOL
MIN
(Note 12)
TYP
MAX
(Note 12)
UNITS
Device Power-(VEXT = VEE) VEXT not used
VCC - VEE
12 (Note 9)
15
18
V
Device Power-(VEXT = VEE + 5.5V)
VCC - VEE
9 (Note 9)
15
18
V
VEXT Optional External Logic Power
VEXT - VEE
5.5 (Note 9)
5.75
6.0
V
Driver Output High Rail
VH
VEE + 1
-
VCC - 0.5
V
Driver Output Low Rail
VL
VEE + 0.5
-
VEE + 6
V
Comparator Output High Rail
COMP-High
VEE + 1
-
VCC - 0.5
V
Comparator Output Low Rail
COMP-Low
VEE + 0.5
-
VEE + 6
V
Ambient Temperature
TA
-40
-
+85
°C
Junction Temperature
TJ
-
-
+150
°C
PARAMETER
Electrical Specifications Test Conditions: VCC = 12V, VEE = -3V, VH = 6V, VL = 0V, Comp-High = 5V, Comp Low = 0V, VEXT = VEE and
LOWSWING = VCC, +25°C; Unless Otherwise specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
6
9
14
Ω
DRIVER DC CHARACTERISTICS
ISL55100B Output Resistance
ROUTD
IO = ±125mA, data not toggling
ISL55100B DC Output Current
IOUTD
Per individual driver
±125
-
-
mA
IOUTDAC
Per individual driver
-
600
-
mA
VOMIN
VH = 200mV, VL = 0V
ISL55100B AC Output Current (Note 13)
ISL55100B Minimum Output Swing
Disabled HIZ Leakage Current
HIZ
185
-
-
mV
VOUT = VCC with VH = VL + VEE or VOUT = VEE
with VH = VL = VCC
-1
0
1
µA
Lowswing Disabled (Note 8)
5
12
16
ns
Lowswing Enabled (Note 8)
6
13
17
ns
-
<1
-
ns
DRIVER TIMING CHARACTERISTICS
Data to DOUT Propagation Delay
tPD
Driver Timing Skew, All Edges (Note 6)
Disable (HIZ) Time
Enable Time
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tDIS
DVREN± transition from enable to disable
15
18
26
ns
tEN
DVREN± transition from disable to enable:
Lowswing disabled (Note 8)
13
15
23
ns
DVREN± transition from disable to enable:
Lowswing enabled (Note 8)
13
18
23
ns
FN6229.2
December 4, 2014
ISL55100B
Electrical Specifications Test Conditions: VCC = 12V, VEE = -3V, VH = 6V, VL = 0V, Comp-High = 5V, Comp Low = 0V, VEXT = VEE and
LOWSWING = VCC, +25°C; Unless Otherwise specified. (Continued)
PARAMETER
SYMBOL
ISL55100B Rise/Fall Times (Note 6)
ISL55100B Rise/Fall Times (Note 6)
ISL55100B Maximum Toggle Frequency
tR, tF
tR, tF
100pF Load
1000pF Load
MIN
TYP
MAX
UNITS
DV = 0.4V (20% to 80%)
-
2.5
-
ns
DV = 1V (20% to 80%)
-
2.5
-
ns
DV = 5V (10% to 90%)
-
3.0
-
ns
DV = 10V (10% to 90%)
-
3.5
-
ns
DV = 14V (10% to 90%)
-
3.5
-
ns
DV = 1V (20% to 80%)
-
9
-
ns
DV = 5V (10% to 90%)
-
11
-
ns
DV = 10V (10% to 90%)
-
14
-
ns
50
65
-
MHz
Standard load, 1k/100pF (Note 7)
-
7.7
-
ns
OS
Lowswing enabled, (VH-VL<2V)
-
20mV+
10% of
output
swing
-
%+V
Input Offset Voltage
VOS
CVA = CVB = 1.5V
-200
-
200
mV
Input Bias Current
IBIAS
VINP - CV(A/B) = ±5V
-
10
30
nA
Output Resistance
ROUTR
18
25
35

tPP
7
12
18
ns
50
65
-
MHz
ISL55100B Min Driver Pulse Width
ISL55100B Overshoot Lowswing Mode
(Note 6)
FMAXD
TEST CONDITIONS
tWIDD
No load, 50% symmetry
RECEIVER DC CHARACTERISTICS
RECEIVER TIMING CHARACTERISTICS
Propagation Delay
Maximum Operating Frequency
FMAXR
Min Pulse Width
tWIDR
Under no load, PWOUT symmetry 50%
Rcvr Channel-to-channel Skew (Note 6)
-
7.7
-
ns
-
<1
-
ns
200
-
-
mV
-
-
-200
mV
-50
0
50
nA
VCC - 5V
V
-
V
DIGITAL INPUTS
Differential Input High Voltage
VDIFFH
VDIG+ - VDIG-
Differential Input Low Voltage
VDIFFL
VDIG+ - VDIG-
Input Current
IIN
Common Mode Input Voltage Range
VCM
VIN = VCC or VEE
VDIFFL not greater than VDIFFH - 0.2V
VDIFFH not less than VDIFFL + 0.2V
VEE + 0.2V
-
POWER SUPPLIES, DRIVER/RECEIVER STATIC CONDITIONS VEXT = VEE, EXTERNAL LOGIC POWER OPTION NOT USED. (Note 10)
Positive Supply Current
ICC
VCC = VH = 12V, VEE = VL = -3V, VEXT = VEE,
outputs unloaded
-
65
85
mA
Negative Supply Current
IEE
VCC = VH = 12V, VEE = VL = -3V, VEXT = VEE,
outputs unloaded
-85
-65
-
mA
VEXT Supply Current
IEXT
VCC = VH = 12, VEE = VL = -3V, VEXT = VEE,
outputs unloaded
-
<1
-
mA
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FN6229.2
December 4, 2014
ISL55100B
Electrical Specifications Test Conditions: VCC = 12V, VEE = -3V, VH = 6V, VL = 0V, Comp-High = 5V, Comp Low = 0V, VEXT = VEE and
LOWSWING = VCC, +25°C; Unless Otherwise specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES, DRIVER/RECEIVER STATIC CONDITIONS VEXT = VEE + 5.5V, EXTERNAL LOGIC POWER OPTION USED. (Note 11)
Positive Supply Current
ICC
VCC = VH = 12V, VEE = VL = -3V, VEXT = VEE
+ 5.5V, outputs unloaded
-
35
50
mA
Negative Supply Current
IEE
VCC = VH = 12V, VEE = VL = -3V, VEXT = VEE
+ 5.5V, outputs unloaded
-50
-35
-
mA
VEXT Supply Current
IEXT
VCC = VH = 12, VEE = VL = -3V, VEXT = VEE +
5.5V, outputs unloaded
-
25
40
mA
NOTES:
6. Lab characterization, room temp, Timing Parameters Matched Stimulus/Loads, Channel-to-Channel Skew < 500ps, 1ns Max by design.
7. Measured across 100pF/1k lump sum load + 15pF PCB/Scope Probe. Cap and Resistor Surface Mount/Stacked ~0.5” from Pin.
8. To Enable LOWSWING, connect LOWSWING to VEE and keep VH < VEE + 5. To disable LOWSWING, connect it to VCC.
9. When VEXT is connected to VEE (External Device Power not used) then the Minimum VCC - VEE is 12V. When VEXT is connected to an external 5.5V
supply, then the minimum VCC - VEE voltage is 9V. Recommended VEXT = 5.5V as referenced to VEE.
10. ICC and IEE values are based on static conditions and will increase with pattern rates. ICC and IEE reach 400mA to 500mA at maximum data rates
(provided sufficient device cooling is employed). These currents can be reduced by 1) Reducing the VCC - VEE operating voltage 2) Utilizing the VEXT
option.
11. When using VEXT = 5.5V, current requirements of the VEXT input can approach 100mA at maximum pattern rates.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.When using VEXT = 5.5V, current requirements of the VEXT input can approach 100mA at maximum pattern rates.
13. Device temperature is closely tied to data-rates, driver loads and overall pin activity. Review “Power Dissipation Considerations” on page 9 for more
information.
Test Circuits and Waveforms
VH
VL
(Note 7)
DATA+
DATADRV EN+
DOUT
DRV EN-
VO
100pF
1kΩ
FIGURE 1. DRIVER SWITCHING TEST CIRCUIT
DATA = 1
DATA-
DATA = 0
400mV
DATA+
0V
tPDLH
tPDHL
VOH (VH)
50%
VO
50%
VOL (VL)
tR
tF
FIGURE 2. DRIVER PROPAGATION DELAY AND TRANSITION TIME MEASUREMENT POINTS
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FN6229.2
December 4, 2014
ISL55100B
Test Circuits and Waveforms (Continued)
DIS
DRV EN-
EN
400mV
DRV EN+
0V
tDISL
VO
(FOR DATA = 0)
tENH
VREF
1V
10%
tDISH
VOL (VL)
tENL
90%
VO
(FOR DATA = 1)
2V
VOH (VH)
VREF
FIGURE 3. DRIVER ENABLE AND DISABLE TIME MEASUREMENT POINTS
COMP HI
CVA
+
QA
5V
VINP
CVB
+
-
QB
COMP LO
FIGURE 4. RECEIVER SWITCHING TEST CIRCUIT
500mV
VINP
0V
0V
-500mV
tPDLH
tPDHL
VOH (5V)
QX
50%
50%
VOL (0V)
FIGURE 5. RECEIVER PROPAGATION DELAY MEASUREMENT POINTS
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FN6229.2
December 4, 2014
ISL55100B
Application Information
The ISL55100B provides Quad pin drivers and Quad dual level
comparator receivers in a small footprint. The four channels
may be used as bidirectional or split channels. Drivers have per
channel level, data and high impedance controls, while
comparators have per channel high and low threshold levels.
Receiver Features
The receivers are four independent window comparators that
feature high output current capability and user defined high and
low output levels to interface with a wide variety of logic
families. Each receiver comprises two comparators and each
comparator has an independent threshold level input, making it
easy to implement window comparator functions. The CVA and
CVB pins set the threshold levels of the A and B comparators
respectively. COMP HIGH and COMP LOW set all the comparator
output levels and COMP HIGH must be more positive than COMP
LOW. These two inputs are unbuffered supply pins, so the
sources driving these pins must provide adequate current for the
expected load. COMP HIGH and COMP LOW typically connect to
the power supplies of the logic device driven by the comparator
outputs. The ‘truth table” for the receivers is given on page 3.
Receiver outputs cannot be placed in a HIZ state and do not
incorporate any on-chip short circuit current protection.
Momentary short circuits to GND or any supply voltage, won’t
cause permanent damage, but care must be taken to avoid
longer duration short circuits. If tolerable to the application,
current limiting resistors can be inserted in series with the QA(0-3)
and QB(0-3) outputs to protect the receiver outputs from damage
due to overcurrent conditions.
Driver Features
The drivers are single-ended outputs featuring a wide voltage
range, an output stage capable of delivering 125mA while
providing a low out resistance and HIZ capability. The driver
output can be toggled to drive one of two user defined output
levels High (VH) or Low (VL).
Driver waveforms are greatly affected by load characteristics. The
ISL55100B actually double bonds the VH(0-3) and VL(0-3) supply
pins for each channel. The Driver Output Pins (DOUT(0-3)) are
triple bonded. Multiple bond wires help reduce the effects of
Inductance between the IC Die (Wafer) and the packaging. Also
the QFN style of packaging reduces inductance over other types
of packaging.
While the inductance of a bond wire might seem insignificant, it
can reduce high-frequency waveform fidelity. So this should be
borne in mind when doing PCB layout and DUT interconnect. Lead
lengths should be kept as short as possible, maintaining as much
decoupling on the drive rails as possible and make sure scope
measurements are made properly. Often the inductance of a
scope probe ground can be the actual cause of the waveform
distortion.
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VH and VL (Driver Output Rails)
Sets of VH and VL pins are designated for each Driver. These
are unbuffered analog inputs that determine the Drive High
(VH) and Drive Low (VL) Voltages that the drivers will deliver.
These inputs are double bonded to reduce inductance and
decrease AC Impedance.
Each VH and VL should be decoupled with 4.7µF and 0.1µF
capacitors to ground. If all four Driver VH/VLs are bussed, then
one 4.7µF can be used. Layouts should also accommodate the
placement of capacitance “across” VH and VL. So in addition to
decoupling the VH/VL pins to ground, they are also decoupled
to each other.
Logic Inputs
The ISL55100B uses differential mode digital inputs and can
therefore mate directly with LVDS or CML outputs. Single- ended
logic families are handled by connecting one of the digital input
pins to an appropriate threshold voltage (e.g., 1.4V for TTL
compatibility).
LOWSWING Circuit Option
The drivers include switchable circuitry that is optimized for
either low (VH-VL < 3V) or high output swings. Configuring the
part is accomplished via the LOWSWING pin. Connecting
LOWSWING to VEE selects the circuits optimized for low
overshoots at low swing operation. Connecting the pin to VCC
enables the large signal circuitry (see Figure 7).
With LOWSWING = VEE, the low swing circuitry activates
whenever VH < VEE + 5V. Set LOWSWING = VEE only if the
output swing (VH-VL) is less than 3V and better than 10%
overshoots are required.
For the best small (low swing) signal performance, the VH/VL
common mode voltage [(VH + VL)/2] must be VEE + 1.5V. So if
VEE = 0V and the desired swing is 500mV, set VH = 1.75V and
VL = 1.25V.
Driver and Receiver Overload Protection
The ISL55100B is designed to provide minimum and balanced
Driver ROUT. Great care should be taken when making use of
the ISL55100B low ROUT drivers as there is no internal
protection. There is no short circuit protection built into either
the driver or the receiver/comparator outputs. Also there are
no junction temperature monitors or thermal shutdown
features.
The driver or receiver outputs may be damaged by more than a
momentary short circuit directly to any low impedance voltage.
Driver protection can be obtained with a 50Ω series
termination resistor that is properly rated.
External Logic Supply Option (VEXT)
Connection of the VEXT Pin to a 5.5V DC Source (referenced to
VEE) will reduce the VCC-VEE current drain. Current drain is
directly proportional to Data Rate. This option will help with
Power Supply/Dissipation should heat distribution become an
issue.
FN6229.2
December 4, 2014
ISL55100B
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit board
layout is necessary for optimum performance. Ground plane
construction is highly recommended, lead lengths should be
as short as possible and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal single
supply operation, where the VEE pin is connected to ground,
one 0.1µF ceramic capacitor should be placed from the VCC
pin to ground. A 4.7µF tantalum capacitor should then be
connected from the VCC pin to ground. This same capacitor
combination should be placed at each supply pin to ground if
split supplies are to be used.
Power Dissipation Considerations
Specifying continuous data rates, driver loads and driver level
amplitudes are key in determining power supply requirements
as well as dissipation/cooling necessities. Driver Output
patterns also impact these needs. The faster the pin activity,
the greater the need to supply current and remove heat.
Figures 17 and 18 address power consumption relative to
frequency of operation. These graphs are based on driving
6.0/0.0V out into a 1kΩ load. Theta JA for the device package
is 23.0, 16.6 and 14.9°C/W based on Airflows of 0, 1 and
2.5 meters per second. The device is mounted per Note 4
under “Thermal Information” on page 4. With the high speed
data rate capability of the ISL55100B, it is possible to exceed
the +150°C “absolute maximum junction temperature” as
operating conditions and frequencies increase. Therefore, it is
important to calculate the maximum junction temperature for
the application to determine if operating conditions need to be
modified for the device to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T JMAX - T AMAX
P DMAX = -------------------------------------------- JA
(EQ. 1)
junction temperature over the ambient temperature of the
user’s system. Plots indicate temperature change as operating
frequency increases (the graph assumes continuous
operation). The user should evaluate various heat sink/cooling
options in order to control the ambient temperature part of the
equation. This is especially true if the users applications
require continuous, high speed operation.
The reader is cautioned against assuming the same level of
thermal performance in actual applications. A careful
inspection of conditions in your application should be
conducted. Great care must be taken to ensure Die
Temperature does not exceed the +150°C Absolute Maximum
Thermal Limits.
Important Note: The ISL55100B package metal pad (EP) is
used for heat sinking of the device. It is electrically connected
to the negative supply potential (VEE). If VEE is tied to ground,
the thermal pad can be connected to ground. Otherwise, the
thermal pad (VEE) must be isolated from other power planes.
Power Supply Sequencing
The ISL55100B references every supply with respect to VEE.
Therefore apply VEE, then VCC followed by the VH, VL busses,
then the COMP High and Comp Low followed by the CVA and
CVB Supplies. Digital Inputs should be set with a differential
bias as soon as possible. In cases where VEXT is being utilized
(VEXT = VEE + 5.5V), it should be powered up immediately after
VCC. Basically, no pin should be biased above VCC or below VEE.
Data Rates
Please note that the Frequency (MHz) in Figures 17 and 18
contain two transitions within each period. A digital application
that requires a new test pattern every 50ns would be running
at a 20MHz Data Rate. Figure 19 reveals 100ns period, in
10MHz frequency parlance, results in two 50ns digital
patterns.
ESD Protection
Figure 6 is the block diagram depicting the ESD protection
networks.
where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
• PDMAX = Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC is the
total quiescent supply current times the total power supply
voltage, plus the power in the IC due to the loads. Power also
depends on number of channels changing state, frequency of
operation. The extent of continuous active pattern
generation/reception will greatly effect dissipation requirements.
The power dissipation curves (Figure 17), provide a way to see
if the device will overheat. The junction temperature rise above
ambient vs operating frequency can be found graphically in
Figure 18. This graph is based on the package type Theta JA
ratings and actual current/wattage requirements of the
ISL55100B when driving a 1k load with a 6V High Level and a
0V Low Rail. The temperatures are indicated as calculated
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9
FN6229.2
December 4, 2014
ISL55100B
VCC
Vcc
Vcc
VH
Vcc Vee
Data+
Vcc
DOUT
Data-
Vee Vcc Vee
VL
Vee
Vcc
Vee
DRVEN+
VEXT
DRVENVee
COMP HIGH
5.5V to 6.0V
ISL55100B
VEE
Vcc
VCC
QA
CVA
COMP LOW
COMP HIGH
VEE
Vee
VINP
Vcc
VCC
QB
COMP LOW
CMV >VEE+0.3 to
<VCC – 5.0V
CVB
VEE
Vee
VEE
FIGURE 6. ESD STRUCTURE BLOCK DIAGRAM
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FN6229.2
December 4, 2014
ISL55100B
Typical Performance Curves
Device installed on Intersil ISL55100B Evaluation Board.
VCC 12.0 DH 6.0
VEE 3.0 DL 0.0
0.5V/DIV
VCC 12.0 DH 6.0
VEE 3.0 DL 0.0
0
0.5V/DIV
1k100pF
2V/DIV
LOWSWING OFF
0
DATA IN
680pF
LOWSWING ON
2200pF
0
1000pF
0
10ns/DIV
10ns/DIV
FIGURE 8. DRIVER WAVEFORMS UNDER VARIOUS LOADS
FIGURE 7. LOWSWING EFFECTS ON DRIVER SHAPE AND TPD
(100pF TO 1k LOAD)
VH (6V) ROUT: DRIVER SOURCES 125mA
DRVEN
0
DATA IN
0
2V/DIV
10
ROUT AT 125mA DC
2V/DIV
TRISTATE/DATA/DOUT TIMING
5
VL (0.0V) ROUT: DRIVER SINKS 125mA
DRIVER OUT
0
0
12
13
8.0
17
18
5.6
4.8
VL (0.0V FIXED) ROUT: DRIVER SINKS 125mA
3.2
2.4
1.6
0.8
18
PROPAGATION DELAY
ROUT AT 125mA DC
6.4
0.0
16
20
VH (1V TO 15V) ROUT: DRIVER SOURCES 125mA
4.0
15
FIGURE 10. ROUT vs DEVICE VOLTAGE
FIGURE 9. DATA/HIZ/DRIVER OUT TIMING
7.2
14
VCC-VEE VOLTS (VEE -3.0 FIXED)
20ns/DIV
2200pF
16
1000pF
14
12
680pF
10
1k 100pF
8
6
4
2
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
VH VOLTS (VL = 0.0)
FIGURE 11. ROUT vs VH RAIL
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11
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VH VOLTS (VL = 0.0)
FIGURE 12. PROPAGATION DELAY vs VH RAIL, VARIOUS LOADS
FN6229.2
December 4, 2014
ISL55100B
Typical Performance Curves
45.0
20
40.5
18
36.0
16
2200pF
31.5
14
TPD IN (ns)
FALL TIME (ns)
Device installed on Intersil ISL55100B Evaluation Board. (Continued)
27.0
22.5
1000pF
18.0
13.5
DRIVER TPD .. NO LOAD
10
8
COMPARATOR TPD .. NO LOAD
6
680pF
4
9.0
1k 100pF
4.5
0.0
12
1
2
3
4
5
6
7
8
9
10
11
12
13
2
0
11
14
12
13
35.0
16
17
18
19
100
31.5
90
2200pF
28.0
80
24.5
70
21.0
60
ICC (mA)
RISE TIME (ns)
15
FIGURE 14. DRIVER AND RECEIVER TPD VARIANCE vs VCC
FIGURE 13. DRIVER FALL TIME vs VH RAIL, VARIOUS LOADS
17.5
1000pF
14.0
10.5
50
40
ICC STATIC CONDITIONS
30
680pF
7.0
20
3.5
0.0
14
VCC-VEE (VEE = -3.0)
VH VOLTS (VL = 0.0)
1k 100pF
1
2
3
4
5
6
7
8
9
10
11
12
13
10
0
11
14
12
13
VH VOLTS (VL = 0.0)
14
15
16
VCC-VEE (VEE = -3.0)
17
18
19
FIGURE 16. STATIC ICC vs VCC
FIGURE 15. DRIVER RISE TIME vs VH RAIL, VARIOUS LOADS
150
9
135
8
12V VCC
7
6
5
4
18V VCC
3
2
9V VCC AND VEXT = 5.5V
1
0
5M 10M 15M 20M 25M 30M 35M 40M 45M 50M 55M 60M
FREQUENCY (Hz)
FIGURE 17. DEVICE POWER DISSIPATION WITH VCC-VEE = 18, 12
AND 9.0 (VEXT = 5.5V) VOLTS. All FOUR PINS MAKING
TWO TRANSITIONS PER PERIOD
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12
TEMPERATURE RISE (°C)
POWER DISSIPATION (W)
AIRFLOW LEGEND A = 0m/s: B = 1.0m/s: C = 2.5m/s
10
A
120
B C
12V VCC
105
90
A
B
C
18V VCC
A
B
C
75
60
45
30
15
0
9V VCC AND VEXT = 5.5V
5M 10M 15M 20M 25M 30M 35M 40M 45M 50M 55M 60M
FREQUENCY (Hz)
FIGURE 18. CALCULATED JUNCTION TEMPERATURE ABOVE
AMBIENT WITH VCC-VEE = 18, 12 AND 9.0
(VEXT = 5.5V) VOLTS. ALL FOUR PINS MAKING TWO
TRANSITIONS PER PERIOD
FN6229.2
December 4, 2014
ISL55100B
Typical Performance Curves
Device installed on Intersil ISL55100B Evaluation Board. (Continued)
VCC 12.0 DH 6.0
VEE 3.0 DL 0.0
2V/DIV 1V/DIV
2V/DIV
VCC 12.0 DH 6.0
VEE 3.0 DL 0.0
0
0
0
10ns/DIV
FIGURE 19. FREQUENCY OF 10MHz = 50ns PATTERN RATE
FIGURE 20. MINIMUM PULSE WIDTH VH 6/8/10V
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
December 4, 2014
FN6229.2
Update the datasheet throughout to Intersil’s new standard.
On page 2, updated the ordering information by adding MSL note.
On “Pin Descriptions” on page 3: Added “This is also the potential of the exposed thermal pad on the package
bottom.” to the VEE row. Added “EP” row.
Page 4: In “Electrical Spec” table, “Min Output Swing” parameter, changed 55100A to 55100B.
Page 4: In “Electrical Spec” table, “AC Output Current” parameter: updated note references.
Page 6: Added Note 10.
On page 9, changed a sentence in the 5th paragraph from: ‘The maximum safe power temperature vs operating
frequency can be found graphically in Figure 18”. to: “The junction temperature rise above ambient vs. operating
frequency can be found graphically in Figure 18”.
On page 9, edited “ESD Protection” paragraph.
On page 10, revised Figure 6.
Figure 18 on page 12, changed the Y-axis label from “Temperature” to “Temperature Rise”.
Added Revision History and About Intersil sections.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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13
FN6229.2
December 4, 2014
ISL55100B
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L72.10x10
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
0.02
0.05
-
A2
-
0.65
1.00
9
0.30
5, 8
A3
b
0.20 REF
0.18
0.25
9
D
10.00 BSC
-
D1
9.75 BSC
9
D2
5.85
E
E1
E2
6.00
6.15
7, 8
10.00 BSC
-
9.75 BSC
5.85
e
6.00
9
6.15
7, 8
0.50 BSC
-
k
0.20
-
-
-
L
0.30
0.40
0.50
8, 10
N
72
2
Nd
18
3
Ne
18
3
P
-
-
0.60
9

-
-
12
9
Rev. 1 11/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P &  are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220VNND-3 except for the "L" min
dimension.
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14
FN6229.2
December 4, 2014
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