DATASHEET

DATASHEET
Dual, High Speed MOSFET Driver
ISL55110, ISL55111
Features
The ISL55110 and ISL55111 are dual high speed MOSFET
drivers intended for applications requiring accurate pulse
generation and buffering. Target applications include
ultrasound, CCD imaging, piezoelectric distance sensing and
clock generation circuits.
• 5V to 12V pulse amplitude
With a wide output voltage range and low ON-resistance, these
devices can drive a variety of resistive and capacitive loads
with fast rise and fall times, allowing high-speed operation
with low skew, as required in large CCD array imaging
applications.
• Low skew
The ISL55110, ISL55111 are compatible with 3.3V and 5V
logic families and incorporate tightly controlled input
thresholds to minimize the effect of input rise time on output
pulse width. The ISL55110 has a pair of in-phase drivers while
the ISL55111 has two drivers operating in anti-phase.
• Low quiescent current
ISL55110 and ISL55111 have a power-down mode for low
power consumption during equipment standby times, making
it ideal for portable products.
• CCD array horizontal driver
The ISL55110 and ISL55111 are available in 16 Ld Exposed
pad QFN packaging and 8 Ld TSSOP. Both devices are
specified for operation over the full -40°C to +85°C
temperature range.
• High current drive 3.5A
• 6ns minimum pulse width
• 1.5ns rise and fall times, 100pF load
• 3.3V and 5V logic compatible
• In-phase (ISL55110) and anti-phase outputs (ISL55111)
• Small QFN and TSSOP packaging
• Pb-free (RoHS compliant)
Applications
• Ultrasound MOSFET driver
• Clock driver circuits
Related Literature
• AN1283, “ISL55110_11EVAL1Z, ISL55110_11EVAL2Z
Evaluation Board User's Manual”
ISL55110 AND ISL55111 DUAL DRIVER
o
o
VDD
IN-A
VH
OA
o
o
o
ENABLE-QFN*
o
IN-B
OB
**
GND
o
o
o
PD
*ENABLE AVAILABLE IN QFN PACKAGE ONLY
**ISL55111 IN-B IS INVERTING
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
January 29, 2015
FN6228.8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2006-2008, 2011-2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL55110, ISL55111
Pin Configurations
ISL55111
(16 LD QFN)
TOP VIEW
NC
NC
NC
NC
NC
NC
NC
NC
ISL55110
(16 LD QFN)
TOP VIEW
16
15
14
13
16
15
14
13
VDD
1
12 OB
ENABLE
2
11 GND
EP
VDD
1
ENABLE
2
12 OB
11
EP
GND
4
9
OA
IN-B
4
9
IN-A
5
6
7
8
5
6
7
8
NC
IN-B
NC
10 VH
NC
3
IN-A
PD
NC
10 VH
NC
3
NC
PD
OA
ISL55111
(8 LD TSSOP)
TOP VIEW
ISL55110
(8 LD TSSOP)
TOP VIEW
VDD
1
8 OB
VDD
1
8 OB
PD
2
7 GND
PD
2
7 GND
IN-B
3
6 VH
IN-B
3
6 VH
IN-A
4
5
IN-A
4
5
OA
OA
Pin Descriptions
16 LD QFN
8 LD TSSOP
PIN
1
1
VDD
10
6
VH
11
7
GND
3
2
PD
2
-
ENABLE
5
4
IN-A
4
3
IN-B, IN-B
9
5
OA
Driver output related to IN-A.
12
8
OB
Driver output related to IN-B.
6, 7, 8, 13, 14,
15, 16
-
NC
No internal connection.
EP
-
EP
Exposed thermal pad. Connect to GND and follow good thermal pad layout guidelines.
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2
FUNCTION
Logic power.
Driver high rail supply.
Ground, return for both VH rail and VDD logic supply. This is also the potential of the QFN’s exposed
pad (EP).
Power-down. Active logic high places part in power-down mode.
QFN packages only. When the ENABLE pin is low, the device will operate normally (outputs controlled
by the inputs). When the ENABLE pin is tied high, the output will be tri-stated. In other words, it will
act as if it is open or floating regardless of what is on the IN-x pins. This provides high-speed enable
control over the driver outputs.
Logic level input that drives OA to VH rail or ground. Not inverted.
Logic level input that drives OB to VH rail or ground. Not inverted on ISL55110, inverted on ISL55111.
FN6228.8
January 29, 2015
ISL55110, ISL55111
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL55110IRZ
55110IRZ
-40 to +85
16 Ld QFN
L16.4x4A
ISL55110IVZ
55110 IVZ
-40 to +85
8 Ld TSSOP
M8.173
ISL55111IRZ
55111IRZ
-40 to +85
16 Ld QFN
L16.4x4A
ISL55111IVZ
55111 IVZ
-40 to +85
8 Ld TSSOP
M8.173
ISL55110EVAL1Z
TSSOP Evaluation Board
ISL55110EVAL2Z
QFN Evaluation Board
ISL55111EVAL1Z
TSSOP Evaluation Board
ISL55111EVAL2Z
QFN Evaluation Board
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL55110, ISL55111. For more information on MSL please see techbrief
TB363.
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3
FN6228.8
January 29, 2015
ISL55110, ISL55111
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VH to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.0V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
VIN-A, VIN-B, PD, ENABLE . . . . . . . . . . . . . . . . (GND - 0.5V) to (VDD + 0.5V)
OA, OB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.5) to (VH + 0.5V)
Maximum Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kV
Thermal Resistance
JA (°C/W) JC (°C/W)
16 Ld (4x4) QFN Package (Notes 5, 6) . . .
45
3.0
8 Ld TSSOP Package (Notes 4, 7) . . . . . . .
140
46
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Drive Supply Voltage (VH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 13.2V
Logic Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For JC, the “case temp” location is taken at the package top center.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise
noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER
VH = +12V, VDD = 2.7V to 5.5V, TA = +25°C, unless otherwise specified.
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
LOGIC CHARACTERISTICS
VIX_LH
Logic Input Threshold - Low-to-High
lIH = 1µA: VIN-A, VIN-B
1.32
1.42
1.52
V
VIX_HL
Logic Input Threshold - High-to-Low
lIL = 1µA: VIN-A, VIN-B
1.12
1.22
1.32
V
VDD
V
VHYS
Logic Input Hysteresis
VIN-A, VIN-B
VIH
Logic Input High Threshold
PD
0.2
VIL
Logic Input Low Threshold
PD
0
0.8
V
VIH
Logic Input High Threshold
ENABLE - QFN only
2.0
VDD
V
0
2.0
V
Logic Input Low Threshold
ENABLE - QFN only
0.8
V
IIX_H
Input Current Logic High
VIN-A, VIN-B = VDD
10
20
nA
IIX_L
Input Current Logic Low
VIN-A, VIN-B = 0V
10
20
nA
II_H
Input Current Logic High
PD = VDD
10
20
nA
10
VIL
II_L
Input Current Logic Low
PD = 0V
II_H
Input Current Logic High
ENABLE = VDD (QFN only)
II_L
Input Current Logic Low
ENABLE = 0V (QFN only)
15
nA
12
µA
-25
nA
DRIVER CHARACTERISTICS
rDS
Driver Output Resistance
IDC
Driver Output DC Current (>2s)
IAC
Peak Output Current
Design Intent; verified via
simulation.
Driver Output Swing Range
OA or OB = “1”, voltage
referenced to GND
VOH to VOL
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4
OA, OB
3
3
6
Ω
100
mA
3.5
A
13.2
V
FN6228.8
January 29, 2015
ISL55110, ISL55111
DC Electrical Specifications
PARAMETER
VH = +12V, VDD = 2.7V to 5.5V, TA = +25°C, unless otherwise specified. (Continued)
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
4.0
6.0
mA
SUPPLY CURRENTS
IDD
IDD-PDN
IH
IH_PDN
Logic Supply Quiescent Current
PD = Low
Logic Supply Power-down Current
PD = High
12
µA
Driver Supply Quiescent Current
PD = Low, outputs unloaded
15
µA
Driver Supply Power-down Current
PD = High
2.5
µA
MAX
(Note 8)
UNITS
AC Electrical Specifications
PARAMETER
VH = +12V, VDD = +3.6V, TA = +25°C, unless otherwise specified.
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)
TYP
SWITCHING CHARACTERISTICS
tR
Driver Rise Time
Figure 2, OA, OB:
CL = 100pF/1k
10% to 90%, VOH - VOL = 12V
1.2
ns
tF
Driver Fall Time
Figure 2, OA, OB:
CL = 100pF/1k
10% to 90%, VOH - VOL = 12V
1.4
ns
tR
Driver Rise Time
Figure 2, OA, OB: CL = 1nF
10% to 90%, VOH - VOL = 12V
6.2
ns
tF
Driver Fall Time
Figure 2, OA, OB: CL = 1nF
10% to 90%, VOH - VOL = 12V
6.9
ns
tpdR
Input to Output Propagation Delay
Figure 3, load 100pF/1k
10.9
ns
tpdF
Input to Output Propagation Delay
10.7
ns
tpdR
Input to Output Propagation Delay
12.8
ns
tpdF
Input to Output Propagation Delay
12.5
ns
tpdR
Input to Output Propagation Delay
14.5
ns
tpdF
Input to Output Propagation Delay
14.1
ns
Figure 3, load 330pF
Figure 3, load 680pF
tSkewR
Channel-to-Channel tpdR Spread with Same
Loads Both Channels
Figure 3, All loads
<0.5
ns
tSkewF
Channel-to-Channel tpdF Spread with Same
Loads Both Channels
Figure 3, All loads
<0.5
ns
FMAX
Maximum Operating Frequency
70
MHz
TMIN
Minimum Pulse Width
6
ns
PDEN
Power-down to Power-on Time
650
ns
PDDIS
Power-on to Power-down Time
40
ns
tEN
Enable time; ENABLE switched high to low.
40
ns
tDIS
Disable time; ENABLE switched low to high.
40
ns
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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FN6228.8
January 29, 2015
ISL55110, ISL55111
VH = 12V
+3V
INPUT

4.7µF
0.1µF
0.4V
IN-X
INPUT
OUTPUT
INPUT RISE AND
FALL TIMES ≤2ns
CL
ISL55110
tf
tr
12V
IN
90%
90%
OUTPUT
10%
10%
0V
FIGURE 2. TEST CIRCUIT; OUTPUT RISE (tR)/FALL (tF) TIMES
VH = 12V
+3V
INPUT

4.7µF
50%
0.1µF
0.4V
IN-X
INPUT
CL
ISL55110
tpdF
tpdR
OUTPUT
INPUT RISE AND
FALL TIMES ≤2ns
50%
12V
IN
50%
OUTPUT OA AND OB ISL55110
OUTPUT OA ISL55111
50%
0V
12V
OUTPUT OB ISL55111
50%
50%
0V
tSKEWR = |tpdR CHN A - tpdR CHN B|
FIGURE 3. TEST CIRCUIT; PROPAGATION (tPD) DELAY
Typical Performance Curves (See “Typical Performance Curves Discussion” on page 11)
7.0
7.0
VDD = 3.6V
IOUT = -50mA
6.3
5.6
+85°C
3.5
4.2
2.8
2.1
2.1
1.4
1.4
0.7
0.7
-40°C
3
4
5
6
7
8
9
10
11
12
VH, DRIVE RAIL (V)
FIGURE 4. DRIVER rON vs VH VOLTAGE (SOURCING CURRENT)
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6
+25°C
3.5
2.8
0.0
+85°C
4.9
+25°C
4.2
5.6
rON (Ω)
rON (Ω)
4.9
VDD = 3.6V
IOUT = +50mA
6.3
13
0.0
3
-40°C
4
5
6
7
8
9
10
VH, DRIVE RAIL (V)
11
12
13
FIGURE 5. DRIVER rON vs VH VOLTAGE (SINKING CURRENT)
FN6228.8
January 29, 2015
ISL55110, ISL55111
Typical Performance Curves (See “Typical Performance Curves Discussion” on page 11) (Continued)
4.00
4.00
IOUT = +50mA
IOUT = -50mA
3.66
3.33
rON ()
rON ()
3.66
VH = 5V
2.66
VH = 12V
2.33
3.33
2.66
VH = 5V
VH = 12V
2.33
2.00
2.5
3.5
4.5
2.00
2.5
5.5
3.5
VDD (V)
4.5
FIGURE 6. rON vs VDD VOLTAGE (SOURCING CURRENT)
FIGURE 7. rON vs VDD VOLTAGE (SINKING CURRENT)
5.0
10
VDD = 3.6V
9
8
7
4.2
IDD (mA)
IDD (mA)
4.6
3.8
6
5
4
3
3.4
2
3.0
2.5
1
VH = 5V TO 12V
3.5
4.5
0
5.5
4
8
VH, DRIVE RAIL (V)
VDD (V)
FIGURE 8. QUIESCENT IDD vs VDD
200
VDD = 3.6V
90
12
FIGURE 9. OPERATING IDD vs VH AT 50MHz (NO LOAD)
100
80
160
70
140
60
120
50
40
100
80
30
60
20
40
10
20
0
VDD = 3.6V
180
IH (mA)
IH (µA)
5.5
VDD (V)
0
4
8
VH, DRIVE RAIL (V)
FIGURE 10. QUIESCENT IH vs VH
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7
12
4
8
VH, DRIVE RAIL (V)
12
FIGURE 11. OPERATING IH vs VH AT 50MHz (NO LOAD)
FN6228.8
January 29, 2015
ISL55110, ISL55111
Typical Performance Curves (See “Typical Performance Curves Discussion” on page 11) (Continued)
180
12.0
160
10.5
140
9.0
120
IH (mA)
200
13.5
IDD (mA)
15.0
7.5
6.0
3.0
80
40
VH = 5.0V
VDD = 3.6V
1.5
20
0
66
100
124
TOGGLE FREQUENCY (MHz)
50
128
FIGURE 12. IDD vs FREQUENCY (DUAL CHANNEL, NO LOAD)
1.5
1.4
1.4
LOGIC (V)
+85°C
1.3
66
100
124
TOGGLE FREQUENCY (MHz)
128
FIGURE 13. IH vs FREQUENCY (DUAL CHANNEL, NO LOAD)
1.5
-40°C
LOGIC (V)
100
60
4.5
0
50
VH = 5.0V
VDD = 3.6V
1.2
1.1
1.3
-40°C
1.2
1.1
+85°C
1.0
2.5
3.5
4.5
1.0
2.5
5.5
3.5
VDD (V)
10
10
9
9
FALL TIME (ns)
RISE TIME (ns)
6
330pF
5
4
3
2
VH = 12.0V
VDD = 3.6V
1
0
-40
-10
+20
+50
PACKAGE TEMPERATURE (°C)
FIGURE 16. tR vs TEMPERATURE
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8
680pF
8
680pF
7
5.5
FIGURE 15. VIL LOGIC THRESHOLDS vs VDD
FIGURE 14. VIH LOGIC THRESHOLDS vs VDD
8
4.5
VDD (V)
+85
VH = 12.0V
VDD = 3.6V
7
6
330pF
5
4
3
2
1
0
-40
-10
+20
+50
PACKAGE TEMPERATURE (°C)
+85
FIGURE 17. tF vs TEMPERATURE
FN6228.8
January 29, 2015
ISL55110, ISL55111
Typical Performance Curves (See “Typical Performance Curves Discussion” on page 11) (Continued)
20
20
680pF
18
16
14
12
10
8
330pF
6
4
VH = 12.0V
VDD = 3.6V
2
0
-40
-10
+20
PACKAGE TEMP (°C)
+50
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
18
680pF
16
14
12
10
8
330pF
6
4
VH = 12.0V
VDD = 3.6V
2
0
-40
+85
FIGURE 18. tpdR vs TEMPERATURE
10
680pF
7 100pF/1k
9
330pF
5
4
3
6
5
4
3
2
1
1
VH = 12.0V
0
2.5
5.5
4.5
3.5
FIGURE 20. tR vs VDD
FIGURE 21. tF vs VDD
12.0
12.0
100pF/1k
10.8
680pF
330pF
100pF/1k
10.8
1000pF
9.6
9.6
8.4
8.4
FALL TIME (ns)
RISE TIME (ns)
5.5
4.5
VDD (V)
VDD (V)
7.2
6.0
4.8
3.6
330pF
680pF
1000pF
7.2
6.0
4.8
3.6
2.4
2.4
1.2
0.0
680pF
330pF
7
2
3.5
+85
1000pF
8 100pF/1k
1000pF
6
0
2.5
+50
10
FALL TIME (ns)
RISE TIME (ns)
8
+20
PACKAGE TEMP (°C)
FIGURE 19. tpdF vs TEMPERATURE
VH = 12.0V
9
-10
1.2
VDD = 3.3V
3
6
9
VH (V)
FIGURE 22. tR vs VH
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9
12
0.0
VDD = 3.3V
3
9
6
12
VH (V)
FIGURE 23. tF vs VH
FN6228.8
January 29, 2015
ISL55110, ISL55111
Typical Performance Curves (See “Typical Performance Curves Discussion” on page 11) (Continued)
20
20
PROPAGATION DELAY (ns)
18
PROPAGATION DELAY (ns)
VH = 12.0V
16
14
12
10
100pF/1k
8
1000pF
6
4
VH = 12.0V
18
16
14
12
10
1000pF
100pF/1k
8
6
4
2
2
0
2.5
3.5
0
2.5
5.5
4.5
3.5
FIGURE 25. tpdF vs VDD
FIGURE 24. tpdR vs VDD
20
20
VDD = 3.3V
16
14
12
10
8
1000pF
100pF/1k
6
4
VDD = 3.3V
18
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
18
2
16
14
12
10
100pF/1k
8
1000pF
6
4
2
0
0
3
6
12
9
3
6
VH (V)
FIGURE 27. tpdF vs VH
1.0
1.0
VH = 12.0V
VDD = 3.6V
0.9
0.8
0.7
0.7
tSkewF (ns)
330pF
0.6
0.5
680pF
0.6
0.4
0.3
0.2
0.2
0.1
0.1
-10
+20
PACKAGE TEMP (°C)
+50
FIGURE 28. tSkewR vs TEMPERATURE
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10
+85
330pF
680pF
0.5
0.3
0.0
-40
VH = 12.0V
VDD = 3.6V
0.9
0.8
0.4
12
9
VH (V)
FIGURE 26. tpdR vs VH
tSkewR (ns)
5.5
4.5
VDD (V)
VDD (V)
0.0
-40
-10
+20
PACKAGE TEMP (°C)
+50
+85
FIGURE 29. tSkewF vs TEMPERATURE
FN6228.8
January 29, 2015
ISL55110, ISL55111
Typical Performance Curves (See “Typical Performance Curves Discussion” on page 11) (Continued)
1.0
0.8
0.8
0.7
0.7
0.6
0.5
680pF
0.4
0.6
0.4
0.3
0.2
0.2
330pF
0.1
330pF
0.0
2.5
680pF
0.5
0.3
0.1
VH = 12.0V
0.9
SKEW (ns)
SKEW (ns)
1.0
VH = 12.0V
0.9
3.5
0.0
2.5
5.5
4.5
3.5
FIGURE 30. tSkewR vs VDD
1.0
1.0
0.8
0.8
0.7
0.7
0.6
680pF
0.5
0.4
VDD = 3.3V
0.9
SKEW (ns)
SKEW (ns)
FIGURE 31. tSkewF vs VDD
VDD = 3.3V
0.9
0.6
680pF
0.5
0.4
0.3
0.3
0.2
0.2
330pF
0.1
0.0
5.5
4.5
VDD (V)
VDD (V)
3
330pF
0.1
6
9
12
0.0
3
rON
The rON source is tested by placing the device in constant drive
high condition and connecting a -50mA constant current
source to the driver output. The voltage drop is measured from
VH to driver output for rON calculations.
The rON sink is tested by placing the device in constant driver
low condition and connecting a +50mA constant current
source. The voltage drop from driver out to ground is measured
for rON calculations.
Dynamic Tests
All dynamic tests are conducted with ISL55110 and ISL55111
evaluation board(s) (ISL55110_11EVAL2Z). Driver loads are
soldered to the evaluation board. Measurements are collected
with P6245 active FET Probes and TDS5104 oscilloscope.
Pulse stimulus is provided by HP8131 pulse generator.
The ISL55110 and ISL55111 evaluation boards provide test
point fields for leadless connection to either an active FET
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9
12
FIGURE 33. tSkewF vs VH
FIGURE 32. tSkewR vs VH
Typical Performance Curves
Discussion
6
VH (V)
VH (V)
probe or differential probe. “TP - IN_A/_B” test points are used
for monitoring pulse input stimulus. “TP - OA/OB” allows
monitoring of driver output waveforms. C6 and C7 are the
usual placement for driver loads. R3 and R4 are not populated
and are provided for user-specified, more complex load
characterization.
Pin Skew
Pin skew measurements are based on the difference in
propagation delay of the two channels. Measurements are
made on each channel from the 50% point on the stimulus
point to the 50% point on the driver output. The difference in
the propagation delay for Channel A and Channel B is
considered to be skew.
Both rising propagation delay and falling propagation delay are
measured and report as tSkewR and tSkewF.
50MHz Tests
50MHz Tests reported as no load actually include evaluation
board parasitics and a single TEK 6545 FET probe. However, no
driver load components are installed and C6 through C9 and
R3 through R6 are not populated.
FN6228.8
January 29, 2015
ISL55110, ISL55111
General
The most dynamic measurements are presented in three
ways:
3. The ambient tests are repeated with VDD of 3.3V and VH
data points of 3V, 6V, 9V and 12V.
1. Over-temperature with a VDD of 3.6V and VH of 12V.
2. At ambient with VH set to 12V and VDD data points of 2.5V,
3.5V, 4.5V and 5.50V.
FIGURE 34. ISL55110_11EVAL2Z (QFN) EVALUATION BOARD
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FN6228.8
January 29, 2015
ISL55110, ISL55111
Detailed Description
Bypassing
The ISL55110 and ISL55111 are dual high-speed MOSFET
drivers intended for applications requiring accurate pulse
generation and buffering. Target applications include ultrasound,
CCD imaging, automotive piezoelectric distance sensing and
clock generation circuits.
The rapid charging and discharging of the load capacitance
requires very high current spikes from the power supplies. A
parallel combination of capacitors, which have a low impedance
over a wide frequency range should be used. A 4.7µF tantalum
capacitor in parallel with a low inductance 0.1µF capacitor is
usually sufficient bypassing.
With a wide output voltage range and low ON-resistance, these
devices can drive a variety of resistive and capacitive loads with
fast rise and fall times, allowing high-speed operation with low
skew as required in large CCD array imaging applications.
The ISL55110 and ISL55111 are compatible with 3.3V and 5V
logic families and incorporate tightly controlled input thresholds
to minimize the effect of input rise time on output pulse width.
The ISL55110 has a pair of in-phase drivers while the ISL55111
has two drivers operating in anti-phase. Both channels of the
device have independent inputs to allow external time phasing if
required.
In addition to driving power MOSFETs, the ISL55110 and
ISL55111 are well suited for other applications such as bus,
control signal and clock drivers for large memory arrays on
microprocessor boards, where the load capacitance is large and
low propagation delays are required. Other potential applications
include peripheral power drivers and charge pump voltage
inverters.
Output Damping
Ringing is a common problem in any circuit with very fast rise or
fall times. Such ringing will be aggravated by long inductive lines
with capacitive loads. Techniques to reduce ringing include:
1. Reduce inductance by making printed circuit board traces as
short as possible.
2. Reduce inductance by using a ground plane or by closely
coupling the output lines to their return paths.
3. Use small damping resistor in series with the output of the
ISL55110 and ISL55111. Although this reduces ringing, it will
also slightly increase the rise and fall times.
4. Use good bypassing techniques to prevent supply voltage
ringing.
Power Dissipation Calculation
The Power dissipation equation has three components:
Input Stage
1. Quiescent power dissipation.
The input stage is a high impedance buffer with rise/fall
hysteresis. This means that the inputs will be directly compatible
with both TTL and lower voltage logic over the entire VDD range.
The user should treat the inputs as high-speed pins and keep rise
and fall times to <2ns.
2. Power dissipation due to internal parasitics.
Output Stage
The ISL55110 and ISL55111 outputs are high-power CMOS
drivers swinging between ground and VH . At VH = 12V, the output
impedance of the inverter is typically 3.0Ω. The high peak current
capability of the ISL55110 and ISL55111 enables it to drive a
330pF load to 12V with a rise time of <3.0ns over the full
temperature range. The output swing of the ISL55110 and
ISL55111 comes within <30mV of the VH and Ground rails.
Application Notes
3. Power dissipation because of the load capacitor.
Power dissipation due to internal parasitics is usually the most
difficult to accurately quantitize. This is primarily due to crowbar
current which is a product of both the high and low drivers
conducting effectively at the same time during driver transitions.
Design goals always target the minimum time for this condition
to exist. Given that how often this occurs is a product of
frequency, crowbar effects can be characterized as internal
capacitance.
Lab tests are conducted with driver outputs disconnected from
any load. With design verification packaging, bond wires are
removed to aid in the characterization process. Based on
laboratory tests and simulation correlation of those results,
Equation 1 defines the ISL55110 and ISL55111 power
dissipation per channel:
Although the ISL55110 and ISL55111 are simply dual level
shifting drivers, there are several areas to which careful attention
must be paid.
P = V DD  3.3e-3 + 10pF  V DD  f + 135pF  VH  f +
2
CL  VH  f (Watts/Channel)
Grounding
• Where 3.3mA is the quiescent current from the VDD. This
forms a small portion of the total calculation. When figuring
two channel power consumption, only include this current
once.
Since the input and the high current output current paths both
include the ground pin, it is very important to minimize any
common impedance in the ground return. Since the ISL55111
has one inverting input, any common impedance will generate
negative feedback and may degrade the delay times and rise
and fall times. Use a ground plane if possible or use separate
ground returns for the input and output circuits. To minimize any
common inductance in the ground return, separate the input and
output circuit ground returns as close to the ISL55110 and
ISL55111 as possible.
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2
2
(EQ. 1)
• 10pF is the approximate parasitic capacitor (inverters, etc.),
which the VDD drives.
• 135pF is the approximate parasitic at the DOUT and its buffers.
This includes the effect of the crowbar current.
• CL is the load capacitor being driven.
FN6228.8
January 29, 2015
ISL55110, ISL55111
Power Dissipation Discussion
Specifying continuous pulse rates, driver loads and driver level
amplitudes are key in determining power supply requirements,
as well as dissipation/cooling necessities. Driver output patterns
also impact these needs. The faster the pin activity, the greater
the need to supply current and remove heat.
As detailed in the “Power Dissipation Calculation” on page 13,
power dissipation of the device is calculated by taking the DC
current of the VDD (logic) and VH current (driver rail) times the
respective voltages and adding the product of both calculations.
The average DC current measurements of IDD and IH should be
done while running the device with the planned VDD and VH
levels and driving the required pulse activity of both channels at
the desired operating frequency and driver loads.
Therefore, the user must address power dissipation relative to
the planned operating conditions. Even with a device mounted
per Notes 4 or 5 under “Thermal Information”, given the high
speed pulse rate and amplitude capability of the ISL55110 and
ISL55111, it is possible to exceed the +150°C “absolute
maximum junction temperature”. Therefore, it is important to
calculate the maximum junction temperature for the application
to determine if operating conditions need to be modified for the
device to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 2:
T JMAX - T AMAX
P DMAX = -------------------------------------------- JA
The maximum power dissipation actually produced by an IC is
the total quiescent supply current times the total power supply
voltage, plus the power in the IC due to the loads. Power also
depends on number of channels changing state and frequency of
operation. The extent of continuous active pulse generation will
greatly effect dissipation requirements.
The user should evaluate various heatsink/cooling options in
order to control the ambient temperature part of the equation.
This is especially true if the user’s applications require
continuous, high-speed operation. A review of the JA ratings of
the TSSOP and QFN packages clearly show the QFN package to
have better thermal characteristics.
The reader is cautioned against assuming a calculated level of
thermal performance in actual applications. A careful inspection
of conditions in your application should be conducted. Great care
must be taken to ensure die temperature does not exceed
+150°C Absolute Maximum Thermal Limits.
Important Note: The ISL55110 and ISL55111 QFN package metal
plane is used for heat sinking of the device. It is electrically
connected to ground (i.e., pin11).
Power Supply Sequencing
Apply VDD, then VH.
Power-Up Considerations
(EQ. 2)
Digital inputs should never be undriven. Do not apply slow analog
ramps to the inputs. Again, place decoupling caps as close to the
package as possible for both VDD and especially VH.
Where:
Special Loading
• TJMAX = Maximum junction temperature
With most applications, the user will usually have a special load
requirement. Please contact Intersil for evaluation boards.
• TAMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
• PDMAX = Maximum power dissipation in the package
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FN6228.8
January 29, 2015
ISL55110, ISL55111
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
January 29, 2015
FN6228.8
Page 1, "Description" section, 4th sentence, removed the word "automotive" before the word piezoelectric".
"Applications", removed 3rd bullet item: "Automotive piezo driver applications"
May 30, 2014
FN6228.7
Throughout document, changed “HIZ” to “ENABLE” and “PDN” pin references to “PD”.
Page 2, “Pin Descriptions” table; Changed “Function” entries for GND and ENABLE pins. Added EP row.
Page 3, “Ordering Info” table; Added “TSSOP” or “QFN” to the Evaluation board entries to clarify.
Page 4 and page 5; Changed “Driver Output Swing Range” Test Conditions entry from “VH voltage to Ground”
to “OA or OB = “1”, Voltage referenced to GND and changed “Driver Supply Quiescent Current” “Test
Conditions” entry from “No resistive load DOUT” to “Outputs Unloaded”. Added “Figure 1” reference to the
driver rise and fall time “Test Conditions”.
Page 5; Changed “tEN” and “tDIS” descriptions.
Figure 2 on page 6: changed “Thresholds” to “Times” in title. Figure 3 on page 6: in “tSKEWR” equation,
changed “CHN 1” and “CHN 2” to “CHN A” and “CHN B” and added “absolute value” indicator. Figures 4 and 5:
changed “Resistance” to “Voltage” in titles.
Figures 6 and 7: changed “Resistance” to “Voltage” in titles. Figures 9 and 11: added “Operating” to titles.
Figure 12: Fixed Y-axis scale. Figures 14 and 15: Added “vs. VDD” to titles.
Figures 32 and 33: changed X-axis Label from “VDD” to “VH”.
Figure 34: Added “QFN” to title.
“Power Dissipation Discussion” on page 14, changed “It is electrically connected to the negative supply
potential ground” to “It is electrically connected to ground (i.e., pin11)” and, in the “Special Loading” section,
removed text “or to request a device characterization to your requirements in our lab”.
August 8, 2013
FN6228.6
Page 4 In Electrical Spec Table changed units from mA to µA
II_H Input Current Logic
High
ENABLE = VDD
(QFN only)-
July 9, 2012
FN6228.5
Page 4- Removed “Recommended Operating Conditions table”, which was located above dc electrical spec.
table and placed in the abs max ratings table to meet Intersil standards.
Page 5 - DC Electrical Spec: Modified IH-PDN parameter (Driver Supply Power-Down Current) Max limit value
from 1µ to 2.5µ.
Added Revision History table on page 15.
February 9, 2011
FN6228.4
For 8 ld TSSOP, added theta JC value of 46C/W. Added foot note that for TSSOP package theta JC the case
temp location is measured in the center of the top of the package.
February 4, 2011
March 14, 2008
Page 1: Added following sentence to 3rd paragraph: "Both inputs of the device have independent inputs to
allow external time phasing if required.”
Updated Tape & Reel note in Ordering Information on page 3 from “Add "-T" suffix for tape and reel.” to new
standard “Add "-T*" suffix for tape and reel.” The "*" covers all possible tape and reel options
Added MSL note to Ordering Information
Page 5: Updated over temp note in Min Max column of spec tables from “Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.” to new standard “Compliance to datasheet limits is assured
by one or more methods: production test, characterization and/or design.”
Page 13: Changed Equation 1 from:
P VDD?3.3e-= 3+10pF?VDD2?f+135pF?VH2?f+ (EQ. 1)
CL?VH2?f (Watts/Channel) To P VDD 3.3e-= × 3+10pF × VDD2 × f+135pF × VH2 × f+ CL × VH2
(Watts/Channel) (EQ. 1)
Page 14: Removed the following sentence from “Power Supply Sequencing”:
“The ISL55110, ISL55111 references both VDD and the VH driver supplies with respect to Ground. Therefore,
apply VDD, then VH.”
Replaced with: “Apply VDD, then VH.”
Added subsection “Power Up Considerations” and moved text that was in the “Power Supply Sequencing”
section to this section. (“Digital Inputs should…especially VH.”)
Page 18- Updated POD M8.173 as follows:
Updated to new POD standards as follows: Moved dimensions from table onto drawing. Added Land Pattern.
No dimension changes.
FN6228.0
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Initial Release
FN6228.8
January 29, 2015
ISL55110, ISL55111
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN6228.8
January 29, 2015
ISL55110, ISL55111
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4A
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGD-10)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
9
A3
b
0.20 REF
0.18
D
0.30
5, 8
4.00 BSC
D1
D2
0.25
9
-
3.75 BSC
2.30
2.40
9
2.55
7, 8
E
4.00 BSC
-
E1
3.75 BSC
9
E2
2.30
e
2.40
2.55
7, 8
0.50 BSC
-
k
0.25
-
-
-
L
0.30
0.40
0.50
8
L1
-
-
0.15
10
N
16
2
Nd
4
3
Ne
4
3
P
-
-
0.60
9
q
-
-
12
9
Rev. 2 3/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & q are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present.
L minus L1 to be equal to or greater than 0.3mm.
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FN6228.8
January 29, 2015
ISL55110, ISL55111
Package Outline Drawing
M8.173
8 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 01/10
A
2
4
3.0 ±0.5
SEE DETAIL "X"
5
8
6.40
CL
4.40 ±0.10
3
4
0.20 C BA
PIN 1
ID MARK
1
4
0.09-0.20
B
0.65
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06
0.10 C
0.10
GAUGE
PLANE
0.25
6
CBA
0°-8°
0.05 MIN
0.15 MAX
0.60 ±0.15
DETAIL "X"
SIDE VIEW
(1.45)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
(5.65)
PACKAGE BODY
OUTLINE
2. Dimension does not include mold flash, protrusions or
gate burrs. Mold flash, protrusions or gate burrs shall
not exceed 0.15 per side.
3. Dimension does not include interlead flash or protrusion.
Interlead flash or protrusion shall not exceed 0.15 per side.
4. Dimensions are measured at datum plane H.
5. Dimensioning and tolerancing per ASME Y14.5M-1994.
(0.35 TYP)
(0.65 TYP)
TYPICAL RECOMMENDED LAND PATTERN
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6. Dimension on lead width does not include dambar protrusion.
Allowable protrusion shall be 0.08 mm total in excess of
dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm.
7. Conforms to JEDEC MO-153, variation AC. Issue E
FN6228.8
January 29, 2015
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