CD4724BMS CMOS 8-Bit Addressable Latch December 1992 Features Pinout • High Voltage Type (20V Rating) CD4724BMS TOP VIEW • Serial Data Input • Active Parallel Output • Storage Register Capability A0 1 16 VDD • Master Clear A1 2 15 RESET • Can Function as Demultiplexer • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V A2 3 14 WRITE DISABLE Q0 4 13 DATA Q1 5 12 Q7 Q2 6 11 Q6 Q3 7 10 Q5 VSS 8 9 Q4 Functional Diagram • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” WRITE DISABLE Applications DATA 14 4 13 5 • Multi-line Decoders 1 A0 • A/D Converters A1 8 2 3 DECODER A2 Description 8 LATCHES 6 7 9 10 11 CD4724BMS 8-bit addressable latch is a serial-input, paralleloutput storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. RESET 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 VDD = 16 VSS = 8 A master RESET input is available, which resets all bits to a logic “0” level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows that data input, while all unaddressed bits are held to a logic “0” level. The CD4724BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4W H1F H6W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1267 File Number 3348 Specifications CD4724BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage VOL15 VOH15 VDD = 15V, No Load VDD = 15V, No Load (Note 3) LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125oC - 1000 µA 3 -55oC - 10 µA 1 +25oC -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA 1, 2, 3 +25oC, +125oC, -55oC - 50 mV 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA Output Current (Sink) Output Current (Source) IOL15 IOH5A VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Output Current (Source) N Threshold Voltage P Threshold Voltage Functional IOH15 VNTH VPTH F VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1268 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4724BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Data to Output SYMBOL TPHL1 TPLH1 CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND Propagation Delay Reset to Output TPHL3 VDD = 5V, VIN = VDD or GND Transition Time 9 10, 11 Propagation Delay Write Disable to Output Propagation Delay Address to Output GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 TPHL4 TPLH4 VDD = 5V, VIN = VDD or GND TTHL TTLH VDD = 5V, VIN = VDD or GND 9 10, 11 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 400 ns - 540 ns - 400 ns - 540 ns - 350 ns - 473 ns - 450 ns - 608 ns - 200 ns - 270 ns NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC MIN MAX UNITS µA - 5 +125oC - 150 µA -55oC, +25oC - 10 µA +125oC - 300 µA - 10 µA +125oC - 600 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V 7-1269 1, 2 1, 2 +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA Specifications CD4724BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Input Voltage Low VIL CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +25oC, +125oC, - 3 V -55oC Input Voltage High VIH Propagation Delay Data to Output TPHL1 TPLH1 Propagation Delay Write Disable to Output TPHL2 TPLH2 VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V 1, 2 +25oC, +125oC, -55oC +7 - V 1, 2, 3 +25oC - 150 ns 1, 2, 3 o +25 C - 100 ns VDD = 10V 1, 2, 3 +25 oC - 160 ns VDD = 15V 1, 2, 3 +25oC - 120 ns o - 160 ns o VDD = 15V Propagation Delay Reset to Output TPHL3 VDD = 15V 1, 2, 3 +25 C - 130 ns Propagation Delay Address to Output TPHL4 TPLH4 VDD = 10V 1, 2, 3 +25oC - 200 ns VDD = 15V 1, 2, 3 +25oC - 150 ns TTLH TTHL VDD = 10V 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 80 ns Transition Time Minimum Address Pulse Width TW VDD = 10V 1, 2, 3 VDD = 15V TW 1, 2, 3 +25 C - 400 MHz VDD = 10V 1, 2, 3 +25oC - 200 MHz 1, 2, 3 +25oC - 125 MHz VDD = 5V 1, 2, 3 +25 oC - 150 ns VDD = 10V 1, 2, 3 +25oC - 75 ns 1, 2, 3 o +25 C - 50 ns VDD = 5V 1, 2, 3 +25 oC - 100 ns VDD = 10V 1, 2, 3 +25oC - 50 ns 1, 2, 3 +25 oC - 35 ns VDD = 5V 1, 2, 3 +25oC - 150 ns VDD = 10V 1, 2, 3 +25oC - 75 ns 1, 2, 3 +25 oC - 50 ns VDD = 5V 1, 2, 3 +25oC - 200 ns VDD = 10V 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 80 ns 1, 2 +25oC - 7.5 pF VDD = 15V Minimum Data Setup Time Data to Write Disable TS VDD = 15V Minimum Data Hold Time Data to Write Disable TH VDD = 15V Minimum Data Pulse Width TW VDD = 15V Input Capacitance CIN o VDD = 5V VDD = 15V Minimum Reset Pulse Width +25 C Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA 1, 4 +25oC -2.8 -0.2 V 1, 4 +25oC - ±1 V N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA 7-1270 Specifications CD4724BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F CONDITIONS VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND NOTES TEMPERATURE MIN MAX UNITS 1, 4 +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL DELTA LIMIT IDD ± 1.0µA IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D READ AND RECORD IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 4 - 7, 9 - 12 1 - 3, 8, 13 - 15 16 7-1271 9V ± -0.5V 50kHz 25kHz Specifications CD4724BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 2 Note 1 4 - 7, 9 - 12 8 1 - 3, 13 - 16 Dynamic BurnIn Note 1 - 1 - 3, 8 16 4 - 7, 9 - 12 8 1 - 3, 13 - 16 Irradiation Note 2 9V ± -0.5V 50kHz 25kHz 4 - 7, 9 - 12 14, 15 13 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Logic Diagram A1 A0 A2 A1 A2 * A0 A0 1 A1 * 2 A1 A1 * A2 3 A1 A1 A1 DATA A2 13 D 14 RESET 15 A1 A1 * WRITE DISABLE A0 A2 A2 * A0 A2 A0 A1 A0 A0 A2 A0 A2 A0 A2 A0 A2 WD D WD R LATCH 0 4 Q0 D WD R LATCH 1 5 Q1 D WD R LATCH 2 6 Q2 D WD R LATCH 3 7 Q3 D WD R LATCH 4 9 Q4 D WD R LATCH 5 10 Q5 D WD R LATCH 6 11 Q6 D WD R LATCH 7 12 Q7 * R R ADDRESS WD VSS = 8 VDD = 16 VDD *ALL INPUTS ARE PROTECTED BY COS/MOS PROTECTION NETWORK Q p n DATA VSS p n FIGURE 1. LOGIC DIAGRAM OF CD4724BMS AND DETAIL OF 1 OF 8 LATCHES 7-1272 CD4724BMS AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) GATE-TO-SOURCE VOLTAGE (VGS) = -5V -10 -15 -20 -25 -15V 10V 7.5 5.0 2.5 5V -30 -10V TRANSITION TIME (tTHL, tTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 150 10V 50 15V 20 30 40 50 60 70 -15 FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 200 10 -10 -15V SUPPLY VOLTAGE (VDD) = 5V 0 0 -5 300 100 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V AMBIENT TEMPERATURE (TA) = +25oC 250 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (TA) = +25oC FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPLH, tPHL) (ns) 10.0 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 -5 -10V GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 AMBIENT TEMPERATURE (TA) = +25oC 15.0 0 FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics 80 90 150 LOAD CAPACITANCE (CL) (pF) SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 50 0 0 100 FIGURE 6. TYPICAL PROPAGATION DELAY TIME (DATA TO QN) vs LOAD CAPACITANCE 200 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE 7-1273 CD4724BMS POWER DISSIPATION (PD) (µW) Typical Performance Characteristics 6 4 2 105 6 4 4 2 (Continued) AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (CL) = 15pF CL = 50pF 10 6 4 2 103 6 4 2 2 10 6 4 1 2 SUPPLY VOLTAGE (VDD) = 15V 5V 10V 10 10V 6 4 0 2 10 2 4 68 100 2 101 4 68 2 4 68 2 4 68 2 4 68 102 103 104 ADDRESS CYCLE TIME (µs) 105 FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION vs ADDRESS CYCLE TIME VDD VDD t2 5 4 7 AST C 1 9 12 6 14 100 KΩ 470 pF 2 OSC OUT 13 R-C CD4047 R 2 (t1 < t2) t1 8 1 CLOCK CD4520 Q1A Q2A Q3A 3 330Ω 14 13 8 STARTS CONVERSION 9 10 15 16 10 * 9 3 4 5 1 2 3 R WD CD4724BMS R 15 DATA Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 4 5 6 7 9 10 11 12 1 2 * 7 LSB 3 12 11 * 13 CD4724BMS OUTPUTS TO DISPLAY VDD 7 5 6 * 4 * CD4001 **HYCOMP HC210SLD - 2R OR EQUIVALENT 6 4 10KΩ + CA3130 3 - 2 1 8 16 10KΩ 56 pF ANALOG IN MSB 1 5 3 4 5 6 7 8 R2R LADDER NETWORK ** OUT 100 KΩ FIGURE 9. A/D CONVERTER 7-1274 2 9 10 11 12 13 CD4724BMS MODE SELECTION ADDRESSED LATCH UNADDRESSED LATCH WD R 0 0 Follows Data Holds Previous State 0 1 Follows Data (Active High 8-Channel Demultiplexer) Reset to “0” 30% A0 1 0 Holds Previous State 1 1 Reset to “0” 70% A1 A2 70% WD tW Reset to “0” WD = Write Disable R = Reset FIGURE 10. DEFINITION OF WRITE DISABLE ON TIME 1 2 3 14 13 A0 A1 A2 A3 DATA IN A0 A1 A2 WD DATA CD4724BMS R Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 4 5 6 7 9 10 11 12 4 5 6 7 D0 D0 D0 D0 D0 D0 D0 D0 1 2 3 4 5 6 7 8 15 VDD * 1 2 3 14 A0 A1 A2 WD Q0 Q1 Q2 Q3 13 DATA CD4724BMS Q4 Q5 Q6 Q7 *1/6 CD4069 R D0 D0 D0 D0 9 D0 10 D0 11 D0 12 D0 9 10 11 12 13 14 15 16 15 VDD FIGURE 11. 1 OF 16 DECODER/DEMULTIPLEXER CD4724BMS DATA Y IN/OUT 2 1/4 CD4016 0 1 3 Q0 D A0 A1 A2 A3 Q1 0 S0 WD S1 S2 R 1 CD4724BMS S5 X IN/OUT D 2 WD WD R Q15 3 WD FIGURE 12. MULTIPLE SELECTION DECODING - 4 X 4 CROSSPOINT SWITCH 7-1275 CD4724BMS Chip Dimensions and Pad Layout Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 1276 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029