A8600 データシート

A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
Features and Benefits
Description
• Four independent, high current switching regulators
• Adjustable 1.0 A/±1.5% always-on asynchronous buck
regulator with an integrated 150 mΩ MOSFET (SW1)
▫ Employs PFM to deliver 3.3 V/40 μA while drawing less
than 50 μA from VIN of 12 V
▫ Operates down to at least 3.6 VIN
• Adjustable 1.5 A/±1.5% asynchronous buck regulator with
an integrated 120 mΩ high-side MOSFET (SW2)
• Adjustable 2.0 A/±1.5% asynchronous buck regulator with
an integrated 110 mΩ MOSFET (SW3)
• Adjustable ±1.5% synchronous buck controller with
integrated gate drivers and current sensing (SW4)
• Fixed 425 kHz, interleaved PWM switching frequency
• EN/SYNC input for PWM frequency scaling
• Adjustable soft-start time for each switching regulator
• All switching regulators provide prebias startup with zero
reverse current
• All switching regulators have overvoltage protection
• External compensation for all switching regulators
Designed to provide the power supply requirements of next
generation car audio and infotainment systems, the A8600
provides all the control and protection circuitry to produce
four high current regulators, each with ±1.5% accuracy. The
A8600 includes control circuitry to implement three adjustable,
asynchronous buck regulators with integrated MOSFETs. Also,
the A8600 provides the control circuitry, gate drivers, and
current sensing to implement a synchronous buck controller
with external MOSFETs. In standby mode, the A8600 draws
less than 50 μA from VIN of 12 V while employing pulse
frequency modulation (PFM) to deliver 3.3 V/40 μA via the
always-on regulator, SW1. The always-on regulator operates
down to at least VIN of 3.6 V (VIN falling).
Continued on the next page…
Package: 48-pin LQFP (suffix JP)
Features of the A8600 include: an EN/SYNC input to either
turn the A8600 on/off or increase/decrease the base pulse
width modulation (PWM) frequency, four adjustable soft-start
times, and four external compensation pins. Output voltage
monitoring of switchers SW2, SW3, and SW4 is provided
by a single, open-drain POK output. In addition, the A8600
provides two high voltage, high-side switches with foldback
overcurrent protection. These two high-side switches actively
block reverse current. The A8600 also provides direct battery
(BU) and switched (accessory) battery (ACC) detectors and
a mute pulse output with an adjustable delay.
Continued on the next page…
Not to scale
Switcher 1
(SW1)
Switcher 2
(SW2)
Adjustable
Adjustable
Output Voltage
Output Voltage
1.0 AAVG / 2.5 APEAK 1.5 AAVG / 2.5 APEAK
Always-On
PWM / PFM
PWM
Asynchronous
Asynchronous
Buck
Buck
Regulator
Regulator
Charge
Pump
Enable and
Synchronization
(EN/SYNC)
425 kHz
180° Shift
Figure 1. A8600 major features
A8600-DS, Rev. 3
Switcher 3
(SW3)
Switcher 4
(SW4)
Adjustable
Output Voltage
2.0 AAVG / 2.5 APEAK
Adjustable
Output Voltage
PWM
Asynchronous
Buck
Regulator
PWM
Synchronous
Buck
Controller
Adjustable ILIM
High-Side Switch 1
(S1)
1.0 Ω Total
with
Foldback Limiting
BU and ACC
Detectors
High-Side Switch 2
(S2)
1.0 Ω Total
with
Foldback Limiting
Mute Pulse
with Delay
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
Features and Benefits (continued)
Description (continued)
• Power OK (POK) open-drain output with de-glitch
• BU and ACC voltage detectors and comparators
• Mute control with programmable delay
• Two internal high-voltage, high-side NMOS switches
(S1 and S2) with foldback short circuit protection
• High-side switches simultaneously controlled on/off
• High-side switches block reverse current
• Internal charge pump for high-side switch biasing
• Withstands surge voltages up to 40 V
• −40°C to 85°C ambient operating temperature range
• 150°C maximum junction temperature
• Thermally enhanced, surface mount package
Protection features of the A8600 include pulse-by-pulse current
limit, hiccup mode short circuit protection, asynchronous diode
protection, BOOT voltage protection, undervoltage lockout, overvoltage protection and thermal shutdown.
The A8600 is supplied in a low profile 48-pin LQFP package (suffix
JP ) with exposed power pad. It is lead (Pb) free, with 100% mattetin leadframe plating.
Selection Guide
Part Number
Operating Ambient
Temperature Range
TA, (°C)
Package
Packing*
Leadframe Plating
A8600EJPTR-T
–40 to 85
48-pin LQFP with
exposed
thermal pad
1500 pieces per
13-in. reel
100% Matte-Tin
*Contact Allegro™ for additional packing options.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
Table of Contents
Specifications
Absolute Maximum Ratings
Thermal Characteristics
Pin-out Diagram and List
Top Level Block Diagram
Typical Application Circuit
SW1/2/3 Detailed Block Diagram
SW4 Detailed Block Diagram
Electrical Characteristics Table
General Specifications
SW1 Regulator
SW2 Regulator
SW3 Regulator
SW4 Controller
S1, S2 Switches
BU and ACC Comparators
CTMR and MUTE
Timing Diagrams
SW1 Normal PWM Operation
SW1 Low IQ and Low IP Operation
SW2/3/4 PWM Operation
S1/2 Operation
BU, ACC, and Mute Operation
Functional Description
Overview
Reference Voltage
PWM Switching Frequency
Enable/Synchronization Input (EN/SYNC)
BIAS Input Pin, Ratings, and Connections
Transconductance Error Amplifier
Slope Compensation
Current Sense Amplifiers
Power MOSFETs
BOOT Regulators
4
4
4
5
6
6
7
8
9
9
10
12
14
16
18
18
19
20
20
21
22
23
24
25
25
25
25
25
26
26
26
26
26
27
SW1/2/3/4 Pulse Width Modulation (PWM) Mode
SW1 Low IP PWM Mode
SW1 Pulse Frequency Modulation (PFM)
and Low IQ Mode
Soft Start (Startup) and Inrush Current Control
Prebiased Startup
High-Side Switches (S1 and S2)
BU and ACC Detectors and MUTE Output
Power OK (POK) Output
Protection Features
Undervoltage Lockout (UVLO)
Thermal Shutdown (TSDL and TSDH)
Pulse-by-Pulse Overcurrent Protection (OCP)
Output Short Circuit (Hiccup Mode) Protection
BOOT Capacitor Protection
Asynchronous Diode Protection
Overvoltage Protection (OVP)
Application Information
27
27
27
28
29
29
31
31
32
32
32
32
33
33
34
34
36
Design and Component Selection
36
Setting the Output Voltage (VSWx, RFBAx, RFBBx) 36
Output Inductor (LSWx)
37
Output Capacitors (CSWx)
37
SW1 Low IQ PFM Ripple Calculation
38
Input Capacitors (CINx)
38
Asynchronous Diode (DSWx)
39
Bootstrap Capacitor (CBOOTx)
40
Soft Start and Hiccup Mode Timing (CSSx)
40
SW4 External MOSFET Selections
41
SW4 Current Sense Resistor
41
Compensation Components (RZx, CZx, CPx) 41
A Generalized Tuning Procedure
43
Power Dissipation and Thermal Calculations
44
PCB Component Placement and Routing
45
Pin Descriptions Table
47
Pin ESD Structures
49
Package Outline Drawing
50
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
Absolute Maximum Ratings1
Characteristic
Symbol
OUTx Pins
Notes
Continuous
BUI, VIN1/2/3, VINS, SSx, MUTE,
POK Pins
BIAS, CSP, CSN Pins
Rating
Unit
–0.3 to 40
V
–0.3 to 40
V
–0.3 to 7
V
HG4 Pin
–0.3 to VIN3 + 7
V
LG4 Pin
–0.3 to 8.5
V
BOOTx Pins
VINx = VIN1 , VIN2 , VIN3
–0.3 to VINx+7
V
LX1/2/3 Pin to GND
Continuous, VINx = VIN1 , VIN2 , VIN3; minimum
voltage is a function of temperature
–0.3 to VINx +1
V
t < 50 ns, VINx = VIN1 , VIN2 , VIN3
–1.0 to VINx +3
V
–1.0 to 37
V
–1.5 to 40
V
LX4 Pin to GND
VLX1 , VLX2 ,
VLX3
VLX4
Continuous, lower limit is a function of
temperature
t < 50 ns
VREG Pin to GND
ACCI Pin2
VVREG
IACCI
t < 100 ms
All Other Pins
–0.3 to 5.5
V
1
mA
–50
mA
–0.3 to 5.5
V
Operating Ambient Temperature
TA
–40 to 85
ºC
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
E temperature range
1Stresses
beyond those listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical
Characteristics table is not implied. Exposure to Absolute Maximum-rated conditions for extended periods may affect device reliability.
2Negative current is defined as coming out of the node or pin, positive current is defined as going into the node or pin.
Thermal Characteristics
Characteristic
Symbol
Package Thermal Resistance,
Junction to Ambient
RθJA
Package Thermal Resistance,
Junction to Pad
RθJP
Test Conditions*
On 4-layer PCB based on JEDEC standard
On 2-layer PCB with 3
in.2
of copper area on 2 sides
Value
Unit
23
ºC/W
44
ºC/W
2
ºC/W
*Additional thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
25 FB4
26 CSN
27 CSP
28 SS4
29 HG4
30 LX4
31 BOOT4
32 LG4
33 PGND
34 NC
Pin-Out Diagram
35 VIN2
36 VIN2
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
LX2 37
24
COMP4
LX2 38
23
POK
BOOT2 39
22
OUT2
SS2 40
21
VINS
FB2 41
20
OUT1
COMP2 42
19
ENS
18
COMP3
FB1 44
17
FB3
BIAS 45
16
SS3
SS1 46
15
BOOT3
BOOT1 47
14
LX3
LX1 48
13
LX3
6
7
EN/SYNC
ACCO
VIN3 12
5
CTMR
VIN3 11
4
VREG
BUI 10
3
GND
9
2
BUO
1
VIN1
MUTE
Function
8
PAD
COMP1 43
ACCI
A8600
Name
Number
Name
Number
ACCI
8
Input to the ACC comparator
FB4
25
ACCO
7
Output of the ACC comparator
GND
3
Ground
BIAS
45
Bias input, supplies internal circuitry when VSW1
is high enough
HG4
29
High side gate drive for buck regulator SW4
LG4
32
Low side gate drive for buck regulator SW4
BOOT1
47
Floating gate drive for buck regulator SW1
LX1
48
Switching node for buck regulator SW1
BOOT2
39
Floating gate drive for buck regulator SW2
LX2
37, 38
Switching node for buck regulator SW2
BOOT3
15
Floating gate drive for buck regulator SW3
LX3
13, 14
Switching node for buck regulator SW3
BOOT4
31
Floating gate drive for buck regulator SW4
LX4
30
Switching node for buck regulator SW4
MUTE
2
Open-drain, active low output of the Mute pulse
circuit
BUI
10
Input to the BU comparator
BUO
9
Output of the BU comparator
COMP1
43
Error amplifier compensation network for
regulator SW1
COMP2
42
Function
Feedback pin for buck regulator SW4
NC
34
Unused
OUT1
20
High-side switch S1 output
Error amplifier compensation network for
regulator SW2
OUT2
22
High-side switch S2 output
PAD
–
Exposed pad for enhanced thermal dissipation
PGND
33
Power ground
COMP3
18
Error amplifier compensation network for
regulator SW3
COMP4
24
Error amplifier compensation network for
regulator SW4
POK
23
Power OK open drain output
SS1
46
Soft start programming for regulator SW1
CSN
26
Current sense pin for buck regulator SW4
SS2
40
Soft start programming for regulator SW2
CSP
27
Current sense pin for buck regulator SW4
SS3
16
Soft start programming for regulator SW3
CTMR
5
Delay programming for the Mute pulse circuit
SS4
28
Soft start programming for regulator SW4
EN/SYNC
6
SWx enable and PFM control, and PWM
synchronization
VIN1
1
Input supply for buck regulator SW1
ENS
19
S1/S2 enable input
VIN2
35, 36
Input supply for buck regulator SW2
FB1
44
Feedback pin for buck regulator SW1
VIN3
11, 12
Input supply for buck regulator SW3 (and SW4)
FB2
41
Feedback pin for buck regulator SW2
VINS
21
S1/S2 high-side switch input
FB3
17
Feedback pin for buck regulator SW3
VREG
4
Internal voltage regulator bypass capacitor pin
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
Top Level Functional Block Diagram and Typical Application Circuit
VBAT
VBAT _FILT
C
A8600
2200 μF
BIAS
≈ 35 V
3.3 to 5.5 V
BOOT 1
VREG POR
A
CP1
RZ1
27 pF
18.7 kΩ
SS1
SS1
Bias
Switch
CSS1
0.68 μF
CZ1
COMP1
COMP1
4.7 nF
VIN1
LDO
CLK0
On
VREG
Off
Delay
2048n
BIAS >3.2V and
BIAS >LDO OUT
C
VIN1
Switcher 1
(SW1)
Adjustable
Always-On
PWM/PFM
Asynchronous
Buck Regulator
LSW1 10μH
VREGPORH
VREGPORL
CSS2
EN
TSDH
2.2 nF
VREG
POR
S
TSD
VIN3
COMP3
SS3
CLK0
Oscillator
180° Shift
with
Synchronization
2.2 nF
VREG
EN
TSDH
Delay
Switcher 3
(SW3)
Adjustable
PWM
Asynchronous
Buck Regulator
VBAT _FILT
VIN3
CBOOT3
112 mΩ
47 nF
LX3
CSN
CSP
POK
RZ4
24.9 kΩ
VREG POR
COMP4
SS4
SS4
CLK180
CSS4
EN
POK2
POK3
POK4
2.2 nF
Optional: ENS
to OUT1 for short
protection for
microcontroller
TSDH
Switcher 4
(SW4)
Adjustable
PWM
Synchronous
Buck Controller
50 kΩ
LX4
50 kΩ
3.70 V
VINS UVLO
+
Optional: To
protect VINS
for Field Decay test
2 μA
CCTMR
0.1 μF
LOAD 1
S1A
C
200 kΩ
215 mV
TSDL
RST
1.205 V
CHARGE
DONE
50 kΩ
60.4 kΩ
1%
1 μF
50 V
1 μF
50 V
LOAD 2
S1A
SET
CTMR
825 kΩ
1%
8 to 32 μs
De-glitch
1 MΩ
1%
B
TC7S H14F
C
BIAS
10 kΩ
9.1 kΩ
BU 3.3V
TC 7S H14F
C
≈ 6.2 V
To
microcontroller
1 μF
BUO
BUI
78.7 kΩ
1%
BUCLEAN
BU 3.3V
15 kΩ
ACCO
≈ 6.2 V
B
Audio
Amplifier
C
BIAS
475 kΩ
1%
5.0V
Optional: MUTE
to VIN1 short
protection for
amplifier
MUTE
Mute
Logic
ACCI
22.1 kΩ
1%
RFBA4
RFBB4
OUT2
1.0 Ω Total
A
60.4 kΩ
1%
200 kΩ
High-Side Switch 2
(S2) with
Foldback Limiting
TSDL
2 μA
VSW4
Adj (5.7 V)
2.5 AAVG
4.0 APEAK
C
VINS
3A
40V
11 kΩ
Schottky for SW4 1.8 kΩ
may be omitted for
very low current
system only
OUT1
1.0 Ω Total
Charge
Pump
–
CSW4
50 μF
FB4
TSDL
200 kΩ
DSW4
3A
40 V
D
LG4
High-Side Switch 1
(S1) with
Foldback Limiting
ENS
RS
15 m Ω
LSW4
10 μH
HG4
PGND
From
microcontroller
ACC
Switch
ShootThrough
Protection
POK4
GND
VBAT _FILT
CBOOT4
0.1 μF
COMP4
22 nF
CZ4
RFBA3
RFBB3
BOOT 4
C
CP4
VSW3
Adj (3.3 V)
2.0 AAVG
2.5 APEAK
14.7 kΩ
VIN3
27 pF
CSW3
50μF
FB3
200 kΩ
Optional: POK
to OUT2 short
protection for
microcontroller
LSW3 10 μH
DSW3
3A
40 V
4.7 kΩ
5.0 V
CIN3
LX3
10 Ω
POK3
15 n
EN/SYNC
To
microcontroller
RFBA2
RFBB2
BOOT 3
VIN S UVLO
CSS3
VSW2
Adj (8V)
1.0 A AVG
2.5 A PEAK
16.2 kΩ
1.8 kΩ
VREG POR
SS3
22 nF
CZ3
CSW2
50 μF
FB2
Q
R
COMP3
LSW2 15 μH
DSW2
3A
40 V
R
S Q
RZ3
VBAT _FILT
CIN2
LX2
10 Ω
TSDL
ENS
18.7 kΩ
RFBA1
RFBB1
LX2
Switcher 2
(SW2)
Adjustable
PWM
Asynchronous
Buck Regulator
POK2
TSDH
CP3
147 kΩ
47 kΩ
VIN2
VIN2
CBOOT2
47 nF
120 mΩ
COMP2
SS2
SS2
22 nF
27 pF
VSW1
Adj 3.3 V
1.0 AAVG
2.5 APEAK
BOOT2
CLK180
CZ2
CSW1
50μF
10pF
FB1
EN/PFM
VREG POR
COMP2
39.2 kΩ
DSW1
3A
40 V
C
1.205V REF
Band
Gap
RZ2
27 pF
CIN1
LX1
10 Ω
VREG
1.0 μF
CP2
CBOOT1
47 nF
150 mΩ
Optional: To
maintain VBOOT1
during very
low VBAT
To
microcontroller
1μF
4.7 kΩ
PAD
A Block active in Low IQ mode
B Current will not flow from ACCI to BUI or any VINx pin
C Current will not flow from ACCO, BUO, MUTE, BIAS, VREG, FB1, POK, or OUTx to any VINx pin
D SW4 lower FET must not cause VSW4 to decay during prebias startup
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
A8600
VIN1/2/3
VIN2/3
ILIM
CLK 0° (SW1/3 )
CLK 180° (SW2)
LOW IP PWM
(SW1 only)
OSCILLATOR
400mV
IF FB x<0. 4V then F /2
IF HICCUP x =1 then F /4
E LS E F
ON
TO FF,M IN
I FBx
+
SLOPE
COMP
G CSA
PWMxRST
S
Q
R
Q
Q
800mVREF
–
400mV
UP P E R FE T ON:
Q = 1 & TO FF,M IN = 0
UP P E R FE T OFF:
FB x OV or
1x OCx = 1 or
1x B OOTx UV or
S S INITx =1 or
HICCUP x = 1
RE S E T
DOMINA NT
PWM
COMPARATOR
ERROR
AMP
FBx
BOOTx
ISENSEx
CLAMP
TGx
LX2,3
LX1,2,3
LOWE R FE T ON :
B OOTx UV & TO FF,M IN = 1
LOWE R FE T OFF :
S S INITx = 1 or
HICCUP x = 1
COMPx M AX
BGx
+
COMPx
SSx
ISS SUx
LX1
ISS HICx
LX1
FA ULT
S W1 only
+
BOOTx
B OOTx – LX x
1K
–
7x B OOTx OV or
30x B OOTx UV
LXx
ISENSEx
COMPxM AX
2.3V
SSx > 2.3V
0.3V
BOOT
MONITOR &
COUNTERS
FBx > 0.3V
OCx
COMPARATOR
& COUNTER
S
Q
R
Q
HICCUPx
E NA B LE
COUNTE R
0 = 30 c ounts
1 = 118 c ounts
TSDH (SW2, SW3 only)
VREG POR
EN (SW2, SW3 only)
EN/PFM (SW1 only)
UVLOx
UVLOON↑
UVLOOF F↓
S W2 and S W3 only
LX2, LX3
RE S E T
DOMINA NT
LX2, 3 or
LG2
FA ULTS
5K
S
Q
R
Q
SSx < 0.2V
0.2V
FBx OV
860mV
FB1
ISENSE1
1x LX1 FAULT
1x BOOT 1 FAULT
UVLO1
EN/PFM
S
Q
R
Q
SSINITx
S W1 only
WA K E/ S LE E P
I PEAK
SW1
FIXED
OFF-TIME
PFM
CONTROL
E NA B LE
TG1
BOOT 1 ON
LOW IP PWM:
All PWM functions
ON & 50% ILIM
S W2 and S W3 only
DEGLITCH
POKx
FBx UV
740mV
S W2 & S W3 only
Figure 2. Detailed functional block diagram for SW1, SW2, and SW3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
A8600
VIN3
ILIM
OSCILLATOR
CLK180
ON
400mV
IF FB 4<0.4V then F / 2
IF HICCUP 4= 1 then F / 4
E LS E F
BOOT 4
TO FF,M IN
IFB4
+
SLOPE
COMP
CSP
GCSA
CSN
PWM4RST
S
Q
Q
R
Q
Q
800mVREF
–
400mV
UP P E R FE T ON:
Q = 1 & T O FF,M IN = 0
UP P E R FE T OFF:
FB 4 OV or
1x OC4 = 1 or
1x B OOT4 UV or
S S INIT4 =1 or
HICCUP4 = 1
RE S E T
DOMINA NT
PWM
COMPARATOR
ERROR
AMP
FB4
ISENSE4
CLAMP
COMP4M AX
HG4
GA TE
DRIV E R
NONOV E RLA P
LOWE R FE T ON:
Q = 1 & T O FF,M IN = 1 or
B OOT4 UV & T O FF,M IN = 1
LOWE R FE T OFF :
S S INIT4 = 1 or
HICCUP4 = 1
LX4
VIN 3
LG4
PGND
+
COMP4
SS4
ISS SU4
+
BOOT 4
B OOT4 – LX 4
BOOT
MONITOR &
COUNTERS
1K
–
7x B OOTx OV or
30x B OOTx UV
LX4
ISENSE4
COMP4M AX
2.3V
SS4 > 2.3V
0.3V
FB4 > 0.3V
OC4
COMPARATOR
& COUNTER
S
Q
R
Q
5K
HICCUP4
E NA B LE
COUNTE R
0 = 30 c ounts
1 = 118 c ounts
TSDH
VREG POR
EN
S
Q
R
Q
SSINIT 4
UVLO4
UVLOON↑
UVLOOF F↓
RE S E T
DOMINA NT
LX4 or
LG2
FA ULTS
LX4
ISS HIC4
S
Q
R
Q
SS4 < 0.2V
0.2V
FB4 OV
860mV
740mV
DEGLITCH
POK 4
FB4 UV
Figure 3. Detailed functional block diagram for SW4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
ELECTRICAL CHARACTERISTICS Valid at 5.5 V ≤ VINx ≤ 26 V, –40°C ≤ TA ≤ 125ºC, –40°C ≤ TJ ≤ 125ºC;
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VBIAS > 3.2 V, ISW1 = 0 mA
−
7.5
10
mA
ILO_IQ0
VIN1 = 12 V, VSW1 = 3.3 V, VEN/SYNC ≤ 0.4 V,
BUO and ACCO open, ISW1 = 40 μA, TA= 25ºC
−
−
50
μA
ILO_IQ1
VIN1 = 12 V, VSW1 = 5.0 V, VEN/SYNC ≤ 0.4 V,
BUO and ACCO open, ISW1 = 200 μA, TA = 25ºC
−
−
250
μA
ILO_IQ2
VIN1 = 12 V, VSW1 = 6.5 V, VEN/SYNC ≤ 0.4 V,
BUO and ACCO open, ISW1 = 1 mA, TA = 25ºC
−
−
750
μA
fOSC
360
425
490
kHz
Synchronization Input Frequency
fSYNC
325
−
525
kHz
Synchronization Input Duty Cycle
DSYNC
45
50
55
%
−
−
2.0
V
4.5 V < VBIAS < 5.5 V, VEN/SYNC rising
−
−
2.6
V
3.0 V < VBIAS < 3.6 V, VEN/SYNC falling
0.8
−
−
V
4.5 V < VBIAS < 5.5 V, VEN/SYNC falling
1.2
−
−
V
−
200
−
mV
mV
GENERAL SPECIFICATIONS
Input Supply Current
Input Supply Current1
IIN1
Input Supply Current, PFM1,3
(Using components shown in Typical
Application Circuit diagram and
table 3.)
Internal Oscillator Frequency
LX1/2/3/4 Switching Frequency
EN/SYNC Synchronization Timing
EN/SYNC Input
EN/SYNC Pin High Threshold
EN/SYNC Pin Low Threshold
EN/SYNC Hysteresis
EN/SYNC Input Resistance
VENIH
VENIL
VENHYS
3.0 V < VBIAS < 3.6 V, VEN/SYNC rising
3.0 V < VBIAS < 3.6 V, VENIH – VENIL
4.5 V < VBIAS < 5.5 V, VENIH – VENIL
RENIN
−
400
−
120
200
280
kΩ
tdOFF
Measured from EN/SYNC pulled low to
SW2/3/4, S1/2, and TSD turned off
−
15
−
PWM
cycles
tdLo_IQ
Measured from EN/SYNC pulled low or TSDH
going high to SW1 entering Low IQ mode
−
2048
−
PWM
cycles
VVREG
VBIAS = 0 V
EN/SYNC Turn-Off Delay
VREG Output and BIAS Input
VREG Output Voltage
2.95
3.05
3.175
V
VREG (REGOK rising)
VREGPORHI VVREG rising
2.86
2.93
2.98
V
VREG (BIAS switch Off and POR)
VREGPORLO VVREG falling
2.85
2.90
2.96
V
−3
10
20
mV
BIAS Switch Turn-On Threshold
VBIAS(TH)
VBIAS − VVREG
Bias Switch Voltage Drop
VBIASSW
VBIAS − VVREG
BIAS Input Voltage Range
VBIAS
−
45
70
mV
3.2
−
5.5
V
Power OK (POK)
POK Low Condition Output Voltage
POK
Leakage1
VPOKO(L)
IPOK = 3 mA
−
−
300
mV
IPOK(LKG)
VPOKO = 5.0 V
−1
−
1
μA
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
ELECTRICAL CHARACTERISTICS (continued) Valid at 5.5 V ≤ VINx ≤ 26 V, –40°C ≤ TA ≤ 125ºC, –40°C ≤ TJ ≤ 125ºC;
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
GENERAL SPECIFICATIONS (continued)
Thermal Protection
SW1/2/3/4 TSD Threshold3
TTSDH
SW1 to Low IQ mode after 2048 cycles, reset by
cycling EN/SYNC, or by a VREG POR
150
165
180
ºC
S1/2 Latched TSD Threshold3
TTSDL
Reset by cycling any of ENS, EN/SYNC, VINS,
or by a VREG POR
140
155
170
ºC
4.0
−
35
V
SW1 (ALWAYS-ON, LOW IQ, PWM/PFM REGULATOR)
Input Voltage
Input Voltage Range2
VIN1
UVLO Start
VUVLOON1
VIN1 rising
3.6
3.8
4.0
V
UVLO Stop
VUVLOOFF1 VIN1 falling
3.2
3.4
3.6
V
UVLO Hysteresis
VUVLOHYS1
−
400
−
mV
Voltage Regulation
Feedback Voltage Accuracy
Output Voltage Setting Range
VFB1
VIN1 ≥ 4.1 V, VFB1 = VCOMP1
788
800
812
mV
VSW1
VSW1(min) value is design target, see footnote 2
for typ and max voltages
3.3
5.0
6.5
V
VIN1 = 3.7 V, ISW1 = 50 mA
3.3
−
−
V
VIN1 = 6.0 V, ISW1 = 1 A
5.0
−
−
V
Output Dropout Voltage
VSW(PWM)1
Low IQ Peak Current Limit
I
PEAK(LO_IQ)
600
800
1000
mA
Low IQ DC Current Capability
IDC(LO_IQ)
500
−
−
mADC
Low IQ Constant OFF Time
tOFF(LO_IQ)
220
300
380
ns
Low IQ Maximum ON Time
tON(LO_IQ)
3.3
4
4.9
μs
−
−
50
mVPP
−
150
170
mΩ
−5
−
5
μA
−
−
10
Ω
Low IQ Mode Voltage Ripple3
VPP1(LO_IQ)
8 V < VIN1 < 12 V, configured as shown in the
Typical Application Circuit
Internal MOSFET2
High-Side MOSFET On-Resistance
High-Side MOSFET Leakage1
Low-Side MOSFET On-Resistance
RDS(on)HS1 TJ = 25ºC, IDS1 = 1.0 A
IHS(LKG)1
TJ < 85°C,VEN/SYNC ≤ 0.8 V, VLX1 = 0 V,
VIN1 = 16 V
RDS(on)LS1 TJ = 25ºC
BOOT Regulator
BOOT Voltage Enable Threshold
VBOOT(TH)1 VBOOT1 rising
1.85
2.10
2.30
V
BOOT Voltage Enable Hysteresis
VBOOT(HYS)1
−
375
−
mV
IFB1
–30
–
–8
nA
Error Amplifier
Feedback Input Bias Current1
Open Loop Voltage Gain
Transconductance
AVOL1
gm1
VCOMP1 = 1.2 V
52
58
65
dB
400 mV < VFB1
550
750
950
μA/V
0 V < VFB1 < 400 mV
275
375
475
μA/V
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
ELECTRICAL CHARACTERISTICS (continued) Valid at 5.5 V ≤ VINx ≤ 26 V, –40°C ≤ TA ≤ 125ºC, –40°C ≤ TJ ≤ 125ºC;
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
−
±75
−
μA
SW1 (ALWAYS-ON, LOW IQ, PWM/PFM REGULATOR) (continued)
Error Amplifier (continued)
Output Current
IEA1
VCOMP1 = 1.2 V
Maximum Output Voltage
VEAO(max)1
1.3
1.7
2.1
V
Minimum Output Voltage
VEAO(min)1
−
−
200
mV
−
1
−
kΩ
COMP1 Pull Down Resistance
RCOMP1
Fault condition
Pulse Width Modulation (PWM)
PWM Ramp Offset
VPWMOFFSET1 VCOMP1 set for 0% duty cycle
−
400
−
mV
tON(MIN)1
80
140
180
ns
Minimum Switch Off-Time
tOFF(MIN)1
40
95
135
ns
COMP1 to SW1 Current Gain
gmPOWER1
−
3.6
−
A/V
SE1
300
450
600
mA/μs
Minimum Controllable On-Time
Slope Compensation
Overcurrent Protection (OCP)
Pulse-by-Pulse Current Limit
ILIM1
tON1 = tON(MIN)1 , fSW = fOSC
3.9
4.4
4.9
A
tON1 = (1 / fOSC) – tOFF(MIN)1 , fSW = fOSC
3.0
3.5
4.0
A
VFB1 rising, PWM mode
840
860
880
mV
−
−10
−
mV
140
200
275
mV
Overvoltage Protection (OVP)
Output Overvoltage Threshold (SW1
Disable)
Overvoltage Hysteresis
VOVO1
VOVOHYS1
VFB1 falling, relative to VOVO1
Soft Start
SS1 Hiccup Reset Voltage
VSSRST1
SS1 Switching Frequency
fSS1
SS1 Startup (Source)
Current1
SS1 Hiccup (Sink) Current1
VSS1 falling due to RSSFLT1
0 V < VFB1 < 300 mV, VCOMP1 at maximum
−
fSW1/4
−
kHz
0 V < VFB1 < 300 mV
−
fSW1/2
−
kHz
300 mV < VFB1
−
fSW1
−
kHz
ISSSU1
Hiccup mode disabled (no fault condition)
−2.50
−2.00
−1.50
μA
ISSHIC1
Hiccup mode enabled
0.75
1.00
1.25
μA
SS1 Delay Time
tdSS1
CSS1 = 0.68 μF
−
136
−
ms
SS1 Ramp Time
tSSRAMP1
CSS1 = 0.68 μF
−
272
−
ms
SS1 Pull Down Resistance
RSSFLT1
Fault condition
−
5
−
kΩ
VSS1 rising
−
2.3
−
V
Hiccup Mode (PWM only, not in PFM)
Hiccup OCP Enable Threshold
Hiccup Operation OCP Count
Hiccup Operation BOOT Shorted
Count
Hiccup Operation BOOT Open Count
VHICEN1
VSS1 > 2.3 V, VFB1 < 0.3 V
−
30
−
PWM
cycles
VSS1 > 2.3 V, VFB1 > 0.3 V
−
118
−
PWM
cycles
tBOOTUV1
−
30
−
PWM
cycles
tBOOTOPEN1
−
7
−
PWM
cycles
tOCPLIM1
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
ELECTRICAL CHARACTERISTICS (continued) Valid at 5.5 V ≤ VINx ≤ 26 V, –40°C ≤ TA ≤ 125ºC, –40°C ≤ TJ ≤ 125ºC;
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
4.4
−
35
V
SW2 (ASYNCHRONOUS BUCK REGULATOR)
Input Voltage
Input Voltage Range2
VIN2
UVLO Start
VUVLOON2
VIN2 rising
4.1
4.25
4.4
V
UVLO Stop
VUVLOOFF2 VIN2 falling
3.6
3.75
3.9
V
UVLO Hysteresis
VUVLOHYS2
−
500
−
mV
Voltage Regulation
Feedback Voltage Accuracy
Output Voltage Setting Range
Output Dropout Voltage3
Internal
VFB2
VIN2 ≥ 4.4 V, VFB2 = VCOMP2
788
800
812
mV
VSW2
VSW2(typ) value is design target, see footnote 2
for min and max voltages
1.2
8.0
9.2
V
VSW(PWM)2 VIN2 = 6.0 V, ISW2 = 1 A
5.0
−
−
V
RDS(on)HS2 TJ = 25ºC, IDS2 = 1.5 A
−
120
140
mΩ
−5
−
5
μA
−
−
10
Ω
1.85
2.10
2.30
V
−
375
−
mV
MOSFET2
High-Side MOSFET On-Resistance
High-Side MOSFET Leakage1
Low-Side MOSFET On-Resistance
IHS(LKG)2
TJ < 85°C,VEN/SYNC ≤ 0.8 V, VLX2 = 0 V,
VIN2 = 16 V
RDS(on)LS2 TJ = 25ºC
BOOT Regulator
BOOT Voltage Enable Threshold
VBOOT(TH)2 VBOOT2 rising
BOOT Voltage Enable Hysteresis
VBOOT(HYS)2
Error Amplifier
Feedback Input Bias Current1
Open Loop Voltage Gain
Transconductance
Output Current
IFB2
AVOL2
gm2
IEA2
Maximum Output Voltage
VEAO(max)2
Minimum Output Voltage
VEAO(min)2
COMP2 Pull Down Resistance
–100
–
–8
nA
VCOMP2 = 1.2 V
52
60
65
dB
400 mV < VFB2
550
750
950
μA/V
0 V < VFB2 < 400 mV
275
375
475
μA/V
VCOMP2 = 1.2 V
−
±75
−
μA
1.3
1.7
2.1
V
−
−
200
mV
Fault condition
−
1
−
kΩ
VPWMOFFSET2 VCOMP2 set for 0% duty cycle
−
400
−
mV
RCOMP2
Pulse Width Modulation (PWM)
PWM Ramp Offset
Minimum Controllable On-Time
tON(MIN)2
80
140
180
ns
Minimum Switch Off-Time
tOFF(MIN)2
40
95
135
ns
COMP2 to SW2 Current Gain
gmPOWER2
−
3.6
−
A/V
SE2
300
450
600
mA/μs
Slope Compensation
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
ELECTRICAL CHARACTERISTICS (continued) Valid at 5.5 V ≤ VIN ≤ 26 V, –40°C ≤ TA ≤ 125ºC, –40°C ≤ TJ ≤ 125ºC;
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
tON2 = tON(MIN)2 , fSW = fOSC
3.9
4.4
4.9
A
tON2 = (1 / fOSC) – tOFF(MIN)2 , fSW = fOSC
3.0
3.5
4.0
A
840
860
880
mV
−
−10
−
mV
SW2 (ASYNCHRONOUS BUCK REGULATOR) (continued)
Overcurrent Protection (OCP)
Pulse-by-Pulse Current Limit
ILIM2
Power OK (POK) Thresholds for Overvoltage (OV) and Undervoltage (UV)
POK Threshold for Overvoltage
POK Hysteresis for Overvoltage
POK Threshold for Undervoltage
POK Hysteresis for Undervoltage
VPOKOV2
VFB2 rising
VPOKOVHYS2 VFB2 falling, relative to VPOKOV2
VPOKUV2
720
740
760
mV
VPOKUVHYS2 VFB2 rising, relative to VPOKUV2
VFB2 falling
−
10
−
mV
VPOKDELAY2 Response to a step input
−
6
−
μs
140
200
275
mV
0 V < VFB2 < 300 mV, VCOMP2 at maximum
−
fSW2/4
−
kHz
0 V < VFB2 < 300 mV
−
fSW2/2
−
kHz
−
fSW2
−
kHz
−30
–20
−10
μA
Power OK (POK) Filtering
POK Delay Time
Soft Start
SS2 Hiccup Reset Voltage
VSSRST2
SS2 Switching Frequency
fSS2
VSS2 falling due to RSSFLT2
300 mV < VFB2
SS2 Startup (Source) Current1
SS2 Hiccup (Sink)
Current1
ISSSU2
Hiccup mode disabled (no fault condition)
ISSHIC2
Hiccup mode enabled
5
10
20
μA
SS2 Delay Time
tdSS2
CSS2 = 22 nF
−
440
−
μs
SS2 Ramp Time
tSSRAMP2
CSS2 = 22 nF
−
880
−
μs
SS2 Pull Down Resistance
RSSFLT2
Fault condition
SS2 Startup Current Ratio
ISSSUTRK2
−
5
−
kΩ
−15
−
+15
%
VSS2 rising
−
2.3
−
V
VSS2 > 2.3 V, VFB2 < 0.3 V
−
30
−
PWM
cycles
VSS2 > 2.3 V, VFB2 > 0.3 V
−
118
−
PWM
cycles
tBOOTUV2
−
30
−
PWM
cycles
tBOOTOPEN2
−
7
−
PWM
cycles
Relative to ISSSU3 or ISSSU4
Hiccup Mode
Hiccup OCP Enable Threshold
Hiccup Operation OCP Count
Hiccup Operation BOOT Shorted
Count
Hiccup Operation BOOT Open Count
VHICEN2
tOCPLIM2
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
ELECTRICAL CHARACTERISTICS (continued) Valid at 5.5 V ≤ VINx ≤ 26 V, –40°C ≤ TA ≤ 125ºC, –40°C ≤ TJ ≤ 125ºC;
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
4.4
−
35
V
SW3 (ASYNCHRONOUS BUCK REGULATOR)
Input Voltage Specifications
Input Voltage Range2
VIN3
UVLO Start
VUVLOON3
VIN3 rising
4.1
4.25
4.4
V
UVLO Stop
VUVLOOFF3 VIN3 falling
3.6
3.75
3.9
V
UVLO Hysteresis
VUVLOHYS3
−
500
−
mV
Voltage Regulation
Feedback Voltage Accuracy
Output Voltage Setting Range
Output Dropout Voltage3
Internal MOSFET
VFB3
VIN3 ≥ 4.4 V, VFB3 = VCOMP3
788
800
812
mV
VSW3
VSW3(typ) value is design target, see footnote 2
for min and max voltages
1.2
3.3
9.2
V
5.0
−
−
V
−
112
130
mΩ
−5
−
5
μA
−
−
10
Ω
1.85
2.10
2.30
V
−
375
−
mV
VSW(PWM)3 Configured as in Ty, VIN3 = 6.0 V, ISW3 = 1 A
Parameters2
High-Side MOSFET On-Resistance
High-Side MOSFET Leakage1
Low-Side MOSFET On-Resistance
RDS(on)HS3 TJ = 25ºC, IDS3 = 2.0 A
IHS(LKG)3
TJ < 85°C,VEN/SYNC ≤ 0.8 V, VLX3 = 0 V,
VIN3 = 16 V
RDS(on)LS3 TJ = 25ºC
BOOT Regulator
BOOT Voltage Enable Threshold
VBOOT(TH)3 VBOOT3 rising
BOOT Voltage Enable Hysteresis
VBOOT(HYS)3
Error Amplifier
Feedback Input Bias Current1
Open Loop Voltage Gain
Transconductance
Output Current
IFB3
AVOL3
gm3
IEA3
Maximum Output Voltage
VEAO(max)3
Minimum Output Voltage
VEAO(min)3
COMP3 Pull Down Resistance
–100
–
–8
nA
VCOMP3 = 1.2 V
52
60
65
dB
400 mV < VFB3
550
750
950
μA/V
0 V < VFB3 < 400 mV
275
375
475
μA/V
VCOMP3 = 1.2 V
−
±75
−
μA
1.3
1.7
2.1
V
−
−
200
mV
Fault condition
−
1
−
kΩ
VPWMOFFSET3 VCOMP3 set for 0% duty cycle
−
400
−
mV
RCOMP3
Pulse Width Modulation (PWM)
PWM Ramp Offset
Minimum Controllable On-Time
tON(MIN)3
80
140
180
ns
Minimum Switch Off-Time
tOFF(MIN)3
40
95
135
ns
COMP3 to SW3 Current Gain
gmPOWER3
−
3.6
−
A/V
SE3
300
450
600
mA/μs
Slope Compensation
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
ELECTRICAL CHARACTERISTICS (continued) Valid at 5.5 V ≤ VINx ≤ 26 V, –40°C ≤ TA ≤ 125ºC, –40°C ≤ TJ ≤ 125ºC;
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
tON3 = tON(MIN)3 , fSW = fOSC
3.9
4.4
4.9
A
tON3 = (1 / fOSC) – tOFF(MIN)3 , fSW = fOSC
3.0
3.5
4.0
A
840
860
880
mV
−
−10
−
mV
SW3 (ASYNCHRONOUS BUCK REGULATOR) (continued)
Overcurrent Protection (OCP)
Pulse-by-Pulse Current Limit
ILIM3
Power OK (POK) Thresholds for Overvoltage (OV) and Undervoltage (UV)
POK Threshold for Overvoltage
POK Hysteresis for Overvoltage
POK Threshold for Undervoltage
POK Hysteresis for Undervoltage
VPOKOV3
VFB3 rising
VPOKOVHYS3 VFB3 falling, relative to VPOKOV3
VPOKUV3
720
740
760
mV
VPOKUVHYS3 VFB3 rising, relative to VPOKUV3
VFB3 falling
−
10
−
mV
VPOKDELAY3 Response to a step input
−
6
−
μs
140
200
275
mV
0 V < VFB3 < 300 mV, VCOMP3 at maximum
−
fSW3/4
−
kHz
0 V < VFB3 < 300 mV
−
fSW3/2
−
kHz
−
fSW3
−
kHz
−30
–20
−10
μA
Power OK (POK) Filtering
POK Delay Time
Soft Start
SS3 Hiccup Reset Voltage
VSSRST3
SS3 Switching Frequency
fSS3
VSS3 falling due to RSSFLT3
300 mV < VFB3
SS3 Startup (Source) Current1
SS3 Hiccup (Sink)
Current1
ISSSU3
Hiccup mode disabled (no fault condition)
ISSHIC3
Hiccup mode enabled
5
10
20
μA
SS3 Delay Time
tdSS3
CSS3 = 22 nF
−
440
−
μs
SS3 Ramp Time
tSSRAMP3
CSS3 = 22 nF
−
880
−
μs
SS3 Pull Down Resistance
RSSFLT3
Fault condition
SS3 Startup Current Ratio
ISSSUTRK3
−
5
−
kΩ
−15
−
+15
%
VSS3 rising
−
2.3
−
V
VSS3 > 2.3 V, VFB3 < 0.3 V
−
30
−
PWM
cycles
VSS3 > 2.3 V, VFB3 > 0.3 V
−
118
−
PWM
cycles
tBOOTUV3
−
30
−
PWM
cycles
tBOOTOPEN3
−
7
−
PWM
cycles
Relative to ISSSU2 or ISSSU4
Hiccup Mode
Hiccup OCP Enable Threshold
Hiccup Operation OCP Count
Hiccup Operation BOOT Shorted
Count
Hiccup Operation BOOT Open Count
VHICEN3
tOCPLIM3
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
15
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
ELECTRICAL CHARACTERISTICS (continued) Valid at 5.5 V ≤ VINx ≤ 26 V, –40°C ≤ TA ≤ 125ºC, –40°C ≤ TJ ≤ 125ºC;
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
4.4
−
35
V
SW4 (SYNCHRONOUS BUCK CONTROLLER WITH GATE DRIVERS)
Input Voltage Specifications
Input Voltage Range2
VIN3
UVLO Start
VUVLOON4
VIN3 rising
4.1
4.25
4.4
V
UVLO Stop
VUVLOOFF4 VIN3 falling
3.6
3.75
3.9
V
UVLO Hysteresis
VUVLOHYS4
−
500
−
mV
Voltage Regulation
Feedback Voltage Accuracy
Output Voltage Setting Range
Output Dropout Voltage3
VFB4
VIN3 ≥ 4.4 V, VFB4 = VCOMP4
788
800
812
mV
VSW4
VSW4(typ) value is design target, see footnote 2
for min and max voltages
1.2
5.7
6.5
V
Configured as in Typical Application Circuit,
VIN4 = 6.0 V, ISW4 = 1 A
5.0
−
−
V
4.0
6.0
6.7
V
VSW(PWM)4
External MOSFET Gate Drivers
HG4 High Output Voltage
VHG4ON
Measured as VHG4 – VIN3
HG4 Low Output Voltage
VHG4OFF
Measured as VHG4 – VLX4 , IHG4 = 100 mA
−
0.20
0.40
V
HG4 Sink Current1
IHG4ON
VHG4 = VIN3 − 2 V
−
1000
−
mA
HG4 Source Current1
IHG4OFF
VHG4 = VIN3 − 2 V
−
−150
−
mA
LG4 High Output Voltage
VLG4ON
VIN3 ≥ 5.5 V
4.0
6.0
7.2
V
LG4 Low Output Voltage
VLG4OFF
ILG4 = 100 mA
−
0.25
0.50
V
LG4 Source Current1
ILG4ON
−
−500
−
mA
LG4 Sink Current1
ILG4OFF
−
600
−
mA
BOOT Regulator
BOOT Voltage Enable Threshold
VBOOT(TH)4 VBOOT4 rising
2.25
2.60
2.90
V
BOOT Voltage Enable Hysteresis
VBOOT(HYS)4
−
375
−
mV
IFB4
–100
–
–8
nA
Error Amplifier
Feedback Input Bias Current1
Open Loop Voltage Gain
AVOL4
Transconductance
gm4
Output Current
IEA4
VCOMP4 = 1.2 V
52
60
65
dB
400 mV < VFB4
550
750
950
μA/V
0 V < VFB4 < 400 mV
275
375
475
μA/V
−
±75
−
μA
VCOMP4 = 1.2 V
Maximum Output Voltage
VEAO(max)4
1.3
1.7
2.1
V
Minimum Output Voltage
VEAO(min)4
−
−
200
mV
−
1
−
KΩ
COMP4 Pull Down Resistance
RCOMP4
Fault condition
Continued on the next page…
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115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
16
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
ELECTRICAL CHARACTERISTICS (continued) Valid at 5.5 V ≤ VINx ≤ 26 V, –40°C ≤ TA ≤ 125ºC, –40°C ≤ TJ ≤ 125ºC;
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
−
400
−
mV
SW4 (SYNCHRONOUS BUCK CONTROLLER WITH GATE DRIVERS) (continued)
Pulse Width Modulation (PWM)
PWM Ramp Offset
VPWMOFFSET4 VCOMP4 set for 0% duty cycle
COMP4 Cycle Skip Level
VCOMPSKIP4 VSS4 < 2.3 V
−
200
−
mV
tON(MIN)4
40
100
150
ns
Minimum Switch Off-Time
tOFF(MIN)4
80
120
160
ns
COMP4 to SW4 Current Gain
gmPOWER4
−
63
−
(A•mΩ)/V
SE4
4.5
6.8
9.0
mV/μs
tON4 = tON(MIN)4
62
75
88
mV
tON4 = (1 / fOSC ) – tOFF(MIN)4, fSW = fOSC
48
60
72
mV
840
860
880
mV
Minimum Controllable On-Time
Slope Compensation
Overcurrent Protection (OCP)
Pulse-by-Pulse Current Limit
ILIM4
Power OK (POK) Thresholds for Overvoltage (OV) and Undervoltage (UV)
POK Threshold for Overvoltage
POK Hysteresis for Overvoltage
POK Threshold for Undervoltage
POK Hysteresis for Undervoltage
VPOKOV4
VFB4 rising
VPOKOVHYS4 VFB4 falling, relative to VPOKOV4
−
−10
−
mV
720
740
760
mV
VPOKUVHYS4 VFB4 rising, relative to VPOKUV4
−
10
−
mV
VPOKDELAY4 Response to a step input
−
6
−
μs
140
200
275
mV
−
fSW4/4
−
kHz
0 V < VFB4 < 300 mV
−
fSW4/2
−
kHz
300 mV < VFB4
−
fSW4
−
kHz
−30
–20
−10
μA
VPOKUV4
VFB4 falling
Power OK (POK) Filtering
POK Delay / De-glitch
Soft Start
SS4 Hiccup Reset Voltage
VSSRST4
VSS4 falling due to RSSFLT4
0 V < VFB4 < 300 mV, VCOMP4 at maximum
SS4 Switching Frequency
SS4 Startup (Source) Current1
Current1
fSS4
ISSSU4
Hiccup mode disabled (no fault condition)
ISSHIC4
Hiccup mode enabled
5
10
20
μA
SS4 Delay Time
tdSS4
CSS4 = 22 nF
−
440
−
μs
SS4 Ramp Time
tSSRAMP4
CSS4 = 22 nF
−
880
−
μs
SS4 Pull Down Resistance
RSSFLT4
Fault condition
−
5
−
KΩ
SS4 Startup Current Ratio
ISSSUTRK4
−15
−
+15
%
SS4 Hiccup (Sink)
Relative to ISSSU2 or ISSSU3
Continued on the next page…
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
17
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
ELECTRICAL CHARACTERISTICS (continued) Valid at 5.5 V ≤ VINx ≤ 26 V, –40°C ≤ TA ≤ 125ºC, –40°C ≤ TJ ≤ 125ºC;
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
−
2.3
−
V
Hiccup Mode
Hiccup OCP Enable Threshold
Hiccup Operation OCP Count
Hiccup Operation BOOT Shorted
Count
Hiccup Operation BOOT Open Count
VHICEN4
VSS4 rising
VSS4 > 2.3 V, VFB4 < 0.3 V
−
30
−
PWM
cycles
VSS4 > 2.3 V, VFB4 > 0.3 V
−
118
−
PWM
cycles
tBOOTUV4
−
30
−
PWM
cycles
tBOOTOPEN4
−
7
−
PWM
cycles
VINS
4.5
−
35
V
tOCPLIM4
HIGH-SIDE SWITCHES (S1, S2)
Input Voltage Range2
UVLO Start
VUVLOONS
VINS rising
4.0
4.2
4.4
V
UVLO Stop
VUVLOOFFS VINS falling
3.5
3.7
3.9
V
UVLO Hysteresis
VUVLOHYSS
−
500
−
mV
Overvoltage Threshold (Rising)
VOVRISES
VINS rising
17.2
18.3
19.4
V
Overvoltage Threshold (Falling)
VOVFALLS
VINS falling
16.9
18.0
19.0
V
MOSFET On-Resistance
RDS(on)S
IS = 250 mA, TJ = 25ºC
−
1.00
1.15
Ω
VINS ≥ 5.5 V, IS = −250 mA, TJ = 25ºC
−
250
290
mV
Voltage Drop
Current Limit1,2
Foldback
Current1
ΔVS
−
100
115
mV
IPEAKS
Not continuous
−570
−450
−270
mA
IFLDBKS
VOUTx = 0 V, VINS = 15 V
−150
−100
−55
mA
−1
−
1
μA
Leakage Current1
ILKGS
Pull Down Resistance
RFLTS
VINS ≥ 4.5 V, IS = −100 mA, TJ = 25ºC
−
200
−
kΩ
Turn-On Delay
tdS
VENS rise to 10% of ΔVOUTx
10
60
200
μs
Output Rise Time
trS
237 Ω / 1 μF load, 10% to 90% of ΔVOUTx
10
60
200
μs
ENS High Threshold
VENSH
−
−
2.0
V
ENS Low Threshold
VENSL
0.8
−
−
V
ENS Hysteresis
ENS Input Resistance
VENSHYS
−
100
−
mV
RINENS
120
200
280
kΩ
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
18
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
ELECTRICAL CHARACTERISTICS (continued) Valid at 5.5 V ≤ VINx ≤ 26 V, –40°C ≤ TA ≤ 125ºC, –40°C ≤ TJ ≤ 125ºC;
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
BU AND ACC COMPARATORS
BUI and ACCI Detect Threshold
BUI and ACCI Input Bias1
BUO Delay
ACCO Delay
BUO and ACCO Output Voltage
BUO and ACCO Forced Low
1.181
1.205
1.229
V
IBUI, IACCI
VDET
VBUI or VACCI ≤ 5.0 V
30
65
100
nA
tdBUO
20 mV input overdrive
−
1.5
5
μs
tdACCO
20 mV input overdrive
−
1.5
5
μs
VBUOH,
VACCOH
IBUO = IACCO = −3 mA
VBIAS –
300 mV
−
VBIAS
V
VBUOL,
VACCOL
IBUO = IACCO = 3 mA
−
−
300
mV
VBUOLF,
VACCOLF
IBUO = IACCO = 3 mA , 2 V < VBIAS < 3 V,
VIN1 < 5.5 V
−
−
300
mV
CTMR and MUTE
CTMR Charge Current1
−2.50
−2.00
−1.50
μA
CTMR Discharge Current1
ICTMR(DIS)
MUTE = low, VCTMR falling
1.50
2.00
2.50
μA
CTMR Upper Threshold
VCTMRVH
VCTMR rising
1.181
1.205
1.229
V
CTMR Lower Threshold
VCTMRVL
VCTMR falling
185
215
245
mV
RCTMR
MUTE = high
−
50
−
kΩ
MUTE Low Output Voltage
VMUTEOL
IMUTE = 3 mA
−
−
300
mV
MUTE Leakage Current1
IMUTELKG
VMUTE = 5.0 V
−1
−
1
μA
725
1000
1275
ms
8
16
32
μs
−
8.5
−
V
CTMR Pull Down Resistance
ICTMR(CHRG) MUTE = low, VCTMR rising
MUTE Rising Delay
tdrMUTE
CCTMR = 0.10 μF
MUTE Falling Delay (De-glitch)
tdfMUTE
From BUO set low to MUTE low
MUTE Self-Protect Shutoff
VMUTE(OFF)
1Negative
current is defined as coming out of the node or pin, positive current is defined as going into the node or pin.
2Thermally limited depending on input voltage, duty cycle, regulator load currents, PCB layout, and airflow.
3Determined by design and characterization, not production tested.
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19
COMP1
SS1
VOUT1
LX1
VIN1
DIODE
FAULT
BOOT
FAULT
OC
FAULT
HICCUP
OC
HIC_EN
TSDL
TSDH
EN/SYNC
ACCo
MODE OFF
2
F
/
SS
F
PWM
HICCUP
F
/
4
VFB<0 .3V : x30
VFB>0.3V: x120
OC
2
F
/
S
S
Vout1 shorted to GND
F/4
OC
VFB<0.3V: x30
VFB>0.3V : x120
HICCUP
2
F
/
SS
F
PWM
HICCUP
x7 OPEN
x30 UV
BOOT
FAULTS
TO
2.3V
FROM
2.3V
x7 OPEN
x30 UV
HICC
UP
BOOT
FAULTS
S
S
2
F
/
SS
F
PWM
x1
DIODE
FAULT
HICCUP
TO
2.3V
2
F
/
FROM
2.3 V
x1
HI
C
DIODE
FAULT
SS
2
F
/
SS
PWM
F
2048
TSDL /
LOW IQ due to TSDH
TSDH
(internal OSC is operational)
15
F
EN/SYNC↓ for 15 cycles or VREG
POR clears the TSDH latch
PWM
LOW IQ
2048
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
Figure 4. SW1 PWM Timing Diagram with EN/SYNC pin high
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20
COMP1
SS1
VOUT1
LX1
VIN1
DIODE
FAULT
BOOT
FAULT
OC
FAULT
HICCUP
OC
HIC_EN
TSDL
TSDH
EN/SYNC
ACCo
MODE OFF
2
F
/
SS
F
LOW-IP PWM
SS>2.3V •
FB>0.74V
2048 LO_IQ
O
C
HICCUP
2
F
/
4
F
/
VFB<0.3V: x30
VFB>0.3 V: x120
Vout1 shorted to GND
S
S
2
F
/
SS
F/4
OC
HICCUP
VFB<0.3V: x30
VFB>0.3 V: x120
LOW-IP PWM
2
F
/
SS
F
LO_IQ
SS>2.3V •
FB>0.74V
2048
x1
x7 OPEN
x30 UV
BOOT
FAULTS
HICCUP
HICC
UP
TO
2.3V
2
F
/
FROM
2.3V
x7 OPEN
x30 UV
HICC
UP
TO
2.3V
2
F
/
FROM
2.3V
x7 OPEN
x30 UV
BOOT
FAULTS
S
S
LOW-IP PWM
BOOT
FAULTS
S
S
2
F
/
SS
SS>2.3V •
FB>0.74V
F
2048
LO_IQ
x1
DIODE
FAULT
HICCUP
HI
C
2
F
/
x1
TO FROM TO FROM
2.3V 2.3V 2.3V 2 .3V
2
F
/
x1
HI
C
DIODE
FAULT
SS
LOW-IP PWM
DIODE
FAULT
SS
2
F
/
SS
SS>2.3V •
FB>0.74V
F
2048
F
PWM
EN/SYNC↑ or
ACCo↑
LO_IQ
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
Figure 5. SW1 Low IQ PWM and Low IP PFM timing, with EN/SYNC low and ACCI low
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21
OFF
COMP2
SS2
VOUT2
LX2
VIN2
DIODE
FAULT
BOOT
FAULT
OC
FAULT
HICCUP
OC
HIC_EN
TSDL
TSDH
EN/SYNC
ACCo
MODE
2
F
/
SS
F
PWM
HICCUP
F
/
4
VFB<0.3 V: x30
VFB >0.3V: x120
OC
2
F
/
S
S
F/4
OC
VFB <0.3V: x30
VFB>0 .3V : x120
HICCUP
2
F
/
SS
F
PWM
HICCUP
x7 OPEN
x30 UV
BOOT
FAULTS
TO
2.3 V
FROM
2 .3V
x7 OPEN
x30 UV
HICC
UP
BOOT
FAULTS
S
S
2
F
/
SS
F
PWM
x1
RESET
15
DIODE
FAULT
2
F
/
SS
F
PWM
TSDL
15
S
S
EN RESET
TSDH
OFF
TSDH
15
2
F
/
OFF
SS
EN/SYNC↓ for 15 cycles or VREG
POR clears the TSDH latch
F
PWM
15
OFF
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
Figure 6. SW2, SW3, and SW4 PWM timing
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
22
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
RESET Sx
RESET Sx
ENs
> 450mATYP
IOUT,Sx
~VINs
VOUT, Sx
Sx_FOLDBACK
165°C
155°C
TJ
TSDH
TSDL
S1/2 LATCH_OFF
PWM2/3/4_LATCH _OFF
LX2, 3, 4
RESET TSDH
EN/SYNC
A
B
C
Figure 7. S1 and S2 Timing
A. The load on one of the high-side switches increases until it
enters foldback. The A8600 junction temperature increases.
When the junction temperature exceeds 155ºC (TSDL) both highside switches (S1, S2) are latched off. This state is maintained
until the high-side switches are reset via the ENS.
exceeds 165ºC (TSDH) switching regulators SW2, SW3, and
SW4 are also latched off, and SW1 enters Low IQ PFM mode.
After TSDH, both high side switches (S1, S2) and the switching
regulators SW2, SW3, and SW4 remain latched off until they are
reset via EN/SYNC.
B. The loads on the A8600 increase and the junction temperature
begins to increase. When the junction temperature exceeds
155ºC (TSDL) both high-side switches (S1, S2) are latched off.
In this case, even though the switches are shut off, the junction
temperature continues to increase. When the junction temperature
C. The load on one of the high-side switches increases until it
enters foldback. The junction temperature increases but does not
exceed 155ºC (TSDL). When the load on the high-side switch
decreases, the switch exits foldback and the output voltage
recovers.
Allegro MicroSystems, LLC
115 Northeast Cutoff
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23
750mV
TSDL
ACCo
ACCi
MUTE
215 mV
CTMR
1.205 V
BUo
BUi
1.205V
VREG
LDOOUT
VBIAS
REG_OK
(Internal signal )
1.205V
RETRIGGER
tD1
tD2
V BIAS > 3.2 and
VBIAS > LDO OUT
tMUTE
16μsTYP
tD1
tD, MUTE
16μsTYP
RETRIGGER
tD1
tD2
tMUTE
t D2
tD2
2V
tD1
tD,MUTE
BUO, ACCO,
MUTE undefined
BUO, ACCO, MUTE
latched LOW
BU O, ACCO,
MUTE valid
3V
VIN1
REMOVED
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
Figure 8. BUx, ACCx and MUTE/CTMR timing
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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24
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
Functional Description
Overview
The A8600 is a highly sophisticated, multi-function IC that
incorporates all the control and protection circuitry necessary to
provide the power supply requirements of next generation car
audio and infotainment systems.
The A8600 features three adjustable asynchronous peak current mode buck regulators with internal MOSFETS. These three
regulators, SW1, SW2, and SW3, can continuously supply 1.0 A,
2.0 A and 2.5 A respectively. A synchronous controller, SW4, was
designed to deliver up to 4 A but can be configured for as much
as 8 A by setting the sense resistor accordingly.
SW1 is an always-on buck regulator that provides Low Quiescent
Input Current (Low IQ) mode. When the EN/SYNC and ACCI
pins are held low, SW1 employs pulse frequency modulation
(PFM) to draw only 10s of microamperes from the input supply
while delivering 3.3V, 5.0V, or 6.5V at no load.
SW4 is an adjustable, synchronous, peak current mode buck
controller with internal MOSFET gate drivers and externally
adjustable current limit.
In addition, the A8600 incorporates two 1 Ω high-side switches,
S1 and S2) which typically provide 250 mA (DC) and 450 mA
(peak), with foldback type overcurrent protection. For thermal
reasons, S1 and S2 are allowed to be on only for input voltages
up to approximately 18.3 V.
The A8600 also offers two detectors (that is, comparators) for
sensing both battery voltage (BU circuit) and battery voltage
remotely applied through a key type ignition switch (ACC circuit). There is also a Mute output with a programmable delay set
by a capacitor at the CTMR pin.
Reference Voltage
The A8600 incorporates an internal reference that allows output
voltages as low as 0.8 V. The accuracy of the internal reference is
±1.5% across the operating temperature range. The output voltage of each regulator is adjusted by connecting a resistor divider
between the respective VSWx nodes and FBx pins of the A8600,
as shown in the Typical Application diagram.
PWM Switching Frequency
The PWM switching frequency of the A8600 is fixed at 425 kHz
and has an accuracy of ±15% across the operating temperature
range. The four buck switchers are interleaved at 180° intervals:
SW1 and SW3 turn on at 0°, and SW2 and SW4 turn on at 180°.
During startup, the PWM switching frequency is reduced to 50%
of the nominal frequency until FBx exceeds 300 mV. This is
done to improve output regulation when VSWx is starting to ramp
upward and the PWM control loop is operating at the minimum
controllable on-time and requires very low duty cycles.
If the voltage at the FBx pin is less than 300 mV, and the COMPx
voltage reaches its maximum level, the PWM switching frequency is reduced to 25% of the nominal frequency. This is done
because a very low FBx voltage combined with a maximum
COMPx voltage indicates the regulator output is shorted to
ground. The extra-low switching frequency allows additional off
(decay) time between LXx pulses so the inductor current does
not climb to a value that may damage the A8600 or the output
inductor.
Enable/Synchronization Input (EN/SYNC)
The Enable/Synchronization input (EN/SYNC pin) provides two
major functions. First, the EN/SYNC pin is a control input that
sets the operating mode of the A8600. When EN/SYNC is a logic
high, all 4 switchers operate in PWM mode and the high-side
switches turn on or off via the ENS input. When EN/SYNC is
a logic low, SW1 operates in low current keep-alive (Low IQ)
mode, and SW2, SW3, SW4, S1, and S2 are turned off.
Second, when an external clock is applied to the EN/SYNC pin,
the A8600 wakes-up, completes soft start at the nominal PWM
frequency, and then synchronizes its PWM to the external clock.
The external clock may be used to either increase or decrease the
A8600 nominal PWM frequency. Synchronization operates when
PWM is in the range from 325 to 550 kHz. When using synchronization, the external clock pulses must satisfy the pulse width,
duty cycle, and rise/fall time requirements shown in the Electrical
Characteristics table in this data sheet.
When EN/SYNC transitions to logic high, the A8600 turns on
and then, provided there are no fault conditions, SW2, SW3, and
SW4 initiate soft start and the output voltages will ramp to their
final voltage in the time set by the soft start capacitors (CSSx).
When EN/SYNC transitions to low, then the A8600 will wait
2048 PWM cycles before transitioning SW1 from PWM to PFM
mode. However after EN/SYNC transitions to low, the A8600
will wait only 15 PWM cycles before shutting off SW2, SW3,
SW4, S1, and S2.
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25
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
BIAS Input Pin, Ratings, and Connections
Slope Compensation
When the A8600 is powering up, it operates an internal LDO
regulator directly from VIN1. However, VIN1 is a relatively high
voltage and an LDO regulator is very inefficient and generates
heat. To improve efficiency, especially in PFM mode, a bias
input is utilized. For most applications, the BIAS pin should be
connected directly to the output of SW1. When VSW1 rises to an
adequate level (approximately 2.93 V), the A8600 stops using the
inefficient LDO and begins running its control circuitry directly
from the output of SW1. This makes the A8600 more efficient
and cooler.
The A8600 incorporates internal slope compensation to allow
PWM duty cycles above 50% for a wide range of input/output
voltages and inductor values. As shown in the Functional Block
Diagram the slope compensation signal is added to the sum of
the current sense amplifier output and the PWM ramp offset. The
slope compensation is based on the internal oscillator at 425 kHz
and does not scale when the regulators are synchronized to an
external clock.
The BIAS pin is designed to operate in the range from
3.2 to 5.5 V. If the output of SW1 is in this range, then the BIAS
pin simply should be routed directly to the VSW1 node. However,
if the output of SW1 is in the range from 5.6 to 6.5 V, then a very
small LDO regulator, capable of at least 10 mA, must be used to
reduce the output at VSW1 to either 3.3 V or 5.0 V before routing
it to the BIAS pin.
The A8600 incorporates high-bandwidth current sense amplifiers to monitor the current in the upper MOSFETs of the three
asynchronous regulators; SW1, SW2, and SW3. For the synchronous controller, SW4, a high-bandwidth differential amplifier is
provided. The positive and negative inputs to this amplifier are
CSP and CSN, respectively. As shown in the Typical Application
diagram, the CSP and CSN pins must be routed to a discrete, current sense resistor, RS, in series with the SW4 output inductor.
Transconductance Error Amplifier
The transconductance error amplifier primary function is to
control the output voltage of the switchers. The error amplifier
circuit is shown in figure 9. Here, it is shown as a three-terminal
input device with two positive and one negative input. The negative input is simply connected to the FBx pin and is used to sense
the feedback voltage for regulation. The two positive inputs are
used for soft start and steady-state regulation. The error amplifier
performs an analog OR selection between its two positive inputs.
The error amplifier regulates either to the soft start pin voltage
(minus an offset of 400 mV) or to the A8600 internal reference,
whichever is lower.
To stabilize the regulator, a series RC compensation network
(RZx and CZx) must be connected from the error amplifier output (the COMPx pin) to GND as shown in the Typical Application diagram. In some instances, an additional, relatively low
value capacitor (CPx) may be connected in parallel with the RZx/
CZx components to roll-off the loop gain at higher frequencies.
However, if the CPx capacitor is too large the phase margin of the
converter may be reduced.
If the switcher is disabled or a fault occurs, the COMPx pin is
immediately pulled to GND via approximately 1 kΩ and PWM
switching is inhibited.
Current Sense Amplifiers
Power MOSFETs
The A8600 includes high-side N-channel MOSFETs with low
RDS(on), for SW1 (150 mΩ), SW2 (120 mΩ), and SW3 (112 mΩ)
capable of continuously supplying 1.0 A, 1.5 A, and 2 A, respectively. The A8600 also includes a 10 Ω low-side MOSFET for
each regulator to insure the boot capacitor is always charged. The
typical RDS(on) increase versus temperature is shown in figure 10.
400 mV
Error Amplifier
SSx
+
+
COMPx
-
VREF
800 mV
VFBx
Figure 9. An A8600 error amplifier
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26
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
BOOT Regulators
Each of the four switchers has a regulator to charge its boot
capacitor. The boot regulators detect undervoltage and overvoltage of the boot capacitor. Also, the boot regulators have a current
limit circuit to protect the boot regulator during a short circuit
condition. SW1, SW2, and SW3 derive their boot voltage from
VIN1, VIN2, and VIN3, respectively. However, SW4 does not
have a VIN pin because it drives external MOSFETs. Therefore, SW4 derives its boot voltage from the VIN3 pin. This sets
a requirement that VIN3 should be approximately equal to the
supply voltage at the drain of the external, high-side MOSFET
(which could be considered to be VIN4).
SW1/2/3/4 Pulse Width Modulation (PWM)
Mode
The A8600s four buck switchers utilize fixed-frequency, peak
current mode control to provide excellent load and line regulation, fast transient response, and ease of compensation.
A high-speed comparator and control logic, capable of pulse
widths less than 180 ns, is included for each of the four buck
switchers. The inverting input of the comparator is connected
to the output of the error amplifier. The non-inverting input
is connected to the sum of the current sense signal, the slope
compensation, and a DC offset voltage (VPWMOFFSETx , nominally 400 mV).
1.8
Normalized On-Resistance, RDS(on)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-40
-20
0
20
40
60
80
100
120
140
160
At the beginning of each PWM cycle, the CLK signal sets the
PWM flip-flop and the upper MOSFET is turned on. When the
summation of the DC offset, slope compensation, and current
sense signal, rises above the error amplifier voltage the PWM
flip-flop is reset and the upper MOSFET is turned off. The PWM
flip-flop is reset dominant so the error amplifier may override the
CLK signal in certain situations. For example, at very light loads
or extremely high input voltage the error amplifier temporarily
reduces its output voltage below the 400 mV DC offset and the
PWM flip-flop ignores one or more of the incoming CLK pulses.
The upper MOSFET does not turn on and the regulator skips
pulses to maintain output voltage regulation.
In PWM mode all of the A8600 fault detection circuits are active.
See the Timing Diagrams section for diagrams showing how
faults are handled when in PWM mode. Also, the Protection
Features section of this datasheet provides a detailed description
of each fault and table 1 presents a summary.
SW1 Low IP PWM Mode
SW1 supports two different levels of PWM current limit: 100%
current limit mode, which is normal PWM operation, and Low IP
PWM mode, in which the current is limited to about 50% of the
typical current limit. Low IP PWM mode is invoked when SW1
is commanded to be in Low IQ PFM mode (see next section) but
is either soft starting (VFB1 < 700 mV) or a fault has occurred.
The purpose of Low IP PWM mode is to give priority to maintaining reliable regulation of VSW1 while enabling all the protection circuits inside the A8600 (high precision comparators,
timers, and counters) that are normally off during Low IQ PFM
mode. There are several faults that cause a transition from
Low IQ PFM mode to Low IP PWM mode: a missing asynchronous diode, an open or shorted boot capacitor, VSW1 shorted to
ground, or LX1 shorted to ground. See the Timing Diagrams section for operation of SW1 in normal PWM mode, and operation
of SW1 when it transitions from Low IQ PFM mode to Low IP
PWM mode.
SW1 Pulse Frequency Modulation (PFM) and
Low IQ Mode
Temperature (°C)
Figure 10. Typical MOSFET RDS(on) versus temperature
SW1 is an always-on buck regulator, with both PWM and PFM
modes of operation (PWM mode is described in the previous section). SW1 operates in Low IQ PFM mode if both the EN/SYNC
and ACCI pins are held low continuously for 2048 clock cycles.
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27
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
In PFM mode, SW1 operates with a switching frequency that
depends on the load condition. The average current drawn from
the input supply depends primarily on the load and how often the
A8600 must wake up to maintain regulation.
A8600 will transition from Low IQ PFM mode to Low IP PWM
mode, and operate at 50% of the normal PWM current limit. See
the Timing Diagrams section for operation of SW1 in Low IQ
PFM mode.
In PFM mode, a comparator monitors the voltage at FB1. If the
voltage at FB1 is above approximately 800 mV, the A8600 will
remain in keep-alive mode and draw extremely low current from
the input supply.
In PFM mode the A8600 dissipates very little power, so the thermal monitoring circuit (TSD) is not required and is disabled to
minimize the quiescent current.
If the voltage at the FB1 pin drops below approximately 800 mV,
the A8600 will wake up, and after a delay of approximately 2 μs
for the IC to fully power-up, turn on the upper MOSFET. VSW1
rises at a rate dependent on the input voltage, inductor value, and
output capacitance.
Soft Start (Startup) and Inrush Current
Control
The upper MOSFET is turned off when either: (1) the upper
MOSFET (that is, the output inductor) current reaches approximately 800 mA, or (2) the upper MOSFET has been on for
approximately 4 μs. After the upper MOSFET is turned off, the
A8600 will delay approximately 300 ns and either: (1) turn the
MOSFET on again if the voltage at FB1 is still below 800 mV or
(2) return to the extremely low current keep-alive mode. Figures
11 and 12 demonstrate PFM mode operation for a light load and
an increased load, respectively.
In PFM mode the following faults are detected: a missing
asynchronous diode, an open or shorted boot capacitor, VSW1
shorted to ground, or LX1 shorted to ground. As described in the
previous section for PWM mode, if any of these faults occur the
VSW1
Inrush currents to the 4 switchers are controlled by the soft start
function. When the A8600 is enabled and all faults are cleared,
the Soft Start pin, SSx, will source ISSSUx and the voltage on the
Soft Start capacitor, CSSx, will ramp upward from 0 V. When
the voltage at the Soft Start pin exceeds approximately 400 mV,
the error amplifier slews its output voltage above the PWM
Ramp Offset (VPWMOFFSETx). At that instant, the upper and lower
MOSFETs will begin switching. As shown in figure 13, there is
a delay (tdSSx) between when the Enable pin transitions high and
the combination of the soft start voltage exceeding 400 mV and
the error amplifier slewing its output enough to initiate PWM
switching.
Once the A8600 begins switching, the error amplifier will
regulate the voltage at the FBx pin to the SSx pin voltage, minus
approximately 400 mV. During the active portion of soft start, the
3.3 V
VSW1
VLX1
3.3 V
tOFF ≈ 300 ns
VLX1
C2
C2
800 mA
800 mA
ILX1
ILX1
C3
C3
C1
C1
t
Figure 11. SW1 PFM operation at VIN1 = 12 V, VSW1 = 3.3 V, VSW1 =
50 mA load, LX1 turns on once every 26 μs to regulate VSW1; shows VSW1
(ch1, 100 mV/div.), VLX1 (ch2, 5 V/div.), ILX1 (ch3, 500 mA/div.),
t = 5 μs/div.
t
Figure 12. SW1 PFM operation at VIN1 = 12 V, VSW1 = 3.3 V, VSW1 =
120 mA load, LX1 turns on twice every 18 μs to regulate VSW1; shows
VSW1 (ch1, 100 mV/div.), VLX1 (ch2, 5 V/div.), ILX1 (ch3, 500 mA/div.),
t = 5 μs/div.
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28
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
voltage at the SSx pin rises from 400 mV to 1.2 V (a difference
of 800 mV), the voltage at the FBx pin rises from 0 V to 800 mV,
and the switcher output voltage (VSWx) will rise from 0 V to the
setpoint determined by the feedback (FBx pin) resistor divider.
When the voltage at the Soft Start pin reaches approximately
1.2 V, the error amplifier will change mode and begin regulating the voltage at the FBx pin to the A8600 internal reference,
800 mV. The voltage at the Soft Start pin will continue to rise to
about 3.3 V. Complete soft start operation from 0 VSWx is shown
in figure 13.
If the A8600 is disabled or a fault occurs, the internal fault latch
is set and the Soft Start pin is discharged via approximately 5 kΩ.
The A8600 will clear the internal fault latch when the voltage at
the SSx pin decays to approximately 200 mV (VSSRSTx).
If the A8600 enters hiccup mode, the capacitor on the Soft Start
pin is discharged by a current sink, ISSHICx . Therefore, the Soft
Start capacitor (CSSx) not only controls the startup time but also
the time between soft start attempts. Hiccup mode operation is
discussed in more detail in the Hiccup Mode Protection section of
this datasheet.
For initial startup, when the voltage at the FBx pin is between
0 and 300 mV, the PWM switching frequency, fSW , is reduced
to fSW/2. This is done to achieve the extremely low duty cycles
required for precise regulation when VINx is relatively high and
VSWx is near 0 V. After VFBx rises above 300 mV, the PWM
switching frequency is increased to fSW . If the output of the
switcher is shorted to ground, the voltage at the FBx pin will
remain less than 300 mV and the voltage at the COMPx pin
3.3 V
C1
will reach its maximum value. If these two conditions occur, the
PWM switching frequency is reduced to fSW/4 to allow additional
off (decay) time between LXx pulses. This prevents the inductor
current from rising to an unusually high value that may damage
the A8600 or the output inductor.
Prebiased Startup
If the output of any of the regulators is prebiased to some voltage, the A8600 will modify the normal startup routine to prevent
discharging the output capacitors. As described previously, the
error amplifier usually becomes active when the voltage at the
Soft Start pin exceeds 400 mV. If the output is prebiased the
FBx pin will be at some non-zero voltage. The A8600 will not
start switching until the voltage at the Soft Start pin increases
to approximately VFBx + 400 mV. When the soft start voltage
exceeds this value, the error amplifier becomes active, the voltage
at the COMPx pin rises, PWM switching starts, and VSWx will
ramp upward starting from the prebias level. Figure 14 shows
startup when the output voltage is prebiased to 2.0 V.
High-Side Switches (S1 and S2)
The A8600 contains two 1 Ω high-side switches, S1 and S2,
capable of delivering at least 250 mA each. The VINS pin provides input voltage and current to both S1 and S2. The outputs
of S1 and S2 are at OUT1 and OUT2, respectively. Both highside switches are constructed from two back-to-back, series
MOSFETs so current will not flow in the reverse direction (back
tdssx
3.3 V
C1
VEN/SYNC
VEN/SYNC
tssx
VSWx rises from 2 V, does not drop to 0 V
2V
VSWx
VSWx
C2
C2
VCOMPx
1.2 V
C3
C3
VSSx
C4
C4
400 mV
ISWx
Switching delayed until
VSSx = VFBx + 400 mV
VCOMPx
VSSx
400 mV
ISWx
C5
C5
t
Figure 13. Normal startup to VSWx = 3.3 V at ISWx = 1.6 A load; shows
VEN/SYNC (ch1, 10 V/div.), VSWx (ch2, 1 V/div.), VCOMP (ch3, 500 mV/div.),
VSSx (ch4, 1 V/div.), VSWx (ch5, 1 A/div.), t = 500 μs/div.
t
Figure 14. Pre-biased startup from VSWx = 2 V rising to 3.3 V at ISWx =
1.6 A load; shows VEN/SYNC (ch1, 10 V/div.), VSWx (ch2, 1 V/div.), VCOMP
(ch3, 500 mV/div.), VSSx (ch4, 1 V/div.), VSWx (ch5, 1 A/div.), t = 500 μs/div.
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29
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
to VINS) through the switches. S1 and S2 are simultaneously
controlled on or off by the ENS pin. The A8600 contains an internal charge pump to provide gate drive to S1 and S2.
capacitive load (> 20 A) and the A8600 may have been damaged
or caused some other system level malfunction, such as UVLO
of the entire IC.
If OUT1 or OUT2 is pulled down relatively slowly by a heavy
load, the switch will protect itself by limiting its current to about
350 mADC . If the output of S1 or S2 drops below 8 V, the switch
will begin to foldback the current. At 0 V output, each switch
typically delivers only 100 mA. However if OUT1 or OUT2 is
very quickly shorted to ground, the switch will allow a relatively
high peak current, approximately 800 mA(peak) at VINS = 18 V,
for a short time. This scheme allows for minimal power dissipation while allowing OUT1/OUT2 startup with capacitive loads
up to 1 μF. For thermal reasons, if VINS exceeds approximately
18.3 V, both S1 and S2 are turned off.
In some applications, S1 and S2 are connected to a wiring harness to supply a remote load at a relatively long distance from
the A8600. The wiring harness will introduce significant series
inductance (4 to 6 μH) between the OUTx pin and the actual
load. This forms an LC tank circuit with very low resistance. If
the load is short circuited to ground, the OUTx pin will transition or ring below ground for a short time. To protect the A8600,
Allegro strongly recommends the use of a 1 A, 30 V (min) diode,
as shown in the Typical Application diagram, to help clamp the
negative voltage at the OUT1/OUT2 pins. Preferably, this clamp
diode would be a Schottky type.
Figure 15 shows the typical DC fold back characteristics of the
high-side switches. Figure 16 shows a high-side switch turning on with VINS = 12 V and a 40 Ω/22 μF load. In figure 16,
notice the switch is starting with foldback limiting, allowing
only 100 mA when VOUTx = 0 V, increasing the current to about
400 mA when VOUTx exceeds 5 V, and providing full output
voltage with a 300 mA load. Without foldback control, the switch
would have allowed an extremely high peak current due to the
For most applications, the VINS pin will share a common input
node with the buck switcher VIN1/2/3/4 pins, as shown in
figure 17. In this configuration, the VINs pin is protected from
negative transients (such as during a Field Decay test) by two
series diodes, the MOSFET body diodes and the external, asynchronous Schottky diodes, DSW1 through DSW4 . Depending on
the application, it may be necessary to isolate the VINS pin from
the switching noise on the VIN1/2/3/4 pins.
20
C1
Output Voltage (V)
15
VENS
10
400 mA
C2
VOUTx
5
100 mA
C3
0
0
50
100
150
200
250
300
350
Current Limit (mA)
Figure 15. Typical DC current fold back versus VOUTx of S1 and S2
400
300 mA
IOUTx
t
Figure 16. S1/S2 OUTx turning on with a load of 40 Ω and 22 μF; shows
VENS (ch1, 5 V/div.), VOUTx (ch2, 5 V/div.), IOUTx (ch3, 200 mA/div.),
t = 500 μs/div.
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30
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
One method to accomplish this is to add an additional LC filter,
as shown in figure 18. In this configuration the body diode
and external Schottky diode from the buck swtichers no longer
protect the VINS pin from negative voltage transients. If the
VINS pin is isolated in any way, Allegro recommends adding a
Schottky diode, DVINS, at the VINS pin as shown in figure 18.
There are two levels of thermal protection in the A8600. A
detailed description of these two levels, how they affect the
operation of S1 and S2, and how they must be reset is provided in
the Protections Features section of this data sheet.
See the Timing Diagrams section for operation of the high-side
switches during current limit and high temperature.
BU and ACC Detectors and MUTE Output
The A8600 includes two relatively simple comparators to monitor
both VBAT/VIN and VBAT/VIN applied through a key-type ignition
switch. The BU comparator monitors VBAT/VIN at the BUI pin.
The ACC comparator monitors the ignition switch at the ACCI
pin. Both comparators have an internal reference of 1.205 V at
their negative pins. Therefore, a resistor divider must be used to
set the BU and ACC thresholds to something higher than 1.205 V,
as shown in the Typical Application diagram. Also, if hysteresis is
necessary, this must be done with an external resistor from BUO
to BUI and ACCO to ACCI, as shown in the Typical Application
diagram.
It should be noted that the ACC comparator also controls the
mode of SW1. If the EN/SYNC and ACCI inputs are low, SW1
will enter Low IQ PFM mode after 2048 PWM cycles. If ACCI
is high, it will immediately force SW1 into normal, high-current
PWM mode.
See the Timing Diagrams section for operation of the BU and
ACC detectors.
The A8600 has an open drain, active low MUTE output with a
programmable on-time. The MUTE output is an open drain output, therefore an external pull-up resistor must be used as shown
in the Typical Application Circuit diagram. The MUTE on-time
is set by a counter and a capacitor from the CTMR pin to ground.
Basically, any time the BU comparator changes state the MUTE
output is pulled low while the CTMR pin transitions 10 times
between VCTMRH and VCTMRL. If the BU comparator changes
state before the counter reaches 10, the counter will be reset to 0
and the MUTE time extended. The BU comparator has a deglitch filter, so any fast transient on BUI lasting less than 16 μs
(typ) will be ignored and a false MUTE will not occur. TTSDL and
TTSDH do not affect the MUTE output.
See Timing Diagrams section for operation of the MUTE and
CTMR pins in conjunction with the BU detector.
Power OK (POK) Output
The A8600 has a Power OK (POK) output. The POK output is
an open drain output, so an external pull-up resistor must be used
as shown in the Typical Application Circuit diagram. The POK
output is pulled low if either an under- or overvoltage condition
occurs at FB2, FB3, or FB4. SW1 is an always-on regulator, so it
does not help control POK. The typical POK thresholds are set at
±60 mV (±7.5% of 800 mV).
VINs
VINs
D_VINs
VBAT
VIN1 - VIN4
BODY
DIODE
SCHOTTKY
Figure 17. VINS pin connected directly to VIN1/2/3/4 pins
VBAT
VIN1 - VIN4
BODY
DIODE
SCHOTTKY
Figure 18. VINS isolated from VIN1/2/3/4, so the addition of DVINS is
required
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31
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
The POK comparators incorporate a small amount of hysteresis,
10 mV (typ), to help reduce chattering due to voltage ripple at
any of the FBx pins.
Protection Features
The A8600 is designed to satisfy the most demanding automotive
and non-automotive applications. In this section, a description of
each protection feature is provided, and table 1 summarizes the
protection features and their operation.
Undervoltage Lockout (UVLO)
For each of the three buck regulators, SW1/2/3, an Undervoltage Lock Out (UVLO) comparator monitors the voltage at the
corresponding VINx pin and keeps the regulator disabled if the
voltage is below the lockout threshold ( VUVLOONx ). Each UVLO
comparator incorporates some hysteresis ( VUVLOHYSx ) to prevent
on/off cycling of the regulator due to resistive or inductive drops
in the VINx path during heavy loading or during startup.
Thermal Shutdown (TSDL and TSDH)
The A8600 has two levels of thermal protection: low (TSDL) and
high (TSDH). TSDL typically occurs at approximately 155°C and
TSDH typically occurs at approximately 165°C.
If the junction temperature of the A8600 exceeds TTSDL , but
remains below TTSDH , S1 and S2 are latched off, in order to
reduce power and give priority to maintaining regulation of the
buck outputs even though the regulator is getting hot. In this case,
the TSDL latch may be reset by setting ENS to logic low after the
A8600 cools. However, if the junction temperature of the A8600
exceeds TTSDH , S1/2, and SW2/3/4 will all be latched off and
SW1 will begin operating in Low IQ mode. For the extremely
high temperature case, the TSDH latch may only be reset by setting EN/SYNC to a logic low for at least 15 PWM counts or by
cycling VIN1.
Pulse-by-Pulse Overcurrent Protection (OCP)
The A8600 monitors the current in the upper MOSFET and if the
current exceeds the pulse-by-pulse over current threshold (ILIMx)
then the upper MOSFET is turned off. Normal PWM operation
resumes on the next clock pulse from the internal oscillator. The
A8600 includes leading edge blanking to prevent falsely triggering the pulse-by-pulse current limit when the upper MOSFET is
turned on. Pulse-by-pulse current limiting is always active.
Because of the addition of the slope compensation ramp to the
inductor current, the A8600 delivers slightly less current at higher
duty cycles than at lower duty cycles. If the synchronization
input is used to reduce the switching frequency, the A8600 will,
in effect, reduce the current limit with frequency too. Figure 19
shows the minimum, typical and maximum pulse-by-pulse current limit at the typical PWM frequency, 425 kHz. Also, figure
19 shows the minimum expected pulse-by-pulse current limit if
the synchronization input is used to reduce the switching frequency to 325 kHz. The exact current each of the buck regulators
can support is heavily dependent on duty cycle, ambient temperature, thermal resistance of the PCB, airflow, component selection,
and nearby heat sources.
5.00
Peak Current Limit (A)
4.50
Maximum at 425 kHz
4.00
Typical at 425 kHz
3.50
Minimum at 425 kHz
3.00
Minimum at 325 kHz
2.50
2,00
1.50
5.0
15.0
25.0
35.0
45.0
55.0
65.0
75.0
85.0
95.0
Duty Cycle (%)
Figure 19. Pulse-by-pulse current limit versus duty cycle and
PWM (SYNC) frequency
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32
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
Output Short Circuit (Hiccup Mode) Protection
Hiccup mode protects the buck switchers when their load is either
too high or when the output of the switcher is shorted to ground.
Hiccup mode operation is shown in figure 20.
When the voltage at the SSx pin is below the Hiccup OCP Enable
Threshold (VHICENx , 2.3 V (typ)) hiccup mode protection is
disabled. After the voltage at the SSx pin exceeds the Hiccup
OCP Enable Threshold, an OCP counter is enabled. The quantity
of OCP pulses allowed then depends on the FBx voltage. If VFBx
is below 300 mV, only 30 OCP counts are allowed. If the FBx
voltage is above 300 mV, the quantity of OCP pulses allowed
increases to 118. This dual count technique provides maximum
thermal protection for the A8600 and allowing robust attempts for
starting with highly capacitive or heavy loads.
If the OCP counter reaches its limit, a latch is set and the COMPx
pin is pulled low by a relatively low resistance (1 kΩ). The
same latch enables a small current sink connected to the SSx
pin (ISSHICx). The result is the voltage at the Soft Start pin will
begin to ramp downward. When the voltage at the Soft Start pin
decays to a much lower level, VSSRSTx (200 mV (typ)) the hiccup
latch will be cleared and the small current sink turned off. At this
instant, the SSx pin will begin to source current (ISSSUx ) and the
voltage at the SSx pin will ramp upward. This marks the begin-
VSWx
C1
C2
Hiccup mode
OCP counter
enabled
VCOMPx
ning of a new, normal soft start cycle as described earlier.
When the voltage at the Soft Start pin exceeds the PWM Ramp
Offset (VPWMOFFSET , 400 mV (typ)) the error amplifier will
force the voltage at the COMPx pin to slew up quickly and PWM
switching will resume. If the short circuit at the switcher output
remains, another hiccup cycle will occur. Hiccups will repeat
until the short circuit is removed or the switcher is disabled. If
the short circuit is removed, the A8600 will soft start normally
and the output voltage will automatically recover to the required
level, as shown in figure 20.
BOOT Capacitor Protection
For each buck switcher, the A8600 monitors the voltage across
the BOOT capacitor to detect if the capacitor is missing or short
circuited. If the BOOT capacitor is missing, the regulator will
enter hiccup mode after 7 PWM cycles. If the BOOT capacitor
is short circuited, the regulator will enter hiccup mode after 30
PWM cycles. For a BOOT fault, hiccup mode operates similarly
to the hiccup mode described for an output short circuit, with
SSx ramping up and down as a timer to initiate repeated soft start
attempts. A BOOT fault is a non-latched condition, so the A8600
will automatically recover when the fault is corrected.
Short
removed
30 OCP
counts
Soft start
to normal
operation
OCP
latched
2.3 V
VSSx
≈5 A
C3
ISWx
200 mV
C4
t
Figure 20. Hiccup mode and recovery to VSWx = 3.3 V at ISWx = 1.6 A;
shows VSWx (ch1, 2 V/div), VCOMPx (ch2, 2 V/div), VSSx (ch3, 1 V/div),
ISSSUx (ch4, 2 A/div); t = 2 ms/div
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33
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
Asynchronous Diode Protection
In most high voltage asynchronous buck regulators, if the asynchronous diode is missing or damaged, the LX pin will transition
to a very high negative voltage when the upper MOSFET turns
off, resulting in damage to the regulator. The A8600 includes
protection circuitry to detect when the asynchronous diode is
missing or damaged. If the LXx pin becomes more negative than
1.25 V (typ) for more than 50 ns (typ), the A8600 will protect
itself to prevent damage. SW1 will enter hiccup mode after 1
missing diode fault. SW2/3/4 will latch off after 1 missing diode
fault. After a latched missing diode fault, the latch must be reset
by either setting EN/SYNC to a logic low or cycling VINx .
Overvoltage Protection (OVP)
The A8600 provides a basic level of overvoltage protection
by monitoring the voltage level at the FBx pin of all four buck
switchers. Two overvoltage conditions can be detected. First, if
the FBx pin is disconnected from its feedback resistor divider, a
tiny internal current source will force the voltage at the FBx pin
to rise. When the voltage at the FBx pin exceeds the overvoltage
threshold (VPOKOVx , 860 mV (typ)), PWM switching will stop.
For SW1, the POK pin level is unaffected by overvoltage, but for
SW2/3/4 the POK pin will be pulled low.
Second, if a higher external voltage supply is accidently shorted
to a switcher output, VFBx will rise above the overvoltage threshold and be detected as an overvoltage condition. PWM switching will stop and the POK pin pulled low (for SW2/3/4). If the
condition causing the overvoltage is removed the regulators will
automatically recover.
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34
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
Table 1: Summary of Fault Mode Operation
Latched
VSSx
SW1/2/3/4 output shorted
to GND
No
Hiccup after 30 or
118 faults
Discharged, then
respond to VSSx rise
Depends on
VSWx
Active, responds
to VCOMPx
Not affected
Auto, remove short
S1/2 output shorted to
GND
No
Not affected
Not affected
Not affected
Not affected
Foldback
limiting
Auto, remove short
SW1/2/3/4 boot capacitor
missing
No
Hiccup, after 7
faults
Discharged, then
respond to VSSx rise
Depends on
VSWx
Off during hiccup
Not affected
Auto, replace capacitor
SW1/2/3/4 boot capacitor
shorted
No
Hiccup, after 30
faults
Discharged, then
respond to VSSx rise
Depends on
VSWx
Off via UVLO
BOOT
Not affected
Auto, unshort capacitor
SW1 asynchronous diode
missing
No
Hiccup, after 1
fault
Discharged, then
respond to VSSx rise
N/A
Active, responds
to VCOMPx
Not affected
Auto, install diode
SW1/2/3/4 asynchronous
diode missing
Yes
Discharged after
1 fault
Discharged
Depends on
VSWx
Forced off
Not affected
EN/SYNC low*
or VREG POR
via VIN1 UVLO
SW1 asynchronous diode
(or LX1) hard short
No
Hiccup after 1 fault
Discharged, then
respond to VSSx rise
N/A
Active, responds
to VCOMPx
Not affected
Auto, remove short
SW1 asynchronous diode
(or LX1) soft short
No
Hiccup after 30
faults
Discharged, then
respond to VSSx rise
N/A
Active, responds
to VCOMPx
Not affected
Auto, remove short
SW1/2/3/4 asynchronous
diode (or LXx) hard short
Yes
Pulled low after
1 fault
Discharged
Depends on
VSWx
Forced off
Not affected
EN/SYNC low*
or VREG POR
via VIN1 UVLO
SW1/2/3/4 asynchronous
diode (or LXx) soft short
No
Hiccup after 30
faults
Discharged, then
respond to VSSx rise
Depends on
VSWx
Active, responds
to VCOMPx
Not affected
Auto, remove short
SW1/2/3/4 FBx pin open
(VFBx floats high)
No
Ramps high for
soft start
Low via loop response
SW2/3/4 low
via VFBx high
(OV)
Off via VCOMPx low
Not affected
Auto, connect FBx pin
SW1/2/3/4 overvoltage
(VFBx > 107.5%)
No
Ramps high for
soft start
Low via loop response
Pulled Low
Forced off
Not affected
Auto, VFBx to normal
range
LG4 more than 8.1 V for
>400 ns
Yes
Pulled low after
1 fault
Discharged
Depends on
VSW4
Latched off
Not affected
EN/SYNC low*
or VREG POR
via VIN1 UVLO
LG4 in high state but
< 1 V for >400 ns
Yes
Pulled low after
1 fault
Discharged
Depends on
VSW4
Latched off
Not affected
EN/SYNC low*
or VREG POR
via VIN1 UVLO
LG4 in low state but > 1 V
for >400 ns
Yes
Pulled low after
1 fault
Discharged
Depends on
VSW4
Latched off
Not affected
EN/SYNC low*
or VREG POR
via VIN1 UVLO
Thermal (TSDL)
Yes
Not affected
Not affected
Depends on
VSWx
Not affected
Off
EN/SYNC low*
or ENS low
or VREG POR
via VIN1 UVLO
SW1 Thermal (TSDH)
Yes
After 2048 PWM cycles, latches in Low IQ mode
Off
EN/SYNC low*
or VREG POR
via VIN1 UVLO
SW2/3/4 Thermal (TSDH)
Yes
Pulled low
Off
EN/SYNC low*
or VREG POR
via VIN1 UVLO
1EN/SYNC
VCOMPx
Pulled low
VPOK
PWM
Switching
Fault Condition
Depends on
VSWx
Latched off
S1, S2
Reset
low requires a logic low for 15 clock cycles.
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35
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
Application Information
Design and Component Selection
In general, the feedback resistors must satisfy the ratio shown in
equation 1 to produce a required output voltage:
Setting the Output Voltage (VSWx, RFBAx, RFBBx)
The output voltage of any switcher, SW1 through SW4, is determined by connecting a resistor divider from the switcher output
node (VSWx) to the switcher FBx pin as shown in figure 21. There
are trade-offs when choosing the value of the feedback resistors. If the series combination (RFBAx+ RFBBx) is relatively low,
then the light load efficiency of the regulator will be reduced.
So to maximize the efficiency, it is best to choose resistors with
higher values. Conversely, if the value of the parallel combination
(RFBAx//RFBBx) is too high, then the switcher may be susceptible
to noise coupling into the FBx pin.
RFBAx
V SWx
FBx PIN
RFBBx
VSWx
–1
0.8 (V)
RFBAx
=
RFBBx
(1)
Table 2 shows the most common output voltages and recommended feedback resistors assuming less than 0.2% efficiency
loss at light load of 100 mA and a parallel combination of 4 kΩ
presented to the FBx pin. For optimal system accuracy, it is recommended that the feedback resistors have tolerances of ≤1% .
SW1 presents some unique challenges when determining its feedback resistor divider. This resistor divider must draw minimum
current from VSW1 or it will raise the input current during Low IQ
operation. With this in mind, Allegro recommends the standard
±1% resistor values shown in table 3.
For Low IQ mode operation, a small feed-forward capacitor
(CFB1) should be connected in parallel with RFBA1, as shown
in figure 22. The purpose of this capacitor is to offset any stray
capacitance (CSTRAY) from FB1 to ground. Without CFB1, the
stray capacitance and the relatively high resistor values used for
the SW1 feedback network form a low pass filter and introduce
lag to the Low IQ PFM feedback path. The feed-forward capaci-
Figure 21. Connecting the feedback divider
CFB1
RFBA1
V SW1
FB1 PIN
Table 2. Recommended Feedback Resistors for
Switchers SW2 through SW4
RFBB1
Cstray
VSW2/3/4
(V)
RFBA2/3/4
(kΩ)
RFBB2/3/4
(kΩ)
1.2
6.04
12.1
1.5
7.50
8.45
1.8
9.09
7.15
2.5
12.4
5.76
3.3
16.5
5.23
5.0
24.9
4.75
VSW1
(V)
RFBA1
(kΩ)
RFBB1
(kΩ)
7.0
34.8
4.53
3.3
163
52.3
7.2 to 12
8.0
40.2
4.42
5.0
249
47.5
4.7 to 8
9.6
47.5
4.32
6.5
365
51.1
3.3 to 6
Figure 22. Addition of CFB1 to cancel stray capacitance
Table 3. Recommended Feedback Components for
Switcher SW1
CFB1
(pF)
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36
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
tor helps to maintain sensitivity during PFM mode and assure the
output voltage ripple is minimized.
final inductor value should allow for 5% to 10% of initial tolerance and 10% to 20% of inductor saturation.
In general, CFB1 should be calculated as:
The saturation current of the inductor should be higher than the
peak current capability of the A8600. Ideally, for output short
circuit conditions, the inductor should not saturate given the highest pulse-by-pulse current limit at minimum duty cycle (ILIMx),
4.9 A (max). This may be too costly. At the very least, the inductor should not saturate given the peak operating current according
to equation 6. In equation 6, VINx(max) is the maximum continuous input voltage, such as 18 V (not a surge voltage).
CFB1 > (1.5 CSTRAY) × ( RFBB1 / RFBA1 )
(2)
where CSTRAY is typically 15 to 25 pF.
Output Inductor (LSWx)
For a peak current mode buck regulator, it is common knowledge that, without adequate slope compensation, the system will
become unstable when the duty cycle exceeds approximately
50%. However, the slope compensation in the A8600 is a fixed
value (SE(x)) . Therefore, it is important to calculate an inductor
value such that the downward slope of the current (SFx) approximately matches the A8600 slope compensation. Equations 3
and 4 can be used to calculate a range of values for the output
inductor based on the well known approach of providing slope
compensation that matches 50% to 100% of downward slope of
the inductor current. In these equations, we assume the minimum
value of slope compensation (SE(X) = 300 mA/μs). Vfx is the
forward voltage of the asynchronous diode:
VSWx+Vfx
(3)
LSWx ≥
0.6 × 10–6
VSWx+Vfx
LSWx ≥
(4)
0.3 × 10–6
More recently, Dr. Raymond Ridley presented a formula to
calculate the amount of slope compensation required to critically
damp the double poles at half the PWM switching frequency.
This formula includes the duty cycle (D), which should be calculated at the minimum input voltage to insure maximum stability:
LSWx ≥
VSWx +Vfx
(VINx (min)+Vfx )
1 – 0.18 ×
VSWx +Vfx
0.45 × 10–6
(5)
Also, note that VINx(min) must be approximately 1 to 1.5 V
above VSWx when calculating the inductor value with equation 5.
Recall that SW4 is a synchronous regulator so Vfx = 0 V should
be used in equations 3 to 5.
If equations 3 to 5 yield an inductor value that is not a standard
value, then the next highest available value should be used. The
ILIMx = 4.4 –
0.45 × 10 –6 × (VSWx +Vfx )
fSWx(max) × (VINx (max)+Vfx )
(6)
Starting with equation 6 and subtracting half of the inductor
ripple current provides us with an interesting equation to predict
the typical DC load capability for any of the buck regulators:
ISWx(DC) = 4.4 –
0.45 × 10 –6 × D
fSWx
VSWx × 1– D
2 × fSWx × LSWx
(7)
After an inductor is chosen, it should be tested during output
short circuit conditions. The inductor current should be monitored
using a current probe. A good design would ensure the inductor or the switcher are not damaged when the output is shorted
to GND at maximum input voltage and at the highest expected
ambient temperature.
Output Capacitors (CSWx)
The output capacitors filter the output voltage to provide an
acceptable level of ripple voltage and they store energy to help
maintain voltage regulation during a load transient. The voltage
rating of the output capacitors must support the output voltage
with sufficient design margin.
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37
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
The ESR can be minimized by simply adding more capacitors in
parallel or by using higher quality capacitors. At the instant of a
fast load transient (di/dt), the output voltage will change by the
amount:
The output voltage ripple (ΔVSWx ) is a function of the output
capacitor parameters: ESRSWx , ESLSWx , and CSWx :
∆VSWx = ∆ILSWx × ESRSWx
+
VINx –VSWx
LSWx
∆ILSWx
+
8 fSWx C SWx
× ESLSWx
∆VSWx = ∆ILOADSWx × ESRSWx +
(8)
The type of output capacitors will determine which terms of
equation 8 are dominant.
For ceramic output capacitors the ESR and ESL are virtually zero
so the output voltage ripple will be dominated by the third term
of equation 8:
∆VSWx =
∆ILSWx
8 fSWx CSWx
(9)
To reduce the voltage ripple of a design using ceramic output
capacitors simply increase the total capacitance, reduce the inductor current ripple (that is, increase the inductor value), or increase
the switching frequency.
For electrolytic output capacitors the value of capacitance will be
relatively high so the third term in equation 8 will be minimized
and the output voltage ripple will be determined primarily by the
first two terms of equation 8:
∆VSWx = ∆ILSWx × ESRSWx +
VINx
× ESLSWx
LSWx
(10)
To reduce the voltage ripple of a design using electrolytic output
capacitors, simply decrease the equivalent ESR and ESL by using
a high quality capacitor, and/or add more capacitors in parallel,
or reduce the inductor current ripple (that is, increase the inductor
value). The ESR of some electrolytic capacitors can be quite high
so Allegro recommends choosing a high quality capacitor with a
datasheet that that clearly documents the ESR or the total impedance. Also, the ESR of electrolytic capacitors usually increases
significantly at cold ambient, which increases the output voltage
ripple and, in many cases, reduces the stability of the system.
The transient response of the A8600 depends on the number and
type of output capacitors. In general, minimizing the ESR of
the output capacitance will result in a better transient response.
di
ESLSWx
dt
(11)
After the load transient occurs, the output voltage will deviate
for a short time. The time will depend on the system bandwidth,
the output inductor value, and output capacitance. After a short
delay, the error amplifier will bring the output voltage back to its
nominal value.
The speed at which the error amplifier brings the output voltage back to its setpoint will depend mainly on the closed-loop
bandwidth of the system. A higher bandwidth usually results in
a shorter time to return to the nominal voltage. However, with
a higher bandwidth system it may be more difficult to obtain
acceptable gain and phase margins. Selection of the compensation components (RZ, CZ, CP) are discussed in more detail in the
Compensation Components section of this datasheet.
SW1 Low IQ PFM Ripple Calculation
After choosing an output inductor and output capacitor(s) for
SW1, its important to calculate the output voltage ripple during
Low IQ PFM mode. With ceramic output capacitors the output
voltage ripple in PWM mode is usually negligible, but that is not
the case during Low IQ PFM mode.
First, we need to calculate the MOSFET on and off times. The
on-time is defined as the time it takes for the inductor current to
reach 800 mA (typ):
tON
=
800 (mA) × LSW1
VIN1 – VSW1– 800 (mA) × (RDS(on)HS1 + RDCLSW1)
(12)
where RDS(on)HS1 is the on-resistance of the SW1 high-side
MOSFET (150 mΩ (typ)) and RDCLSW1 is the DC resistance
of the output inductor, LSW1. The on-time during PFM mode is
internally limited to approximately 4 μs.
The off-time is defined as the time it takes for the inductor current to decay from 800 mA (typ) to 0 A:
tOFF =
800 (mA) × LSW1
VSW1+Vf1
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(13)
38
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
where the duty cycle is:
Lastly, the PFM output voltage ripple can be calculated:
∆VSW1(PFM) =
D ≈ (VSWx+ Vfx ) / ( VIN + Vfx )
800 (mA) × (tON + tOFF)
2 × CSW1
(14)
If the PFM output voltage ripple appears to be too high, then the
output capacitance of SW1 should be increased. The PFM output
voltage ripple will increase as the input voltage decreases.
Notice that tON will increase as the output to input voltage ratio
( VSW1 / VIN1 ) increases. If the VSW1 / VIN1 ratio is too high, the
system will not be able to achieve 800 mA within only 1 PFM
pulse. In this case the on-time will be limited to approximately
4 μs and a second PFM pulse will be required, about 300 ns later,
as shown in figure 12.
Input Capacitors (CINx)
Three factors should be considered when choosing the input
capacitors. First, they must be chosen to support the maximum
expected input voltage, with adequate design margin. Second,
their rms current rating must be higher than the expected rms
input current to the switcher. Third, they must have enough
capacitance, and a low enough ESR, to limit the input voltage
dV/dt to something much less than the hysteresis of the UVLO
circuitry (nominally 400 mV for the A8600) at maximum loading
and minimum input voltage.
The input capacitors must deliver the rms current according to:
Irms = ISWx D × (1– D)
(15)
and Vfx is the forward voltage of the asynchronous diode, DSWx .
Figure 23 shows the normalized input capacitor rms current
versus duty cycle. To use this graph, simply find the operational
duty cycle (D) on the x-axis and determine the input/output current multiplier on the y-axis. For example, at a 20% duty cycle,
the input/output current multiplier is 0.400. Therefore, if the
regulator is delivering 2.0 A of steady-state load current, the input
capacitor(s) must support 0.400 × 2.0 A or 0.8 Arms .
The input capacitors must limit the voltage deviations at the
VINx pin to something significantly less than the A8600 UVLO
hysteresis during maximum load and minimum input voltage.
Equation 17 allows us to calculate the minimum input capacitance:
CINx ≥
0.50
(17)
The D × (1–D) term in equation 17 has an absolute maximum
value of 0.25 at 50% duty cycle. So for example, a very conservative design, based on ISWx = 2 A, fSW(min) = 325 kHz, D × (1–D)
= 0.25, and ΔVINx = 150 mV:
2 (A) × 0.25
= 10.2 μF
325 (kHz) × 150 (mV)
A good design accommodates the DC-bias effect on a ceramic
capacitor: as the applied voltage approaches the rated value, the
capacitance value decreases. This effect is very pronounced with
the Y5V and Z5U temperature characteristic devices (as much as
90% reduction) so these types should be avoided. The X5R and
X7R type capacitors should be the primary choices due to their
stability versus both DC bias and temperature.
0.45
0.40
Irms / ISWx
ISWx × D × (1– D)
fSWx (min) × (∆VINx (min)
where ΔVINx(min) is chosen to be much less than the hysteresis
of the VINx UVLO comparator (ΔVINx(min) ≤ 150 mV is recommended), and fSW(min) is the lowest expected PWM frequency.
CINx ≥
0.55
(16)
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0
10
20
30
40
50
60
Duty Cycle (%)
Figure 23. Input capacitor ripple versus duty cycle
70
80
90
100
For all ceramic capacitors, the DC-bias effect is even more pronounced on smaller case sizes, so a good design uses the largest
affordable case size (such as 1206 or 1210). Also, its advisable
to select input capacitors with plenty of design margin in the
voltage rating, in order to accommodate the worst case transient
input voltage (that is, load dump as high as 40 V for automotive
applications).
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39
A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
Equation 17 should be used for each of the four buck switchers
to calculate the required amount of ceramic input capacitance
for each switcher. In the PCB layout, the input capacitor(s) for
each buck switcher should be placed close to the switcher they
support.
Asynchronous Diode (DSWx)
There are three requirements for the asynchronous diodes.
First, the asynchronous diode must be able to withstand the regulators input voltage when the high-side MOSFET is on. Therefore, the design should have a diode with a reverse voltage rating
(Vrx) higher than the maximum expected input voltage (that is,
the surge voltage).
Second, the forward voltage of the diode (Vfx) should be minimized or the regulator efficiency will suffer. Also, if Vfx is too
high the missing diode protection in the A8600 could be falsely
activated. A Schottky-type diode that can maintain a very low
Vf when the regulator output is shorted to ground at the coldest
ambient temperature is highly recommended.
Third, the asynchronous diode must conduct the output current
when the high-side MOSFET is off. Therefore, the average forward current rating of this diode (Ifavgx) must be high enough to
deliver the load current according to equation 17, such that:
Ifavgx ≥ ISWx(max) (1 – D )
SW4 with its relatively large external MOSFET, 100 nF is recommended. This capacitor should be a high-quality ceramic, such as
an X5R or X7R, with a voltage rating of at least 16 V.
For SW1/2/3, the A8600 incorporates a 10 Ω low-side MOSFET
to insure that the bootstrap capacitor is always charged, even
when the regulator is lightly loaded or prebiased.
Soft Start and Hiccup Mode Timing (CSSx)
The soft start time of the A8600 is determined by the value of the
capacitance on the SSx pin (CSSx).
When the A8600 is enabled, the voltage at the SSx pin will start
from 0 V and be charged by the soft start current, ISSSUx. However, PWM switching will not begin instantly because the voltage
at the SSx pin must rise above 400 mV. The soft start delay (tdSSx)
can be calculated using:
tdSSx = CSSx ×
400 (mV)
ISSSUx
(20)
If the A8600 is starting into a very heavy load, a very fast soft
start time may cause the switcher to exceed the pulse-by-pulse
overcurrent threshold. This can occur because the total of the full
load current, the inductor ripple current, and the additional current required to charge the output capacitors
(18)
ICO = CSWx × VSWx / tSS
(21)
where ISWx(max) is the maximum continuous putput current of
the regulator, and the minimum duty cycle is:
D(min) = (VSWx+ Vfx ) / ( VINx (max) + Vfx )
(19)
Even though SW4 is a synchronous controller, it requires an
external Schottky diode from LX4 to ground (DSW4), as shown
in the Typical Application Circuit diagram. This diode will
conduct during the non-overlap time and must clamp the LX4
pin to a relatively low (negative) voltage. Without this Schottky
diode the LX4 pin will become more and more negative. Eventually, the negative voltage will forward-bias the substrate parasitic
base-emitter junction and/or the LX4 ESD structure, which could
lead to malfunction or even destruction of the A8600.
Bootstrap Capacitor (CBOOTx)
A bootstrap capacitor must be connected between the BOOTx
and LXx pins to provide floating gate drive to the high-side
MOSFET. Usually, SW1/2/3 require only 47 nF. However, for
}
I LIM
I OUT
Output
capacitor
current, I CO
t SS
Figure 24. Output current (ICO) during startup
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A8600
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
is higher than the pulse-by-pulse current threshold, as shown in
figure 24. This phenomenon is more pronounced when using high
value, electrolytic-type output capacitors.
To avoid prematurely triggering hiccup mode, the soft start
capacitor, CSSx, should be calculated using the following formula:
CSSx ≥
ISSSSUx × VSWx × CSWx
0.8 (V) × ICOx
The upper and lower MOSFETs must support the SW4 peak
output current according to the following equations:
Upper MOSFET:
IDHS4 ≥ ISW4 (peak) ×
VSW4
VIN4 (min)
(26)
Lower MOSFET:
(22)
where VSWx is the output voltage, CSWx is the output capacitance,
ICOx is the amount of current allowed to charge the output capacitance during soft start (Allegro recommends an ICOx between
0.1 and 0.3 A).
Higher values of ICO result in faster soft start times. Howewer,
lower values of ICO ensure that hiccup mode is not falsely triggered. Allegro recommends starting the design with an ICO of
0.1 A and increasing it only if the soft start time is too slow. If
a non-standard capacitor value for CSSx is calculated, the next
larger value should be used.
The output voltage ramp time, tSSRAMPx, can be calculated by
using either of the following methods:
C
(24)
tSSx = VSWx × SWx
ICOx
or
tSSx = 0.8 (V) × CSSx
(25)
ISSSUx
When the A8600 is in hiccup mode, the CSSx capacitor is used
as a timing capacitor and sets the hiccup period. The SSx pin
charges the CSSx capacitor with ISSSUx during a startup attempt,
and discharges the CSSx capacitor with ISSHICx between startup
attempts. Because the ratio of the SSx pin currents is 2:1, the time
between hiccups will be at least twice as long as the startup time.
Therefore, the effective duty-cycle of the A8600 will be very low
when the output is shorted to ground, and the junction temperature will be kept low.
SW4 External MOSFET Selections
The external MOSFETs for SW4 must withstand the maximum
expected input voltage. In an automotive environment this is usually the 40 V load dump situation. The BOOT4 regulator shown
in the Typical Application Circuit diagram, internal gate drivers,
and protection circuits were optimized for MOSFETs with less
than12 nC of gate charge at VGS = 5 V.
IDHS4 ≥ ISW4 (peak) × 1 –
VSW4
VIN4 (max)
(27)
Examples of several 40 V MOSFETs with less than 12 nC of gate
charge are shown in table 4.
SW4 Current Sense Resistor
The current limit of SW4 at its minimum on-time (tON(min)) is
determined by the value of the external sense resistor according
to the following equation:
ISW4(peak) at t ON (min) =
ILIM4
75 (mV) (typ)
=
RSENSE4
RSENSE4
(28)
Notice that this sets the current limit at tON(min) only. The
actual current limit will depend on the duty cycle and switching
frequency as shown in equations 5 and 6. Therefore, the sense
resistor should be chosen to support the required load current
(plus some margin) at a relatively high duty cycle and minimum
switching frequency.
Compensation Components (RZx, CZx, CPx)
To compensate the system, it is important to understand where
the buck power stage, load resistance, and output capacitance
form their poles and zeros in frequency. Also, its important to
understand that the compensated error amplifier introduces a zero
Table 4: Possible 40 V MOSFETs for SW4
Typical at
VGS= 4.5 V
Part Number
Manufacturer
(A)
(mΩ)
nC
FDS8449
Fairchild
6.8
26
8
Si4446DY
Vishay
4.9
37
8
DMN4034SSS
Diodes, Inc.
5.5
39
5
NTMS5838NL
ON Semi
7
25
9
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Quadruple Output Regulator with Two High-Side Switches,
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A8600
and two more poles, and where these should be placed to maximize system stability, provide a high bandwidth, and optimize the
transient response.
First, we will take a look at the power stage of the A8600, the
output capacitors, and the load resistance. This circuitry is commonly referred as the control-to-output transfer function. The low
frequency gain of this section depends on the COMPx to VSWx
node current gain (gmPOWERx), and the value of the load resistor
(RLOADx). The DC gain (0 Hz) of the control-to-output (CTO) is:
gCTO(0Hz)x = gmPOWERx × RLOADx
(29)
The control-to-output transfer function has a pole (fP1),
formed by the output capacitance (CSWx) and load resistance
(RLOADx), at:
fP1x =
1
2 × RLOAD × CSWx
(30)
The control-to-output transfer function also has a zero (fZ1)
formed by the output capacitance (CSWx) and its associated ESR:
fZ1x =
1
2 × ESRx × CSWx
(31)
For a design with very low-ESR type output capacitors (such as
ceramic or OS-CON™ output capacitors), the ESR zero (fZ1) is
Gain (dB)
20
GCO0Hz = 13.6 dB
fP1 = 1.9 kHz
Next, we will take a look at the feedback resistor divider,
(RFBAx and RFBBx), the error amplifier (gm), and its compensation network RZ-CZ-CP. It greatly simplifies the transfer function
derivation if ROx (error amplifier output impedance) >> RZx , and
CZx >> CP x. In most cases, ROx > 2 MΩ, 1 kΩ < RZx < 50 kΩ,
220 pF < CZx < 47 nF, and CPx < 100 pF, so the following analysis should be very accurate.
The low frequency gain of the control section (GC0Hz) is formed
by the feedback resistor divider and the error amplifier. It can be
calculated using:
GC0Hz =
=
0
-20
-40
90
0
Double Pole at
212.5 kHz
-90
-180
101
RFBBx
RFBAx +RFBBx
VFBx
VSWx
VFBx
× gmx × ROx
× gmx × ROx
× AVOLx
VSWx
(32)
where VSWx is the output voltage, VFBx is the reference voltage
(0.8 V), gmx is the error amplifier transconductance (750 μA/V),
and ROx is the error amplifier output impedance (AVOLx/gmx).
-60
180
Phase (°)
A Bode plot of the control-to-output transfer function for SW3
as shown in the Typical Application Circuit diagram, with VSW3
= 3.3 V, ISW3 = 2 A, and RLOAD3 = 1.65 Ω) is shown in figure 25.
The pole at fP1 can be seen at 1.9 kHz while the ESR zero (fZ1)
occurs at a very high frequency, 636 kHz (this is typical for a
design using ceramic output capacitors). Note, there is more than
90° of total phase shift because of the double-pole at half the
switching frequency.
=
60
40
usually at a high frequency, so it can be ignored. On the other
hand, if the ESR zero falls below or near the 0 dB crossover frequency of the system (such as for electrolytic output capacitors),
then it should be cancelled by the pole formed by the CPx capacitor and the RZx resistor (discussed and identified later as fP3).
102
103
104
105
106
The transfer function of the Type-II compensated error amplifier
has a (very) low frequency pole (fP2) dominated by the output
error amplifier output impedance ROx and the CZx compensation
capacitor:
Frequency (Hz)
fP2x =
1
2 × ROx
× CZx
(33)
Figure 25. Control-to-output Bode plot for SW3
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Quadruple Output Regulator with Two High-Side Switches,
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A8600
The transfer function of the Type-II compensated error amplifier
also has frequency zero (fZ2) dominated by the RZx resistor and
the CZx capacitor:
fP2x =
1
2 × RZx
(34)
× CZx
Gain (dB)
Lastly, the transfer function of the Type-II compensated error
amplifier has a higher frequency pole (fP3) dominated by the RZx
resistor and the CPx capacitor:
60 GCO0Hz = 45.6 dB
40
fP2 = 54 Hz
20
fZ1 = 3.8 kHz
fP3 = 315 kHz
0
-20
-40
Phase (°)
-60
180
1
(35)
× CPx
2 × RZx
A Bode plot of the error amplifier and its compensation network
is shown in figure 26, in which fP2 , fP3 , and fZ2 are indicated on
the magnitude plot. Notice that the zero (fZ2 at 3.8 kHz) has been
placed so that it is in the vicinity of the pole at fP1 previously
shown at 1.9 kHz in the control-to-output Bode plot, figure 25.
Placing fZ2 just above fP1 will result in excellent phase margin,
but relatively slow transient recovery time, as we will see later.
Finally, we take a look at the combined Bode plot of both the
control-to-output and the compensated error amplifier; see the red
curve shown in figure 27. Careful examination of this plot shows
that the magnitude and phase of the entire system (red trace) are
simply the sum of the error amplifier response (blue trace) and
the control-to-output response (green trace). As shown in figure 27, the bandwidth (fc) of this system is 36 kHz and the phase
margin is 66 degrees.
A Generalized Tuning Procedure
90
0
-90
-180
101
fP3x =
102
103
104
105
106
Frequency (Hz)
1) Choose the system bandwidth, fC , which is the frequency at
which the magnitude of the gain will cross 0 dB. Recommended
values for fC , based on the PWM switching frequency, are in the
range: fSW / 20 < fC < fSW / 10. A higher value of fC will generally
provide a better transient response, and a lower value of fC will
make it easier to obtain higher gain and phase margins.
Figure 26. Compensated error amplifier Bode plot (SW3)
3.32
60
fC = 36 kHz
20
0
-20
-40
Phase (°)
-60
180
PM = 66°
90
9 kHz / 57°
3.30
Output Voltage, VSWx (V)
Gain (dB)
40
3.8 kHz / 66°
3.28
3.26
3.24
0
3.22
-90
-180
101
102
103
104
105
Frequency (Hz)
Figure 27. Bode plot of the complete SW3 system (red curve)
106
3.20
440
480
520
560
600
640
680
720
760
800
Recovery Time (μs)
Figure 28. Transient recovery comparison for fZ2 at 3.8 kHz / 66° and
9 kHz / 57°
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Quadruple Output Regulator with Two High-Side Switches,
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A8600
2) Calculate the RZx resistor value to set the required system
bandwidth (fC):
2 × CSWx
RZx = fC × VSWx ×
(36)
VFBx
gmPOWERx × gmx
3) Determine the frequency of the pole (fP1) formed by CSWx and
RLOAD by using equation 30 (repeated here):
fP1x =
1
2 × RLOAD × CSWx
< CZx <
1
2 × RZx× 1.5 × fP1x
(34)
To maximize system stability (that is, to have the most gain
margin), use a higher value of CZX. To optimize transient
recovery time, at the expense of some phase margin, use a lower
value of CZX . Figure 28 shows the output voltage recovery time
due to a 1A load transient for the system shown in figure 27
(fZ2 = 3.8 kHz, 66° phase margin) and a system with fZ2 at 1/4 the
crossover frequency, or 9 kHz. The system with fZ2 at 9 kHz
has 57° of phase margin but recovers about twice as fast as the
other system.
5) Calculate the frequency of the ESR zero (fZ1) formed by the
output capacitor(s) by using equation 31 (repeated here):
fZ1x =
The power dissipated in the A8600 is the sum of the power dissipated from the VIN supply current (PIN), the power dissipated due
to the switching of the internal power MOSFETs (PSW1/2/3), the
power dissipated due to the rms current being conducted by the
internal MOSFET (PCOND1/2/3), the power dissipated by the four
internal gate drivers (PDRIVER1/2/3/4), and the power dissipated
due to the rms current being conducted by the two high-side
switches (PS1/S2).
The power dissipated from the VIN supply current can be calculated using the following equation:
4) Calculate a range of values for the CZx capacitor:
4
2 × RZx× fCx
Power Dissipation and Thermal Calculations
1
2 × ESRx × CSWx
5a) If fZ1 is at least 1 decade higher than the target crossover
frequency (fC) then fZ1 can be ignored. This is usually the case
for a design using ceramic output capacitors. Use equation 35
to calculate the value of CPx by setting fP3 to either 5 × fC or
fSW / 2, whichever is higher.
5b) Conversely, if fZ1 is near or below the target crossover frequency (fC) then use equation 35 to calculate the value of CPx by
setting fP3 equal to fZ1. This is usually the case for a design using
high ESR electrolytic output capacitors.
PINTOTAL = VINx × IQ + (VINx – VGSx)
× (3 × QG + QG4) × fSW
(35)
where VINx is the input voltage, IQ is the input quiescent current
drawn by the A8600 (nominally 7.5 mA), VGS is the MOSFET
gate drive voltage (typically 5 V), QG is the internal MOSFET
gate charge (approximately 2.5 nC), QG4 is the external MOSFET
gate charge for SW4, and fSW is the PWM switching frequency.
The power dissipated by the internal high-side MOSFET while it
is switching can be calculated using the following equation:
PSW1/2/3 ≥
VIN1/2/3 × ISW1/2/3x ×(tr + tf ) × fSW
2
(36)
where VINx is the input voltage, ISWx is the regulator output current, fSWx is the PWM switching frequency, and tr and tf are the
rise and fall times measured at the VLXx node. The exact rise and
fall times at the VSWx node will depend on the external components and PCB layout so each design should be measured at full
load. Approximate values for both tr and tf range from 5 to 10 ns.
The power dissipated by the internal high-side MOSFETs while
they are conducting can be calculated using the following equation:
2
PCOND1/2/3 = Irms(FET)1/2/3
× RDS(on)HS1/2/3
=
2
VSW1/2/3+Vf1/2/3
∆IL1/2/3
2
× ILSW1/2/3 + 12
VIN1/2/3+Vf1/2/3
× RDS(on)HS1/2/3
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A8600
Quadruple Output Regulator with Two High-Side Switches,
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where ISWx is the regulator output current, ΔILx is the peak-topeak inductor ripple current, RDS(on)HSx is the on-resistance of
the high-side MOSFET, and Vfx is the forward voltage of the
asynchronous diode.
The RDS(on)of the high-side MOSFET will have some initial
tolerance plus an increase from self-heating and elevated ambient temperatures. A conservative design should accommodate
an RDS(on) with at least a 15% initial tolerance plus 0.39%/°C
increase due to temperature.
The sum of the power dissipated by the internal gate driver can
be calculated using the following equation:
PDRIVER = (3 × QG + QG4 ) × VGS × fSW
(38)
where VGS is the gate drive voltage (typically 5 V for all
four buck switchers), QG is the gate charge to drive internal
MOSFET1/2/3 to VGS = 5 V (about 2.5 nC each), QG4 is the gate
charge to drive the external MOSFET to VGS = 5 V (this must
come from the MOSFET datasheet), and fSW is the PWM switching frequency.
The power dissipated by the high-side switches (S1, S2) can be
calculated using th following equation:
PS1/S2 = I 2S1/S2 × RDS(on)S1/S2
(39)
where Ix is the DC current through high-side switches S1 and S2,
and RDS(on)Sx is the on-resistance of the switch (typically 1 Ω),
Finally, the total power dissipated (PTOTAL) is the sum of the previous equations for all four switchers and the high-side switches:
PTOTAL = PINTOTAL + PSW1/2/3 + PDRIVER + PS1/S2
(40)
The average junction temperature can be calculated with the following equation:
TJ = PTOTAL + RθJA + TA
(41)
where PTOTAL is the total power dissipated as described in
equation 40, RθJA is the junction-to-ambient thermal resistance
(23°C/W on a 4-layer PCB), and TA is the ambient temperature.
The maximum junction temperature will be dependent on how
efficiently heat can be transferred from the PCB to ambient air.
The thermal pad on the bottom of the IC should be connected
to a at least one ground plane using multiple vias for optimum
performance. A small amount of airflow can improve the thermal
performance considerably.
As with any regulator, there are limits to the amount of power
that can be delivered and heat that can be dissipated before
risking thermal shutdown. There are tradeoffs between ambient
operating temperature, input voltage, output voltage, output current, switching frequency, PCB thermal resistance, airflow, and
other nearby heat sources. Even a small amount of airflow will
will reduce junction temperature considerably.
PCB Component Placement and Routing
A good PCB layout is critical if the A8600 is to provide clean,
stable output voltages. Follow these guidelines to insure good
PCB layout. Figure 28 shows a typical buck converter schematic
with the critical power paths/loops. Figure 29 shows an example
PCB component placement and routing (for SW3) with the same
critical power paths/loops from the schematic.
1) By far, the highest di/dt in the asynchronous buck regulator
occurs at the instant the upper FET turns on and the capacitance
of the asynchronous Schottky diode (200 to 1000 pF) is quickly
charged to VINx . The ceramic input capacitors must deliver this
fast, short pulse of current. Therefore, the loop from the ceramic
input capacitors through the upper FET and into the asynchronous diode to ground should be minimized. Ideally these components are all connected using only the top layer traces (that is, do
not use vias to other power or signal layers).
2) When the upper FET is on, current flows from the input supply
and capacitors, through the upper FET, into the load via the output inductor, and back to ground. This loop should be minimized
and have relatively wide traces.
3) When the upper FET is off, free-wheeling current flows from
ground, through the asynchronous diode, into the load via the
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A8600
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output inductor, and back to ground. This loop should be minimized and have relatively wide traces.
4) The voltage on the LXx nodes transition from 0 V to VINx very
quickly and are the root cause of many noise issues. It is best to
place the asynchronous diode and output inductor close to the
A8600 to minimize the size of the LXx polygon. Also, keep lowlevel analog signals (such as FBx and COMPx) away from the
LXx polygon.
5) Place the feedback resistor dividers (RFBAx and RFBBx) very
close to the FBx pin. Ground this resistor divider as close as possible to the A8600.
6) The two traces to the SW4 sense resistor should be run in
parallel back to CSP and CSN.
7) To have the highest output voltage accuracy, the output voltage
sense trace (from VSWx to RFBAx) should be connected as close
as possible to the load.
8) Place the compensation components (RZx, CZx, and CPx) as
close as possible to the COMPx pin. Place vias to the GND plane
as close as possible to these components.
9) Place the soft start capacitor (CSSx) as close as possible to the
SSx pin. Place a via to the GND plane as close as possible to this
component.
10) Place the boot strap capacitor (CBOOTx) near the BOOTx
pin and keep the routing to this capacitor as short as possible.
11) When routing the input and output ceramic capacitors, use
multiple vias to GND and place the vias as close as possible to
the pads of the component.
12) To minimize PCB losses and improve system efficiency,
the input and output traces should be as wide as possible and be
duplicated on multiple layers, if possible.
13) To improve thermal performance, place multiple vias to the
GND plane around the anode of the asynchronous diode.
14) The thermal pad under the A8600 must connect to the GND
plane using multiple vias. More vias will ensure the lowest junction temperature and highest efficiency.
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Quadruple Output Regulator with Two High-Side Switches,
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Loop 3
VIN3
Loop 1
Loop 2
LX3
Q3
CIN3 CIN2 CIN1
D3
(VSW3)
...
LSW3
RSNUB3
(CSWx)
CO1
CSNUB3
VOUT3
CO5
LOAD
...
Figure 28. Typical buck converter PCB layout, with critical paths and loops shown
Loop 1 (Red): At the instant Q3 turns on, the Schottky diode D3 (which is very capacitive), must be very quickly charged and shut off. The
spike of charging current must come from the input capacitors, CIN1/2/3. This spike of current is quite large and will be an EMI/EMC issue
if loop 1 is not minimized. Therefore, the input capacitors and Schottky diode D3 must be placed be on the same (top) layer, be located near
each other, and be grounded at virtually the same point on the PCB.
Loop 2 (Brown): When Q3 is off, free-wheeling inductor current must flow from ground through diode D3, into the output inductor, out to the
load and return via ground. While Q3 is off, the voltage on the output capacitors will decrease. The output capacitors and Schottky diode D3
must be placed on the same (top) layer, be located near each other, and be grounded at virtually the same point on the PCB.
Loop 3 (Blue): When Q3 is on, current flows from the input supply and input capacitors through the output inductor and into the load. At this
time the voltage on the output capacitors will increase.
Q3
VIN
Loop 1
GND
LOAD
Loop 3
Loop 2
Figure 29. Example PCB component placement and routing, example shows SW3
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Quadruple Output Regulator with Two High-Side Switches,
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A8600
Table 5. Pin Descriptions Table
Name
Number
Pin Connection
If Pin Function Not Used
Description
General
EN/SYNC
6
EN/PFM control and PWM synchronization input
BIAS
45
Bias input, supplies internal circuitry when VSW1 is high enough
((Always used))
Ground
VREG
4
Internal voltage regulator bypass capacitor pin
(Always used)
POK
23
Power OK open drain output
Open
GND
3
Ground
(Always used)
PAD
–
Exposed pad for enhanced thermal dissipation
(Always used, connect to ground)
Internal Asynchronous Always-On Buck Regulator (SW1)
VIN1
1
Input supply for buck regulator SW1
(Always used)
LX1
48
Switching node for buck regulator SW1
(Always used)
BOOT1
47
Floating gate drive for buck regulator SW1
(Always used)
FB1
44
Feedback pin for buck regulator SW1
(Always used)
COMP1
43
Error amplifier compensation network for regulator SW1
(Always used)
SS1
46
Soft start programming for regulator SW1
(Always used)
VIN2
35
Input supply for buck regulator SW2
Internal Asynchronous Buck Regulator (SW2)
Ground
VIN2
36
Input supply for buck regulator SW2
Ground
LX2
37
Switching node for buck regulator SW2
Ground
LX2
38
Switching node for buck regulator SW2
Ground
NC
34
Unused, this pin should be left unconnected
N/A
BOOT2
39
Floating gate drive for buck regulator SW2
Ground
FB2
41
Feedback pin for buck regulator SW2
FB3 or FB4
COMP2
42
Error amplifier compensation network for regulator SW2
Ground
SS2
40
Soft start programming for regulator SW2
Ground
VIN3
11
Input supply for buck regulator SW3
VIN supply (or Ground1)
VIN3
12
Input supply for buck regulator SW3
VIN supply (or Ground1)
LX3
13
Switching node for buck regulator SW3
BOOT3 (or Ground1)
LX3
14
Switching node for buck regulator SW3
BOOT3 (or Ground1)
BOOT3
15
Floating gate drive for buck regulator SW3
LX3 (or Ground1)
FB3
17
Feedback pin for buck regulator SW3
FB2 or FB4
Internal Asynchronous Buck Regulator (SW3)
COMP3
18
Error amplifier compensation network for regulator SW3
Ground
SS3
16
Soft start programming for regulator SW3
Ground
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
48
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
Table 5. Pin Descriptions Table (continued)
Name
Number
Pin Connection
If Pin Function Not Used
Description
External Synchronous Buck Regulator (SW4)
LX4
30
Switching node for buck regulator SW4
BOOT4 (or Ground1)
BOOT4
31
Floating gate drive for buck regulator SW4
LX4 (or Ground1)
HG4
29
High side gate drive for buck regulator SW4
Open (or Ground1)
LG4
32
Low side gate drive for buck regulator SW4
Open (or Ground1)
PGND
33
Power ground
(Always used)
CSP
27
Current sense pin for buck regulator SW4
Ground
CSN
26
Current sense pin for buck regulator SW4
Ground
FB4
25
Feedback pin for buck regulator SW4
FB2 or FB3
COMP4
24
Error amplifier compensation network for regulator SW4
Ground
SS4
28
Soft start programming for regulator SW4
Ground
BU, ACC, and Mute Functions
BUI
10
Input to the BU comparator
Ground
BUO
9
Output of the BU comparator
Open
ACCI
8
Input to the ACC comparator
Ground
ACCO
7
Output of the ACC comparator
Open
CTMR
5
Delay programming for the MUTE pulse circuit
Ground
MUTE
2
Open-drain, active LOW output of the MUTE pulse circuit
Open
VINS
21
Input to the high-side switches
VIN supply (or Ground2)
ENS
19
Input to enable/disable both high-side switches
Ground
OUT1
20
High-side switch S1 output
OUT2 or Open
(or Ground2)
OUT2
22
High-side switch S2 output
OUT1 or Open
(or Ground2)
High-Side Switches (S1, S2)
1Connect
2Connect
to Ground instead, if also SW3 and SW4 both are not used.
to Ground instead, if also S1 and S2 both are not used.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
49
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
PIN ESD STRUCTURES: (Note: The HV clamp is shown where needed, but there is only 1 common HV clamp in the IC)
PIN
CIRCUIT
LV
HV
GND
PIN
PGND
Low Voltage Pins;
FBX, EN/SYNC, VREG, BIAS, CSP, CSN,
LG4, BUO, ACCO, CTMR, ACCI
HV
GND
High Voltage Pins with Clamp:
BUI, SSX, ENS
PIN
GND
PGND
PGND
PGND
PGND
GND to PGND
High Voltage Pins;
OUT1, OUT2, VINS, MUTE, POK
VINx
BOOT4
BOOTx
HG4
HV
LXx
LX4
HV
PGND
PGND
SW1, SW2, and SW3 Power Pins;
VIN1, VIN2, VIN3, LX1, LX2, LX3,
BOOT1, BOOT2, BOOT3
PGND
PGND
SW4 Output Pins; BOOT4, HG4, LX4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
50
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
Package Outline Drawing
Package JP, 48-Pin LQFP
0.30
9.00 ±0.20
0.50
1.70
7.00 ±0.20
7º
4° ±4
0º
+0.05
0.15 –0.06
C
B
9.00 ±0.20 7.00 ±0.20
5.00
5.00
8.60
0.60 ±0.15
48
(1.00)
A
1
48
2
1 2
0.25
5.00
SEATING PLANE
GAGE PLANE
5.00
8.60
48X
SEATING
PLANE
0.08 C
0.22 ±0.05
0.50
C
1.60 MAX
1.40 ±0.05
0.10 ±0.05
C
PCB Layout Reference View
For Reference Only
(reference JEDEC MS-026 BBCHD)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351
QFP50P900X900X160-48M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
51
Quadruple Output Regulator with Two High-Side Switches,
BU/ACC Voltage Detectors, and Mute Delay
A8600
Revision History
Revision
Revision Date
Rev. 3
December 5, 2012
Description of Revision
Editorial changes
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permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
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Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
52
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