DATASHEET

EL5421T
®
Data Sheet
September 25, 2009
12MHz Rail-to-Rail Input-Output Buffer
Features
The EL5421T is a high voltage rail-to-rail input-output buffer
with low power consumption. The EL5421T contains four
buffers. Each buffer exhibits beyond the rail input capability,
rail-to-rail output capability and is unity gain stable.
• 12MHz -3dB bandwidth
The maximum operating voltage range is from 4.5V to 19V. It
can be configured for single or dual supply operation, and
typically consumes only 500µA per buffer. The EL5421T has
an output short circuit capability of ±200mA and a
continuous output current capability of ±70mA.
• 12V/µs Slew Rate
The EL5421T features a slew rate of 12V/µs. Also, the
device provides common mode input capability beyond the
supply rails, rail-to-rail output capability, and a bandwidth of
12MHz (-3dB). This enables the buffers to offer maximum
dynamic range at any supply voltage. These features make
the EL5421T an ideal buffer solution for use in TFT-LCD
panels as a VCOM or static gamma buffer, and in high speed
filtering and signal conditioning applications. Other
applications include battery power and portable devices,
especially where low power consumption is important.
• Unity-gain Stable
The EL5421T is available in a space saving 10 Ld MSOP
package and operates over an ambient temperature range
of -40°C to +85°C.
• TFT-LCD Panels
FN6922.0
• 4 Unity Gain Buffers
• 4.5V to 19V Maximum Supply Voltage Range
• 500µA Supply Current (per buffer)
• ±70mA Continuous Output Current
• ±200mA Output Short Circuit Current
• Beyond the Rails Input Capability
• Rail-to-rail Output Swing
• Built-in Thermal Protection
• -40°C to +85°C Ambient Temperature Range
• Pb-free (RoHS compliant)
Applications
• VCOM Buffers
• Electronics Notebooks
Ordering Information
PART
NUMBER
(Note)
EL5421TIYZ*
• Electronics Games
PART
MARKING
BBBLA
PACKAGE
(Pb-Free)
10 Ld MSOP
PKG.
DWG. #
M10.118A
*Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
• Personal Communication Devices
• Personal Digital Assistants (PDA)
• Portable Instrumentation
• Wireless LANs
• Office Automation
• Active Filters
• ADC/DAC Buffers
Pinout
EL5421T
(10 LD MSOP)
TOP VIEW
VOUTA 1
VINA 2
VS+ 3
VINB 4
VOUTB 5
1
10 VOUTD
9 VIND
8 VS7 VINC
6 VOUTC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Elantec is a registered trademark of Elantec Semiconductor, Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5421T
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . +19.8V
Input Voltage Range (VINx) . . . . . . . . . . . .(VS-)-0.5V to (VS+)+0.5V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . ±70mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3000V
Thermal Resistance Junction-to-Ambient (Typical)
θJA (°C/W)
10 Ld MSOP (Note 1). . . . . . . . . . . . . . . . . . . . . . . .
160
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . .See Figure 27 and 28
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 10kΩ to 0V, TA = +25°C unless otherwise specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
3
13
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
TCVOS
Average Offset Voltage Drift (Note 2)
IB
Input Bias Current
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
AV
Voltage Gain
VCM = 0V
4
VCM = 0V
2
-4.5V ≤ VOUTx ≤ 4.5V
0.992
µV/°C
50
nA
1.008
V/V
-4.85
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = +5mA
ISC
Short Circuit Current
VCM = 0V, Source: VOUTx short to VS-,
Sink: VOUTx short to VS+
IOUT
Output Current
-4.94
4.85
4.94
V
±200
mA
±70
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-)
Supply Voltage Range
IS
Supply Current (Per Buffer)
VCM = 0V, No load
PSRR
Power Supply Rejection Ratio
Supply is moved from ±2.25V to ±9.5V
4.5
500
60
19
V
750
µA
75
dB
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 3)
-4.0V ≤ VOUTx ≤ 4.0V, 20% to 80%
12
V/µs
tS
Settling to +0.1% (Note 4)
AV = +1, VOUTx = 2V step,
RL= 10kΩ, CL= 8pF
500
ns
BW
-3dB Bandwidth
RL= 10kΩ, CL= 8pF
12
MHz
CS
Channel Separation
f = 5MHz
75
dB
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = 0V, RL = 10kΩ to 2.5V, TA = +25°C unless otherwise specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
3
13
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
TCVOS
Average Offset Voltage Drift (Note 2)
IB
Input Bias Current
2
VCM = 2.5V
4
VCM = 2.5V
2
µV/°C
50
nA
FN6922.0
September 25, 2009
EL5421T
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = 0V, RL = 10kΩ to 2.5V, TA = +25°C unless otherwise specified. (Continued)
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
RIN
Input Impedance
1
GW
CIN
Input Capacitance
2
pF
AV
Voltage Gain
0.5 ≤ VOUTx ≤ 4.5V
0.992
1.008
V/V
150
mV
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -2.5mA
VOH
Output Swing High
IL = +2.5mA
ISC
Short Circuit Current
VCM = 0V, Source: VOUTx short to VS-,
Sink: VOUTx short to VS+
IOUT
Output Current
30
4.85
4.97
V
±125
mA
±70
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-)
Supply Voltage Range
IS
Supply Current (Per Buffer)
VCM = 2.5V, No load
PSRR
Power Supply Rejection Ratio
Supply is moved from 4.5V to 19V
4.5
500
60
19
V
750
µA
75
dB
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 3)
1V ≤ VOUTx ≤ 4V, 20% to 80%
12
V/µs
tS
Settling to +0.1% (Note 4)
AV = +1, VOUTx = 2V step,
RL= 10kΩ, CL= 8pF
500
ns
BW
-3dB Bandwidth
RL= 10kΩ, CL= 8pF
12
MHz
CS
Channel Separation
f = 5MHz
75
dB
Electrical Specifications
PARAMETER
VS+ = +18V, VS- = 0V, RL = 10kΩ to 9V, TA = +25°C unless otherwise specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
4
15
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
TCVOS
Average Offset Voltage Drift (Note 2)
IB
Input Bias Current
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
AV
Voltage Gain
VCM = 9V
5
VCM = 9V
0.5 ≤ VOUTx ≤ 17.5V
2
0.992
µV/°C
50
nA
1.008
V/V
150
mV
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -9mA
VOH
Output Swing High
IL = +9mA
ISC
Short Circuit Current
VCM = 9V, Source: VOUTx short to VS-,
Sink: VOUTx short to VS+
IOUT
Output Current
100
17.85
17.90
V
±200
mA
±70
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-)
Supply Voltage Range
IS
Supply Current (Per Buffer)
VCM = 9V, No load
PSRR
Power Supply Rejection Ratio
Supply is moved from 4.5V to 19V
4.5
550
60
19
V
750
µA
75
dB
12
V/µs
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 3)
3
1V ≤ VOUTx ≤14V, 20% to 80%
FN6922.0
September 25, 2009
EL5421T
Electrical Specifications
PARAMETER
VS+ = +18V, VS- = 0V, RL = 10kΩ to 9V, TA = +25°C unless otherwise specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
tS
Settling to +0.1% (Note 4)
AV = +1, VOUTx = 2V step,
RL= 10kΩ, CL= 8pF
500
ns
BW
-3dB Bandwidth
RL= 10kΩ, CL= 8pF
12
MHz
CS
Channel Separation
f = 5MHz
75
dB
NOTES:
2. Measured over -40°C to +85°C ambient operating temperature range. See the typical TCVOS production distribution shown in the
“Typical Performance Curves” on page 5
3. Typical slew rate is an average of the slew rates measured on the rising (20% to 80%) and the falling (80% to 20%) edges of the output signal.
4. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output level settles within
a ±0.1% error band. The range of the error band is determined by: Final Value(V)±[Full Scale(V)*0.1%]
4
FN6922.0
September 25, 2009
EL5421T
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0
28
VS = ±5V
TA = +25°C
TYPICAL
PRODUCTION
DISTRIBUTION
QUANTITY (AMPLIFIERS)
QUANTITY (AMPLIFIERS)
Typical Performance Curves
16
12
8
4
0
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
INPUT OFFSET VOLTAGE (mV)
INPUT BIAS CURRENT (nA)
INPUT OFFSET VOLTAGE (mV)
3
5
7
9
11
13
INPUT OFFSET VOLTAGE DRIFT (|µV|/°C)
15
2
VS = ±5V
5
0
0
50
100
TEMPERATURE (°C)
VS = ±5V
1
0
-1
-2
-50
150
FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE
0
50
100
TEMPERATURE (°C)
150
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
-4.91
4.95
VS = ±5V
IOUT = 5mA
OUTPUT LOW VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
1
FIGURE 2. INPUT OFFSET VOLTAGE DRIFT
10
4.93
4.91
4.89
-50
TYPICAL
PRODUCTION
DISTRIBUTION
20
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
-5
-50
VS = ±5V
-40°C TO +85°C
24
0
50
100
TEMPERATURE (°C)
150
FIGURE 5. OUTPUT HIGH VOLTGE vs TEMPERATURE
5
-4.92
VS = ±5V
IOUT = -5mA
-4.93
-4.94
-4.95
-4.96
-50
0
50
100
TEMPERATURE (°C)
150
FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE
FN6922.0
September 25, 2009
EL5421T
Typical Performance Curves (Continued)
14
VS = ±5V
RL = 10kΩ
VS = ±5V
RL = 10kΩ
1.0016
SLEW RATE (V/µs)
VOLTAGE GAIN (V/V)
1.0018
1.0014
1.0012
1.0010
1.0008
-50
0
50
100
TEMPERATURE (°C)
13
12
11
-50
150
525
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
TA = +25°C
VS = ±5V
NO LOAD
INPUTS AT GND
500
475
0
50
100
TEMPERATURE (°C)
150
20
600
550
500
450
400
350
2
GAIN (dB)
8
FIGURE 11. SLEW RATE vs SUPPLY VOLTAGE
6
10
1kΩ
560Ω
-5
-10
8
10
10kΩ
0
12
4
6
SUPPLY VOLTAGE (±V)
6
8
SUPPLY VOLTAGE (±V)
5
TA = +25°C
AV = 1
RL = 10kΩ
CL = 8pF
16
4
FIGURE 10. SUPPLY CURRENT PER CHANNEL vs SUPPLY
VOLTAGE
FIGURE 9. SUPPLY CURRENT PER CHANNEL vs
TEMPERATURE
SLEW RATE (V/µs)
150
650
550
4
2
50
100
TEMPERATURE (°C)
FIGURE 8. SLEW RATE vs TEMPERATURE
FIGURE 7. VOLTAGE GAIN vs TEMPERATURE
450
-50
0
150Ω
VS = ±5V
AV = 1
CL = 8pF
-15
100k
1M
10M
FREQUENCY (Hz)
100M
FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS RL
FN6922.0
September 25, 2009
EL5421T
Typical Performance Curves (Continued)
200
20
OUTPUT IMPEDANCE (Ω)
100pF
GAIN (dB)
10
0
50pF
8pF
-10
1000pF
-20 VS = ±5V
AV = 1
RL = 10kΩ
-30
100k
1M
10M
VS = ±5V
AV = 1
RL = OPEN
VOUTx = +13dBm
160
120
80
40
0
100M
1k
10k
FREQUENCY (Hz)
0
12
VS = ±5V
TA = +25°C
-10
10
-20
8
6
VS = ±5V
TA = +25°C
AV = 1
RL = 10kΩ
CL = 8pF
4
2
0
10k
-30
-40
-50
PSRR+
-60
-70
100k
1M
FREQUENCY (Hz)
PSRR-
-80
1k
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 15. MAXIMUM OUTPUT SWING vs FREQUENCY
FIGURE 16. PSRR vs FREQUENCY
1000
0.050
TA = +25°C
VS = ±5V
RL = 10kΩ
AV = 1
VIN = 1.4VRMS
0.045
0.040
100
THD+N (%)
VOLTAGE NOISE (nV/√Hz)
10M
FIGURE 14. OUTPUT IMPEDANCE vs FREQUENCY
PSRR (dB)
MAXIMUM OUTPUT SWING (VP-P)
FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS CL
100k
1M
FREQUENCY (Hz)
10
0.035
0.030
0.025
0.020
0.015
0.010
1
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 17. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY
7
0.005
100
1k
10k
FREQUENCY (Hz)
100k
FIGURE 18. TOTAL HARMONIC DISTORTION + NOISE vs
FREQUENCY
FN6922.0
September 25, 2009
EL5421T
Typical Performance Curves (Continued)
-60
80
OVERSHOOT (%)
-70
XTALK(dB)
100
MEASURED CH A TO D, OR B TO C
OTHER COMBINATIONS YIELD
IMPROVED REJECTION
VS = ±5V
AV = 1
VINx = 0dBm
-80
-90
-100
40
VS = ±5V
TA = +25°C
AV = 1
RL = 10kΩ
VINx = ±50mV
20
10k
100k
1M
FREQUENCY (Hz)
0
10
10M
4
3
2
VS = ±5V
TA = +25°C
AV = 1
RL = 10kΩ
CL = 8pF
1000
VS = ±5V
TA = +25°C
AV = 1
RL= 10kΩ
CL =8pF
1V/DIV
5
100
LOAD CAPACITANCE (pF)
FIGURE 20. SMALL SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
FIGURE 19. CHANNEL SEPARATION vs FREQUENCY
RESPONSE
0.1%
1
0
-1
-2
0.1%
-3
6V STEP
-4
-5
100
200
300
400
500
SETTLING TIME (ns)
600
700
1µs/DIV
FIGURE 22. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 21. STEP SIZE vs SETTLING TIME
VS = ±5V
TA = +25°C
AV = 1
RL= 10kΩ
CL =8pF
50mV/DIV
STEP SIZE (V)
60
200ns/DIV
100mV STEP
FIGURE 23. SMALL SIGNAL TRANSIENT RESPONSE
8
FN6922.0
September 25, 2009
EL5421T
Typical Performance Curves (Continued)
EL5421T
(10LD MSOP shown)
1
VOUTA
VOUTA
VOUTD
10
VOUTD
RLA
C LA
R LD
2
VINA+
VINA
VIND
9
VIND+
49.9
49.9
3
VS+
+
4.7µF
Vs+
Vs-
8
0.1µF
V S0.1µF
4
VINB+
VINB
VINC
+
4.7µF
7
VINC+
49.9
49.9
5
VOUTB
C LB
C LD
VOUTB
VOUTC
6
VOUTC
RLB
R LC
C LC
FIGURE 24. BASIC TEST CIRCUIT
Pin Descriptions
PIN NUMBER
PIN NAME
1
VOUTA
2
FUNCTION
EQUIVALENT CIRCUIT
Buffer A Output
(Reference Circuit 1)
VINA
Buffer A Input
(Reference Circuit 2)
3
VS+
Positive Power Supply
4
VINB
Buffer B Input
(Reference Circuit 2)
5
VOUTB
Buffer B Output
(Reference Circuit 1)
6
VOUTC
Buffer C Output
(Reference Circuit 1)
7
VINC
Buffer C Input
(Reference Circuit 2)
8
VS-
9
VIND
10
VOUTD
Negative Power Supply
Buffer D Input
(Reference Circuit 1)
Buffer D Output
(Reference Circuit 2)
VS+
VS+
VOUTx
VINx
GND
CIRCUIT 1
9
VSVS-
CIRCUIT 2
FN6922.0
September 25, 2009
EL5421T
Applications Information
VS = ±2.5V, TA = +25°C, VINx = 6VP-P, RL = 10kΩ to GND
OUTPUT
The EL5421T features a slew rate of 12V/µs. Also, the
device provides common mode input capability beyond the
supply rails, rail-to-rail output capability, and a bandwidth of
12MHz (-3dB). This enables the buffers to offer maximum
dynamic range at any supply voltage.
Operating Voltage, Input and Output Capability
FIGURE 25. OPERATION WITH BEYOND-THE-RAILS INPUT
The EL5421T can operate on a single supply or dual supply
configuration. The EL5421T operating voltage ranges from a
minimum of 4.5V to a maximum of 19V. This range allows for
a standard 5V (or ±2.5V) supply voltage to dip to -10%, or a
standard 18V (or ±9V) to rise by +5.5% without affecting
performance or reliability.
The EL5421T output typically swings to within 50mV of
positive and negative supply rails with load currents of
±5mA. Decreasing load currents will extend the output
voltage range even closer to the supply rails. Figure 26
shows the input and output waveforms for the device in a
unity-gain configuration. Operation is from ±5V supply with a
10kΩ load connected to GND. The input is a 10VP-P
sinusoid and the output voltage is approximately 9.9VP-P.
Refer to the “Electrical Specifications” Table beginning on
page 2 for specific device parameters. Parameter variations
with operating voltage, loading and/or temperature are
shown in the “Typical Performance Curves” on page 5.
INPUT
VS = ±5V, TA = +25°C, VINx = 10VP-P, RL = 10kΩ to GND
5V/DIV
The input common-mode voltage range of the EL5421T
extends 500mV beyond the supply rails. Also, the EL5421T
is immune to phase reversal. However, if the common mode
input voltage exceeds the supply voltage by more than 0.5V,
electrostatic protection diodes in the input stage of the
device begin to conduct. Even though phase reversal will not
occur, to maintain optimal reliability it is suggested to avoid
input overvoltage conditions. Figure 25 shows the input
voltage driven 500mV beyond the supply rails and the device
output swinging between the supply rails.
100µs/DIV
INPUT
OUTPUT
The EL5421T is a high voltage rail-to-rail input-output buffer
with low power consumption. The EL5421T contains four
buffers. Each buffer exhibits beyond the rail input capability,
rail-to-rail output capability and is unity gain stable.
1V/DIV
Product Description
100µs/DIV
FIGURE 26. OPERATION WITH RAIL-TO-RAIL INPUT AND
Output Current
The EL5421T is capable of output short circuit currents of
200mA (source and sink), and the device has built-in
protection circuitry which limits the short circuit current to
±200mA (typical).
To maintain maximum reliability the continuous output
current should never exceed ±70mA. This ±70mA limit is
determined by the characteristics of the internal metal
interconnects. Also, see “Power Dissipation” on page 11 for
detailed information on ensuring proper device operation
and reliability for temperature and load conditions.
Unused Buffers
It is recommended that any unused buffers have their inputs
tied to the ground plane.
Driving Capacitive Loads
As load capacitance increases, the -3dB bandwidth will
decrease and peaking can occur. Depending on the
application, it may be necessary to reduce peaking and to
improve device stability. To improve device stability a
snubber circuit or a series resistor may be added to the
output of the EL5421T.
A snubber is a shunt load consisting of a resistor in series
with a capacitor. An optimized snubber can improve the
10
FN6922.0
September 25, 2009
EL5421T
phase margin and the stability of the EL5421T. The
advantage of a snubber circuit is that it does not draw any
DC load current or reduce the gain.
Another method to reduce peaking is to add a series output
resistor (typically between 1Ω to 10Ω). Depending on the
capacitive loading, a small value resistor may be the most
appropriate choice to minimize any reduction in gain.
Where:
• i = 1 to 4
(1, 2, 3, 4 corresponds to Channel A, B, C, D respectively)
• VS = Total supply voltage (VS+ - VS-)
• VS+ = Positive supply voltage
• VS- = Negative supply voltage
Power Dissipation
With the high-output drive capability of the EL5421T buffers,
it is possible to exceed the +150°C absolute maximum
junction temperature under certain load current conditions. It
is important to calculate the maximum power dissipation of
the EL5421T in the application. Proper load conditions will
ensure that the EL5421T junction temperature stays within a
safe operating region.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T JMAX – T AMAX
P DMAX = --------------------------------------------Θ JA
(EQ. 1)
• ISMAX = Maximum supply current per buffer
(ISMAX = EL5421T quiescent current ÷ 4)
• VOUT = Output voltage
• ILOAD = Load current
Device overheating can be avoided by calculating the
minimum resistive load condition, RLOAD, resulting in the
highest power dissipation. To find RLOAD set the two PDMAX
equations equal to each other and solve for VOUT/ILOAD.
Reference the package power dissipation curves, Figures 27
and 28, for further information.
8
POWER DISSIPATION (W)
where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• ΘJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation allowed
The total power dissipation produced by an IC is the total
quiescent supply current times the total power supply
voltage, plus the power dissipation in the IC due to the loads,
or:
P DMAX = Σi [ V S × I SMAX + ( V S + – V OUT i ) × I LOAD i ]
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
7
625mW
MSOP10
θJA = +200°C/W
6
5
4
3
2
1
0
0
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
150
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
(EQ. 2)
when sourcing, and:
P DMAX = Σi [ V S × I SMAX + ( V OUT i – V S - ) × I LOAD i ]
when sinking.
(EQ. 3)
POWER DISSIPATION (W)
JEDEC JESD51-7 HIGH EFFECTIVE
1.0 THERMAL CONDUCTIVITY TEST BOARD
0.9
781mW
0.8
MSOP10
θJA = +160°C/W
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
11
FN6922.0
September 25, 2009
EL5421T
Thermal Shutdown
The EL5421T has a built-in thermal protection which ensures
safe operation and prevents internal damage to the device
due to overheating. When the die temperature reaches
+165°C (typical) the device automatically shuts OFF the
outputs by putting them in a high impedance state. When the
die cools by +15°C (typical) the device automatically turns
ON the outputs by putting them in a low impedance or
(normal) operating state.
Power Supply Bypassing and Printed Circuit
Board Layout
performance. Ground plane construction is highly
recommended, trace lengths should be as short as possible
and the power supply pins must be well bypassed to reduce
any risk of oscillation.
For normal single supply operation (the VS- pin is connected
to ground) a 4.7µF capacitor should be placed from VS+ to
ground, then a parallel 0.1µF capacitor should be connected
as close to the device as possible. One 4.7µF capacitor may
be used for multiple devices. For dual supply operation the
same capacitor combination should be placed at each
supply pin to ground.
The EL5421T can provide gain at high frequency, so good
printed circuit board layout is necessary for optimum
Revision History
DATE
REVISION
CHANGE
9/10/09
FN6922.0
Issued File Number FN6922. Initial release of Datasheet with file number FN6922 making this
a Rev 0.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN6922.0
September 25, 2009
EL5421T
Package Outline Drawing
M10.118A (JEDEC MO-187-BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
A
3.0 ± 0.1
0.25
10
DETAIL "X"
CAB
0.18 ± 0.05
SIDE VIEW 2
4.9 ± 0.15
3.0 ± 0.1
1.10 Max
B
PIN# 1 ID
1
2
0.95 BSC
0.5 BSC
TOP VIEW
Gauge
Plane
0.86 ± 0.09
H
0.25
C
3°±3°
SEATING PLANE
0.55 ± 0.15
0.10 ± 0.05
0.10 C
0.23 +0.07/ -0.08
0.08 C A B
DETAIL "X"
SIDE VIEW 1
5.80
4.40
3.00
NOTES:
0.50
0.30
1.
Dimensions are in millimeters.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Plastic or metal protrusions of 0.15mm max per side are not
included.
Plastic interlead protrusions of 0.25mm max per side are not
included.
4.
1.40
5.
Dimensions “D” and “E1” are measured at Datum Plane “H”.
TYPICAL RECOMMENDED LAND PATTERN
6.
This replaces existing drawing # MDP0043 MSOP10L.
13
FN6922.0
September 25, 2009
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