DATASHEET

EL9211, EL9212, EL9214
®
Data Sheet
August 10, 2007
100MHz 100mA VCOM Amplifiers
Features
The EL9211, EL9212, and EL9214 feature 1, 2, and 4
channel high power output amplifiers. They are designed
primarily for generation of VCOM voltages in TFT-LCD
applications. Each amplifier features a -3dB bandwidth of
130MHz with slew rates of 115V/µs. Each device comes in a
thermal package and can drive 300mA peak per output.
• 1, 2, and 4 channel versions
FN7007.1
• 130MHz -3dB bandwidth
• 115V/µs slew rate
• 300mA peak output current
• Supply voltage from 5V to 13.5V
All units are available in Pb-free packaging only and are
specified for operation over the -40°C to +85°C temperature
range.
• Low supply current - <2.4mA per channel
Ordering Information
Applications
PART NUMBER
(Note)
EL9211IWZ-T7*
PART
MARKING
PACKAGE
(Pb-Free)
BAAD
PKG.
DWG. #
5 Ld SOT-23
Tape and Reel
MDP0038
BAAD
5 Ld SOT-23
Tape and Reel
MDP0038
EL9211IYEZ
BBBAA
8 Ld HMSOP
MDP0050
EL9211IYEZ-T7*
BBBAA
8 Ld HMSOP
Tape and Reel
MDP0050
EL9211IYEZ-T13*
BBBAA
8 Ld HMSOP
Tape and Reel
MDP0050
EL9212IYEZ
BBCAA
8 Ld HMSOP
MDP0050
EL9212IYEZ-T7*
BBCAA
8 Ld HMSOP
Tape and Reel
MDP0050
8 Ld HMSOP
Tape and Reel
MDP0050
BBCAA
• TFT-LCD VCOM supply
• Electronics notebooks
• Computer monitors
EL9211IWZ-T7A*
EL9212IYEZ-T13*
• Pb-free available (RoHS compliant)
• Electronics games
• Touch-screen displays
• Portable instrumentation
Pinouts
OUT 1
EL9214IREZ
9214IRE Z
14 Ld HTSSOP MDP0048
EL9214IREZ-T7*
9214IRE Z
14 Ld HTSSOP MDP0048
Tape and Reel
EL9214IREZ-T13*
9214IRE Z
14 Ld HTSSOP MDP0048
Tape and Reel
5 VS+
VS- 2
NC 1
IN- 2
+ -
IN+ 3
4 IN-
IN+ 3
8 NC
7 VS+
+
6 OUT
VS- 4
VOUTA 1
VINA- 2
8 VS+
+
VINA+ 3
VS- 4
+
5 NC
EL9214
(14 LD HTSSOP)
TOP VIEW
EL9212
(8 LD HMSOP)
TOP VIEW
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
EL9211
(8 LD HMSOP)
TOP VIEW
EL9211
(5 LD SOT-23)
TOP VIEW
VOUTA 1
7 VOUTB
VINA- 2
6 VINB-
VINA+ 3
5 VINB+
VS+ 4
14 VOUTD
- +
+ -
12 VIND+
11 VS-
VINB+ 5
VINB- 6
VOUTB 7
1
13 VIND-
10 VINC+
- +
+ -
9 VINC8 VOUTC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2007. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL9211, EL9212, EL9214
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+15V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS +0.5V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . 100mA
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
VS+ = +6V, VS- = -6V, RL = 10kΩ, RF = 0Ω, CL = 10pF to 0V, Gain = -1, TA = +25°C, unless otherwise
specified.
Electrical Specifications
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 2)
TYP
MAX
(Note 2)
UNIT
-6
-1
+2
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 6V
TCVOS
Average Offset Voltage Drift
(Note 1)
IB
Input Bias Current
VCM = 6V
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
1.35
pF
VREG
Load Regulation
CMIR
Common Mode Input Range
CMRR
Common Mode Rejection Ratio
AVOL
Open Loop Gain
VCOM = 6V, -100mA < IL < 100mA
For VIN from -0.5 to +12.5V
10
-1.4
µV/°C
-0.4
µA
-20
+20
mV
-0.5
+12.5
V
75
100
dB
55
70
dB
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = +5mA
ISC
Short Circuit Current
0.9
10.7
1.1
V
10.94
V
300
mA
75
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS from 4.5V to 10.5V
IS
Total Supply Current
EL9211 (no load)
2.3
2.9
mA
EL9212 (no load)
4.5
5
mA
EL9214 (no load)
8.8
9.6
mA
50
DYNAMIC PERFORMANCE
SR
Slew Rate (Note)
2V step, 20% to 80%
tS
Settling to +0.1% (AV = -1)
BW
-3dB Bandwidth
90
115
V/µs
(AV = -1), VO = 2V step
30
ns
RL = 10kΩ, CL = 10pF, AV = +1
130
MHz
RL = 10kΩ, CL = 10pF, AV = -1
52
MHz
GBWP
Gain-Bandwidth Product
RL = 10kΩ, CL = 10pF
63
MHz
PM
Phase Margin
RL = 10kΩ, CL = 10pF
43
°
NOTE:
1. Slew rate is measured on rising and falling edges.
2. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
2
FN7007.1
August 10, 2007
EL9211, EL9212, EL9214
Typical Performance Curves
8
8
6
VS = ±6V
6
AV = +1
4 CL = 10pF
RL=1kΩ
4
0
GAIN (dB)
GAIN (dB)
2
RL=10kΩ
-2
RL=100Ω
-4
2
VS = ±6V
AV = +1
RF = 0Ω
RL = 10kΩ
0
CL=10pF
-2
-4
CL=0pF
-6
-6
-8
-8
-10
-10
-12
100k
1M
100M
10M
-12
100k
500M
1M
FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS RL
80
200
70
PHASE
150
50
100
40
50
30
0
20
-50
GAIN
-20
-100
VS = ±6V
RL = 10kΩ
CL = 10pF
1k
10k
PHASE (°)
GAIN (dB)
60
-150
1M
100k
10M
OUTPUT IMPEDANCE (Ω)
250
70
-10
500M
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS CL
80
10
100M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
0
CL=18pF
-200
-250
100M
VS = ±6V
AV = +1
60
50
40
30
20
10
0
-10
-20
100k
1M
FREQUENCY (Hz)
10M
100M
FREQUENCY (Hz)
FIGURE 3. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 4. CLOSED LOOP OUTPUT IMPEDANCE vs
FREQUENCY
10
0
VS = ±6V
-10
-10
-20
PSRRCMRR (dB)
PSRR (dB)
-20
-30
-40
-50
-60
-30
-40
-50
-60
-70
PSRR+
-70
-80
-80
-90
1k
VS = ±6V
-90
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 5. PSRR
3
100M 500M
-100
1k
10k
100k
1M
10M
100M 500M
FREQUENCY (Hz)
FIGURE 6. CMRR
FN7007.1
August 10, 2007
EL9211, EL9212, EL9214
Typical Performance Curves
(Continued)
-20
CHANNEL SEPARATION
-40
VOLTAGE NOISE (nV/÷Hz)
VS = ±6V
AV = +1
RL = 10kΩ
-30
-50
-60
-70
-80
-90
-100
1000
100
10
-110
1
-120
100k
1M
100
100M
10M
1k
10k
FREQUENCY (Hz)
100M 500M
12
0.0260
0.0250
MAX OUTPUT SWING (VOP-P)
VS = ±6V
AV = +1
RF = 0Ω
VO(P-P) = 1V
RL = 50Ω
0.0255
THD+N (%)
10M
FIGURE 8. VOLTAGE NOISE vs FREQUENCY
FIGURE 7. CHANNEL SEPARATION FOR EL9212/EL9214
0.0245
0.0240
0.0235
0.0230
0.0225
1k
10k
FREQUENCY (Hz)
10
8
6
4
2
0
10k
0.0202
100k
VS = ±6V
AV = +1
RL = 10kΩ
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 10. MAXIMUM OUTPUT SWING vs FREQUENCY
FIGURE 9. THD + NOISE vs FREQUENCY
4.5
80
VS = ±6V
AV = +1
RL = 10kΩ
VIN = ±50mV
70
4.0
3.5
60
VOUT - VS- (V)
OVERSHOOT (%)
1M
100k
FREQUENCY (Hz)
50
40
VS = ±6V
RF = 6kΩ
VIN+ = 6V
3.0
2.5
2.0
1.5
1.0
30
20
0.5
0
20
40
60
80
100
120
LOAD CAPACITANCE (pF)
FIGURE 11. SMALL SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
4
140
0
0
0.05
0.10
0.15
0.20
ISINK (A)
FIGURE 12. VOUT - VS- vs ISINK
FN7007.1
August 10, 2007
EL9211, EL9212, EL9214
Typical Performance Curves
(Continued)
4.5
4.0
VS+ - VOUT (V)
3.5
VS = ±6V
RF = 6kΩ
VIN+ = 6V
CH 2
3.0
VS = ±6V
AV = +1
RL = 10kΩ
VIN
2.5
2.0
1.5
CH 1
VOUT
1.0
0.5
0
0
0.05
0.10
ISOURCE (A)
0.15
0.20
FIGURE 13. VS+ - VOUT vs ISOURCE
CH 2
FIGURE 14. LARGE SIGNAL TRANSIENT RESPONSE
VS = ±6V
AV = +1
RL = 10kΩ
VIN
CH 2
VOUT
CH 1
FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 16. GOING INTO SATURATION POSITIVE EDGE
CH 2
FIGURE 17. GOING INTO SATURATION NEGATIVE EDGE
5
FIGURE 18. DELAY TIME
FN7007.1
August 10, 2007
EL9211, EL9212, EL9214
Typical Performance Curves
(Continued)
3
0.5
2.5
POWER DISSIPATION (W)
±IS
IS (mA)
2
1.5
1
0.5
0
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
0.45
0.4 435mW
0.35
SOT23-5/6
0.3
θJA=230°C/W
0.25
0.2
0.15
0.1
0.05
0
2
2.5
3
3.5
4
4.5
5
5.5
0
6
VS (±V)
VOLTAGE
POWER DISSIPATION (W)
POWER DISSIPATION (W)
3.5
391mW
0.4
SOT23-5/6
0.3
θJA = +256°C/W
0.25
0.2
0.15
0.1
0.05
0
25
50
75 85 100
125
150
150
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD HTSSOP EXPOSED DIEPAD SOLDERED
TO PCB PER JESD51-5
3 2.632W
HTSSOP14
2.5
θJA = +38°C/W
2
1.5
1
0.5
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
POWER DISSIPATION (W)
125
0
0
1
75 85 100
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
0.35
50
AMBIENT TEMPERATURE (°C)
FIGURE 19. SUPPLY CURRENT(PER AMPLIFIER) vs SUPPLY
0.45
25
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
0.9
0.8 694mW
0.7
HTSSOP14
0.6
θJA = +144°C/W
0.5
0.4
0.3
0.2
0.1
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
6
FN7007.1
August 10, 2007
EL9211, EL9212, EL9214
Pin Descriptions
EL9211
(5 LD
SOT-23)
EL9211
(8 LD
HMSOP)
EL9212
(8 LD
HMSOP)
EL9214
(14 LD
HTSSOP)
PIN
NAME
1
6
1
1
VOUTA
FUNCTION
EQUIVALENT CIRCUIT
Amplifier A output
VS+
GND
VS-
CIRCUIT 1
4
2
2
2
VINA-
Amplifier A inverting input
VS+
VS-
CIRCUIT 2
3
3
3
3
VINA+
5
7
8
4
VS+
5
5
VINB+
Amplifier B non-inverting input
(Reference Circuit 2)
6
6
VINB-
Amplifier B inverting input
(Reference Circuit 2)
7
7
VOUTB
Amplifier B output
(Reference Circuit 1)
8
VOUTC
Amplifier C output
(Reference Circuit 1)
9
VINC-
Amplifier C inverting input
(Reference Circuit 2)
10
VINC+
Amplifier C non-inverting input
(Reference Circuit 2)
11
VS-
12
VIND+
Amplifier D non-inverting input
(Reference Circuit 2)
13
VIND-
Amplifier D inverting input
(Reference Circuit 2)
14
VOUTD
Amplifier D output
(Reference Circuit 1)
2
4
4
1, 5, 8
NC
7
Amplifier A non-inverting input
(Reference Circuit 2)
Positive power supply
Negative power supply
Not connected
FN7007.1
August 10, 2007
EL9211, EL9212, EL9214
Application Information
Product Description
The EL9211, EL9212, and EL9214 voltage feedback
amplifiers are fabricated using a high voltage CMOS
process. They exhibit rail-to-rail input and output capability,
are unity gain stable and have low power consumption
(2.4mA per amplifier). These features make the EL9211,
EL9212, and EL9214 ideal for a wide range of generalpurpose applications. Connected in voltage follower mode
and driving a load of 10K, the EL9211, EL9212, and EL9214
have a -3dB bandwidth of 130MHz while maintaining a
115V/µs slew rate. The EL9211 is a single amplifier, EL9212
is a dual amplifier, and EL9214 is a quad amplifier.
Operating Voltage, Input, and Output
The EL9211, EL9212, and EL9214 are specified with a
single nominal supply voltage from 5V to 13.5V or a split
supply with its total range from 5V to 13.5V. Most EL9211,
EL9212, and EL9214 specifications are stable over both the
full supply range and operating temperatures of -40°C to
+85°C. Parameter variations with operating voltage and/or
temperature are shown in the typical performance curves.
Unused Amplifiers
It is recommended that any unused amplifiers in a dual and
quad package be configured as a unity gain follower. The
inverting input should be directly connected to the output
and the non-inverting input tied to the ground plane.
Power Supply Bypassing and Printed Circuit
Board Layout
The EL9211, EL9212, and EL9214 can provide gain at high
frequency. As with any high-frequency device, good printed
circuit board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible and the power supply
pins must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the -VS pin is
connected to ground, a 0.1µF ceramic capacitor should be
placed from +VS to pin and -VS to pin. A 4.7µF tantalum
capacitor should then be connected in parallel, placed in the
region of the amplifier. One 4.7µF capacitor may be used for
multiple devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are to be
used.
Short Circuit Current Limit
The EL9211, EL9212, and EL9214 will limit the short circuit
current to 300mA if the output is directly shorted to the
positive or negative supply. If an output is shorted
indefinitely, the power dissipation could easily increase such
that the device may be damaged. Maximum reliability is
maintained if the output continuous current never exceeds
±65mA. This limit is set by the design of the internal metal
interconnects.
Output Phase Reversal
The EL9211, EL9212, and EL9214 are immune to phase
reversal as long as the input voltage is limited from
-VS -0.5V to +VS +0.5V. Although the device's output will not
change phase, the input's over-voltage should be avoided. If
an input voltage exceeds supply voltage by more than 0.6V,
electrostatic protection diodes placed in the input stage of
the device begin to conduct and over-voltage damage could
occur.
8
FN7007.1
August 10, 2007
EL9211, EL9212, EL9214
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
1
2X
2
3
0.20 C
5
2X
e
0.20 M C A-B D
B
b
NX
0.15 C A-B
1
3
SOT23-5
SOT23-6
A
1.45
1.45
MAX
A1
0.10
0.10
±0.05
A2
1.14
1.14
±0.15
b
0.40
0.40
±0.05
c
0.14
0.14
±0.06
D
2.90
2.90
Basic
E
2.80
2.80
Basic
E1
1.60
1.60
Basic
e
0.95
0.95
Basic
e1
1.90
1.90
Basic
L
0.45
0.45
±0.10
L1
0.60
0.60
Reference
N
5
6
Reference
D
2X
TOLERANCE
Rev. F 2/07
NOTES:
C
A2
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
SEATING
PLANE
A1
0.10 C
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
NX
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
(L1)
6. SOT23-5 version has no center lead (shown as a dashed line).
H
A
GAUGE
PLANE
c
L
9
0.25
0° +3°
-0°
FN7007.1
August 10, 2007
EL9211, EL9212, EL9214
HTSSOP (Heat-Sink TSSOP) Family
MDP0048
0.25 M C A B
D
HTSSOP (HEAT-SINK TSSOP) FAMILY
A
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 20 LD 24 LD 28 LD 38 LD TOLERANCE
PIN #1 I.D.
E
E1
1
0.20 C B A
2X
N/2 LEAD TIPS
(N/2)
TOP VIEW
B
D1
EXPOSED
THERMAL PAD
E2
1.20
1.20
1.20
1.20
Max
0.075
0.075
0.075
0.075
±0.075
A2
0.90
0.90
0.90
0.90
0.90
+0.15/-0.10
b
0.25
0.25
0.25
0.25
0.22
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
6.50
7.80
9.70
9.70
±0.10
D1
3.2
4.2
4.3
5.0
7.25
Reference
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
E2
3.0
3.0
3.0
3.0
3.0
Reference
e
0.65
0.65
0.65
0.65
0.50
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
N
14
20
24
28
38
Reference
NOTES:
0.05
e
1.20
0.075
Rev. 3 2/07
BOTTOM VIEW
C
A
A1
H
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEATING
PLANE
0.10 C
N LEADS
3. Dimensions “D” and “E1” are measured at Datum Plane H.
0.10 M C A B
b
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
SEE DETAIL “X”
c
END VIEW
L1
A A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
10
FN7007.1
August 10, 2007
EL9211, EL9212, EL9214
HMSOP (Heat-Sink MSOP) Package Family
E
B
0.25 M C A B
E1
MDP0050
HMSOP (HEAT-SINK MSOP) PACKAGE FAMILY
MILLIMETERS
1
N
SYMBOL
D
(N/2)+1
(N/2)
PIN #1
I.D.
A
HMSOP8 HMSOP10
TOLERANCE
NOTES
A
1.00
1.00
Max.
-
A1
0.075
0.075
+0.025/-0.050
-
A2
0.86
0.86
±0.09
-
b
0.30
0.20
+0.07/-0.08
-
c
0.15
0.15
±0.05
-
D
3.00
3.00
±0.10
1, 3
D1
1.85
1.85
Reference
-
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
E2
1.73
1.73
Reference
-
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
-
TOP VIEW
E2
EXPOSED
THERMAL PAD
D1
BOTTOM VIEW
Rev. 1 2/07
e
NOTES:
H
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
C
SEATING
PLANE
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
0.08 M C A B
b
0.10 C
N LEADS
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
L1
A
c
END VIEW
SEE DETAIL "X"
A2
GAUGE
0.25 PLANE
L
3° ±3°
A1
DETAIL X
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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11
FN7007.1
August 10, 2007
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