DATASHEET

ISL45042A
®
Data Sheet
July 9, 2008
FN6158.4
LCD Module Calibrator
Features
The VCOM voltage of an LCD panel needs to be adjusted to
remove flicker. The ISL45042A can be used to digitally
adjust a panel’s VCOM voltage by controlling its output sink
current. The output of the ISL45042A is connected to an
external voltage divider and an external VCOM buffer
amplifier. In this application, the user can control the VCOM
voltage with 7-bit accuracy (128 steps). Once the desired
VCOM setting is obtained, the settings can be stored in the
non-volatile EEPROM memory, which would then be
automatically recalled during every power-up.
• 128-Step Adjustable Sink Current Output
The VCOM adjustment and non-volatile memory
programming is through a single interface pin (CTL). Once
the desired programmed value is obtained, the Counter
Enable pin (CE) can be used to prevent further adjustment
or programming.
The full-scale sink current of the ISL45042A is set using an
external resistor connected to the SET pin. The full-scale
sink current determines the lowest voltage of the external
voltage divider.
The ISL45042A is available in an 8 Ld 3mmx3mm TDFN
package with a maximum thickness of 0.8mm for ultra thin
LCD panel design.
• 2.6V to 3.6V Logic Supply Voltage Operating Range
• 4.5V to 20V Analog Supply Voltage Range
• Rewritable EEPROM for storing the optimum VCOM value
• Output Adjustment Enable/Disable Control
• Output Guaranteed Monotonic Over-Temperature
• Two Pin Adjustment, Programming and Enable
• Ultra Thin 8 Ld 3mmx3mm DFN (0.8mm max)
• Pb-Free (RoHS compliant)
Applications
• LCD Panels
Ordering Information
PART NUMBER
(Note)
TEMP.
RANGE
PART
(°C)
MARKING
PKG.
DWG. #
ISL45042AIRZ
42AZ
-40 to +85 8 Ld 3x3 TDFN
L8.3x3A
ISL45042AIRZ-T*
42AZ
-40 to +85 8 Ld 3x3 TDFN
Tape and Reel
L8.3x3A
ISL45042AIRZ-TK* 42AZ
-40 to +85 8 Ld 3x3 TDFN
Tape and Reel
L8.3x3A
Pinout
ISL45042A
(8 LD TDFN)
TOP VIEW
PACKAGE
(Pb-Free)
*Please refer to TB347 for details on reel specifications.
OUT 1
8
SET
AVDD 2
7
CE
N/C 3
6
CTL
GND 4
5
VDD
1
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005-2008. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL45042A
Pin Descriptions
PIN
FUNCTION
OUT
Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink
current divided by 128. See SET pin function in “Pin Descriptions” on page 2 for the maxim adjustable sink current setting.
AVDD
High-Voltage Analog Supply. Connects to top of external resistor divider to determine the VCOM voltage. Typically 10V to 20V. Bypass
to GND with 0.1µF de-coupling capacitor.
N/C
No Connect. Not internally connected.
GND
Ground connection.
VDD
ISL45042A power supply input. Bypass to GND with 0.1µF de-coupling capacitor.
CTL
Internal Counter Up/Down Control and Internal EEPROM Programming Control Input. If CE is high, a mid-to-low transition increments
the 7-bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT. A mid-to-high
transition decrements the 7-bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage
at OUT. Applying 4.9V and above with appropriately arranged timing will overwrite EEPROM with the contents in the 7-bit counter.
See EEPROM Programming section in “Electrical Specifications” table on page 4 for details.
CE
Counter Enable Pin. Connect CE to VDD to enable adjustment of the output sink current. Float or connect CE to GND to prevent
further adjustment or programming (note: the CE pin has an internal pull-down resistor).
SET
Maximum Sink Current Adjustment Point. Connect a resistor from the SET pin to GND to set the maximum adjustable sink current of
the OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET.
Block Diagram
ISL45042A
AVDD
CE
400kΩ
TO
500kΩ
IBIAS
UP
IOUT
DWN
CTL
DIGITAL INTERFACE
ANALOG DCP AND
PWRUP
CURRENT OUTPUT
UP/DOWN COUNTER
WITH THRESHOLD
POR
SENSORS
PRGM
BLOCK
WITH PRESET
SET
LATCHES
READ
PRGM MEMORY
POR
EEPROM
OR
PRGM
GND
NVL MEMORY
VDD
2
FN6158.4
July 9, 2008
ISL45042A
Absolute Maximum Ratings
Thermal Information
VDD to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4V
Input Voltages to GND
SET, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V
CTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +17V
Output Voltages to GND
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V
ESD Rating
Human Body Model
Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75kV
CTL to GND (No EEPROM Disruption) . . . . . . . . . . . . . . . .8kV
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
8 Ld TDFN Package. . . . . . . . . . . . . . .
47
12
Moisture Sensitivity (see Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Erase/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10,000
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 years @ +85°C
Operating Conditions
Temperature Range
ISL45042AIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, RSET = 24.9kΩ; Unless Otherwise Specified.
Typicals are at TA = +25°C
PARAMETER
SYMBOL
TEMP
(°C)
MIN
(Note 9)
TYP
0 to 85
3
-
3.6
V
For Operation
Full
2.6
-
3.6
V
CE = VDD (Note 7)
Full
-
-
50
µA
CE = GND
Full
-
-
20
µA
Full
4.5
-
20
V
TEST CONDITIONS
MAX
(Note 9) UNITS
DC CHARACTERISTICS
VDD Supply Range
VDD
VDD Supply Current
IDD
For Programming
AVDD Supply Range
AVDD
AVDD Supply Current
IAVDD
(Note 4)
Full
-
-
20
µA
CTL High Voltage
CTLIH
2.6V < VDD < 3.6V
Full
0.7*VDD
-
0.8*VDD
V
CTL Low Voltage
CTLIL
2.6V < VDD < 3.6V
Full
0.2*VDD
-
0.3*VDD
V
CTL High Rejected Pulse Width
CTLIHRPW
Full
20
-
-
µs
CTL Low Rejected Pulse Width
CTLILRPW
Full
20
-
-
µs
CTL High Minimum Pulse Width
CTLIHMPW
Full
-
-
200
µs
CTL Low Minimum Pulse Width
CTLILMPW
Full
-
-
200
µs
CTLMTC
Full
-
-
10
µs
CTL = GND
Full
-
-
10
µA
CTL = VDD
Full
-
-
10
µA
(Note 6)
Full
-
10
-
pF
CTL Minimum Time Between
Counts
CTL Input Current
ICTL
CTL Input Capacitance
CTLCAP
CE Input Low Voltage
CEIL
2.6V < VDD < 3.6V
Full
-
-
0.4
V
CE Input High Voltage
CEIH
2.6V < VDD < 3.6V
Full
0.64*VDD
-
-
V
CE Minimum Start-Up Time
CEST
(Note 6)
Full
-
1
-
ms
2.6V < VDD < 3.6V, (Note 3)
Full
4.9
-
15.75
V
CTL EEPROM Program Voltage
CTLPROM
3
FN6158.4
July 9, 2008
ISL45042A
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, RSET = 24.9kΩ; Unless Otherwise Specified.
Typicals are at TA = +25°C (Continued)
PARAMETER
SYMBOL
CTL EEPROM Programming
Signal Time
CTLPT
Programming Time
TEST CONDITIONS
>4.9V
PT
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9) UNITS
Full
200
-
-
µs
Full
-
-
100
ms
SET Voltage Resolution
SETVR
(Note 5)
Full
7
7
7
Bits
SET Differential Nonlinearity
SETDN
Monotonic Over-Temperature
Full
-
-
±1
LSB
SET Zero-Scale Error
SETZSE
Full
-
-
±2
LSB
SET Full-Scale Error
SETFSE
Full
-
-
±8
LSB
SET Current
SET External Resistance
AVDD to SET Voltage Attenuation
ISET
Through RSET (Note 8)
Full
-
20
-
µA
SETER
To GND, AVDD = 20V
Full
10
-
200
kΩ
To GND, AVDD = 4.5V
Full
2.25
-
45
kΩ
Full
-
1:20
-
V/V
Full
-
20
-
µs
Full
VSET + 0.5V
-
13
V
25 to 55
-
<10
-
mV
AVDD to SET
OUT Settling Time
OUTST
OUT Voltage Range
to ±0.5 LSB Error Band (Note 6)
VOUT
OUT Voltage Drift
OUTVD
(Note 6)
NOTES:
3. CTL signal only needs to be greater than 4.9V to program EEPROM.
4. Tested at AVDD = 20V.
5. The Counter value is set to mid-scale ±4 LSB’s in the Production.
6. Simulated and Determined via Design and NOT Directly Tested.
7. Simulated Maximum Current Draw when Programming EEPROM is 23mA; should be considered when designing Power Supply.
8. A Typical Current of 20µA is Calculated using the AVDD = 10V and RSET = 24.9kΩ. Reference “RSET Resistor” on page 6.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Application Information
AVDD
AVDD
ISL45042A
CTL
CE
SET
ISINK
The application circuit to adjust the VCOM voltage in an LCD
panel is shown in Figure 1. The ISL45042A has a 128-step
sink current resolution. The output is connected to an
external voltage divider, that results in decreasing the output
VCOM voltage as you increase the ISL45042A sink current.
R1
OUT
R2
RSET
CTL Pin
VCOM
BLUE
GREEN
RED
+
-
COLUMN
DRIVER
SINGLE PIXEL
IN LCD PANEL
FIGURE 1. VCOM ADJUSTMENT IN AN LCD PANEL
4
The adjustment of the output VCOM voltage and the
programming of the non-volatile memory are provided
through a single pin called CTL when the CE pin is high.
The output VCOM voltage is increased with a mid (VDD/2) to
high transition (0.8*VDD) on the CTL pin. The output VCOM
voltage is decreased with a mid (VDD/2) to low transition
(0.3*VDD) on the CTL pin (see Figure 7). Once the minimum
or maximum value is reached on the 128 steps, the device
will not overflow or underflow beyond that minimum or
maximum value.
Programming of the non-volatile memory occurs when the
CTL pin exceeds 4.9V. The CTL signal needs to remain
above 4.9V for more than 200µs. The level and timing
FN6158.4
July 9, 2008
ISL45042A
needed to program the non-volatile memory is given in
Figure 2. It then takes a maximum of 100ms for the
programming to be completed inside the device.
CTL VOLTAGE
>200µs
4.9V
CE Pin
To adjust the output voltage, the CE pin must be pulled high
(VDD). The CE pin has an internal pull-down resistor to
prevent unwanted reprogramming of the EEPROM. The
impedance of this resistor is 400kΩ to 500kΩ (see
RINTERNAL in Figure 6).
The CE pin has a Schmitt trigger on the input to prevent
false triggering during slow transitions of the CE pin.
Transitions of the CE pin are recommended to be less than
10µs.
CTLPT
TIME
FIGURE 2. EEPROM PROGRAMMING
When the part is programmed, the counter setting is loaded
into the non-volatile memory. This value will be loaded from
the nonvolatile memory during initial power-up or when the
CE pin is pulled low.
Once the programming is completed, it is recommended that
the user float the CLT pin. The CTL pin is internally tied to a
resistor network connected to ground. If left floating, the
voltage at the CTL pin will equal VDD/2. Under these
conditions, no additional pulses will be seen by the Up/Down
counter via the CTL pin. To prevent further programming,
ground the CE pin.
CTL should have a noise filter to reduce bouncing or noise
on the input that could cause unwanted counting when the
CE pin is high. The board should have an additional ESD
protection circuit, with a series 1kΩ resistor and a shunt
0.01µF capacitor connected on the CTL pin, (see Figure 3).
Replacing Existing Mechanical Potentiometer
Circuits
Figure 4 shows the common adjustment mechanical circuits
and equivalent replacement with the ISL45042A.
Expected Output Voltage
The ISL45042A provides an output sink current, which
lowers the voltage on the external voltage divider (VCOM
output voltage). Equations 1 and 2 can be used to calculate
the output current (IOUT) and output voltage (VOUT) values.
AV DD
Setting
I OUT = --------------------- x --------------------------20 ( R SET )
128
(EQ. 1)
R1
⎛ R2 ⎞
⎛
⎞
Setting
V OUT = ⎜ ---------------------⎟ AV DD ⎜ 1 – --------------------- x ---------------------------⎟
128
R
+
R
20
(
R
⎝ 1
⎝
2⎠
SET )⎠
(EQ. 2)
NOTE: Where setting is an integer between 1 and 128.
1kΩ
To avoid unintentional adjustment, the ISL45042A
guarantees to reject CTL pulses shorter than 20µs.
During Initial Power-up (only), to avoid the possibility of a
false pulse (since the internal comparators come up in an
unknown state), the very first CTL pulse is ignored. See
Figure 7 for the timing information.
ISL45042A
CTL
0.01µF
FIGURE 3. EXTERNAL ESD PROTECTION ON CTL PIN
AVDD
Ra
AVDD
AVDD
Rb
VCOM
+
ISL45042A
SET
R1
+
OUT
VCOM
R2
Rc
R1 = R a
R2 = R b + R c
RSET
RSET = (Ra(Rb + Rc)) / 20Rb
FIGURE 4. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING THE ISL45042A
5
FN6158.4
July 9, 2008
ISL45042A
Table 1 gives the calculated value of VOUT for resistors
values of: RSET = 24.9kΩ, R1 = 200kΩ, R2 = 243kΩ, and
AVDD = 10V.
TABLE 1. CALCULATED VCOM OUTPUT VOLTAGES
SETTING VALUE
VOUT
1
5.468
10
5.313
20
5.141
30
4.969
40
4.797
50
4.625
60
4.453
70
4.281
80
4.109
90
3.936
100
3.764
110
3.592
128
3.282
2. CE pin = VDD.
3. Change counter value with CTL pin to desired value.
4. CTL = more than 4.9V and 200ms. Counter value
programmed.
5. Change the counter value with CTL pin to a different
value.
6. CE pin = Ground.
7. Check that the output value is the one programmed in
Step 4.
Generating VDD and CE supply from a Larger
Voltage Source
The external RSET resistor sets the full-scale sink current that
determines the lowest voltage of the external voltage divider R1
and R2 (see Figure 1). The voltage difference between the
VOUT pin and ISET pin (see Figure 5) has to be greater than
1.75V. This will keep the output MOS transistor in the saturation
region. Expected current settings and 7-bit accuracy occurs
when the output MOS transistor is operating in the saturation
region. Figure 5 shows the internal connection for the output
MOS transistor. The value of the AVDD supply sets the voltage
at the source of the output transistor. This voltage is equal to
(Setting/128) x (AVDD/20). The ISET current is therefore equal
to (Setting/128) x (AVDD/20 x RSET). The value of the Drain
voltage is found using Equation 2. The values of R1 and R2 in
Equation 2, should be determined (setting equal to 128) so the
minimum value of VOUT is greater than 1.75V + AVDD/20.
VOUT PIN
AVDD = 15V
R1
AVDD
VSAT
0.5V
RSET
The following sequence can be used to verify the
programmed value without having to sequence the VDD
supply. To verify the programmed value, follow the following
steps. The ISL45042A will read memory contents and be set
to that value when the CE pin is grounded.
1. Power-up the ISL45042A.
RSET Resistor
SETTING AV DD
----------------------------x -----------------128
20
Verifying the Programmed Value
The CE pin has an internal pull-down resistor (see
RINTERNAL in Figure 6). The impedance of this resistor is
400kΩ to 500kΩ. If your design is using a resistor divider
network to generate the 3.3V supply (for both VDD and CE to
enable programming) from a larger voltage source, the
400kΩ (worst case) resistor needs to be taken into account
as a parallel resistance when the CE pin is connected to this
source. Another design concern is to be able to provide
enough supply current during programming. The ISL45042A
draws about 2mA during this process. Recommended
resistor values are shown in Figure 6. This design will result
in an additional 0.83mA quiescent current flowing through
resistors RA and RB.
VCC = 5V
ISL45042A
RA
2kΩ
CE
VCE
CE LOGIC
SCHMITT
TRIGGER
RB
4kΩ
RINTERNAL = 400kΩ to 500kΩ
R2
ISET PIN
FIGURE 6. APPLICATION GENERATING VDD AND VCE
VOLTAGES
FIGURE 5. OUTPUT CONNECTION CIRCUIT EXAMPLE
Power Supply Sequence
The recommendation for power supply sequence would be
to power down the part first (VDD, AVDD), after 100ms if
programming has occurred, and then power-down the
control power supplies (CTL, CE).
6
FN6158.4
July 9, 2008
ISL45042A
ISL45042A Truth Table
TABLE 2. TRUTH TABLE
The ISL45042A truth table is shown in Table 2. For proper
operation the CE should be disabled (pulled low) before
powering the device down to assure that the glitches and
transients will not cause unwanted EEPROM overwriting.
INPUT
OUTPUT
CTL
CE
VDD
OUT
ICC
MEMORY
Mid to Hi
Hi
VDD
Increment
Normal
X
Mid to Lo
Hi
VDD
Decrement
Normal
X
X
Lo
VDD
No Change Increased
Read
>4.9V
Hi
VDD
No Change Increased
Program
.
CEST
CTLIHRPW
CTLMTC
CTL HIGH
CTL VDD/2
CTL LOW
CTLIHMPW
CTLILMPW
CTLILRPW
CE
STOP PROGRAMMING
START PROGRAMMING
COUNTER
OUTPUT
START PROGRAMMING
UNDEF.
78
79
NOTE:
AFTER POWER IS 1ST APPLIED,
THE VERY 1ST CTL PULSE IS IGNORED
7A
7B
7A
IGNORES 1ST PULSE
AFTER PROGRAMMING
VCOM
THE TIMING DIAGRAM ABOVE SHOWS POST POWER-UP TIMING.
FIGURE 7. ISL45042A TIMING DIAGRAM
7
FN6158.4
July 9, 2008
ISL45042A
Thin Dual Flat No-Lead Plastic Package (TDFN)
L8.3x3A
2X
0.15 C A
A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.15 C B
E
SYMBOL
MIN
A
0.70
A1
-
A3
6
INDEX
AREA
b
TOP VIEW
B
0.10 C
//
C
SEATING
PLANE
SIDE VIEW
D2
(DATUM B)
A3
7
-
0.30
0.35
5, 8
2.40
7, 8, 9
1.60
7, 8, 9
-
2.30
-
1.50
-
0.65 BSC
-
k
0.25
-
-
-
L
0.20
0.30
0.40
8
N
8
Nd
4
8
2
3
Rev. 3 11/04
NOTES:
D2/2
1
6
INDEX
AREA
0.08 C
0.80
0.05
3.00 BSC
1.40
e
A
0.02
NOTES
3.00 BSC
2.20
E
E2
0.75
MAX
0.20 REF
0.25
D
D2
NOMINAL
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
NX k
4. All dimensions are in millimeters. Angles are in degrees.
(DATUM A)
E2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2/2
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
e
8
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
5
(Nd-1)Xe
REF.
0.10 M C A B
BOTTOM VIEW
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-WEEC-2 except for the “L” min
dimension.
CL
(A1)
NX (b)
L1
5
10 L
e
SECTION "C-C"
TERMINAL TIP
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
FN6158.4
July 9, 2008
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