DATASHEET

Programmable VCOM Calibrator with EEPROM and
Output Buffer
ISL24212
Features
The ISL24212 is an 8-bit programmable current sink that can be
used in conjunction with an external voltage divider to generate a
voltage source (VCOM) positioned between the analog supply
voltage and ground. The current sink’s full-scale range is
controlled by an external resistor, RSET. With the appropriate
choice of external resistors R1 and R2, the VCOM voltage range
can be controlled between any arbitrary voltage range. The
ISL24212 has an 8-bit data register and 8-bit EEPROM for storing
both a volatile and a permanent value for its output, accessible
through a single up/down counter interface pin (CTL). After the
part is programmed with the desired VCOM value, the Counter
Enable pin (CE) can be grounded to prevent further changes. On
every power-up, the EEPROM contents are automatically
transferred to the data register and the pre-programmed output
voltage appears at the VCOM_OUT pin.
• Adjustable 8-bit, 256-Step, Current Sink Output
The ISL24212 also features an integrated, wide-bandwidth, high
output drive buffer amplifier that can directly drive the VCOM
input of an LCD panel.
• LCD Panel VCOM Generator
The ISL24212 is available in an 10 Ld 3mm x 3mm TDFN
package. This package has a maximum height of 0.8mm for very
low profile designs. The ambient operating temperature range is
-40°C to +85°C.
VDD
6
• 60MHz VCOM Buffer/Amplifier
• On-Chip 8-Bit EEPROM
• Up/Down Counter Interface
• Guaranteed Monotonic Over-Temperature
• 4.5V to 19.0V Analog Supply Range for Normal Operation
(10.8V Minimum Analog Supply Voltage for Programming)
• 2.25V to 3.6V Logic Supply Voltage Operating Range
• Pb-free (RoHS-compliant)
• Ultra-Thin 10 Ld TDFN (3x3x0.8mm max)
Applications
• Electrophoretic Display VCOM Generator
Related Literature
• See Application Note “ISL24212IRTZ-EVALZ Evaluation Board
User Guide” (Coming Soon)
AVDD
3
R1
I/O PIN*
MICROCONTROLLER
I/O PIN
7
8
DVR_OUT
2
CTL
CE
ISL24212
INN
VCOM_OUT
SET
1
R2
LCD PANEL
10
VCOM
9
RSET
5
* 0, 1, TRISTATE
FIGURE 1. TYPICAL ISL24212 APPLICATION
March 15, 2011
FN7590.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL24212
Block Diagram
AVDD
VDD
6
DNC
CTL
CE
3
4
7
DIGITAL
INTERFACE
UP/DOWN
COUNTER
VCOM BUFFER
AMPLIFER
ANALOG DCP
AND
CURRENT SINK
DAC
REGISTERS
DVR_OUT
Q1
8
2
A1
8-Bit EEPROM
A2
10
VCOM_OUT
1
INN
CS
9
SET
5
GND
FIGURE 2. BLOCK DIAGRAM OF THE ISL24212
Pin Configuration
ISL24212
(10 LD TDFN)
TOP VIEW
10 VCOM_OUT
INN 1
DVR_OUT 2
AVDD 3
EXPOSED
THERMAL
PAD*
9 SET
8 CE
DNC 4
7 CTL
GND 5
6 VDD
(*CONNECT THERMAL PAD TO GND)
Pin Descriptions
PIN
NAME
PIN
NUMBER
INN
1
Negative input of the op amp. To create a unity-gain VCOM voltage buffer, connect this pin to the VCOM_OUT pin.
DVR_OUT
2
Current Sink Output. The sink current into the DVR_OUT (Digital Variable Resistor) pin is equal to the DAC setting times the maximum
adjustable sink current divided by 256. See the “SET” pin function description (pin 9) for setting the maximum adjustable sink
current.
AVDD
3
High-Voltage Analog Supply. Bypass to GND with 0.1µF capacitor.
DNC
4
Do Not Connect to external circuitry. It is acceptable to ground this pin.
GND
5
Ground connection.
VDD
6
Digital power supply input. Bypass to GND with 0.1µF capacitor.
CTL
7
Up/Down Control for internal counter and Internal EEPROM Programming Control Input. When CE is high:
A low-to-mid transition increments the 8-bit counter, adding 1 to the DAC setting, increasing the DVR_OUT sink current, and
lowering the divider voltage at the DVR_OUT pin.
A high-to-mid transition decrements the 8-bit counter, subtracting 1 from the DAC setting, decreasing the DVR_OUT sink current,
and increasing the divider voltage at the DVR_OUT pin.
To program the EEPROM, take this pin to >4.9V (see “CTL EEPROM Programming Signal Time” in the “Electrical Specification”
table on page 5 for details). Float when not in use.
FUNCTION
2
FN7590.0
March 15, 2011
ISL24212
Pin Descriptions (Continued)
PIN
NAME
PIN
NUMBER
CE
8
Counter Enable Pin. Connect CE to VDD to enable adjustment of the output sink current. Float or connect CE to GND to prevent
further adjustment or programming (Note: the CE pin has an internal 500nA pull-down sink current). The EEPROM value will be
copied to the register on a VOH to VOL transition.
SET
9
Maximum Sink Current Adjustment Point. Connect a resistor from SET to GND to set the maximum adjustable sink current of the
DVR_OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET.
VCOM_OUT
10
Output of the buffer amplifier
PAD
-
FUNCTION
Thermal pad should be connected to system ground plane to optimize thermal performance.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL24212IRTZ
4212
ISL24212IRTZ-EVALZ
Evaluation Board
INTERFACE
TEMP RANGE
(°C)
COUNTER
-40 to +85
PACKAGE
(Pb-Free)
10 Ld 3x3 TDFN
PKG.
DWG. #
L10.3x3A
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page ISL24212. For more information on MSL please see techbrief TB363.
3
FN7590.0
March 15, 2011
ISL24212
Absolute Maximum Ratings
Thermal Information
Supply Voltage
AVDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
Input Voltage with respect to Ground
SET, INN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
SCL, SDA and WP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDD+0.3V
Output Voltage with respect to Ground
DVR_OUT, VCOM_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD
Continuous Output Current
DVR_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
VCOM_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100mA
ESD Ratings
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 7kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 2kV
Latch Up (Tested per JESD 78, Class II, Level A). . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
10 Ld TDFN Package (Notes 4, 5) . . . . . . .
53
11
Moisture Sensitivity (see Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Range
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 19V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5), VCOM_OUT pin
connected to INN, unless otherwise specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
DC CHARACTERISTICS
VDD
VDD Supply Range - Operating
2.25
3.6
V
AVDD
AVDD Supply Range Supporting EEPROM Programming
10.8
19
V
AVDD
AVDD Supply Range for Wide-Supply Operation without
EEPROM Programming
4.5
19
V
IDD
VDD Supply Current
CTL = 0.5*VDD
95
300
µA
IAVDD
AVDD Supply Current
CTL = 0.5*VDD
3.8
6.5
mA
DVR_OUT CHARACTERISTICS
SETZSE
SET Zero-Scale Error
±3
LSB
SETFSE
SET Full-Scale Error
±8
LSB
VDVR_OUT
SET VD
IDVR_OUT
DVR_OUT Voltage Range
VSET + 1.75
AVDD
SET Voltage Drift
7
Maximum DVR_OUT Sink Current
4
V
µV/°C
mA
INL
Integral Non-Linearity
±2
LSB
DNL
Differential Non-Linearity
±1
LSB
OUTPUT AMPLIFIER CHARACTERISTICS
VOS
TCVOS
IB
Input Offset Voltage
±2
Input Offset Voltage Drift
-6.3
Input Bias Current
±0.01
±15
mV
µV/°C
±1
μA
CMRR
Common-Mode Rejection Ratio
55
75
dB
PSRR
Power Supply Rejection Ratio
60
82
dB
AVOL
Open Loop Gain
55
75
VOL
Output Swing Low
IL = -5mA
4
50
dB
150
mV
FN7590.0
March 15, 2011
ISL24212
Electrical Specifications
Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5), VCOM_OUT pin
connected to INN, unless otherwise specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
SYMBOL
PARAMETER
VOH
Output Swing High
ISC
Short Circuit Current (Sinking)
TEST CONDITIONS
IL = 5mA
Short Circuit Current (Sourcing)
SR
tS
BW
MIN
(Note 6)
TYP
MAX
(Note 6)
17.85
17.9
V
300
430
mA
UNITS
450
555
mA
Slew Rate (Rising)
1KΩ || 8pF Load
70
116
V/µs
Slew Rate (Falling)
1KΩ || 8pF Load
50
93
V/µs
Settling Time to 0.2%
150
ns
-3dB Bandwidth
60
MHz
EEPROM CHARACTERISTICS
tPROG
EEPROM Programming Time (internal)
100
ms
UP/DOWN COUNTER CONTROL INPUTS (SEE FIGURE 11)
VIH
CE and CTL Input Logic High Threshold
VIL
CE and CTL Input Logic Low Threshold
ICS_PD
ICTL
tST
0.7*VDD
CE Input Pull Down Current Sink
CTL Input Bias Current
CE to CTL Start Delay
V
0.5
0.3*VDD
V
1.5
µA
CTL = GND (sourcing)
7
15
µA
CTL = VDD (sinking)
7
15
µA
50
µs
tREAD
EEPROM Recall Time (after CE de-asserted)
10
ms
tH_REJ
CTL High Pulse Rejection Width
20
µs
tL_REJ
CTL Low Pulse Rejection Width
20
µs
tH_MIN
CTL High Minimum Valid Pulse Width
200
µs
tL_MIN
CTL Low Minimum Valid Pulse Width
200
µs
tMTC
CTL Minimum Time Between Counts
10
µs
VPROG
CTL EEPROM Program Voltage (see Figure 9)
4.9
tPROG
CTL EEPROM Programming Signal Time
19
V
200
µs
tH_PROP
CTL High-to-Mid to DVR_OUT propagation time
65
µs
tL_PROP
CTL Low-to-Mid to DVR_OUT propagation time
65
µs
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
5
FN7590.0
March 15, 2011
ISL24212
Application Information
AVDD
LCD panels have a VCOM (common voltage) that must be precisely
set to minimize flicker. Figure 3 shows a typical VCOM adjustment
circuit using a mechanical potentiometer, and the equivalent
circuit replacement using the ISL24212. Having a digital counter
interface enables automatic, digital flicker minimization during
production test and alignment. After programming, the counter
interface is no longer needed - the ISL24212 automatically powers
up with the correct VCOM voltage programmed previously.
The ISL24212 uses a digitally controllable potentiometer (DCP),
with 256 steps of resolution (see Figure 4) to change the current
drawn at the DVR_OUT pin, which then changes the voltage
created by the R1 - R2 resistor divider (see Figure 5). The DVR_OUT
voltage is then buffered by A2 to generate a buffered output voltage
at the VCOM_OUT pin, capable of directly driving the VCOM input of
an LCD panel. The amount of current sunk is controlled by the
setting of the DCP, which is recalled at power-up from the
ISL24212’s internal EEPROM. The EEPROM is typically
programmed during panel manufacture. As noted in the
“Electrical Specifications” on page 4, the ISL24212 requires a
minimum AVDD voltage of 10.8V for EEPROM programming, but
will work in normal operation down to 4.5V after the EEPROM
has been programmed, with no additional EEPROM writing.
AVDD
REGISTER
VALUE
19R
255
AVDD
20
254
253
VDCP
252
R
251
2
1
0
FIGURE 4. SIMPLIFIED SCHEMATIC OF DCP
Output Current Sink
Figure 5 shows the schematic of the DVR_OUT current sink. The
combination of amplifier A1, transistor Q1, and resistor RSET
forms a voltage-controlled current source, with the voltage
determined by the DCP setting.
AVDD
RA
RB
R1
I DVR_OUT
DVR_ OUT
AVDD
VCOM
R1 = RA
R2
RC
R2 = RB+RC
RSET = RARB + RARC
VDCP
20RB
VCOM_OUT
Q1
A2
VDD
AVDD
VSAT
R1
ISL24212
IOUT
R2
VOUT
A1
AVDD
VCOM_OUT
DVR_OUT
INN
VCOM
GND
INN
SET
SET
IOUT
VSET = VDCP = IOUT * RSET
RSET
RSET
FIGURE 5. CURRENT SINK CIRCUIT
FIGURE 3. MECHANICAL ADJUSTMENT REPLACEMENT
DCP (Digitally Controllable Potentiometer)
The DCP controls the voltage that ultimately controls the SET
current. Figure 4 shows the relationship between the register
value and the DCP’s tap position. Note that a register value of 0
selects the first step of the resistor string. The output voltage of
the DCP is given in Equation 1:
RegisterValue + 1 AV DD
V DCP = ⎛ ---------------------------------------------------⎞ ⎛ --------------⎞
⎝
⎠ ⎝ 20 ⎠
256
6
The external RSET resistor sets the full-scale (maximum) sink current
that can be pulled from the DVR_OUT node. The relationship
between IDVR_OUT and Register Value is shown in Equation 2.
V DCP
RegisterValue + 1 AV DD
1
I DVROUT = ------------- = ⎛ ---------------------------------------------------⎞ ⎛ --------------⎞ ⎛ -------------⎞
⎝
⎠ ⎝ 20 ⎠ ⎝ R
⎠
256
R SET
SET
(EQ. 2)
(EQ. 1)
FN7590.0
March 15, 2011
ISL24212
The maximum value of IDVR_OUT can be calculated by
substituting the maximum register value of 255 into Equation 2,
resulting in Equation 3:
First, verify that our chosen RSET meets the minimum
requirement described in Equation 5:
A VDD
------------------DVROUT ( MAX ) = 20R
SET
15
⎛
⎞
⎛
⎞
------⎜
⎟
⎜
⎟
16
( 7.5kΩ ) > ⎜ R SET ( MIN ) = ⎜ ------------------------------⎟ = 0.163kΩ⎟
15
⎜ ⎛ 6.5V – -------⎞ ⎟
⎜
⎟
⎝⎝
⎝
⎠
20⎠ ⎠
(EQ. 3)
Equation 2 can also be used to calculate the unit sink current
step size per Register Code, resulting in Equation 4:
AV DD
I STEP = ---------------------------------------------( 256 ) ( 20 ) ( R SET )
(EQ. 4)
Determination of RSET
The ultimate goal for the ISL24212 is to generate an adjustable
voltage between two endpoints, VCOM_MIN and VCOM_MAX, with
a fixed power supply voltage, AVDD. This is accomplished by
choosing the correct values for RSET, R1 and R2. The exact value
of RSET is not critical. Values from 1k to more than 100k will
work under most conditions. Equation 5 calculates the minimum
RSET value:
AV DD
⎛
⎞
-------------⎜
⎟
16
R SET ( MIN ) = ⎜ ------------------------------------------------------⎟ ( kΩ )
⎜
AV DD ⎟
⎜⎛V
– --------------⎞ ⎟
⎝ ⎝ OUT ( MIN )
20 ⎠ ⎠
(EQ. 5)
Note that this is the absolute minimum value for RSET. Larger
RSET values reduce quiescent power, since R1 and R2 are
proportional to RSET. The ISL24212 is tested with a 5kΩ RSET.
Determination of R1 and R2
With AVDD, VCOM(MIN) and VCOM(MAX) known and RSET chosen
per the above requirements, R1 and R2 can be determined using
Equations 6 and 7:
⎛ V COM ( MAX ) – V COM ( MIN ) ⎞
R 1 = 5120 ⋅ R SET ⎜ ---------------------------------------------------------------------------------⎟
⎝ 256 ⋅ V COM ( MAX ) – V COM ( MIN )⎠
(EQ. 6)
V COM ( MAX ) – V COM ( MIN )
⎛
⎞
R 2 = 5120 ⋅ R SET ⎜ ---------------------------------------------------------------------------------------------------------------------⎟
255
AV
⋅
⎝
DD + V COM ( MIN ) – 256 ⋅ V COM ( MAX )⎠
(EQ. 7)
Final Transfer Function
The voltage at the DVR_OUT pin can be calculated from
Equation 8:
⎛ R2 ⎞ ⎛
RegisterValue + 1 ⎛ R 1 ⎞ ⎞
V DVROUT = AV DD ⎜ --------------------⎟ ⎜ 1 – --------------------------------------------------- ⎜ --------------------⎟ ⎟
R
+
R
256
⎝ 20R SET⎠ ⎠
⎝ 1 2⎠ ⎝
(EQ. 8)
With amplifier A2 in the unity-gain configuration (VCOM_OUT tied
to INN as shown in Figure 5), VDVROUT = VCOM_OUT = VCOM.
Example
As an example, suppose the AVDD supply is 15V, the desired
VCOM_MIN= 6.5V and the desired VCOM_MAX = 8.5V. RSET is
arbitrarily chosen to be 7.5kΩ.
7
(EQ. 9)
Using Equations 6 and 7, calculate the values of R1 and R2:
8.5 – 6.5
R 1 = 5120 ⋅ 7500 ⋅ ⎛ --------------------------------------⎞ = 35.4kΩ
⎝ 256 ⋅ 8.5 – 6.5⎠
(EQ. 10)
8.5 – 6.5
R 2 = 5120 ⋅ 7500 ⋅ ⎛ ------------------------------------------------------------------⎞ = 46.4kΩ
⎝ 255 ⋅ 15 + 6.5 – 256 ⋅ 8.5⎠
(EQ. 11)
Table 1 shows the resulting VCOM voltage as a function of register
value for these conditions.
TABLE 1. EXAMPLE VDVR_OUT vs REGISTER VALUE
REGISTER VALUE
VDVR_OUT (V)
0
8.49
20
8.34
40
8.18
60
8.02
80
7.87
100
7.71
120
7.55
127
7.50
140
7.40
160
7.24
180
7.09
200
6.93
220
6.77
240
6.62
255
6.50
Output Voltage Span Calculation
It is also possible to calculate VCOM(MIN) and VCOM(MAX) from the
existing resistor values.
VCOM_MIN occurs when the greatest current, IDVR(MAX), is drawn
from the middle node of the R1/R2 divider. Substituting
RegisterValue = 255 into Equation 8 gives the following:
⎛ R1 ⎞ ⎞
⎛ R2 ⎞ ⎛
V COM ( MIN ) = AV DD ⎜ --------------------⎟ ⎜ 1 – ⎜ --------------------⎟ ⎟
R
+
R
⎝ 20R SET⎠ ⎠
⎝ 1 2⎠ ⎝
(EQ. 12)
Similarly, RegisterValue = 0 for VCOM(MAX):
⎛ R2 ⎞ ⎛
1 ⎛ R1 ⎞ ⎞
V COM ( MAX ) = AV DD ⎜ --------------------⎟ ⎜ 1 – ---------- ⎜ --------------------⎟ ⎟
256 ⎝ 20R SET⎠ ⎠
⎝ R1 + R2 ⎠ ⎝
(EQ. 13)
FN7590.0
March 15, 2011
ISL24212
By finding the difference of Equation 13 and Equation 12, the total
span of VCOM can be found:
⎛ R2 ⎞
1 ⎛ R1 ⎞
V COM SPAN = AV DD ⎜ --------------------⎟ ⎛ 1 – ----------⎞ ⎜ --------------------⎟
⎝
⎠ ⎝ 20R
R
+
R
256
⎝ 1 2⎠
SET⎠
(EQ. 14)
Do not remove VDD or AVDD within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed, may result in
corrupted data in the EEPROM.
Assuming that the IDVROUT(MIN) = 0 instead of ISTEP, the
expression in Equation 14 simplifies to:
Operating and Programming
Supply Voltage and Current
⎛ R 1 ⋅ R 2 ⎞ ⎛ AV DD ⎞
⎛ R1 ⋅ R2 ⎞
V COM SPAN = ⎜ --------------------⎟ ⎜ --------------------⎟ = ⎜ --------------------⎟ I DVROUT ( MAX )
⎝ R 1 + R 2⎠ ⎝ 20R SET⎠
⎝ R 1 + R 2⎠
(EQ. 15)
To program the EEPROM, AVDD must be ≥10.8V. If further
programming is not required, the ISL24212 will operate over an
AVDD range of 4.5V to 19V.
DVR_OUT Pin Leakage Current
During EEPROM programming, IDD and IAVDD will temporarily be
4-5x higher for up to 100ms (tPROG).
When the voltage on the DVR_OUT pin is greater than 10V, an
additional leakage current flows into the pin in addition to the
ISET current. Figure 6 shows the ISET current and the DVR_OUT
pin current for DVR_OUT pin voltage up to 19V. In applications
where the voltage on the DVR_OUT pin will be greater than 10V,
the actual output voltage will be lower than the voltage
calculated by Equation 8 due to this extra current. The graph in
Figure 6 was measured with RSET = 4.99kΩ.
0.30
REGISTER = 255
CURRENT (mA)
SET PIN CURRENT
When a mid-high-mid transition is detected on the CTL pin (see
Figure 11), the internal register value counts down by one at the
trailing (high-mid) edge, and the output VCOM voltage is
increased according to Equation 8. Similarly, when a mid-low-mid
transition is detected on the CTL pin, the internal register value
counts up by one at the trailing (low-mid) edge, and the output
VCOM voltage is decreased. Once the maximum or minimum
value is reached, the counter saturates and will not overflow or
underflow beyond those values.
12
CTL should have a noise filter to reduce bouncing or noise on the
input that could cause unwanted counts when the CE pin is high.
Figure 8 shows a simple debouncing circuit consisting of a series
1kΩ resistor and a shunt 0.01µF capacitor connected on the CTL
pin. To avoid unintentional adjustment, the ISL24212 guarantees
to reject CTL pulses shorter than 20µs.
OUT PIN CURRENT
0.20
0.15
0.10
0.05
2
4
6
The ISL24212 allows the adjustment of the output VCOM voltage
and the programming of the non-volatile memory through a
single pin (CTL) when the CE (counter enable) pin is high. The CTL
pin is biased so that its voltage is set to VDD/2 if the driving
circuit is set to Tristate or High Impedance (Hi-Z), allowing
up/down operation using common digital I/O logic.
CTL Pin
0.25
0.00
0
Up/Down Counter Interface
8
10
14
16
18
20
OUT PIN VOLTAGE (V)
FIGURE 6. DVR_OUT PIN LEAKAGE CURRENT
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 7. When applying power, VDD should be applied before or
at the same time as AVDD. The minimum time for tVS is 0µs.
When removing power, the sequence of VDD and AVDD is not
important.
AVDD
CLOSE TO
PROGRAM
EEPROM
1kΩ
ISL24212
CTL
0.01µF
VDD
FIGURE 8. EXTERNAL DEBOUNCER ON CTL PIN
This pin is pulled above 4.9V to program the EEPROM. See
“Programming the EEPROM” on page 9 for details.
AVDD
tVS
FIGURE 7. POWER SUPPLY SEQUENCE
8
After CE (Counter Enable) is asserted and after programming
EEPROM, the very first CTL pulse is ignored (see Figure 11) to
avoid the possibility of a false count (CTL state may be unknown
after programming).
FN7590.0
March 15, 2011
ISL24212
CE Pin
1. Power-up the ISL24212. The EEPROM value will be loaded.
To change the counter controlling the output voltage, the CE
(Counter Enable) pin must be pulled high (VDD). When the CE pin
is pulled low, the counter value is loaded from EEPROM, which
takes 10ms (during which the inputs should remain constant).
The CE pin has an internal pull-down to keep it at a logic low
when not being driven. CE should be pulled low before powering
the device down to ensure that any glitches or transients during
power-down will not cause unwanted EEPROM overwriting.
2. Set the CE pin to VDD.
3. Change the VOUT voltage using the CTL pin to the desired
value, noting that first pulse will be ignored.
4. Pull the CTL pin to 4.9V or higher for at least 200µs. The
counter value will be written to EEPROM after 100ms.
5. Change the VOUT value (using the CTL pin) to a different value,
noting that first pulse after programming will be ignored.
6. Set the CE pin to 0V. The stored output value will be loaded
from EEPROM after 10ms.
The CE pin has a Schmitt trigger on the input to prevent false
triggering during slow transitions of the CE pin. The CE pin
transition time should be 10µs or less.
7. Verify that the output value is the same value programmed in
Step 4.
Programming the EEPROM
The CTL pin should be left floating after programming. The
voltage at the CTL pin will be internally biased to VDD/2 to ensure
that no additional pulses will be seen by the Up/Down counter. To
prevent further changes, ground the CE pin.
To program the non-volatile EEPROM, pull the CTL pin above 4.9V
for more than 200µs. The level and timing is shown in Figure 9. It
then takes a maximum of 100ms after CTL crosses 4.9V for the
programming to be completed inside the device.
Typical Application Circuit
CTL VOLTAGE
Shown below in Figure 10 is a typical circuit that can be used to
program the ISL24212 via the up/down counter interface. Three
momentary push-button switches are required. SW1 connected
between CTL and AVDD allows the user to bring CTL above VDD for
programming the EEPROM, SW2 connected to VDD to pull CTL up,
and SW3 connected to GND to pull CTL to down. All the switches
should have 1kΩ current-limiting resistors in series.
EEPROM
OPERATION
COMPLETE
>200µs
4.9V
100ms
tPROG
For adjustment and programming to occur, the CE pin has to be
set to VDD. This can be achieved by a single-pull double-throw
switch (SW4) connected between VDD and GND.
TIME
FIGURE 9. EEPROM PROGRAMMING
Note that pressing the UP button increments the counter, but
results in VCOM_OUT decreasing. Similarly, pressing the DOWN
button decrements the counter, and results in VCOM_OUT
increasing.
When the part is programmed, the data in the counter register is
written into the EEPROM. This value will be loaded from the
EEPROM during subsequent power-ups as well as when the CE
pin is pulled low. The ISL24212 is factory-programmed to
mid-scale. As with asserting CE, the first pulse after a program
operation is ignored. The EEPROM contents can be written and
verified using the following steps:
VDD
AVDD
1kΩ
CLOSE TO
PROGRAM
EEPROM
SW1
ENABLE
ADJUST /
PROGRAM
VDD
SW4
AVDD
VDD
AVDD
R1
0.1µF
0.1µF
1kΩ
R2
DISABLE
SW2
VDD
UP
CE
AVDD
DVR_OUT
ISL24212
VCOM_OUT
CTL
0.01µF
GND
SET
INN
VCOM to LCD Panel
DOWN
SW3
RSET
1kΩ
FIGURE 10. TYPICAL APPLICATION CIRCUIT
9
FN7590.0
March 15, 2011
ISL24212
Up/Down Counter Waveforms
The operation modes of the ISL24212 is shown in Table 2.
TABLE 2. ISL 24212 OPERATION MODES
INPUT
OUTPUT
CTL
CE
COUNTER
VCOM_OUT
X
Lo
X
Lo to Hi
Hi to Mid
Hi
Decrement
Increase
No Change
Lo to Mid
Hi
Increment
Decrease
No Change
Mid to >4.9V
Hi
No Change
No Change
Write Counter
Value to EEPROM
>4.9V to Mid
Hi
X
Hi to Lo
EEPROM
No Change
Ignore first CTL pulse
No Change
Ignore next CTL Pulse
EEPROM
Read Value
No Change
Programmed
Value
No Change
Figure 11 shows the associated waveforms.
NOTE:
AFTER COUNTER ENABLE IS ASSERTED,
THE FIRST CTL PULSE IS IGNORED
VPROG = 4.9V
tPROG
tST
FIRST PULSE AFTER
PROGRAMMING IS
IGNORED
FIRST PULSE AFTER
ASSERTING CE IS
IGNORED
tH_REJ
tMTC
tREAD
CTL HIGH
CTL VDD/2
CTL LOW
tL_REJ
tH_MIN
tL_MIN
CE
DISABLE ADJUSTMENT
tL_PROP
ENABLE ADJUSTMENT
tH_PROP
ENABLE ADJUSTMENT
AVDD
VDD
COUNTER
OUTPUT
78
ASSUME COUNTER
STARTS WITH VALUE 78
79
7A
7B
WRITE 7B TO
EEPROM
7A
7B
7A
DEASSERTING CE
RELOADS 7B
FROM EEPROM
VCOM
EXAMPLE POST POWER-UP TIMING
FIGURE 11. COUNTER INTERFACE TIMING DIAGRAM
10
FN7590.0
March 15, 2011
ISL24212
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
3/15/11
FN7590.0
CHANGE
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL24212
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Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
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11
FN7590.0
March 15, 2011
ISL24212
Package Outline Drawing
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
3.00
A
2.0 REF
6
PIN 1
INDEX AREA
B
8X 0.50 BSC
5
1
6
PIN 1
INDEX AREA
10X 0 . 30
3.00
1.50
0.15
(4X)
10
0.10 M C A B
0.05 M C
5
4 10 X 0.25
TOP VIEW
2.30
( 2.30 )
BOTTOM VIEW
0 .80 MAX
SEE DETAIL "X"
0.10 C
C
(2.90)
SEATING PLANE
0.08 C
(1.50)
SIDE VIEW
(10 X 0.50)
0 . 2 REF
5
C
( 8X 0 .50 )
( 10X 0.25 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
Angular ±2.50°
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7.
12
Compliant to JEDEC MO-229-WEED-3 except exposed pad length (2.30mm).
FN7590.0
March 15, 2011
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