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TERSFebruary
20, 2008
1-888-IN
Data Sheet
Programmable 18-Channel Gamma with
1-Channel VCOM with Reference
The EL5625 represents a high integration programmable
buffer solution from Intersil. The device integrates 18channels of programmable buffers, with a single
programmable VCOM, a reference output, and a supply side
LDO.
• 18-channel programmable gamma
- Rail-to-rail
• Single VCOM amplifier
- 1A peak output
• 11-bit resolution per output
• Accuracy ±0.5%
The VCOM output also features 11-bits of resolution. The
generated voltage is connected to the non-inverting input of
the integrated VCOM amplifier. This amplifier has a shortcircuit current of 1A, 100mA continuous.
• Integrated reference
- Very accurate - 0.75%
The integrated low drop-out regulator is used, in conjunction
with an external transistor, to provide a solid supply voltage
to the device. It features 200mV minimum drop-out and has
very good load regulation for the cleanest gamma and VCOM
outputs.
• Thermal protection
• Integrated supply LDO
- Low drop out - 200mV
• +7V to +16V supply
• 38 Ld QFN
• Pb-free (RoHS compliant)
Applications
The EL5625 also includes over-temperature protection and
is available in a 38 Ld QFN package.
• LCD-TVs
Pinout
• TFT-LCD displays
• Flat panel monitors
Ordering Information
PART NUMBER
(See Note)
32 OUTH
33 OUTG
34 OUTF
35 OUTE
36 OUTD
37 OUTC
38 OUTB
FN7488.1
Features
The 18-channel programmable buffers have 11-bit resolution
and rail-to-rail outputs. Each output is capable of driving
15mA continuous.
EL5625
(38 LD QFN)
TOP VIEW
EL5625
OUTA 1
31 OUTI
LDO_COMP 2
30 VS
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
EL5625ILZ
5625ILZ
38 Ld QFN
MDP0046
EL5625ILZ-T13
5625ILZ
38 Ld QFN
(Tape and Reel)
MDP0046
*Please refer to TB347 for details on reel specifications.
LDO_IN 3
29 GND
VSD 4
28 CAP
SDI 5
27 LDO_OUT
SCLK 6
26 REFH
THERMAL
PAD
ENA 7
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
25 REFL
SDO 8
24 INNCOM
RD_WRBAR 9
23 GND
EXT_OSC 10
22 OUTCOM
RESET 11
21 VS
OUTR 12
1
OUTK 19
OUTL 18
OUTM 17
OUTN 16
OUTO 15
OUTP 14
OUTQ 13
20 OUTJ
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC.
Copyright Intersil Americas LLC. 2006, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5625
Absolute Maximum Ratings (TA = +25°C)
Supply Voltage between VS and GND. . . . . . 4.5V(min) to 18V(max)
Supply Voltage between VSD and GND 3V(min) to VS and +7(max)
Maximum Continuous Output Current (Gamma) . . . . . . . . . . . 15mA
Maximum Continuous Output Current (VCOM) . . . . . . . . . . . 100mA
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5k and CL = 200pF to 0V, TA = +25°C, unless
otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
11
15
mA
1.1
1.35
mA
100
200
mV
50
150
mV
SUPPLY
IS
Supply Current
ISD
Digital Supply Current
No load
ANALOG
VOL
Output Swing Low (Chan 1-16)
Sinking 5mA (VREFH = 15V, VREFL = 0)
Output Swing Low (Chan 17, 18)
VOH
Output Swing High (Chan 1, 2)
Sourcing 5mA (VREFH = 15V, VREFL = 0)
Output Swing High (Chan 3-18)
14.85
14.95
V
14.8
14.9
V
ISC
Short Circuit Current
RL = 10
100
130
mA
PSRR
Power Supply Rejection Ratio
VS+ is moved from 14V to 16V
50
70
dB
VCOM
45
60
dB
4
ms
tD
Program to Out Delay
VAC
Accuracy Referred to the Ideal Value
Code = 512
20
mV
VMIS
Channel to Channel Mismatch
Code = 512
2
mV
VDROOP
Droop Voltage
RINH
Input Resistance @ VREFH, VREFL
REG
Load Regulation
BG
Band Gap
1
25
IOUT = 5mA step
1.227
2
32
mV/ms
k
1
3
mV/mA
1.242
1.257
V
DIGITAL
VIH
Logic 1 Input Voltage
VIL
Logic 0 Input Voltage
FCLK
Clock Frequency
5
MHz
tS
Setup Time
20
ns
tH
Hold Time
20
ns
tLC
Load to Clock Time
20
ns
tCE
Clock to Load Line
20
ns
tDCO
Clock to Out Delay Time
10
ns
RSDIN
SDIN Input Resistance
1
G
TPULSE
Minimum Pulse Width for EXT_OSC
Signal
5
µs
2
2
V
1
Negative edge of SCLK
V
FN7488.1
February 20, 2008
EL5625
Electrical Specifications
PARAMETER
VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5k and CL = 200pF to 0V, TA = +25°C, unless
otherwise specified. (Continued)
DESCRIPTION
Duty Cycle
Duty Cycle for EXT_OSC Signal
F_OSC
Internal Refresh Oscillator Frequency
INL
DNL
CONDITIONS
MIN
TYP
MAX
UNIT
50
%
21
kHz
Integral Nonlinearity Error
1.3
LSB
Differential Nonlinearity Error
0.5
LSB
10
MHz
9
V/µs
1000
mA
OSC_Select = 0
VCOM CHARACTERISTICS
BW
Bandwidth of VCOM
SR
Slew Rate
ISC
Short-Circuit Current
5
3
FN7488.1
February 20, 2008
EL5625
Typical Application Diagram
LDO_IN
+15V
+
VS
LDO_OUT
0.1µF
LDO_COMP
+5V
VSD
+
V=1.242
0.1µF
REFH
HIGH REFERENCE
VOLTAGE
+13V
0.1µF
19
CHANNEL
REGISTERS
OUTA
VOLTAGE
SOURCES
COLUMN
(SOURCE)
DRIVER
OUTB
OUTQ
LCD PANEL
OUTR
RESET
OUTCOM
VCOM
+
-
RF
INNCOM
CAP
MICROCONTROLLER
+2V
REFL
SDI
SCLK
ENA
0.1µF
CONTROL IF
RD_WRBAR
SDO
LCD
TIMING
CONTROLLER
EXT_OSC
HORIZONTAL RATE
4
FN7488.1
February 20, 2008
EL5625
Pin Descriptions
PIN NUMBER
PIN NAME
PIN TYPE
1
OUTA
Analog Output
2
LDO_COMP
Analog Input
LDO compensation capacitor
3
LDO_IN
Analog Input
LDO inverting input
4
VSD
Power
5
SDI
Logic Input
Serial data input
6
SCLK
Logic Input
Serial data clock
7
ENA
Logic Input
Chip select, low enables data input to logic
8
SDO
Logic Output
Serial data output
9
RD_WRBAR
Analog Input
Read, write select: “0” = write, “1” = read
10
EXT_OSC
Input/Output
Oscillator pin for synchronizing
11
RESET
Analog Input
Reset all registers: “0” = reset
12
OUTR
Analog Output
Channel R output voltage
13
OUTQ
Analog Output
Channel Q output voltage
14
OUTP
Analog Output
Channel P output voltage
15
OUTO
Analog Output
Channel O output voltage
16
OUTN
Analog Output
Channel N output voltage
17
OUTM
Analog Output
Channel M output voltage
18
OUTL
Analog Output
Channel L output voltage
19
OUTK
Analog Output
Channel K output voltage
20
OUTJ
Analog Output
Channel J output voltage
21, 30
VS
Power
22
OUTCOM
Analog Output
23, 29
GND
Power
24
INNCOM
Analog Input
VCOM inverting input
25
REFL
Analog Input
Low reference voltage
26
REFH
Analog Input
High reference voltage
27
LDO_OUT
Analog Output
28
CAP
Analog
31
OUTI
Analog Output
Channel I output voltage
32
OUTH
Analog Output
Channel H output voltage
33
OUTG
Analog Output
Channel G output voltage
34
OUTF
Analog Output
Channel F output voltage
35
OUTE
Analog Output
Channel E output voltage
36
OUTD
Analog Output
Channel D output voltage
37
OUTC
Analog Output
Channel C output voltage
38
OUTB
Analog Output
Channel B output voltage
5
PIN DESCRIPTION
Channel A output voltage
Positive power supply for digital circuits (3.3V - 5V)
Positive supply voltage for analog circuits (4.5V - 16.5V)
VCOM output
Ground
LDO output
Decoupling capacitor for internal reference
FN7488.1
February 20, 2008
EL5625
Typical Performance Curves
VS=VREFH=15V
VS=VREFH=15V
5mA
0mA
0mA
5mA
CL=180pF
CL=1nF
CL=4.7nF
200mV/DIV
200mV/DIV
CL=4.7nF
CL=1nF
CL=180pF
M=400ns/DIV
M=400ns/DIV
FIGURE 1. TRANSIENT LOAD REGULATION (SOURCING)
FIGURE 2. TRANSIENT LOAD REGULATION (SINKING)
SCLK
SCLK
SDI
SDI
ENA
ENA
OUTA
OUTA
M=400µs/DIV
M=400µs/DIV
FIGURE 3. LARGE SIGNAL RESPONSE (RISING FROM 0V
TO 8V)
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD LPP EXPOSED DIEPAD SOLDERED TO
PCB PER JESD51-5
3
QFN38
3.33W
2.5
1
POWER DISSIPATION (W)
POWER DISSIPATION (W)
3.5
FIGURE 4. SMALL SIGNAL RESPONSE (FALLING FROM
200mV TO 100mV)
JA=30°C/W
2
1.5
1
0.5
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 5. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
6
QFN38
0.8
0.80W
JA=125°C/W
0.6
0.4
0.2
0
0
JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 6. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7488.1
February 20, 2008
EL5625
General Description
TABLE 1. CONTROL BITS LOGIC TABLE
The EL5625 is designed to produce the reference voltages
required in TFT-LCD applications. Each output is
programmed to the required voltage with 11 bits of
resolution. Ref-High and Ref-Low pins determine the high
and low voltages of the output range. These outputs can be
driven to within 50mV of the power rails of the EL5625.
Programming of each output, 18 buffers and 1 Vcom, is
performed using the USB interface.
BIT
NAME
DESCRIPTION
B15
A4
Channel Address
B14
A3
Channel Address
B13
A2
Channel Address
B12
A1
Channel Address
B11
A0
Channel Address
B10
D10
Data
USB Interface
B9
D9
Data
The EL5625 uses USB interface to control the 18 Gamma
channels and Vcom channel (Figure 7). Software is available
for download on Intersil’s website.
B8
D8
Data
B7
D7
Data
B6
D6
Data
B5
D5
Data
B4
D4
Data
B3
D3
Data
B2
D2
Data
B1
D1
Data
B0
D0
Data
FIGURE 7. USB INTERFACE
Serial Interface
The EL5625 is programmed through a three-wire serial
interface. The start and stop conditions are defined by the
ENA signal. While the ENA is low, the data on the SDI (serial
data input) pin is shifted into the 16-bit shift register on the
positive edge of the SCLK (serial clock) signal. The MSB
(bit 15) is loaded first and the LSB (bit 0) is loaded last (see
Table 1). After the full 16-bit data has been loaded, the ENA
is pulled high and the addressed output channel is updated.
The SCLK is disabled internally when the ENA is high. The
SCLK must be low before the ENA is pulled low.
The Serial Timing Diagram and parameters table show the
timing requirements for three-wire signals.
The serial data has a minimum length of 16 bits, the MSB
(most significant bit) is the first bit in the signal. The bits are
allocated to the following functions (also refer to the Control
Bits Logic Table).
• Bits 15 through 11 select the channel to be written to, these
are binary coded with channel A = 0, and channel R = 17
• The 11-bit data is on bits 10 through 0. Some examples of
data words are shown in the table of Serial Programming
Examples
7
FN7488.1
February 20, 2008
EL5625
Serial Timing Diagram
ENA
tHE
tSE
T
tr
tf
tHE
tSE
SCLK
tSD
tHD
SDI
B15
tw
B14
B13
B12-B2
B1
B0
t
MSB
LOAD MSB FIRST, LSB LAST
LSB
TABLE 2. SERIAL TIMING PARAMETERS
PARAMETER
RECOMMENDED OPERATING RANGE
DESCRIPTION
T
200ns
Clock Period
tr/tf
0.05 * T
Clock Rise/Fall Time
tHE
10ns
ENA Hold Time
tSE
10ns
ENA Setup Time
tHD
10ns
Data Hold Time
tSD
10ns
Data Setup Time
tW
0.50 * T
Clock Pulse Width
VCOM Amplifier
CLOCK OSCILLATOR
The VCOM amplifier is designed to control the voltage on the
back plate of an LCD display. This plate is capacitively
coupled to the pixel drive voltage which alternately cycles
positive and negative at the line rates for the display. Thus
the amplifier must be capable of sourcing and sinking
capacitive pulse of current, which can be quite large (100mA
for typical applications).
The EL5625 requires an internal clock or external clock to
refresh its outputs. The outputs are refreshed at the falling OSC
clock edges. The output refreshed switches open at the rising
edges of the OSC clock. The driving load shouldn’t be changed
at the rising edges of the OSC clock. Otherwise, it will generate
a voltage error at the outputs. This clock may be input or output
via the clock pin labelled EXT_OSC. The internal clock is
provided by an internal oscillator running at approximately
21kHz and can be output to the EXT_OSC pin. In a 2 chip
system, if the driving loads are stable, one chip may be
programmed to use the internal oscillator; then the OSC pin will
output the clock from the internal oscillator. The second chip
may have the OSC pin connected to this clock source.
Analog Section
TRANSFER FUNCTION
The transfer function is:
data
V OUT  IDEAL  = V REFL + -------------   V REFH - V REFL 
2048
where data is the decimal value of the 11-bit data binary
input code.
The output voltages from the EL5625 will be derived from
the reference voltages present at the VREFL and VREFH
pins. The impedance between those two pins is about 32k.
Care should be taken that the system design holds these two
reference voltages within the limits of the power rails of the
EL5625. GND < VREFH  VS and GND  VREFL  VREFH.
8
For transient load application, the external clock mode
should be used to ensure all functions are synchronized
together. The positive edge of the external clock to the OSC
pin should be timed to avoid the transient load effect. The
Application Drawing shows the LCD H rate signal used, here
the positive clock edge is timed to avoid the transient load of
the column driver circuits.
FN7488.1
February 20, 2008
EL5625
TABLE 3. OSC CONTROL LOGIC TABLE WITH BAND GAP TRIM SELECTION
Band Gap Trim
(mV)
INT/EXT
Name
A4
A3
A2
A1
A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
13.5
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
-24.3
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
43.74
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
-78.73
1
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
141.7
1
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
13.5
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
1
-24.3
1
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
43.74
1
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
-78.73
1
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
141.7
1
0
0
1
1
0
0
0
1
0
0
1
0
0
0
0
Internal OSC
External OSC
TABLE 4. CHANNEL ADDRESS OF OUTPUT CHANNEL
OUT CHANNEL
REGISTER ADDRESS
A
0
0
0
0
0
0
0
0
0
B
1
0
0
0
0
1
0
0
0
C
2
0
0
0
1
0
0
0
0
D
3
0
0
0
1
1
0
0
0
E
4
0
0
1
0
0
0
0
0
F
5
0
0
1
0
1
0
0
0
G
6
0
0
1
1
0
0
0
0
H
7
0
0
1
1
1
0
0
0
I
8
0
1
0
0
0
0
0
0
J
9
0
1
0
0
1
0
0
0
K
10
0
1
0
1
0
0
0
0
L
11
0
1
0
1
1
0
0
0
M
12
0
1
1
0
0
0
0
0
N
13
0
1
1
0
1
0
0
0
O
14
0
1
1
1
0
0
0
0
P
15
0
1
1
1
1
0
0
0
Q
16
0
0
0
0
0
0
0
0
R
17
0
0
0
0
1
0
0
0
VCOM
18
1
0
0
1
0
0
0
0
INT/EXT &
BAND GAP TRIM
19
1
0
0
1
1
0
0
0
9
CHANNEL ADDRESS
FN7488.1
February 20, 2008
EL5625
CHANNEL OUTPUTS
Each of the channel outputs has a rail-to-rail buffer. This
enables all channels to have the capability to drive to within
50mV of the power rails, (see Electrical Characteristics for
details).
When driving large capacitive loads, a series resistor should
be placed in series with the output (Usually between 5 and
50).
Each of the channels is updated on a continuous cycle, the
time for the new data to appear at a specific output will
depend on the exact timing relationship of the incoming data
to this cycle.
at the rising edge of the OSC signal. Since at the rising edge
of the OSC clock, the refreshed switches are being opened,
if the load changes at that time, it will generate an error
output voltage. For a fixed load condition, the internal
oscillator can be used.
For the transient load condition, the external OSC mode
should be used to avoid the conflict between the rising edge
of the OSC signal and the changing load. So a timing delay
circuit will be needed to delay the OSC signal and avoid the
rising edge of the OSC signal and changing the load at the
same time.
TRANSIENT LOAD RESPONSE
The best-case scenario is when the data has just been
captured and then passed on to the output stage
immediately; this can be as short as 48µs. In the worst-case
scenario, this will be 860µs for EL5625, when the data has
just missed the cycle at f_OSC = 21kHz.
When a large change in output voltage is required, the
change will occur in 2V steps, thus the requisite number of
timing cycles will be added to the overall update time. This
means that a large change of 16V can take between 6.8ms
and 7.2ms depending on the absolute timing relative to the
update cycle.
FIGURE 9.
Output Stage and the Use of External
Oscillator
Simplified output sample and hold amp stage for one
channel.
CH
1.3V
VIN
+
-
+
-
S1
1.3V
+
-
VOUT
S2
Channel 3 --- sinking and sourcing 5mA current
Channel 2 --- EXT_OSC signal
Channel 1 --- VOUT
Here, the OSC signal is synchronized to the load signal. The
rising edge of the OSC signal is then delayed by some
amount of time and gives enough time for CH to be charged
to a new voltage before the switches are opened.
CHANNEL TO CHANNEL REFRESH
OSC
FIGURE 8.
The output voltage is generated from the DAC, which is VIN
in the above circuit. The refreshed switches are controlled by
the internal or external oscillator signal. When the OSC clock
signal is low, switches S1 and S2 are closed. The output
VOUT = VIN and at the same time the sample and hold cap
CH is being charged. When the OSC clock signal is high, the
refreshed switches S1 and S2 are opened and the output
voltage is maintained by CH. This refreshed process will
repeat every 18 clock cycles for each channel. The time
takes to update the output depends on the timing at the VIN
and the state of the switches. It can take 1 to 19 clock cycles
to update each output.
For the sample and hold capacitor CH to maintain the
correct output voltage, the driving load shouldn’t be changed
10
FIGURE 10.
Ch1 --- Output1
Ch3 --- Output2
Ch2 --- EXT_OSC
FN7488.1
February 20, 2008
EL5625
At the falling edge of the OSC, output 1 is being refreshed
and one clock cycle later, output 2 is being refreshed. The
spike you see here is the response of the output amplifier
when the refreshed switches are closed. When driving a big
capacitor load, there will be ringing at the spikes because
the phase margin of the amplifier is decreased.
when sourcing, and:
The speed of the external OSC signal shouldn’t be greater
than 70kHz because for the worst condition, it will take at
least 4µs to charge the sample and hold capacitor CH. The
pulse width has to be at least 4µs long. From our lab test, the
duty cycle of the OSC signal must be greater than 30%.
• i = 18
POWER DISSIPATION
With the 100mA maximum continues output drive capability
for VCOM channel, it is possible to exceed the 125°C
absolute maximum junction temperature. Therefore, it is
important to calculate the maximum junction temperature for
the application to determine if load conditions need to be
modified for the part to remain in the safe operation.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX - T AMAX
P DMAX = -------------------------------------------- JA
where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
• PDMAX = Maximum power dissipation in the package
The maximum power dissipation actually produced by the IC
is the total quiescent supply current times the total power
supply voltage and plus the power in the IC due to the loads.
P DMAX = V S  I S +    V S - V OUT i   I LOAD i 
P DMAX = V S  I S +   V OUT i  I LOAD i 
when sinking.
Where:
• VS = Supply voltage
• IS = Quiescent current
• VOUTi = Output voltage of the i channel
• ILOADi = Load current of the i channel
By setting the two PDMAX equations equal to each other, we
can solve for the RLOADs to avoid the device overheat. The
package power dissipation curves provide a convenient way
to see if the device will overheat.
THERMAL SHUTDOWN
The EL5625 has an internal thermal shutdown circuitry that
prevents overheating of the part. When the junction
temperature goes up to about 150°C, the part will be
disabled. When the junction temperature drops down to
about 120°C, the part will be enabled. With this feature, any
short circuit at the outputs will enable the thermal shutdown
circuitry to disable the part.
POWER SUPPLY BYPASSING AND PRINTED CIRCUIT
BOARD LAYOUT
Good printed circuit board layout is necessary for optimum
performance. A low impedance and clean analog ground
plane should be used for the EL5625. The traces from the
two ground pins to the ground plane must be very short. The
thermal pad of the EL5625 should be connected to the
analog ground plane. Lead length should be as short as
possible and all power supply pins must be well bypassed. A
0.1µF ceramic capacitor must be place very close to the VS,
VREFH, VREFL, and CAP pins. A 4.7µF local bypass
tantalum capacitor should be placed to the VS, VREFH, and
VREFL pins.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN7488.1
February 20, 2008
EL5625
QFN (Quad Flat No-Lead) Package Family
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY
(COMPLIANT TO JEDEC MO-220)
A
MILLIMETERS
D
N
(N-1)
(N-2)
B
1
2
3
PIN #1
I.D. MARK
E
(N/2)
2X
0.075 C
2X
0.075 C
N LEADS
TOP VIEW
0.10 M C A B
(N-2)
(N-1)
N
b
L
SYMBOL QFN44 QFN38
TOLERANCE
NOTES
A
0.90
0.90
0.90
0.90
±0.10
-
A1
0.02
0.02
0.02
0.02
+0.03/-0.02
-
b
0.25
0.25
0.23
0.22
±0.02
-
c
0.20
0.20
0.20
0.20
Reference
-
D
7.00
5.00
8.00
5.00
Basic
-
Reference
8
Basic
-
Reference
8
Basic
-
D2
5.10
3.80
5.80 3.60/2.48
E
7.00
7.00
8.00
1
2
3
6.00
E2
5.10
5.80
5.80 4.60/3.40
e
0.50
0.50
0.80
0.50
L
0.55
0.40
0.53
0.50
±0.05
-
N
44
38
32
32
Reference
4
ND
11
7
8
7
Reference
6
NE
11
12
8
9
Reference
5
MILLIMETERS
PIN #1 I.D.
3
QFN32
SYMBOL QFN28 QFN24
QFN20
QFN16
A
0.90
0.90
0.90
0.90
0.90
±0.10
-
A1
0.02
0.02
0.02
0.02
0.02
+0.03/
-0.02
-
b
0.25
0.25
0.30
0.25
0.33
±0.02
-
c
0.20
0.20
0.20
0.20
0.20
Reference
-
D
4.00
4.00
5.00
4.00
4.00
Basic
-
D2
2.65
2.80
3.70
2.70
2.40
Reference
-
(E2)
(N/2)
NE 5
7
(D2)
BOTTOM VIEW
0.10 C
e
C
SEATING
PLANE
TOLERANCE NOTES
E
5.00
5.00
5.00
4.00
4.00
Basic
-
E2
3.65
3.80
3.70
2.70
2.40
Reference
-
e
0.50
0.50
0.65
0.50
0.65
Basic
-
L
0.40
0.40
0.40
0.40
0.60
±0.05
-
N
28
24
20
20
16
Reference
4
ND
6
5
5
5
4
Reference
6
NE
8
7
5
5
4
Reference
5
Rev 11 2/07
0.08 C
N LEADS
& EXPOSED PAD
SEE DETAIL "X"
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
SIDE VIEW
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
(c)
C
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
2
A
(L)
A1
N LEADS
DETAIL X
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7. Inward end of terminal may be square or circular in shape with radius
(b/2) as shown.
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.
12
FN7488.1
February 20, 2008
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