DATASHEET

Programmable VCOM Calibrator with EEPROM
ISL24201
Features
The ISL24201 provides an 8-bit programmable current sink that
is used in conjunction with an external voltage divider and buffer
amplifier to generate a voltage source that is positioned between
the analog supply voltage and ground. The current sink’s
resolution is controlled by an external resistor, RSET, and the
span of the VCOM voltage is controlled by the voltage divider
resistor ratio and the source impedance of R1 and R2. This
device has an 8-bit data register and 8-bit EEPROM for storing a
volatile and a permanent value for its output. The ISL24201 has
an I2C bus interface that is used to read and write to its registers
and EEPROM. At power-up the EEPROM value is transferred to
the data register and output.
• 8-bit, 256-Step, Adjustable Sink Current Output
• On-Chip 8-Bit EEPROM
The ISL24201 is available in an 8 Ld 3mm x 3mm TDFN
package. This package has a maximum height of 0.8mm for very
low profile designs. The ambient operating temperature range is
-40°C to +85°C.
• Resistive Sensor Driver
• 4.5V to 18V Analog Supply Voltage Operating Range
• 2.25V to 3.6V Logic Supply Voltage Operating Range
• 400kHz, I2C Interface
• Output Guaranteed Monotonic Over-Temperature
• Pb-free (RoHS-compliant)
Applications
• LCD Panel VCOM Generator
• Electrophoretic Display VCOM Generator
• Low Power Current Loop
Related Literature
• See AN1621 for ISL24201 Evaluation Board Application Note
“ISL24201IRTZ-EVALZ Evaluation Board User Guide”
Typical Application
VDD
3.3V
AVDD
LCD PANEL
2
5
R1
6
MICROCONTROLLER
I2C
PORT
I/O PIN
7
SCL
3
OUT
SDA
1
VCOM
ISL24201
SET
R2
8
WP
RSET
4
EL5411T
FIGURE 1. APPLICATION SHOWING ISL24201 WITH A BUFFER AMPLIFIER
December 9, 2010
FN7586.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL24201
Block Diagram
VDD
AVDD
5
SDA
SCL
6
2
I2C
INTERFACE
7
ANALOG DCP
AND
CURRENT SINK
DAC
REGISTERS
1
OUT
Q1
WP
3
A1
8-BIT EEPROM
8
CURRENT
SINK
SET
ISL24201
4
GND
FIGURE 2. BLOCK DIAGRAM OF THE ISL24201
Pin Descriptions
Pin Configuration
ISL24201
(8 LD TDFN)
TOP VIEW
OUT 1
AVDD 2
PIN
NAME
PIN
NUMBER
OUT
1
Adjustable Sink Current Output Pin. The current
sunk into the OUT pin is equal to the DAC setting
times the maximum adjustable sink current
divided by 256. See the “SET” pin function
description below (pin 8) for the maximum
adjustable sink current setting.
AVDD
2
High-Voltage Analog Supply. Bypass to GND
with 0.1µF capacitor.
WP
3
EEPROM Write Protect. Active Low.
0 = Programming disabled;
1 = Programming allowed. This pin has an
internal pull-down current sink
GND
4
Ground connection.
VDD
5
System power supply input. Bypass to GND
with 0.1µF capacitor.
SDA
6
I2C Serial Data Input and Output
SCL
7
I2C Clock Input
SET
8
Maximum Sink Current Adjustment Point.
Connect a resistor from SET to GND to set the
maximum adjustable sink current of the OUT
pin. The maximum adjustable sink current is
equal to (AVDD/20) divided by RSET.
PAD
-
Thermal pad should be connected to system
ground plane to optimize thermal performance.
8 SET
7 SCL
PAD
WP 3
6 SDA
GND 4
5 VDD
(THERMAL PAD CONNECTS TO GND)
2
FUNCTION
FN7586.1
December 9, 2010
ISL24201
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL24201IRTZ
201Z
ISL24201IRTZ-EVALZ
Evaluation Board
INTERFACE
TEMP RANGE
(°C)
I2C
-40 to +85
PACKAGE
(Pb-Free)
8 Ld 3x3 TDFN
PKG.
DWG. #
L8.3x3A
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page ISL24201. For more information on MSL please see techbrief TB363.
3
FN7586.1
December 9, 2010
ISL24201
Absolute Maximum Ratings
Thermal Information
Supply Voltage
AVDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
Input Voltage with respect to Ground
SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
SCL, SDA and WP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDD+0.3V
Output Voltage with respect to Ground
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD
Continuous Output Current
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Ratings
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 7kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . .1.5kV
Latch Up (Tested per JESD 78, Class II, Level A). . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld TDFN Package (Notes 4, 5). . . . . . . . .
53
11
Moisture Sensitivity (see Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Range
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 19V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5); unless otherwise
specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
DC CHARACTERISTICS
VDD
VDD Supply Range - Operating
2.25
3.6
V
AVDD
AVDD Supply Range Supporting EEPROM Programming
10.8
19
V
AVDD
AVDD Supply Range for Wide-Supply Operation
(not supporting EEPROM Programming)
4.5
19
V
IDD
VDD Supply Current
WP = SCL = SDA = VDD
37
65
µA
IAVDD
AVDD Supply Current
WP = SCL = SDA = VDD
24
38
µA
OUT CHARACTERISTICS
SETZSE
SET Zero-Scale Error
±3
LSB
SETFSE
SET Full-Scale Error
±8
LSB
VOUT
OUT Voltage Range
IOUT < 0.5mA
VSET + 0.4
AVDD
SET Voltage Drift
7
IOUT
Maximum OUT Sink Current
4
INL
Integral Non-Linearity
SET VD
DNL
Differential Non-Linearity
2
I C INPUTS AND OUTPUT
I2CVIH
SDA, SCL Logic 1 Input Voltage
I2CVIL
I2CH
SDA, SCL Logic 0 Input Voltage
IL
VOLS
mA
±2
LSB
±1
LSB
1.44
V
0.55
SDA, SCL Hysteresis
260
Input Leakage Current of SDA, SCL
SDA Output Logic Low
VIH
WP Input Logic High
VIL
WP Input Logic Low
VWPH
WP Input Hysteresis
ILWPN
WP Input Leakage Current
I = -3mA
mV
µA
0.4
V
V
0.3VDD
260
4
V
±1
0.7VDD
-0.20
V
μV/°C
-0.5
V
mV
-1
µA
FN7586.1
December 9, 2010
ISL24201
Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5); unless otherwise
specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
2
I C TIMING
PARAMETER
MIN
(Note 6)
TEST CONDITIONS
TYP
MAX
(Note 6)
UNITS
400
kHz
fCLK
I2C Clock Frequency
tSCH
I2C Clock High Time
0.6
µs
tSCL
I2C Clock Low Time
1.3
µs
tDSP
I2C Spike Rejection Filter Pulse Width
tSDS
I2C Data Set Up Time
250
ns
tSDH
I2C Data Hold Time
250
ns
tBUF
I2C Time Between Stop and Start
200
µs
tSTS
I2C Repeated Start Condition Set-up
0.6
µs
tSTH
I2C Repeated Start Condition Hold
0.6
µs
tSPS
I2C Stop Condition Set-up
0.6
µs
CSDA
SDA Pin Capacitance
CS
SCL Pin Capacitance
tW
EEPROM Write Cycle Time
0
50
ns
10
pF
10
pF
100
ms
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Application Information
The ISL24201 provides the ability to adjust the VCOM voltage
during production test and alignment, under digital control, to
minimize the flicker of an LCD panel. A digitally controlled
potentiometer (DCP), with 256 steps of resolution, adjusts the sink
current of the OUT pin. Figure 3 shows the VCOM adjustment using
a mechanical potentiometer circuit and the equivalent circuit
replacement with the ISL24201.
The output is connected to an external voltage divider, as shown in
Figure 3, so that the ISL24201 will have the ability to reduce the
voltage on the output by increasing the OUT pin sink current. The
amount of current sunk is controlled by the I2C serial interface.
AVDD
RA
R1 = RA
RB
VCOM
R2 = RB+RC
RSET = RARB + RARC
RC
20RB
VDD
AVDD
ISL24201
or
ISL24202
R1
OUT
SET
AVDD
IOUT
VCOM
R2
RSET
FIGURE 3. MECHANICAL ADJUSTMENT REPLACEMENT
5
FN7586.1
December 9, 2010
ISL24201
DCP (Digitally Controlled Potentiometer)
Figure 4 shows the relationship between the register value and
the resistor string of the DCP. Note that the register value of zero
actually selects the first step of the resistor string. The output
voltage of the DCP is given by Equation 1:
RegisterValue + 1 A VDD
V DCP = ⎛ ---------------------------------------------------⎞ ⎛ --------------⎞
⎝
⎠ ⎝ 20 ⎠
256
AVDD
AVDD
(EQ. 1)
19R
(EQ. 3)
Equation 2 can also be used to calculate the unit sink current
step size by removing the Register Value term from it as shown in
Equation 4.
(EQ. 4)
The voltage difference between the OUT pin and SET pin, which are
also the drain and source of the output transistor, should be greater
than the minimum saturation voltage for the IOUT(MAX) being used.
This will keep the output transistor in its saturation region to
maintain linear operation over the full range of register values.
255
254
253
VDCP
Figure 6 shows IDS vs VDS for transistor Q1. The line labeled
"Minimum Saturation Voltage" is the minimum voltage that should
be maintained across the drain and source of Q1. To find the
minimum saturation voltage for a specific condition, locate the
voltage at the intersection of the IOUT(MAX) value from Equation 3
and the line labeled "Minimum Saturation Voltage".
252
R
A VDD
I OUT ( MAX ) = -------------------20R SET
A VDD
I STEP = ---------------------------------------------( 256 ) ( 20 ) ( R SET )
REGISTER
VALUE
20
The maximum value of IOUT can be calculated by substituting the
maximum register value of 255 into Equation 2, resulting in
Equation 3:
251
2
1
0
4.5
MINIMUM SATURATION
VOLTAGE
4.0
SATURATION REGION
3.5
FIGURE 4. SIMPLIFIED SCHEMATIC OF DIGITAL CONTROL
POTENTIOMETER (DCP)
IDS (mA)
3.0
Output Current Sink
2.5
2.0
1.5
Figure 5 shows the schematic of the OUT pin current sink. The
circuit made up of amplifier A1, transistor Q1, and resistor RSET
forms a voltage controlled current source.
1.0
0.5
0
AVDD
AVDD
R1
0
1
2
3
4
5
6
VDS (V)
7
8
9
10
FIGURE 6. IDS vs VDS FOR THE ISL24201 OUTPUT TRANSISTOR
OUT
VOUT
VDCP
Q1
A1
R2
VSAT
SET
IOUT
VSET = (IOUT)*(RSET) = VDCP
RSET
FIGURE 5. CURRENT SINK CIRCUIT
The external RSET resistor sets the full-scale sink current that
determines the lowest output voltage of the external voltage divider
R1 and R2. IOUT is calculated as shown by Equation 2:
V DCP
RegisterValue + 1 A VDD
1
I OUT = ------------- = ⎛ ---------------------------------------------------⎞ ⎛ --------------⎞ ⎛ -------------⎞
⎝
⎠ ⎝ 20 ⎠ ⎝ R
⎠
256
R SET
SET
6
(EQ. 2)
FN7586.1
December 9, 2010
ISL24201
The maximum voltage on the SET pin is AVDD/20 and is added to
the minimum voltage difference between the VOUT and SET pins to
calculate the minimum VOUT voltage, as shown in Equation 5.
The output voltage, VOUT, of the OUT pin can be calculated from
Equation 6:
⎛ R2 ⎞ ⎛
RegisterValue + 1 ⎛ R 1 ⎞ ⎞
V OUT = A VDD ⎜ --------------------⎟ ⎜ 1 – --------------------------------------------------- ⎜ --------------------⎟ ⎟
R
+
R
256
⎝ 20R SET⎠ ⎠
⎝ 1 2⎠ ⎝
(EQ. 6)
While Equation 6 can be used to calculate the output voltage, it
does not help select the values of R1, R2 and RSET to obtain a
specific range of VCOM voltages.
Output Voltage Span Calculation
The span of the output voltage is typically centered around the
nominal VCOM voltage value, which is typically near half of the
AVDD voltage. The high VCOM voltage occurs with the register
value of zero, while the low VCOM voltage occurs with the register
value of 255. Figure 7 shows the definition of several terms used
later in the text.
A VDD
10
kΩ
=
TH
Output Voltage
0.5
R
(EQ. 5)
OUT PIN MAXIMUM CURRENT (mA)
A VDD
V OUT ( MIN ) ≥ -------------- + MinimumSaturationVoltage
20
0.6
0.4
0.3
0.2
R TH
0.1
R TH
0
0
=
kΩ
25
kΩ
= 50
00k Ω
R TH = 1
1
2
3
4
5
6
VCOM SPAN (V)
FIGURE 8. GRAPH of VCOM SPAN vs MAXIMUM OUTCURRENT
AND RTH
To make a final selection of the resistor values for R1 and R2, The
supply voltage AVDD and the value of RSET are specified. The
calculations for R1 and R2 are shown in Equations 9 and 10:
H IG H V CO M V O LTAG E
N O M IN AL V CO M VO LTAG E
40R SET ( SPAN )
R 1 = -----------------------------------------A VDD + SPAN
(EQ. 9)
40R SET ( SPAN )
R 2 = -----------------------------------------A VDD – SPAN
(EQ. 10)
SPAN
LO W V CO M V O LTA G E
The R1 and R2 calculations are based on the span of the VCOM
voltage being centered at half the AVDD voltage.
GND
FIGURE 7. VOLTAGE LEVELS FOR VCOM
There are three variables that control the VCOM calibrator’s
operating point; the span of the VCOM voltage, the maximum
current sink and the source impedance of the resistive divider.
Figure 8 shows a range of operating points for these three variables
and a quick way to estimate a specific operating point. The X-axis is
the span of the VCOM voltage (High VCOM Voltage - Low VCOM
Voltage), and the Y-axis is the maximum sink current set by RSET.
The individual plots of each RTH show the VCOM span plotted against
the maximum OUT sink current given that value of source
impedance of the voltage divider. RTH is the Thevenin equivalent
resistance of the voltage divider R1 and R2, which is the resistance
of the parallel combination of R1 and R2, as shown in Equation 7.
R1 R2
R TH = -------------------R1 + R2
As an example, AVDD = 15V, the maximum value for ISET is
selected to be 100µA and the required span is 2V. Using Figure 8
as a guide, the VCOM maximum is equal to 8.5V and the VCOM
minimum is equal to 6.5V. Rearranging equation and calculation
the value of RSET:
A VDD
15
R SET = ------------------------------------- = -------------------------------------- = 7500Ω
20I OUT ( MAX )
20 ( 0.000100 )
(EQ. 11)
Calculating the value of R1 is shown in Equation 12.
40 ( 7500 ) ( 2 )
R 1 = ----------------------------------- = 39.29kΩ
15 + 2
(EQ. 12)
Calculating the value of R2 is shown in Equation 13.
40 ( 7500 ) ( 2 )
R 2 = ----------------------------------- = 46.15kΩ
15 – 2
(EQ. 13)
(EQ. 7)
The span of the VCOM voltage is shown by Equation 8.
V COM SPAN = I SET ( R TH )
(EQ. 8)
7
FN7586.1
December 9, 2010
ISL24201
Table 1 shows the calculated results of the VCOM voltage with
these values.
OUT and SET Pin Current vs. OUT Pin Voltage
Register = 255
TABLE 1. EXAMPLE VOUT vs REGISTER VALUE
VOUT (V)
0
8.49
20
8.34
40
8.18
60
8.02
80
7.87
100
7.71
120
7.55
127
7.50
140
7.40
160
7.24
180
7.09
200
6.93
220
6.77
240
6.62
255
6.50
0.250
SET Pin Current
0.150
0.100
0.050
0.000
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
OUT Pin Voltage (V)
FIGURE 9. OUT PIN LEAKAGE CURRENT
Power Supply Sequence
Figure 6 is used to find the minimum saturation voltage for an
IOUT maximum of 100µA, which is about 0.3V. The minimum
VOUT is 6.5V, which also meets the minimum VOUT - VSET
requirements specified in Equation 14:
15V
V OUT MIN = 6.5V > ---------- + 0.3V = 1.05V
20
OUT Pin Current
0.200
Current (mA)
REGISTER VALUE
0.300
(EQ. 14)
OUT Pin Leakage Current
When the voltage on the OUT pin is greater than 10V, there is a
leakage current flowing into the pin in addition to the ISET
current. Figure 9 shows the ISET current and the OUT pin current
for OUT pin voltage up to 19V. In applications where the voltage
on the OUT pin will be greater than 10V, the actual output voltage
will be lower than the voltage calculated by Equation 6. The
graph in Figure 9 was measured with RSET = 4.99kΩ.
The recommended power supply sequencing is shown in
Figure 10. When applying power, VDD should be applied before or
at the same time as AVDD. The minimum time for tVS is 0µs.
When removing power, the sequence of VDD and AVDD is not
important.
VDD
AVDD
tVS
FIGURE 10. POWER SUPPLY SEQUENCE
Do not remove VDD or AVDD within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
Operating and Programming
Supply Voltage and Current
To program the EEPROM, AVDD must be ≥10.8V. If programming
is not required, the ISL24201 will operate over an AVDD range of
4.5V to 19V.
During EEPROM programming, IDD and IAVDD will temporarily be
higher than their quiescent currents. Figure 11 shows a typical
IDD and IAVDD current profile during EEPROM programming. The
current pulses are Erase and Write cycles. The EEPROM
programming algorithm is shown in Figure 12. The algorithm
allows up to 4 erase cycles and 4 programming cycles, however
typical parts only require 1 cycle of each, sometimes 2 when
AVDD is near the minimum 10.8V limit.
8
FN7586.1
December 9, 2010
ISL24201
ISL24201 Programming
VDD
Programming
Current
2.7mA
200µA
50µA
~1ms
IAVDD
Programming
Current
90µA
The ISL24201 accepts I2C bus address and data when the WP
pin is at or above VIH (>0.7VDD). The ISL24201 ignores the I2C
bus when the WP pin is at or below VIL (<0.3VDD). Figure 13
shows the serial data format for writing the register and
programming the EEPROM. Figure 14 shows the serial data
format for reading the DAC register. Table 2 shows the truth table
for reading and writing the device.
TABLE 2. ISL24201 READ AND WRITE CONTROL
IP
I2C BITS
WP PIN
R/W
PROGRAM
0
1
X
Read Register.
0
0
1
Will acknowledge I2C
transactions. Will not write to
register
0
0
0
Will acknowledge I2C
transactions. Will not write to
EEPROM.
1
1
X
Read DAC Register
1
0
1
Write DAC Register
1
0
0
Program EEPROM
25µA
100ms
Max
FIGURE 11. IDD AND IAVDD CURRENT PROFILE DURING EEPROM
PROGRAMMING
S ta rt E E P R O M
P ro g ra m m in g
FUNCTION
E ra s e P u ls e
A re E E P R O M
C e lls E ra s e d ?
No
Yes
The ISL24201 uses a 6 bit I2C address, which is “100111xx”. The
complete read and write protocol is shown in Figures 13 and 14.
W rite P u ls e
A re
E E P R O M C e lls
P ro g ra m m e d ?
I2C Bus Signals
No
Yes
EEPROM
P ro g ra m m in g
C o m p le te
FIGURE 12. EEPROM PROGRAMMING FLOWCHART
9
Programming the EEPROM memory transfers the current DAC
register value to the EEPROM and occurs when the control bits
select the programming mode and the AVDD voltage is >10.8V.
After the EEPROM programming cycle is started, the WP pin can
be returned to logic low while the while it completes, which takes
a maximum of 100ms.
The ISL24201 uses fixed voltages for its I2C thresholds, rather
than the percentage of VDD described in the I2C specification
(see Table 3). This should not cause a problem in most systems,
but the I2C logic levels in a specific design should be checked to
ensure they are compatible with the ISL24201.
TABLE 3. ISL24201 I2C BUS LOGIC LEVELS
SYMBOL
ISL24201
I2C STANDARD
I2CVIL
0.55V
0.3*VDD
I2CV
1.44V
0.7*VDD
IH
FN7586.1
December 9, 2010
ISL24201
I2C Read and Write Format
IS L 2 4 2 0 1 I 2 C W rite
B y te 1
B y te 2
D a ta
LSB
6 b it A d d re ss
S tart
MSB
1
R/W
ACK
LSB
0
0
1
1
1
D0
D a ta
P ro g ram
A
D7
S to p
LSB
M SB
0
ACK
D6
D5
D4
R / W = 0 = W rite
R/W = 1 = Read
D3
D2
P
D1
A
W hen R/W = 0
P = 0 = E E P R O M P ro g ra m m in g
P = 1 = R e g iste r W rite
FIGURE 13. I2C WRITE FORMAT
ISL24201 I2C Read
Byte 2
Byte 1
X
6 bit Address
Start
MSB
1
R/W
ACK
LSB
0
0
1
1
1
X
1
Data
Start
ACK
MSB
A
D7
Stop
LSB
D6
D5
D4
D3
D2
D1
D0
A
R/W = 0 = Write
R/W = 1 = Read
FIGURE 14. I2C READ FORMAT
10
FN7586.1
December 9, 2010
ISL24201
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
CHANGE
12/9/10
FN7586.1
On page 5, corrected MIN spec for “tBUF” from 125µs to 200µs.
12/1/10
FN7586.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL24201
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/sear
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN7586.1
December 9, 2010
ISL24201
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
3.00
( 1.95)
A
B
3.00
( 8X 0.50)
6
PIN 1
INDEX AREA
(4X)
(1.50)
( 2.90 )
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
2X 1.950
PIN #1
INDEX AREA
0.10 C
0.75 ±0.05
6X 0.65
C
0.08 C
1
SIDE VIEW
6
1.50 ±0.10
8
8X 0.30 ±0.05
8X 0.30 ± 0.10
2.30 ±0.10
C
4
0.10 M C A B
0 . 2 REF
5
0 . 02 NOM.
0 . 05 MAX.
DETAIL "X"
BOTTOM VIEW
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
either a mold or mark feature.
12
FN7586.1
December 9, 2010
Similar pages