DATASHEET

DATASHEET
TFT-LCD I2C Programmable VCOM Calibrator
ISL45041
Features
The VCOM voltage of an LCD panel needs to be adjusted to
remove flicker. The ISL45041 part provides a digital interface
to control the sink current output that attaches to an external
voltage divider. The increase in output sink current lowers the
voltage on the external divider, which is applied to an external
VCOM buffer amplifier. The desired VCOM setting is loaded from
an external source via a standard 2-wire I2C serial interface. At
power-up, the part automatically comes up at the last
programmed EEPROM setting.
• 128-step adjustable sink current output
An external resistor attaches to the SET pin and sets the
full-scale sink current that determines the lowest voltage of
the external voltage divider.
The ISL45041 is available in an 8 Ld 3mmx3mm TDFN
package with a maximum thickness of 0.8mm for ultra thin
LCD panel design.
An evaluation kit complete with software to control the DCP
from a computer is available. Reference Application Note
AN1275 and “Ordering Information” on page 2.
• 2.25V to 3.6V logic supply voltage operating range (2.6V
minimum programming voltage)
• 4.5V to 18V analog supply voltage operating range (10.8V
minimum programming voltage)
• I2C interface with addresses 100111x and 100110x
• On-chip 7-Bit EEPROM
• Output adjustment SET pin
• Output guaranteed monotonic over-temperature
• Thin 8 Ld 3mmx3mm DFN (0.8mm max)
• Pb-free (RoHS compliant)
Applications
• LCD panels
Related Literature
• AN1208 “LCD screens don't flicker - or do they?”
• AN1275, “ISL45041EVAL1Z User’s Manual”
AVDD
VDD
5
SDA
SCL
6
I2C
INTERFACE
7
2
ANALOG DCP
AND
CURRENT SINK
DAC
REGISTERS
1
OUT
Q1
WP
3
A1
7-BIT EEPROM
8
CURRENT SINK
SET
ISL45041
4
GND
FIGURE 1. BLOCK DIAGRAM
April 22, 2016
FN6189.6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC. 2005- 2007, 2010, 2014, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL45041
Pin Configuration
ISL45041
(8 LD TDFN)
TOP VIEW
OUT
1
8
SET
AVDD
2
7
SCL
WP
3
6
SDA
GND
4
5
VDD
PAD
Pin Descriptions
PIN
PIN
NUMBER NAME
TYPE
PULL U/D
FUNCTION
1
OUT
Output
Adjustable Sink Current Output Pin. The current that sinks into the OUT pin is equal to the DAC setting times
the maximum adjustable sink current divided by 128. See SET pin function description for the maximum
adjustable sink current setting.
2
AVDD
Supply
High-Voltage Analog Supply. Bypass to GND with 0.1µF capacitor.
3
WP
Input
4
GND
Supply
Ground connection
5
VDD
Supply
Digital power supply input. Bypass to GND with 0.1µF capacitor.
6
SDA
In/Out
I2C Serial Data Input and Output
7
SCL
Input
I2C Clock Input
8
SET
Analog
Maximum Sink Current Adjustment Point. Connect a resistor from SET to GND to set the maximum
adjustable sink current of the OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided
by RSET.
Pad
Power
Thermal pad. Electrically connected to GND. Connect to ground plane on PCB to maximize thermal
performance.
Pull-Down Write Protect. Active Low. To enable programming, connect to 0.7*VDD supply or greater. The WP pin is
designed for static control. It has an internal pull-down current sink. To avoid the possibly overwriting the
EEPROM contents, no frequency above 1Hz should be applied to this input. Care should be taken to avoid
any glitches on the input. When removing or applying mechanical jumpers, always ensure the VDD power is
off. A high to low transition on the WP pin results in the register contents being loaded with EEPROM data.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL45041IRZ
041Z
ISL45041EVAL1Z
Evaluation Board
TEMP.
RANGE
(°C)
0 to +85
PACKAGE
(Pb-Free)
8 Ld 3x3 TDFN
PKG.
DWG. #
L8.3x3A
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL45041. For more information on MSL, please see Technical Brief
TB363.
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FN6189.6
April 22, 2016
ISL45041
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4V
Input Voltages to GND
SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V
Output Voltages to GND
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +AVDD
ESD Rating
Human Body Model
Device (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Input Pins (SCL, SDA) (Tested per JESD22-A114E) . . . . . . . . . . . . . . 4kV
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld TDFN Package (Notes 4, 5). . . . . . . . .
53
11
Moisture Sensitivity (see Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ; (See Figure 2) Unless otherwise
specified. Typicals are at TA = +25°C. Boldface limits apply across the operating temperature range, 0°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
POWER SUPPLY CHARACTERISTICS
VDD Supply Range Supporting EEPROM Programming
VDD
2.6
3.6
V
AVDD Supply Range Supporting EEPROM Programming
AVDD
10.8
18
V
VDD Supply Range for Wide-supply Operation
(not supporting EEPROM programming)
VDD
2.25
3.6
V
AVDD Supply Range for Wide-supply Operation
(not supporting EEPROM programming)
AVDD
2.6V < VDD < 3.6V
4.5
18
V
2.25V < VDD < 2.6V
4.5
13
V
VDD Supply Current
IDD
(Note 7)
65
µA
AVDD Supply Current
IAVDD
(Note 8)
38
µA
7
Bits
1
LSB
DC CHARACTERISTICS
SET Voltage Resolution
SETVR
SET Differential Nonlinearity
SETDN
SET Zero-scale Error
SETZSE
3
LSB
SET Full-scale Error
SETFSE
8
LSB
SET Current (RSET = 24.9kΩ and AVDD = 10V)
SET External Resistance
ISET
SETER
AVDD to SET Voltage Attenuation
AVDD to
SET
OUT Settling Time
OUTST
OUT Voltage Range
VOUT
SET Voltage Drift
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SETVD
3
7
7
Monotonic Over-temperature
Through RSET (Note 11)
20
µA
To GND, AVDD = 18V
5
200
kΩ
To GND, AVDD = 4.5V
2.25
45
kΩ
To GND, AVDD = 15V, VDD = 3V
VOUT > 2.5V (Note 12)
1.0
200
kΩ
(Note 9)
To 0.5 LSB Error Band
(Note 9)
1:20
V/V
8
µs
VSET + 0.5V
25°C < TA < 55°C (Note 9)
13
<10
V
mV
FN6189.6
April 22, 2016
ISL45041
Electrical Specifications
Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ; (See Figure 2) Unless otherwise
specified. Typicals are at TA = +25°C. Boldface limits apply across the operating temperature range, 0°C to +85°C. (Continued)
PARAMETER
SYMBOL
SDA, SCL Input Logic High
I2CVIH
SDA, SCL Input Logic Low
I2CVIL
SDA, SCL Hysteresis
TEST CONDITIONS
MIN
(Note 6)
TYP
0.7*VDD
V
0.55
260
(Note 9)
SDA Output Logic High
VOHS
SDA Output Logic Low
VOLS
WP Input Logic High
VIH
WP Input Logic Low
VIL
WP Hysteresis
V
mV
VDD - 0.4
V
at 3mA
0.4
0.7*VDD
V
V
0.3*VDD
(Note 9)
WP Input Current
MAX
(Note 6) UNITS
0.14VDD
V
V
ILWPN
0.20
35
µA
SCL Clock Frequency
fSCL
0
400
kHz
I2C Clock High Time
tSCH
0.6
µs
I2C Clock Low Time
tSCL
1.3
µs
I2C Spike Rejection Filter Pulse Width
tDSP
0
I2C Data Set Up Time
tSDS
100
ns
I2C Data Hold Time
tSDH
900
ns
I2C SDA, SCL Input Rise Time
tICR
Dependent on Load (Note 10)
20 + 0.1*Cb
1000
ns
I2C SDA, SCL Input Fall Time
tICF
(Note 10)
20 + 0.1*Cb
300
ns
I2C Bus Free Time Between Stop and Start
tBUF
200
µs
I2C Repeated Start Condition Set-up
tSTS
0.6
µs
I2C Repeated Start Condition Hold
tSTH
0.6
µs
I2C Stop Condition Set-up
tSPS
0.6
µs
I2C Bus Capacitive Load
Cb
400
pF
CSDA
10
pF
I2C Timing
SDA Pin Capacitance
50
ns
SCL Pin Capacitance
CS
10
pF
EEPROM Write Cycle Time
tW
100
ms
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. IDD current may increase to 2mA for 45ms or less during each EEPROM programming operation.
8. IAVDD current may increase to 1mA for 30ms or less during each EEPROM programming operation.
9. Simulated and Determined via Design and NOT Directly Tested.
10. Simulated and Designed According to I2C Specifications.
11. A typical Current of 20µA is Calculated using AVDD = 10V and RSET = 24.9kΩ. Reference “RSET Resistor” in Figure 3.
12. Minimum value of RSET resistor guaranteed when: AVDD = 15V, VDD = 3.0V and when voltage on the VOUT pin is greater than 2.5V. Reference Equation 2
on page 5 with Setting = 128.
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April 22, 2016
ISL45041
Application Information
RSET Resistor
This device provides the ability to reduce the flicker of an LCD
panel by adjustment of the VCOM voltage during production test
and alignment. A 128-step resolution is provided under digital
control, which adjusts the sink current of the output. The output is
connected to an external voltage divider, so that the device will
have the capability to reduce the voltage on the output by
increasing the output sink current.
The external RSET resistor sets the full-scale sink current, ISET
maximum, that determines the lowest voltage of the external
voltage divider R1 and R2 (Figure 2). The voltage difference between
the OUT pin and SET pin (Figure 3), which are also the drain and
source of the output transistor, must be greater than 1.75V. This will
keep the output transistor in its saturation region to maintain linear
operation over the full range of register values. Expected current
settings and 7-bit accuracy occurs when the output MOS transistor is
operating in the saturation region. Figure 3 shows the internal
connection for the output MOS transistor. The value of the AVDD
supply sets the voltage at the source of the output transistor. This
voltage is equal to (Setting/128) x (AVDD/20). The ISET current is
therefore equal to (Setting/128) x (AVDD/20 x RSET). The drain
voltage is calculated using Equation 2. The values of R1 and R2
(Equation 2) should be determined using IOUT maximum (setting
equal to 128) so the minimum value of VOUT is greater than 1.75V +
AVDD/20.
AVDD
AVDD
ISL45041
R1
+
OUT
SET
RSET
IOUT
R2
FIGURE 2. OUTPUT CONNECTION CIRCUIT EXAMPLE
Expected Output Voltage
AV DD
Setting
I OUT = --------------------- x --------------------------20  R SET 
128
(EQ. 1)
R1
 R2 


Setting
V OUT =  --------------------- AV DD  1 – --------------------- x ---------------------------
20  R SET 
128
 R 1 + R 2

(EQ. 2)
Table 1 gives the calculated value of VOUT using the resistor values
of: RSET = 24.9kΩ, R1 = 200kΩ, R2 = 243kΩ and AVDD = 10V.
TABLE 1.
SETTING VALUE
VOUT
(V)
1
5.468
10
5.313
20
5.141
30
4.969
40
4.797
50
4.625
60
4.453
70
4.281
80
4.109
90
3.936
100
3.764
110
3.592
128
3.282
5
AVDD = 15V
R1
AVDD
The ISL45041 provides an output sink current, which lowers the
voltage on the external voltage divider (VCOM output voltage).
Equations 1 and 2 can be used to calculate the output current
(IOUT) and output voltage (VOUT) values. The setting is the register
value +1 with a value between 1 and 128.
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OUT PIN
AV
DD
SETTING
----------------------------x -----------------20
128
The adjustment of the output is provided by the 2-wire I2C serial
interface.
VSAT
0.5V
RSET
R2
SET PIN
FIGURE 3. OUTPUT CONNECTION CIRCUIT EXAMPLE
Ramp-Up of the VDD Power Supply
The ramp-up from 10% VDD to 90% VDD level must be achieved
in 10ms or less to ensure that the EEPROM and power-on-reset
circuits are synchronized and the correct value is read from the
EEPROM Memory.
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 3. When applying power, VDD should be applied before or
at the same time as AVDD. The minimum time for tVS is 0µs.
When removing power, the sequence of VDD and AVDD is not
important.
VDD
AVDD
tVS
FIGURE 3. POWER SUPPLY SEQUENCE
Do not remove VDD or AVDD within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
FN6189.6
April 22, 2016
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I2C Bus Format
ISL45041 I2C WRITE FORMAT
BYTE 1
BYTE 2
DON’T
CARE
6 BIT ADDRESS
START
MSB
ACK
R/W
LSB
PROGRAM
DATA
ACK
STOP
LSB
MSB
6
1
0
0
1
1
1
X
0
A
D7
D6
D5
D4
R/W = 0 = WRITE
R/W = 1 = READ
D3
D2
P
D1
A
WHEN R/W = 0
P = 0 = EEPROM PROGRAMMING
P = 1 = REGISTER WRITE
BYTE 1
BYTE 2
DON’T
CARE
6 BIT ADDRESS
START
MSB
1
R/W
ACK
LSB
0
0
1
1
1
X
1
START
DATA
ACK
MSB
A
LSB
D7
D6
D5
R/W = 0 = WRITE
R/W = 1 = READ
FIGURE 4. ISL45041 I2C READ AND WRITE FORMAT
I2C Addressing
FN6189.6
April 22, 2016
The ISL45041 will respond identically to either of two I2C address: 1001110x and
1001111x. 100111x is the preferred address. To prevent bus conflicts, ensure that
there are no other devices on the I2C bus with either of the above addresses.
D4
D3
D2
D1
D0
A
STOP
ISL45041
ISL45041 I2C READ FORMAT
ISL45041
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
April 22, 2016
FN6189.6
Removed AN1244 from related literature section.
October 30, 2014
FN6189.5
Updated datasheet to Intersil’s new standards.
Added related Literature on page 1.
Moved Block Diagram to page 1.
Moved the Pin Configurations and Ordering Information to page 2.
Added Pad to “Pin Descriptions” on page 2.
In Table 1 on page 5, updated typo in first row (VOUT value) from “5.486” to “5.468” and added (V) units to
header.
Added revision history and About Intersil sections.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN6189.6
April 22, 2016
ISL45041
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
3.00
( 1.95)
A
B
3.00
( 8X 0.50)
6
PIN 1
INDEX AREA
(4X)
(1.50)
( 2.90 )
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
2X 1.950
6X 0.65
PIN #1
INDEX AREA
0.10 C
0.75 ±0.05
C
0.08 C
1
SIDE VIEW
6
1.50 ±0.10
8
8X 0.30 ±0.05
8X 0.30 ± 0.10
2.30 ±0.10
C
4
0.10 M C A B
0 . 2 REF
5
0 . 02 NOM.
0 . 05 MAX.
DETAIL "X"
BOTTOM VIEW
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7.
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Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
FN6189.6
April 22, 2016
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