DATASHEET

HA5351
Data Sheet
April 25, 2013
FN3690.11
64ns Sample and Hold Amplifier
Features
The HA5351 is a fast acquisition, wide bandwidth sample
and hold amplifier, built with the Intersil HBC-10 BiCMOS
process. This sample and hold amplifier offers a combination
of desirable features; fast acquisition time (70ns to 0.01%
maximum), excellent DC precision and extremely low power
dissipation, making it ideal for use in systems that sample
multiple signals and require low power.
• Fast Acquisition to 0.01%. . . . . . . . . . . . . . . . . 70ns (Max)
The HA5351 is in an open loop configuration with fully
differential inputs providing flexibility for user defined
feedback. In unity gain the HA5351 is completely self-contained
and requires no external components. The on-chip 15pF
hold capacitor is completely isolated to minimizing droop
rate and reducing sensitivity to pedestal error. The HA5351
is available in 8 lead SOIC package for minimizing board
space and ease of layout.
• Low Power Dissipation . . . . . . . . . . . . . . . .220mW (Max)
HA5351IBZ
PART
MARKING
TEMP.
RANGE (°C)
5351 IBZ
-40 to +85
PACKAGE
(Pb-free)
8 Ld SOIC
PKG.
DWG. #
M8.15
Functional Diagram
V+
6
V3
15pF
8
+
+
GM
1
+IN
S/H
• Low Droop Rate . . . . . . . . . . . . . . . . . . . . . . 2µV/µs (Max)
• Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . . 40MHz
• Total Harmonic Distortion (Hold Mode) . . . . . . . . . -72dBc
- (VIN = 5VP-P at 1MHz)
• Fully Differential Inputs
• On Chip Hold Capacitor
• Pb-Free (RoHS Compliant)
• Synchronous Sampling
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
-IN
• Low Pedestal Error. . . . . . . . . . . . . . . . . . . . ±10mV (Max)
Applications
Ordering Information
PART
NUMBER
(Note)
• Low Offset Error . . . . . . . . . . . . . . . . . . . . . . . ±2mV (Max)
AV
• Wide Bandwidth A/D Conversion
• Deglitching
• Peak Detection
• High Speed DC Restore
Pinout
HA5351
(8 LD SOIC)
TOP VIEW
+IN
1
8
-IN
NC
2
7
GND
V-
3
6
V+
OUT
4
5
S/H
CTRL
4
OUT
-
5
BUFFER
HA5351
7
GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2003, 2006, 2007, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HA5351
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . .+11V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
Voltage Between Sample and Hold Control and Ground. . . . . +5.5V
Output Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . ±37mA
Thermal Resistance (Typical, Note 1)
Operating Conditions
θJA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profilesee link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Test Conditions: VSUPPLY = ±5V; CH = Internal = 15pF, Digital Input: VIL = 0V (Sample), VIH = 4.0V (Hold).
Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF,
Unless Otherwise Specified
Electrical Specifications
TEMP.
(°C)
MIN
Input Voltage Range
Full
Input Resistance (Note 2)
+25
Input Capacitance
+25
Input Offset Voltage
+25
-2
Full
-3.0
Offset Voltage Temperature Coefficient
Full
-
15
Bias Current
Full
-
Offset Current
Full
-1.5
PARAMETER
TEST CONDITIONS
TYP
MAX
UNITS
-2.5
-
+2.5
V
100
500
-
kΩ
-
-
5
pF
-
2
mV
-
3.0
mV
-
µV/°C
2.5
5
µA
-
+1.5
µA
INPUT CHARACTERISTICS
Common Mode Range
Full
-2.5
-
+2.5
V
±2.5V, Note 3
Full
60
80
-
dB
VOUT = ±2.5V
+25
95
108
-
dB
Full
85
-
-
dB
25
-
40
-
MHz
200mV Step
+25
-
8.5
-
ns
Overshoot
200mV Step
+25
0
-
30
%
Slew Rate
5V Step
Full
88
105
-
V/µs
+25, +85
2.1
-
5.0
V
-40
2.4
-
5.0
V
Full
0
-
0.8
V
Common Mode Rejection Ratio
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
Unity Gain -3dB Bandwidth
TRANSIENT RESPONSE
Rise Time
DIGITAL INPUT CHARACTERISTICS
Input Voltage
VIH
VIL
Input Current
VIL = 0V
Full
-1.0
-
1.0
µA
VIH = 5V
Full
-1.0
-
1.0
µA
OUTPUT CHARACTERISTICS
Output Voltage
RL = 510Ω
Full
-3.0
-
+3.0
V
Output Current
RL = 100Ω
+25, +85
20
25
-
mA
-40
15
-
-
mA
Full Power Bandwidth
5VP-P, AV = +1, -3dB
Full
-
13
-
MHz
Output Resistance
Hold Mode
+25
-
0.02
-
Ω
Total Output Noise
(DC to 10MHz)
Sample Mode
+25
-
325
-
µVRMS
Hold Mode
+25
-
325
-
µVRMS
2
FN3690.11
April 25, 2013
HA5351
Test Conditions: VSUPPLY = ±5V; CH = Internal = 15pF, Digital Input: VIL = 0V (Sample), VIH = 4.0V (Hold).
Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF,
Unless Otherwise Specified (Continued)
Electrical Specifications
PARAMETER
TEMP.
(°C)
MIN
TYP
MAX
UNITS
VIN = 4.5VP-P, fIN = 100kHz
+25
-
-80
-
dBc
VIN = 5VP-P, fIN = 1MHz
+25
-
-74
-
dBc
TEST CONDITIONS
DISTORTION CHARACTERISTICS
SAMPLE MODE
Total Harmonic Distortion
Signal to Noise Ratio
(RMS Signal to RMS Noise)
VIN = 1VP-P, fIN = 10MHz
+25
-
-57
-
dBc
VIN = 4.5VP-P, fIN = 100kHz
+25
-
73
-
dB
VIN = 4.5VP-P, fIN = 100kHz,
fS ≅ 100kHz
+25
-
-78
-
dBc
VIN = 5VP-P, fIN = 1MHz,
fS ≅ 1MHz
+25
-
-72
-
dBc
VIN = 1VP-P, fIN = 10MHz,
fS ≅ 1MHz
+25
-
-51
-
dBc
VIN = 4.5VP-P, fIN = 100kHz,
fS ≅ 100kHz
+25
-
70
-
dB
0V to 2.0V Step to ±1mV
+25
-
53
-
ns
0V to 2.0V Step to 0.01%
(±200μV)
+25
-
64
70
ns
-2.5V to +2.5V Step to 0.01%
(±500µV)
+25
-
90
100
ns
+25
-
0.3
-
µV/µs
HOLD MODE (50% Duty Cycle S/H)
Total Harmonic Distortion
Signal to Noise Ratio
(RMS Signal to RMS Noise)
SAMPLE AND HOLD CHARACTERISTICS
Acquisition Time
Droop Rate
Full
-2
-
2
µV/µs
Hold Step Error
VIL = 0V, VIH = 4.0V, tR = 5ns
Full
-10
-
+10
mV
Hold Mode Settling Time
To ±1mV
+25
-
50
-
ns
Hold Mode Feedthrough
5VP-P, 500kHz, Sine
+25
-
72
-
dB
+25
-
+1
-
ns
EADT (Effective Aperture Delay Time)
Aperture Time (Note 2)
+25
-
10
-
ns
Aperture Uncertainty
+25
-
10
20
ps
Positive Supply Current
Full
-
20
22
mA
Negative Supply Current
Full
-
20
22
mA
Full
60
74
-
dB
POWER SUPPLY CHARACTERISTICS
PSRR
10% Delta
NOTES:
2. Derived from Computer Simulation only, not tested.
3. +CMRR is measured from 0V to +2.5V, -CMRR is measured from 0V to -2.5V.
3
FN3690.11
April 25, 2013
HA5351
Typical Performance Curves
0.1
OUTPUT (V)
OUTPUT (V)
2
0
0.0
-0.1
-2
0
100
200
300
TIME (ns)
400
500
200
FIGURE 1. LARGE SIGNAL RESPONSE
400
TIME (ns)
600
FIGURE 2. SMALL SIGNAL RESPONSE
2
60
0
40.163156MHz
-3dB
-4
GAIN
0dB AT 21.34MHz
20
-30
-60
0
-6
1M
10M
1k
100M
²
-90
²
-120
PHASE
-119.86°
-20
-8
100k
0
10k
FREQUENCY (Hz)
100k
1M
PHASE (°)
-2
GAIN (dB)
GAIN (dB)
40
-150
-180
100M
10M
FREQUENCY (Hz)
FIGURE 3. UNITY GAIN FREQUENCY RESPONSE
FIGURE 4. CLOSED LOOP GAIN/PHASE AV = +1000
2
60
200mVP-P
50
-3dB BANDWIDTH (MHz)
GAIN (dB)
0
13.241189MHz
-3dB
-2
²
-4
-6
-8
10k
4 TYPICAL UNITS
40
30
20
10
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 5. 5VP-P FULL POWER FREQUENCY RESPONSE
4
0
±3.5
±4
±4.5
±5
SUPPLY VOLTAGE (V)
±5.5
±6
FIGURE 6. -3dB BANDWIDTH vs SUPPLY VOLTAGE
FN3690.11
April 25, 2013
HA5351
Typical Performance Curves (Continued)
160
0.5
3 TYPICAL UNITS
+SLEW RATE
-SLEW RATE
3 TYPICAL UNITS
150
140
SLEW RATE (V/μs)
DROOP RATE (μV/μs)
0.4
0.3
0.2
UNIT #1
130
120
110
UNIT #3
UNIT #2
100
0.1
90
0
-50
0
50
TEMPERATURE (°C)
80
-50
100
FIGURE 7. DROOP RATE vs TEMPERATURE
100
FIGURE 8. SLEW RATE vs TEMPERATURE
65
9
4 TYPICAL UNITS
HOLD MODE SETTLING TIME (ns)
4 TYPICAL UNITS
8
RISE TIME (ns)
0
50
TEMPERATURE (°C)
7
6
5
4
-50
0
50
TEMPERATURE (°C)
60
55
50
45
40
35
30
-50
100
FIGURE 9. RISE TIME vs TEMPERATURE
0
50
TEMPERATURE (°C)
100
FIGURE 10. HOLD MODE SETTLING vs TEMPERATURE
3
0V TO 4V S/H CTRL
0.01
10
1
0
0.00
5
S/H
CONTROL
67.25ns
-1
S/H CONTROL (V)
OUTPUT
OUTPUT (V)
PEDESTAL ERROR (mV)
2
0
-0.01
-2
0
10
20
30
40
S/H CONTROL RISE TIME (ns)
FIGURE 11. PEDESTAL vs S/H CONTROL RISE TIME
5
50
3.0E-7
TIME (ns)
FIGURE 12. ACQUISITION TIME (0.01%, 0V TO 2V STEP)
FN3690.11
April 25, 2013
HA5351
Typical Performance Curves (Continued)
OUTPUT
0.02
0.00
5
-0.02
51.4 ns
-0.04
S/H CONTROL (V)
OUTPUT (V)
10
0
0
20
40
TIME (ns)
60
80
FIGURE 13. HOLD MODE SETTLING TIME (±200μV)
Die Characteristics
TRANSISTOR COUNT:
156
SUBSTRATE POTENTIAL:
V-
Metallization Mask Layout
GND
HA5351
GND
GND
V+
V+
V+
S/H CONTROL
-IN
VOUT
VOUT
+IN
V-
V-
V-
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
6
FN3690.11
April 25, 2013
HA5351
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
7
FN3690.11
April 25, 2013
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