Working Draft T13 1410D Revision 3b 26 February 2002 Information Technology AT Attachment with Packet Interface - 6 (ATA/ATAPI-6) This is an internal working document of T13, a Technical Committee of Accredited Standards Committee NCITS. As such, this is not a completed standard and has not been approved. The contents may be modified by the T13 Technical Committee. This document is made available for review and comment only. Permission is granted to members of NCITS, its technical committees, and their associated task groups to reproduce this document for the purposes of NCITS standardization activities without further permission, provided this notice is included. All other rights are reserved. Any commercial or for-profit replication or republication is prohibited. T13 Technical Editor: Peter T. McLean Maxtor Corporation 2190 Miller Drive Longmont, CO 80501-6744 USA Tel: 303-678-2149 Fax: 303-682-4811 Email: [email protected] Reference number ANSI NCITS.*** - xxxx Printed February, 26, 2002 11:08AM T13/1410D revision 3b Other Points of Contact: T13 Chair Pete McLean Maxtor Corporation 2452 Clover Basin Drive Longmont, CO 80501 Tel: 303-678-2149 Fax: 303-682-4811 T13 Vicechair Dan Colegrove IBM Corporation 2903 Carmelo Drive Henderson, NV 89052 Tel: 702 614-6119 Fax: 702 614-7995 NCITS Secretariat Administrator Standards Processing 1250 Eye Street, NW Suite 200 Washington, DC 20005 Tel: 202-737-8888 Fax: 202-638-4922 Email: [email protected] T13 Reflector See reflector instructions on the T13 Web Site at http://www.t13.org T13 Web Site http://www.t13.org T13 Anonymous FTP Site ftp.t13.org T13 mailings Global Engineering 15 Inverness Way East Englewood, CO 80112-5704 Tel: 303-792-2181 or 800-854-7179 Fax: 303-792-2192 T13/1410D revision 3b DOCUMENT STATUS Revision 0 – 20 April 2000 Document created from ATA/ATAPI-5-revision 3 (T13/1321Dr3). Added proposal D99121R1 Multisector error log proposal as requested at the 8/24-27/99 plenary meeting. Added proposal D99131R6 Automatic acoustic management as requested at the 4/18-19/00 plenary meeting. Revision 0a – 28 June 2000 Added changes requested by the ANSII editor for ATA/ATAPI-5. Added proposal E00108R0 clearing of DEV at reset with 400µs replaced with 1ms. Added the ATAPI portion of proposal E00118R0 Device 0 responding for Device 1. Added proposal E00120R2 Ultra DMA 100 with requested timing diagram modifications. Made changes requested at the June 20-22 2000 plenary meeting. Revision 0b - 2 October 2000 Added changes from E00136R1 ATA/ATAPI-5 issues list Added E00101R6 48-bit LBA Added E00126R2 Revised Annex D Added E00142R2 READ VERIFY modification Made changes requested during change bar review at the 8/28-31/00 plenary Revision 1 - 1 November 2000 Added proposal E00137R0, proposal to modify ID word 50. Added proposal E144R1, modify FLUSH CACHE command. Added proposal E00140R1, Device cnfiguration overlay proposal. Made changes indicated in E00136R3, ATA/ATAPI-5 issues list. Made changes requested during change bar review at the 10/16-20/00 plenary. Revision 1a - 18 December 2000 Replaced cable detect description in 5.2.11. Added error codes in DEVICE CONFIGURATION SET command error output. Made changes requested during change bar review at the 12/12-14/00 plenary. Revision 1b - 14 March 2001 Added proposal e00110r1 Proposal to obsolete CHS. Added proposal e00116r1 180 ns min PIO transfer period proposal. Added proposal e00159r3 Mandatory IDENTIFY DEVICE fields. Added proposal e00163r2 Media serial number proposal. Added proposal e01108r0 WD ATA DCO concerns. Made changes requested during change bar review at the 2/20-22/01 plenary. Revision 1c - 4 June 2001 Added proposal d99128r10 Proposal for Audio Visual feature set except log. Added proposal e00157r1 Small format card adapter proposal. Added proposal e01106r0 Cable detection issues. Added proposal e01117r1 Proposal to obsolete IDENTIFY PACKET DEVICE word 126. Made changes requested during change bar review at the 4/24-25/01 plenary. T13/1410D revision 3b Revision 1d - 26 June 2001 Added proposal e00138r4 General purpose logging feature. Added the logs associated with d99128r10 Audio Visual feature set. Made changes requested during change bar review at the 6/19-20/01 plenary meeting Revision 1e – 26 June 2001 Same as revision 1d with the change bars eliminated. Revision 2 - 2 August 2001 Made editorial changes requested during the 7/24-26/2001 editorial review. Revision 2a - 26 September 2001 Made changes requested during change bar review at the 8/21-23/2001 plenary meeting. Revision 2b - 30 October 2001 Removed proposal d99128r10 Proposal for Audio Visual feature set including logs as requested at the 10/2325/2001 plenary meeting. Made editorial changes requested at the 10/23-25/2001 plenary meeting. Revision 3 – 30 October 2001 Same as revision 2b but without change bars. Revision 3a – 14 December 2001 Made changes agreed to during letter ballot comment resolution, e01143r1. Revision 3b – 26 February 2002 Made changes contianed in e02109r0 resolution of public review comments. Made changes requested by the ANSI editor. T13/1410D revision 3b ANSI® NCITS.***-xxxx American National Standard for Information Technology AT Attachment with Packet Interface - 6 (ATA/ATAPI-6) Secretariat Information Technology Industry Council Approved mm dd yy American National Standards Institute, Inc. Abstract This standard specifies the AT Attachment Interface between host systems and storage devices. It provides a common attachment interface for systems manufacturers, system integrators, software suppliers, and suppliers of intelligent storage devices. It includes the Packet Command feature set implemented by devices commonly known as ATAPI devices. This standard maintains a high degree of compatibility with the AT Attachment Interface with Packet Interface – 5 (ATA/ATAPI-5), NCITS 340-2000, and while providing additional functions, is not intended to require changes to presently installed devices or existing software. T13/1410D revision 3b American National Standard Approval of an American National Standard requires verification by ANSI that the requirements for due process, consensus, and other criteria for approval have been met by the standards developer. Consensus is established when, in the judgment of the ANSI Board of Standards Review, substantial agreement has been reached by directly and materially affected interests. Substantial agreement means much more than a simple majority, but not necessarily unanimity. Consensus requires that all views and objections be considered, and that effort be made towards their resolution. The use of American National Standards is completely voluntary; their existence does not in any respect preclude anyone, whether he has approved the standards or not, from manufacturing, marketing, purchasing, or using products, processes, or procedures not conforming to the standards. The American National Standards Institute does not develop standards and will in no circumstances give interpretation on any American National Standard. Moreover, no person shall have the right or authority to issue an interpretation of an American National Standard in the name of the American National Standards Institute. Requests for interpretations should be addressed to the secretariat or sponsor whose name appears on the title page of this standard. CAUTION NOTICE: This American National Standard may be revised or withdrawn at any time. The procedures of the American National Standards Institute require that action be taken periodically to reaffirm, revise, or withdraw this standard. Purchasers of American National Standards may receive current information on all standards by calling or writing the American National Standards Institute. CAUTION: The developers of this standard have requested that holders of patents that may be required for the implementation of the standard, disclose such patents to the publisher. However, neither the developers nor the publisher have undertaken a patent search in order to identify which, if any, patents may apply to this standard. As of the date of publication of this standard and following calls for the identification of patents that may be required for the implementation of the standard, notice of one or more such claims has been received. By publication of this standard, no position is taken with respect to the validity of this claim or of any rights in connection therewith. The patent holders have, however, filed a statement of willingness to grant a license under these rights on reasonable and nondiscriminatory terms and conditions to applicants desiring to obtain such a license. Details may be obtained from the publisher. No further patent search is conducted by the developer or the publisher in respect to any standard it processes. No representation is made or implied that licenses are not required to avoid infringement in the use of this standard. Published by American National Standards Institute 11 West 42nd Street, New York, New York 10036 Copyright nnnn by American National Standards Institute All rights reserved. T13/1410D revision 3b Contents 1 2 3 4 5 6 7 Page Scope .....................................................................................................................................1 Normative references ................................................................................................................1 2.1 Approved references........................................................................................................1 2.2 References under development.........................................................................................2 2.3 Other references .............................................................................................................2 Definitions, abbreviations, and conventions .................................................................................2 3.1 Definitions and abbreviations ............................................................................................2 3.2 Conventions ...................................................................................................................5 Interface physical and electrical requirements .............................................................................10 4.1 Cable configuration .........................................................................................................10 4.2 Electrical characteristics .................................................................................................11 Interface signal assignments and descriptions ............................................................................16 5.1 Signal summary .............................................................................................................16 5.2 Signal descriptions .........................................................................................................17 General operational requirements...............................................................................................22 6.1 Command delivery ..........................................................................................................22 6.2 Register delivered data transfer command sector addressing ..............................................22 6.3 Interrupts .......................................................................................................................23 6.4 General feature set .........................................................................................................23 6.5 Multiword DMA...............................................................................................................25 6.6 Ultra DMA feature set......................................................................................................26 6.7 Host determination of cable type by detecting CBLID- ........................................................28 6.8 PACKET Command feature set ........................................................................................30 6.9 Overlapped feature set.....................................................................................................31 6.10 Queued feature set .........................................................................................................32 6.11 Power Management feature set ........................................................................................33 6.12 Advanced Power Management feature set .........................................................................36 6.13 Security Mode feature set................................................................................................36 6.14 Self-monitoring, analysis, and reporting technology feature set............................................42 6.15 Host Protected Area feature set .......................................................................................44 6.16 CFA feature set ..............................................................................................................47 6.17 Removable Media Status Notification and Removable Media feature sets .............................48 6.18 Power-Up In Standby feature set ......................................................................................50 6.19 Automatic Acoustic Management feature set ....................................................................50 6.20 48-bit Address feature set................................................................................................51 6.21 Device Configuration Overlay feature set............................................................................53 6.22 Media Card Pass Through Command feature set ...............................................................55 6.23 General Purpose Logging feature set ................................................................................56 Interface register definitions and descriptions ..............................................................................56 7.1 Device addressing considerations.....................................................................................56 7.2 I/O register descriptions ..................................................................................................63 7.3 Alternate Status register..................................................................................................63 7.4 Command register ..........................................................................................................64 7.5 Data port........................................................................................................................65 7.6 Data register ..................................................................................................................65 7.7 Device register................................................................................................................66 7.8 Device Control register ....................................................................................................67 7.9 Error register ..................................................................................................................68 7.10 Features register ............................................................................................................69 7.11 LBA High register ...........................................................................................................69 7.12 LBA Low register ............................................................................................................70 7.13 LBA Mid register.............................................................................................................70 7.14 Sector Count register ......................................................................................................71 7.15 Status register................................................................................................................71 Page i T13/1410D revision 3b 8 Command descriptions ............................................................................................................. 74 8.1 CFA ERASE SECTORS ................................................................................................. 75 8.2 CFA REQUEST EXTENDED ERROR CODE ..................................................................... 77 8.3 CFA TRANSLATE SECTOR ............................................................................................ 80 8.4 CFA WRITE MULTIPLE WITHOUT ERASE....................................................................... 82 8.5 CFA WRITE SECTORS WITHOUT ERASE....................................................................... 84 8.6 CHECK MEDIA CARD TYPE........................................................................................... 86 8.7 CHECK POWER MODE ................................................................................................. 88 8.8 DEVICE CONFIGURATION ............................................................................................. 90 8.9 DEVICE RESET............................................................................................................. 101 8.10 DOWNLOAD MICROCODE ............................................................................................. 103 8.11 EXECUTE DEVICE DIAGNOSTIC .................................................................................... 105 8.12 FLUSH CACHE .............................................................................................................. 106 8.13 FLUSH CACHE EXT ....................................................................................................... 108 8.14 GET MEDIA STATUS ..................................................................................................... 111 8.15 IDENTIFY DEVICE ......................................................................................................... 113 8.16 IDENTIFY PACKET DEVICE ........................................................................................... 135 8.17 IDLE.............................................................................................................................. 148 8.18 IDLE IMMEDIATE ........................................................................................................... 150 8.19 MEDIA EJECT ............................................................................................................... 151 8.20 MEDIA LOCK................................................................................................................. 153 8.21 MEDIA UNLOCK ............................................................................................................ 155 8.22 NOP.............................................................................................................................. 157 8.23 PACKET........................................................................................................................ 159 8.24 READ BUFFER.............................................................................................................. 164 8.25 READ DMA ................................................................................................................... 166 8.26 READ DMA EXT............................................................................................................. 168 8.27 READ DMA QUEUED..................................................................................................... 171 8.28 READ DMA QUEUED EXT .............................................................................................. 175 8.29 READ LOG EXT ............................................................................................................. 180 8.30 READ MULTIPLE ........................................................................................................... 188 8.31 READ MULTIPLE EXT .................................................................................................... 191 8.32 READ NATIVE MAX ADDRESS....................................................................................... 194 8.33 READ NATIVE MAX ADDRESS EXT ................................................................................ 196 8.34 READ SECTOR(S)......................................................................................................... 199 8.35 READ SECTOR(S) EXT .................................................................................................. 201 8.36 READ VERIFY SECTOR(S) ............................................................................................ 204 8.37 READ VERIFY SECTOR(S) EXT...................................................................................... 206 8.38 SECURITY DISABLE PASSWORD.................................................................................. 209 8.39 SECURITY ERASE PREPARE........................................................................................ 211 8.40 SECURITY ERASE UNIT ................................................................................................ 212 8.41 SECURITY FREEZE LOCK ............................................................................................. 214 8.42 SECURITY SET PASSWORD ......................................................................................... 216 8.43 SECURITY UNLOCK ...................................................................................................... 219 8.44 SEEK............................................................................................................................ 221 8.45 SERVICE ...................................................................................................................... 223 8.46 SET FEATURES ............................................................................................................ 224 8.47 SET MAX....................................................................................................................... 230 1.48 SET MAX ADDRESS EXT ............................................................................................... 240 1.49 SET MULTIPLE MODE ................................................................................................... 243 1.50 SLEEP.......................................................................................................................... 245 1.51 SMART ......................................................................................................................... 247 1.52 STANDBY ..................................................................................................................... 274 1.53 STANDBY IMMEDIATE................................................................................................... 276 1.54 WRITE BUFFER ............................................................................................................ 277 1.55 WRITE DMA .................................................................................................................. 279 Page ii T13/1410D revision 3b 1.56 WRITE DMA EXT............................................................................................................281 1.57 WRITE DMA QUEUED....................................................................................................284 1.58 WRITE DMA QUEUED EXT .............................................................................................289 1.59 WRITE LOG EXT ............................................................................................................294 1.60 WRITE MULTIPLE ..........................................................................................................297 1.61 WRITE MULTIPLE EXT ...................................................................................................299 1.62 WRITE SECTOR(S)........................................................................................................303 1.63 WRITE SECTOR(S) EXT .................................................................................................305 9 Protocol ..................................................................................................................................308 9.1 Power-on and hardware reset protocol ..............................................................................311 9.2 Software reset protocol....................................................................................................315 9.3 Bus idle protocol.............................................................................................................320 9.4 Non-data command protocol ............................................................................................331 9.5 PIO data-in command protocol.........................................................................................333 9.6 PIO data-out command protocol.......................................................................................337 9.7 DMA command protocol..................................................................................................341 9.8 PACKET command protocol ............................................................................................344 9.9 READ/WRITE DMA QUEUED command protocol..............................................................356 9.10 EXECUTE DEVICE DIAGNOSTIC command protocol.........................................................361 9.11 DEVICE RESET command protocol .................................................................................365 9.12 Signature and persistence...............................................................................................366 9.13 Ultra DMA data-in commands ..........................................................................................367 9.14 Ultra DMA data-out commands ........................................................................................370 9.15 Ultra DMA CRC rules ......................................................................................................372 9.16 Single device configurations .............................................................................................374 10 Timing.....................................................................................................................................375 10.1 Deskewing .....................................................................................................................375 10.2 Transfer timing................................................................................................................376 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Page Byte order..................................................................................................................................10 Byte order..................................................................................................................................10 DC characteristics ......................................................................................................................11 AC characteristics ......................................................................................................................12 Driver types and required termination ............................................................................................13 Typical series termination for Ultra DMA .......................................................................................15 Interface signal name assignments...............................................................................................16 Cable type identification ..............................................................................................................20 Host detection of CBLID- .............................................................................................................30 Security mode command actions ................................................................................................41 48-bit addresses ........................................................................................................................51 28-bit addresses ........................................................................................................................52 Media Card type references ........................................................................................................56 Device repsonse to DOIW-/DOIR- ................................................................................................57 Device is not selected, DMACK- is not asserted ...........................................................................58 Device is selected, DMACK- is not asserted.................................................................................59 Device is selected, DMACK- is asserted (for Multiword DMA only)..................................................60 Device 1 is selected and Device 0 is responding for Device 1..........................................................61 Device is in Sleep mode, DEVICE RESET is not implemented, DMACK- is not asserted..................62 Device is in Sleep mode, DEVICE RESET is implemented, DMACK- is not asserted .......................63 Extended error codes .................................................................................................................79 CFA TRANSLATE SECTOR information.......................................................................................81 Device Configuration Overlay Features register values....................................................................90 Page iii T13/1410D revision 3b 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Device Configuration Identify data structure .................................................................................. 95 Device Configuration Overlay data structure.................................................................................. 99 Diagnostic codes ....................................................................................................................... 106 IDENTIFY DEVICE information.................................................................................................... 115 Minor revision number ................................................................................................................ 127 IDENTIFY PACKET DEVICE information...................................................................................... 137 Automatic standby timer periods ................................................................................................. 148 Log address defintion ................................................................................................................. 181 General Purpose Log directory .................................................................................................... 183 Extended Comprehensive SMART error log .................................................................................. 184 Extended Error Log data structure............................................................................................... 185 Command data structure ............................................................................................................ 185 Error data structure.................................................................................................................... 186 State field values ....................................................................................................................... 186 Extended self-test log data structure ........................................................................................... 187 Extended self-test log descriptor entry ......................................................................................... 188 Security password content ......................................................................................................... 210 SECURITY ERASE UNIT password............................................................................................. 214 SECURITY SET PASSWORD data content ................................................................................. 218 Identifier and security level bit interaction ..................................................................................... 219 SET FEATURES register definitions ............................................................................................ 226 Transfer/mode values ................................................................................................................. 227 Advanced power management levels............................................................................................ 228 Automatic acoustic management levels ....................................................................................... 229 SET MAX Features register values .............................................................................................. 230 SET MAX SET PASSWORD data content ................................................................................... 234 SMART Feature register values ................................................................................................... 247 SMART EXECUTE OFF-LINE IMMEDIATE Sector Number register values ...................................... 256 Device SMART data structure ..................................................................................................... 259 Off-line data collection status byte values..................................................................................... 260 Self-test execution status byte values.......................................................................................... 260 Log address definition ................................................................................................................ 263 SMART log directory .................................................................................................................. 264 SMART summary error log sector ............................................................................................... 265 Error log data structure............................................................................................................... 265 Command data structure ............................................................................................................ 266 Error data structure.................................................................................................................... 267 State field values ....................................................................................................................... 267 Comprehensive error log ............................................................................................................. 268 Self-test log data structure.......................................................................................................... 269 Self-test log descriptor entry ....................................................................................................... 269 Equations for parallel generation of a CRC polynomial ................................................................... 374 Register transfer to/from device................................................................................................... 378 PIO data transfer to/from device .................................................................................................. 380 Multiword DMA data transfer....................................................................................................... 381 Ultra DMA data burst timing requirements.................................................................................... 386 Ultra DMA data burst timing descriptions ..................................................................................... 387 Ultra DMA sender and recipient IC timing requirements ................................................................. 388 Figures Page 1 State diagram convention ............................................................................................................ 8 2 Ultra DMA termination with pull-up or pull-down ............................................................................. 15 3 Cable select example ................................................................................................................. 21 Page iv T13/1410D revision 3b 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Alternate cable select example ....................................................................................................22 Example configuration of a system with a 40-conductor cable.........................................................29 Example configuration of a system where the host detects a 40-conductor cable..............................29 Example configuration of a system where the host detects an 80-conductor cable............................30 Power management state diagram ...............................................................................................34 Security mode state diagram .......................................................................................................38 SET MAX security state diagram.................................................................................................46 Device Configuration Overlay state diagram ..................................................................................54 Overall host protocol state sequence ...........................................................................................309 Overall device protocol state sequence.........................................................................................310 Host power-on or hardware reset state diagram.............................................................................311 Device power-on or hardware reset state diagram..........................................................................312 Host software reset state diagram ...............................................................................................315 Device 0 software reset state diagram..........................................................................................317 Device 1 software reset state diagram..........................................................................................319 Host bus idle state diagram ........................................................................................................321 Additional host bus idle state diagram with overlap or overlap and queuing.......................................323 Device bus idle state diagram......................................................................................................326 Additional device bus idle state diagram with overlap or overlap and queuing....................................328 Host non-data state diagram .......................................................................................................332 Device non-data state diagram ....................................................................................................332 Host PIO data-in state diagram ...................................................................................................334 Device PIO data-in state diagram.................................................................................................336 Host PIO data-out state diagram .................................................................................................338 Device PIO data-out state diagram...............................................................................................340 Host DMA state diagram ............................................................................................................342 Device DMA state diagram..........................................................................................................343 Host PACKET non-data and PIO data command state diagram......................................................345 Device PACKET non-data and PIO data command state diagram ...................................................348 Host PACKET DMA command state diagram ...............................................................................351 Device PACKET DMA command state diagram ............................................................................354 Host DMA QUEUED state diagram..............................................................................................357 Device DMA QUEUED command state diagram............................................................................359 Host EXECUTE DEVICE DIAGNOSTIC state diagram ...................................................................361 Device 0 EXECUTE DEVICE DIAGNOSTIC state diagram..............................................................362 Device 1 EXECUTE DEVICE DIAGNOSTIC command state diagram...............................................364 Host DEVICE RESET command state diagram.............................................................................365 Device DEVICE RESET command state diagram..........................................................................366 Example parallel CRC generator..................................................................................................374 Register transfer to/from device ...................................................................................................377 PIO data transfer to/from device...................................................................................................379 Initiating a Multiword DMA data burst...........................................................................................382 Sustaining a Multiword DMA data burst.......................................................................................383 Device terminating a Multiword DMA data burst ...........................................................................384 Host terminating a Multiword DMA data burst ..............................................................................385 Initiating an Ultra DMA data-in burst.............................................................................................389 Sustained Ultra DMA data-in burst...............................................................................................390 Host pausing an Ultra DMA data-in burst......................................................................................391 Device terminating an Ultra DMA data-in burst ..............................................................................392 Host terminating an Ultra DMA data-in burst.................................................................................393 Initiating an Ultra DMA data-out burst...........................................................................................394 Sustained Ultra DMA data-out burst.............................................................................................395 Device pausing an Ultra DMA data-out burst.................................................................................396 Host terminating an Ultra DMA data-out burst...............................................................................397 Device terminating an Ultra DMA data-out burst ............................................................................398 Page v T13/1410D revision 3b Annexes A B C D E Page Connectors and cable assemblies ................................................................................................ 399 Device determination of cable type................................................................................................ 419 Signal integrity and UDMA implementation guide ........................................................................... 422 Bibliography ............................................................................................................................... 476 ATA command set summary ........................................................................................................ 477 Page vi T13/1410D revision 3b Foreword (This foreward is not part of American National Standard NCITS ***-****.) This AT Attachment with Packet Interface - 6 (ATA/ATAPI-6) standard is designed to maintain a high degree of compatibility with the AT Attachment with Packet Interface – 5 (ATA/ATAPI-5) standard. This standard was developed by the ATA ad hoc working group of Accredited Standards Committee NCITS during 2000 and 2001. The standards approval process started in 2001. This document includes annexes that are informative and are not considered part of the standard. Requests for interpretation, suggestions for improvement and addenda, or defect reports are welcome. They should be sent to the NCITS Secretariat, Information Technology Industry Council, 1250 Eye Street, NW, Suite 200, Washington, DC 20005-3922. This standard was processed and approved for submittal to ANSI by Accredited Standards Committee on Information Processing Systems, NCITS. Committee approval of the standard does not necessarily imply that all committee members voted for approval. At the time it approved this standard, the NCITS Committee had the following members: , Chair , Vice-Chair , Secretary Organization Represented ......................................................................Name of Representative Technical Committee T13 on ATA Interfaces, that reviewed this standard, had the following members: Pete McLean, Chairman Dan Colegrove, Vice-Chairman Mark Evans, Secretary Technical Committee T13 on ATA Interfaces, that developed this standard, had the following additional participants: Page vii T13/1410D revision 3b Introduction This standard encompasses the following: Clause 1 describes the scope. Clause 2 provides normative references. Clause 3 provides definitions, abbreviations, and conventions used within this document. Clause 4 contains the electrical and mechanical characteristics. Clause 5 contains the signal descriptions of the AT Attachment Interface. Clause 6 describes the general operating requirements of the AT Attachment Interface. Clause 7 contains descriptions of the registers of the AT Attachment Interface. Clause 8 contains descriptions of the commands of the AT Attachment Interface. Clause 9 contains the protocol of the AT Attachment Interface. Clause 10 contains the interface timing diagrams. Page viii T13/1410D revision 3b AMERICAN NATIONAL STANDARD NCITS ***-nnnn American National Standard for Information Systems Information Technology AT Attachment with Packet Interface – 6 (ATA/ATAPI-6) 1 Scope This standard specifies the AT Attachment Interface between host systems and storage devices. It provides a common attachment interface for systems manufacturers, system integrators, software suppliers, and suppliers of intelligent storage devices. The application environment for the AT Attachment Interface is any host system that has storage devices contained within the processor enclosure. This standard defines the connectors and cables for physical interconnection between host and storage device, as well as the electrical and logical characteristics of the interconnecting signals. It also defines the operational registers within the storage device, and the commands and protocols for the operation of the storage device. This standard maintains a high degree of compatibility with the AT Attachment with Packet Interface – 5 standard (ATA/ATAPI-5), NCITS 340-2000, and while providing additional functions, is not intended to require changes to presently installed devices or existing software. 2 Normative references The following standards contain provisions that, through reference in the text, constitute provisions of this standard. At the time of publication, the editions indicated were valid. All standards are subject to revision, and parties to agreements based on this standard are encouraged to investigate the possibility of applying the most recent editions of the standards listed below. Copies of the following documents can be obtained from ANSI: Approved ANSI standards, approved and draft international and regional standards (ISO, IEC, CEN/CENELEC, ITUT), and approved and draft foreign standards (including BSI, JIS, and DIN). For further information, contact ANSI Customer Service Department at 212-6424900 (phone), 212-302-1286 (fax), or via the World Wide Web at http://www.ansi.org. Additional availability contact information is provided below as needed. 2.1 Approved references The following approved ANSI standards, approved international and regional standards (ISO, IEC, CEN/CENELEC, ITUT), may be obtained from the international and regional organizations who control them. SCSI-3 Primary Commands (SPC) Multimedia Commands (MMC) [ANSI X3.301-1997] (PACKET command feature set device types) [ANSI X3.304-1997] (PACKET command feature set sense codes) Page 1 T13/1410D revision 3b Multimedia Commands - 2 (MMC-2) [ANSI NCITS 333-2000] (PACKET command feature set commands) Protected Area Run Time Interface Extensions [ANSI NCITS 346-2001] SCSI Primary Commands - 2 (SPC-2) [ANSI NCITS 351-2001] (PACKET command feature set commands) To obtain copies of these documents, contact Global Engineering or NCITS. 2.2 References under development At the time of publication, the following referenced standards were still under development. For information on the current status of the document, or regarding availability, contact the relevant standards body or other organization as indicated. SCSI Primary Commands - 3 (SPC-3) Multimedia Commands - 3 (MMC-3) ATAPI for Rewritable Media [T10/1416-D] (PACKET command feature set commands) [T10/1363-D] (PACKET command feature set commands) [SFF8070i] For more information on the current status of the T10 documents, contact NCITS. To obtain copies of T10 or SFF documents, contact Global Engineering. 2.3 Other references The following standard and specifications are also referenced. PC Card Standard , February 1995, PCMCIA (68-pin Connector) For the PC Card Standard published by the Personal Computer Memory Card International Association, contact PCMCIA at 408-433-2273. CompactFlash Association Specification, Revision 1.4 For the CompactFlash Association Specification published by the CompactFlash Association, contact the CompactFlash Association at http://www.compactflash.org. ATA Packet Interface (ATAPI) for Streaming Tape QIC-157 revision D For QIC specifications published by Quarter-Inch Cartridge Drive Standards, Inc., contact them at 805 9633853. 3 Definitions, abbreviations, and conventions 3.1 Definitions and abbreviations For the purposes of this standard, the following definitions apply: 3.1.1 ATA (AT Attachment): ATA defines the physical, electrical, transport, and command protocols for the internal attachment of storage devices to host systems. 3.1.2 ATA-1 device: A device that complied with ANSI X3.221-1994, the AT Attachment Interface for Disk Drives. ANSI X3.221-1994 has been withdrawn. 3.1.3 ATA-2 device: A device that complied with ANSI X3.279-1996, the AT Attachment Interface with Extensions. ANSI X3.279-1996 has been withdrawn. 3.1.4 ATA-3 device: A device that complies with ANSI X3.298-1997, the AT Attachment-3 Interface. Page 2 T13/1410D revision 3b 3.1.5 ATA/ATAPI-4 device: A device that complies with ANSI NCITS 317-1998, AT Attachment Interface with Packet Interface Extensions. 3.1.6 ATA/ATAPI-5 device: A device that complies with ANSI NCITS 340-2000, the AT Attachment with Packet Interface -5. 3.1.7 ATA/ATAPI-6 device: A device that complies with this standard. 3.1.8 ATAPI (AT Attachment Packet Interface) device: A device implementing the Packet Command feature set. 3.1.9 bus release: For devices implementing overlap, the term bus release is the act of clearing both DRQ and BSY to zero before the action requested by the command is completed. This allows the host to select the other device or deliver another queued command. 3.1.10 byte count: The value placed in the Byte Count register by the device to indicate the number of bytes to be transferred during this DRQ assertion when executing a PACKET PIO data transfer command. 3.1.11 byte count limit: The value placed in the Byte Count register by the host as input to a PACKET PIO data transfer command to specify the maximum byte count that may be transferred during a single DRQ assertion. 3.1.12 CFA: The CompactFlash Association that created the specification for compact flash memory that uses the ATA interface. 3.1.13 check condition: For devices implementing the PACKET Command feature set, this indicates an error or exception condition has occurred. 3.1.14 CHS (cylinder-head-sector): This term defines an obsolete method of addressing the data on the device by cylinder number, head number, and sector number. 3.1.15 command aborted: Command completion with ABRT set to one in the Error register and ERR set to one in the Status register. 3.1.16 command acceptance: A command is considered accepted whenever the currently selected device has the BSY bit cleared to zero in the Status register and the host writes to the Command register. An exception exists for the DEVICE RESET command (see 8.9). 3.1.17 Command Block registers: Interface registers used for delivering commands to the device or posting status from the device. 3.1.18 command completion: Command completion is the completion by the device of the action requested by the command or the termination of the command with an error, the placing of the appropriate error bits in the Error register, the placing of the appropriate status bits in the Status register, the clearing of both BSY and DRQ to zero, and the asserting of INTRQ if nIEN is cleared to zero and the command protocol specifies that INTRQ be asserted. 3.1.19 command packet: A command packet is a data structure transmitted to the device during the execution of a PACKET command that includes the command and command parameters. 3.1.20 command released: When a device supports overlap or queuing, a command is considered released when a bus release occurs before command completion. 3.1.21 Control Block registers: Interface registers used for device control and to post alternate status. 3.1.22 CRC: Cyclical Redundancy Check used to check the validity of certain data transfers. Page 3 T13/1410D revision 3b 3.1.23 device: Device is a storage peripheral. Traditionally, a device on the interface has been a hard disk drive, but any form of storage device may be placed on the interface provided the device adheres to this standard. 3.1.24 device selection: A device is selected when the DEV bit of the Device register is equal to the device number assigned to the device by means of a Device 0/Device 1 jumper or switch, or use of the CSEL signal. 3.1.25 DMA (direct memory access) data transfer: A means of data transfer between device and host memory without host processor intervention. 3.1.26 don’t care: A term to indicate that a value is irrelevant for the particular function described. 3.1.27 driver: The active circuit inside a device or host that sources or sinks current to assert or negate a signal on the bus. 3.1.28 DRQ data block: This term describes a unit of data words transferred during a single assertion of DRQ when using PIO data transfer. A data block is transferred between the host and the device as a complete unit. For all PIO data transfer commands except READ MULTIPLE, WRITE MULTIPLE, and PACKET, a DRQ data block is one sector, 512 bytes. For READ MULTIPLE and WRITE MULTIPLE commands the DRQ data block is the number of sectors indicated in word 59 of the IDENTIFY DEVICE response. For PACKET command the DRQ data block for transfer of the command packet is the number of bytes indicated in word 0 of the IDENTIFY PACKET DEVICE response. 3.1.29 interrupt pending: Interrupt pending is an internal state of a device that causes the device to notify the host of an event by asserting INTRQ if nIEN is cleared to zero and the device is selected (see 6.3). 3.1.30 LBA (logical block address): This term defines the addressing of data on the device by the linear mapping of sectors. 3.1.31 master: In ATA-1, Device 0 was referred to as the master. Throughout this document the term Device 0 is used. 3.1.32 native max address: The highest address a device accepts in the factory default condition, that is, the highest address that is accepted by the SET MAX ADDRESS command. 3.1.33 overlap: Overlap is a protocol that allows devices that require extended command time to perform a bus release so that commands may be executed by the other device on the bus. 3.1.34 packet delivered command: A command that is delivered to the device using the PACKET command via a command packet that contains the command and the command parameters. 3.1.35 PIO (programmed input/output) data transfer: PIO data transfers are performed by the host processor utilizing accesses to the Data register. 3.1.36 queued: Command queuing allows the host to issue concurrent commands to the same device. Only commands included in the Overlapped feature set may be queued. In this standard, the queue contains all commands for which command acceptance has occurred but command completion has not occurred. 3.1.37 read command: A command that causes the device to read data from the media (e.g., READ SECTOR(S), READ DMA, etc.). Page 4 T13/1410D revision 3b 3.1.38 register delivered command: A command that is delivered to the device by placing the command and all of the parameters for the command in the device Command Block registers. 3.1.39 register transfers: Register transfers refer to the host reading and writing any device register except the Data register. Register transfers are 8 bits wide. 3.1.40 released: Indicates that a signal is not being driven. For drivers capable of assuming a high-impedance state, this means that the driver is in the high impedance state. For open-collector drivers, the driver is not asserted. 3.1.41 sector: A uniquely addressable set of 256 words (512 bytes). 3.1.42 signature: A unique set of values placed in the Command Block registers by the device to allow the host to distinguish devices implementing the PACKET Command feature set from those devices not implementing the PACKET Command feature set.. 3.1.43 slave: In ATA-1, Device 1 was referred to as the slave. Throughout this document the term Device 1 is used. 3.1.44 SMART: Self-Monitoring, Analysis, and Reporting Technology for prediction of device degradation and/or faults. Throughout this document this is noted as SMART. 3.1.45 Ultra DMA burst: An Ultra DMA burst is defined as the period from an assertion of DMACK- to the subsequent negation of DMACK- when an Ultra DMA transfer mode has been enabled by the host. 3.1.46 unit attention condition: A state that a device implementing the PACKET Command feature set maintains while the device has asynchronous status information to report to the host. 3.1.47 unrecoverable error: An unrecoverable error has occurred when the device sets either the ERR bit or the DF bit to one in the Status register at command completion. 3.1.48 VS (vendor specific): This term is used to describe bits, bytes, fields, and code values that are reserved for vendor specific purposes. These bits, bytes, fields, and code values are not described in this standard, and may vary among vendors. This term is also applied to levels of functionality whose definition is left to the vendor. NOTE − Industry practice could result in conversion of a Vendor Specific bit, byte, field, or code value into a defined standard value in a future standard. 3.1.50 write command: A command that causes the device to write data to the media (e.g., WRITE SECTOR(S), WRITE DMA, etc.). 3.2 Conventions Lowercase is used for words having the normal English meaning. Certain words and terms used in this standard have a specific meaning beyond the normal English meaning. These words and terms are defined either in clause 3 or in the text where they first appear. The names of abbreviations, commands, fields, and acronyms used as signal names are in all uppercase (e.g., IDENTIFY DEVICE). Fields containing only one bit are usually referred to as the "name" bit instead of the "name" field. (see 3.2.6 for the naming convention used for naming bits.) Names of device registers begin with a capital letter (e.g., LBA Mid register). The expression “word n” or “bit n” shall be interpreted as indicating the content of word n or bit n. Page 5 T13/1410D revision 3b 3.2.1 Precedence If there is a conflict between text, figures, and tables, the precedence shall be tables, figures, then text. 3.2.2 Lists Ordered lists, those lists describing a sequence, are of the form: a) b) c) Unordered list are of the form: 1) 2) 3) 3.2.3 Keywords Several keywords are used to differentiate between different levels of requirements and optionality. 3.2.3.1 expected: A keyword used to describe the behavior of the hardware or software in the design models assumed by this standard. Other hardware and software design models may also be implemented. 3.2.3.2 mandatory: A keyword indicating items to be implemented as defined by this standard. 3.2.3.3 may: A keyword that indicates flexibility of choice with no implied preference. 3.2.3.4 obsolete:A keyword indicating that the designated bits, bytes, words, fields, and code values that may have been defined in previous standards are not defined in this standard and shall not be reclaimed for other uses in future standards. However, some degree of functionality may be required for items designated as “obsolete” to provide for backward compatibility. An obsolete bit, byte, word, field, or code value shall never be reclaimed for any other use in any future standard. Obsolete commands should not be used by the host. Commands defined as obsolete may be command aborted by devices conforming to this standard. However, if a device does not command abort an obsolete command, the minimum that is required by the device in response to the command is command completion. 3.2.3.5 optional: A keyword that describes features that are not required by this standard. However, if any optional feature defined by the standard is implemented, the feature shall be implemented in the way defined by the standard. 3.2.3.6 reserved: A keyword indicating reserved bits, bytes, words, fields, and code values that are set aside for future standardization. Their use and interpretation may be specified by future extensions to this or other standards. A reserved bit, byte, word, or field shall be set to zero, or in accordance with a future extension to this standard. The recipient shall not check reserved bits, bytes, words, or fields. Receipt of reserved code values in defined fields shall be treated as a command parameter error and reported by returning command aborted. 3.2.3.7 retired: A keyword indicating that the designated bits, bytes, words, fields, and code values that had been defined in previous standards are not defined in this standard and may be reclaimed for other uses in future standards. If retired bits, bytes, words, fields, or code values are used before they are reclaimed, they shall have the meaning or functionality as described in previous standards. Page 6 T13/1410D revision 3b 3.2.3.8 shall: A keyword indicating a mandatory requirement. Designers are required to implement all such mandatory requirements to ensure interoperability with other products that conform to this standard. 3.2.3.9 should: A keyword indicating flexibility of choice with a strongly preferred alternative. Equivalent to the phrase “it is recommended”. 3.2.4 Numbering Numbers that are not immediately followed by a lowercase "b" or "h" are decimal values. Numbers that are immediately followed by a lowercase "b" (e.g., 01b) are binary values. Numbers that are immediately followed by a lowercase "h" (e.g., 3Ah) are hexadecimal values. 3.2.5 Signal conventions Signal names are shown in all uppercase letters. All signals are either high active or low active signals. A dash character ( - ) at the end of a signal name indicates the signal is a low active signal. A low active signal is true when the signal is below ViL, and is false when the signal is above ViH. No dash at the end of a signal name indicates the signal is a high active signal. A high active signal is true when the signal is above ViH, and is false when the signal is below ViL. Asserted means that the signal is driven by an active circuit to the true state. Negated means that the signal is driven by an active circuit to the false state. Released means that the signal is not actively driven to any state (see 4.2.1). Some signals have bias circuitry that pull the signal to either a true state or false state when no signal driver is actively asserting or negating the signal. Control signals that may be used for more than one mutually exclusive functions are identified with their function names separated by a colon (e.g., DIOW-:STOP). SIGNAL(n:m) denotes a set of signals, for example, DD(15:0). 3.2.6 Bit conventions Bit names are shown in all uppercase letters except where a lowercase n precedes a bit name. If there is no preceding n, then when BIT is set to one the meaning of the bit is true, and when BIT is cleared to zero the meaning of the bit is false. If there is a preceding n, then when nBIT is cleared to zero the meaning of the bit is true and when nBIT is set to one the meaning of the bit is false. True False True False TEST Bit setting=1 Bit setting=0 nTEST Bit setting=0 Bit setting=1 Bit (n:m) denotes a set of bits, for example, bits (7:0). 3.2.7 State diagram conventions State diagrams shall be as shown in Figure 1. Page 7 T13/1410D revision 3b State designator: State_name Entry condition Transition label Transition action State designator: State_name Transition condition Transition label Exit condition Transition label Transition action State_name Transition action Transition condition Transition label Transition action State re-entry BSY v DRQ v REL v SERV v C/D v I/O v INTRQ V DMARQ V PDIAGV DASPV Figure 1 − State diagram convention Each state is identified by a state designator and a state name. The state designator is unique among all states in all state diagrams in this document. The state designator consists of a set of letters that are capitalized in the title of the figure containing the state diagram followed by a unique number. The state name is a brief description of the primary action taken during the state, and the same state name may appear in other state diagrams. If the same primary function occurs in other states in the same state diagram, they are designated with a unique letter at the end of the name. Additional actions may be taken while in a state and these actions are described in the state description text. In device command protocol state diagrams, the state of bits and signals that change state during the execution of this state diagram are shown under the state designator:state_name, and a table is included that shows the state of all bits and signals throughout the state diagram as follows: v = bit value changes. 1 = bit set to one. 0 = bit cleared to zero. x = bit is don’t care. V = signal changes. A = signal is asserted. N = signal is negated. R = signal is released. X = signal is don’t care. Each transition is identified by a transition label and a transition condition. The transition label consists of the state designator of the state from which the transition is being made followed by the state designator of the state to which the transition is being made. In some cases, the transition to enter or exit a state diagram may come from or go to a number of state diagrams, depending on the command being executed. In this case, the state designator is labeled xx. The transition condition is a brief description of the event or condition that causes the transition to occur and may include a transition action, indicated in italics, that is taken when the transition occurs. This action is described fully in the transition description text. Upon entry to a state, all actions to be executed in that state are executed. If a state is re-entered from itself, all actions to be executed in the state are executed again. Transitions from state to state shall be instantaneous. Page 8 T13/1410D revision 3b 3.2.8 Timing conventions Certain symbols are used in the timing diagrams. These symbols and their respective definitions are listed below. or - signal transition (asserted or negated) or - data transition (asserted or negated) - data valid - undefined but not necessarily released - asserted, negated or released - released - the “other” condition if a signal is shown with no change All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown towards the bottom of the page relative to the asserted condition. The interface uses a mixture of negative and positive signals for control and data. The terms asserted and negated are used for consistency and are independent of electrical characteristics. In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. The following illustrates the representation of a signal named TEST going from negated to asserted and back to negated, based on the polarity of the signal. Assert Negate Assert Negate TEST > V iH < V iL TEST< V iL > V iH 3.2.9 Byte ordering for data transfers Data is transferred in blocks using either PIO or DMA protocols. PIO data transfers occur when the BSY bit is cleared to zero and the DRQ bit is set to one. These transfers are usually 16-bit but CFA devices may implement 8-bit PIO transfers. Data is transferred in blocks of one or more bytes known as a DRQ block. DMA data transfers occur when the host asserts DMACK- in response to the device asserting DMARQ. DMA transfers are always 16-bit. Each assertion of DMACK- by the host defines a DMA data burst. A DMA data burst is two or more bytes. Assuming a DRQ block or a DMA burst of data contains "n" bytes of information, the bytes are labeled Byte(0) through Byte(n-1), where Byte(0) is first byte of the block, and Byte(n-1) is the last byte of the block. Table 1 shows the order the bytes shall be presented in when such a block of data is transferred on the interface using 16-bit PIO and DMA transfers. Table 2 shows the order the bytes shall be presented in when such a block or burst of data is transferred on the interface using 8-bit PIO. Page 9 T13/1410D revision 3b Table 1 − Byte order DD 15 DD 14 First transfer Second transfer ........ Last transfer DD 13 DD 12 DD 11 DD 10 DD 9 DD 8 DD 7 DD 6 DD 5 DD 4 DD 3 Byte (1) Byte (3) Byte (0) Byte (2) Byte (n-1) Byte (n-2) DD 2 DD 1 DD 0 Table 2 − Byte order DD 7 DD 6 DD 5 First transfer Second transfer ........ Last transfer DD 4 DD 3 DD 2 DD 1 DD 0 Byte (0) Byte (1) Byte (n-1) NOTE − The above description is for data on the interface. Host systems and/or host adapters may cause the order of data as seen in the memory of the host to be different. Some parameters are defined as a string of ASCII characters. ASCII data fields shall contain only code values 20h through 7Eh. For the string “Copyright”, the character “C” is the first byte, the character “o” is the second byte, etc. When such fields are transferred, the order of transmission is: the 1st character (“C”) is on DD(15:8) of the first word, the 2nd character (“o”) is on DD(7:0) of the first word, the 3rd character (“p”) is on DD(15:8) of the second word, the 4th character (“y”) is on DD(7:0) of the second word, the 5th character (“r”) is on DD(15:8) of the third word, the 6th character (“i”) is on DD(7:0) of the third word, the 7th character (“g”) is on DD(15:8) of the fourth word, the 8th character (“h”) is on DD(7:0) of the fourth word, the 9th character (“t”) is on DD(15:8) of the fifth word, the 10th character (“space”) is on DD(7:0) of the fifth word, etc. Word (n:m) denotes a set of words, for example, words (103:100). 4 Interface physical and electrical requirements Connectors and cables are documented in annex A. 4.1 Cable configuration This standard defines an interface containing a single host or host adapter and one or two devices. One device is configured as Device 0 and the other device as Device 1. The designation of a device as Device 0 or Device 1 may be made in a number of ways including but not limited to: − − a switch or a jumper on the device; use of the Cable Select (CSEL) pin. The host shall be placed at one end of the cable. It is recommended that for a single device configuration the device be placed at the opposite end of the cable from the host. If a single device configuration is implemented Page 10 T13/1410D revision 3b with the device not at the end of the cable, a cable stub results that may cause degradation of signals. Single device configurations with the device not at the end of the cable shall not be used with Ultra DMA modes. 4.2 Electrical characteristics Table 3 defines the DC characteristics of the interface signals. Table 4 defines the AC characteristics. These characteristics apply to both host and device unless otherwise specified. IoL IoLDASP IoH IoHDMARQ IZ IZDD7 ViH ViL VoH VoL VDD3 V+ V− VHYS VTHRAVG VoH2 Table 3 − DC characteristics Description Min Max Driver sink current (see note 1) 4 mA Driver sink current for DASP (see note 1) 12 mA Driver source current (see note 2) 400 µA Driver source current for DMARQ (see note 2) 500 µA Device pull-up current on DD(15:8), DD(6:0), -100 µA 200 µA and STROBE when released Device pull-up current on DD7 when released -100 µA 10 µA Voltage input high 2.0 VDC 5.5 VDC Voltage input low 0.8 VDC Voltage output high at IoH min (see note 3) 2.4 VDC Voltage output low at IoL min (see note 3) 0.5 VDC Additional DC characteristics for Ultra DMA modes greater than 4 DC supply voltage to drivers and receivers 3.3 V – 8% 3.3 V + 8% Low to high input threshold 1.5 V 2.0 V High to low input threshold 1.0 V 1.5 V Difference between input thresholds: 320 mV ((V+current value) − (V−current value)) Average of thresholds: ((V+current value) + (V−current 1.3 V 1.7 V value))/2 Voltage output high at -6 mA to +3 mA (at VoH2 VDD3 – 0.51 VDD3 + 0.3 the output shall be able to supply and sink VDC VDC current to VDD3) (see note 3) Voltage output low at 6 mA (see note 3) 0.51 VDC VoL2 NOTES − 1 IoLDASP shall be 12 mA minimum to meet legacy timing and signal integrity. 2 IoH value at 400 µA is insufficient in the case of DMARQ that is pulled low by a 5.6 kΩ resistor. 3. Voltage output high and low values shall be met at the source connector to include the effect of series termination. Page 11 T13/1410D revision 3b SRISE SFALL Chost Cdevice SRISE2 SFALL2 VDSSOH VDSSOL VHSSOH VHSSOL VRING Cdevice2 Cratio Table 4 − AC characteristics Description Min Rising edge slew rate for any signal (see note 1) Falling edge slew rate for any signal (see note 1) Host interface signal capacitance at the host connector (see note 4) Device interface signal capacitance at the device connector (see note 4) Additional AC characteristics for Ultra DMA modes greater than mode 4 Rising edge slew rate for DD(15:0) and STROBE (see note 1) 0.40 V/ns Falling edge slew rate for DD(15:0) and STROBE (see note 1) 0.40 V/ns Induced signal to conductor side of device connector for any non- VDD3 – 500 switching data signal at VoH due to simultaneous switching of all mV other data lines high and low by the device (see note 2) Same as VDSSOH except non-switching data signal at VoL (see note 2) Induced signal to conductor side of host connector for any non- VDD3 – 600 switching data signal at VoH due to simultaneous switching of all mV other data lines high and low by the host (see note 2) Same as VHSSOH except non-switching data signal at VoL (see note 2) AC voltage at recipient connector (see note 3) -1 V Device capacitance measured at the connector pin (see note 4) Ratio of the highest DD(15:0) or STROBE signal capacitance as measured at the connector to the lowest DD(15:0) or STROBE signal capacitance. Max 1.25 V/ns 1.25 V/ns 25 pf 20 pf 1.0 V/ns 1.0 V/ns 500 mV 600 mV 6V 17 pf 1.5 NOTES – 1 The sender shall be tested while driving an 18” long, 80-conductor cable with PVC insulation material. The signal under test shall be cut at a test point so that it has no trace, cable, or recipient loading after the test point. All other signals should remain connected through to the recipient. The test point may be located at any point between the sender's series termination resistor and 0.5" or less of conductor exiting the connector. If the test point is on a cable conductor rather than the PCB, an adjacent ground conductor shall also be cut within 0.5" of the connector. The test load and test points should then be soldered directly to the exposed source side connectors. The test load consists of a 15 or 40 pf, 5%, 0.08” by 0.05” surface mount or smaller size, capacitor from the test point to ground. Slew rates shall be met for both capacitor values. Measurements shall be taken at the test point using a <1 pf, >100 kΩ, 1 GHz or faster probe and a 500 MHz or faster oscilloscope. The average rate shall be measured from 20 to 80% of the settled VoH level with data transitions at least 120 ns apart. The settled VoH level shall be measured as the average output high level under the defined testing conditions from 100 ns after 80% of a rising edge until 20% of the subsequent falling edge. 2 Vsso shall be tested with the same test cable configuration as described in note 1 for slew rate except with the test load described here and the cut-cable-conductor configuration. For both VoL and VoH measurements, the test load shall consist of a 90.9 Ω 1% resistor and a 0.1 µf 20% capacitor in series to ground. Both resistor and capacitor shall be 0.08” by 0.05” surface mount or smaller size. The order of components should be signal-resistor-capacitor-ground. Refer to 4.2.2.3 for PCB layout requirements related to VSSO. 3 The sender shall not generate voltage peaks higher then these absolute limits on any data line DD(15:0) with all data lines switching simultaneously and a single recipient at end of cable. The test load shall be an 18" long, 40-conductor cable operated in Ultra DMA mode 2, as well as, an 18", long 80conductor cable operated in the highest Ultra DMA mode supported. 4 Capacitance measured at 1 MHz. Page 12 T13/1410D revision 3b 4.2.1 Driver types and required termination Signal Table 5 − Driver types and required termination Source Driver type Host Device (see note 1) (see note 2) (see note 2) Host TP Bidir TS Device TS 5.6 kΩ PD Host TS Notes RESETDD(15:0) 3 DMARQ DIOR-:HDMARDY:HSTROBE DIOW-:STOP Host TS IORDY:DDMARDYDevice TS 4.7 kΩ PU 6,10 :DSTROBE CSEL Host Ground 10 kΩ PU 4, 6 DMACKHost TP INTRQ Device TS 10 kΩ 5 DA(2:0) Host TP PDIAG-:CBLIDDevice TS 10 kΩ PU 2,6,7,8 CS0- CS1Host TP DASPDevice OC 10 kΩ PU 6,9 NOTES − 1 TS=Capable of a high-impedance output state; OC=Open Collector; TP=Totem-pole; PU=Pull-up; PD=Pull-down. 2 All resistor values are the minimum (lowest allowed) except for the 10 kΩ PU on PDIAG-:CBLID- which shall have a tolerance of ±5% or less. 3 Devices shall not have a pull-up resistor on DD7. The host shall have a 10 kΩ pull-down resistor and not a pull-up resistor on DD7 to allow a host to recognize the absence of a device at power-up so that a host shall detect BSY as being cleared when attempting to read the Status register of a device that is not present. 4 When used as CSEL, this line is grounded at the host and a 10 kΩ pull-up is required at both devices. 5 A 10 kΩ pull-down or pull-up, depending upon the level sensed, should be implemented at the host. 6 Pull-up values are based on +5 V Vcc. Except for the pull-up on PDIAG-:CBLID- which shall be to +5 VCC for backward compatibility, pull-ups may be to VDD3. For systems supporting Ultra DMA modes greater than 4, the host pull-up on IORDY:DDMARDY-:DSTROBE should be to VDD3. 7 Hosts that do not support Ultra DMA modes greater than mode 2 shall not connect to the PDIAG:CBLID- signal. 8 The 80-conductor cable assembly shall meet the following requirements: the PDIAG-:CBLID- signal shall be connected to ground in the host connector of the cable assembly; the PDIAG-:CBLIDsignal shall not be connected between the host and the devices; and, the PDIAG-:CBLID- signal shall be connected between the devices. 9 The host shall not drive DASP-. If the host connects to DASP- for any purpose, the host shall ensure that the signal level detected on the interface for DASP- shall maintain VoH and VoL compatibility, given the IoH and IoL requirements of the DASP- device drivers. 10 For host systems not supporting modes greater than Ultra DMA mode 4, a pull-up of 1 kΩ may be used. 4.2.2 Electrical characteristics for Ultra DMA Hosts that support Ultra DMA transfer modes greater than mode 2 shall not share signals between primary and secondary I/O ports. They shall provide separate drivers and separate receivers for each cable. Page 13 T13/1410D revision 3b 4.2.2.1 Cable configuration The following table defines the host transceiver configurations for a dual cable system configuration for all transfer modes. Transfer mode All PIO and Multiword DMA Optional host transceiver configuration One transceiver may be used for signals to both ports. Ultra DMA 0, 1, 2 One transceiver may be used for signals to both ports except DMACK-. Ultra DMA modes > 2 One transceiver may be used for signals to both ports for RESET-, INTRQ, DA(2:0), CS0-, CS1-, and DASP-. Recommended host Mandatory host transceiver configuration transceiver configuration DIOR-, DIOW-, and IORDY Either DIOR-, DIOW-, and should have a separate IORDY or CS0- and CS1transceiver for each port. shall have a separate transceiver for each port. DIOR-, DIOW-, and IORDY Either DIOR-, DIOW-, and should have a separate IORDY or CS0- and CS1transceiver for each port. shall have a separate transceiver for each port. DMACK- shall have a separate transceiver for each port. RESET-, INTRQ, DA(2:0), All signals shall have a CS0-, CS1-, and DASP- separate transceiver for should have a separate each port except for transceiver for each port. RESET-, INTRQ, DA(2:0), CS0-, CS1-, and DASP-. The following table defines the system configuration for connection between devices and systems for all transfer modes. Transfer mode Single device direct connection configuration (see note 1) May be used. 40-conductor cable connection configuration (see note 2) May be used. 80-conductor cable connection configuration (see note 2) May be used (see note 3) All PIO and Multiword DMA Ultra DMA May be used. May be used. May be used (see note 3) 0, 1, 2 Ultra DMA May be used (see note 4). Shall not be used. May be used (see note 4). modes > 2 NOTES – 1 Direct connection is a direct point-to-point connection between the host connector and the device connector. 2 The 40-conductor cable assembly and the 80-conductor cable assembly are defined in Annex A. 3 80-conductor cable assemblies may be used in place of 40-conductor cable assemblies to improve signal quality for data transfer modes that do not require an 80-conductor cable assembly. 4 Either a single device direct connection configuration or an 80-conductor cable connection configuration shall be used for systems operating with Ultra DMA modes greater than 2. 4.2.2.2 Series termination required for Ultra DMA Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA modes. Table 6 describes typical values for series termination at the host and the device. For host systems and devices supporting Ultra DMA modes greater than 4, the output and bi-directional series termination values for DD(15:0) and STROBE signals shall be chosen so that the sum of the driver output resistance at VoL2 or VoH2 and the series termination resistance is between 50 and 85 Ω. For these systems, the STROBE input shall use the same series termination resistance value as the data lines. Page 14 T13/1410D revision 3b Table 6 − Typical series termination for Ultra DMA Signal Host Termination Device Termination DIOR-:HDMARDY-:HSTROBE 22 ohm 82 ohm DIOW-:STOP 22 ohm 82 ohm CS0-, CS133 ohm 82 ohm DA0, DA1, DA2 33 ohm 82 ohm DMACK22 ohm 82 ohm DD15 through DD0 33 ohm 33 ohm DMARQ 82 ohm 22 ohm INTRQ 82 ohm 22 ohm IORDY:DDMARDY-:DSTROBE 82 ohm 22 ohm RESET33 ohm 82 ohm NOTE − Only those signals requiring termination are listed in this table. If a signal is not listed, series termination is not required for operation in an Ultra DMA mode. Figure 2 shows signals also requiring a pull-up or pull-down resistor at the host. The actual termination values should be selected to compensate for transceiver and trace impedance to match the characteristic cable impedance. VCC or V DD3 Receiver Connector Connector IORDY Receiver Driver DMARQ Connector DD 7 Receiver Figure 2 − Ultra DMA termination with pull-up or pull-down 4.2.2.3 PCB trace requirements for Ultra DMA The longest DD(15:0) trace shall be no more than 0.5" longer than either STROBE trace as measured from the IC pin to the connector. The shortest DD(15:0) trace shall be no more than 0.5" shorter than either STROBE trace as measured from the IC pin to the connector. PCB trace layout is a factor in meeting the Vsso values in table 4. Page 15 T13/1410D revision 3b 5 Interface signal assignments and descriptions 5.1 Signal summary The physical interface consists of receivers and drivers communicating through a set of conductors using an asynchronous interface protocol. Table 7 defines the signal names. For connector descriptions see annex A. For driver and termination definition see 4.2.1. For signal protocol and timing see clause 9 and clause 10. Table 7 − Interface signal name assignments Description Host Dir Cable select (see note) Chip select 0 Chip select 1 Data bus bit 0 ↔ Data bus bit 1 ↔ Data bus bit 2 ↔ Data bus bit 3 ↔ Data bus bit 4 ↔ Data bus bit 5 ↔ Data bus bit 6 ↔ Data bus bit 7 ↔ Data bus bit 8 ↔ Data bus bit 9 ↔ Data bus bit 10 ↔ Data bus bit 11 ↔ Data bus bit 12 ↔ Data bus bit 13 ↔ Data bus bit 14 ↔ Data bus bit 15 ↔ Device active or slave (Device 1) present (see note) Device address bit 0 Device address bit 1 Device address bit 2 DMA acknowledge DMA request ← Interrupt request ← I/O read DMA ready during Ultra DMA data-in bursts Data strobe during Ultra DMA data-out bursts I/O ready ← DMA ready during Ultra DMA data-out bursts ← Data strobe during Ultra DMA data-in bursts ← I/O write Stop during Ultra DMA data bursts Passed diagnostics (see note) Cable assembly type identifier (see note) Reset NOTE − See signal descriptions and annex A for information on source of Page 16 Dev Acronym CSEL → CS0→ CS1DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 DASP→ DA0 → DA1 → DA2 → DMACKDMARQ INTRQ → DIOR→ HDMARDY→ HSTROBE IORDY DDMARDYDSTROBE → DIOW→ STOP PDIAGCBLID→ RESETthese signals T13/1410D revision 3b 5.2 Signal descriptions 5.2.1 CS(1:0)- (Chip select) These are the chip select signals from the host used to select the Command Block or Control Block registers (see 7.2). When DMACK- is asserted, CS0- and CS1- shall be negated and transfers shall be 16 bits wide. 5.2.2 DA(2:0) (Device address) This is the 3-bit binary coded address asserted by the host to access a register or data port in the device (see 7.2). 5.2.3 DASP- (Device active, device 1 present) During the reset protocol, DASP- shall be asserted by Device 1 to indicate that the device is present. At all other times, DASP- may be asserted by the selected active device. 5.2.4 DD(15:0) (Device data) This is an 8- or 16-bit bi-directional data interface between the host and the device. DD(7:0) are used for 8-bit register transfers. Data transfers are 16-bits wide except for CFA devices that implement 8-bit data transfers. 5.2.5 DIOR-:HDMARDY-:HSTROBE (Device I/O read:Ultra DMA ready:Ultra DMA data strobe) DIOR- is the strobe signal used by the host to read device registers or the Data port. Data is tranferred on the negation of this signal. HDMARDY- is a flow control signal for Ultra DMA data-in bursts. This signal is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data-in bursts. The host may negate HDMARDY- to pause an Ultra DMA data-in burst. HSTROBE is the data-out strobe signal from the host for an Ultra DMA data-out burst. Both the rising and falling edge of HSTROBE latch the data from DD(15:0) into the device. The host may stop generating HSTROBE edges to pause an Ultra DMA data-out burst. 5.2.6 DIOW-:STOP (Device I/O write:Stop Ultra DMA burst) DIOW- is the strobe signal used by the host to write device registers or the Data port. Data is tranferred on the negation of this signal. DIOW- shall be negated by the host prior to initiation of an Ultra DMA burst. STOP shall be negated by the host before data is transferred in an Ultra DMA burst. Assertion of STOP by the host during an Ultra DMA burst signals the termination of the Ultra DMA burst. 5.2.7 DMACK- (DMA acknowledge) This signal shall be used by the host in response to DMARQ to initiate DMA transfers. For Multiword DMA transfers, the DMARQ/DMACK- handshake is used to provide flow control during the transfer. For Ultra DMA, the DMARQ/DMACK- handshake is used to indicate when the function of interface signals changes. When DMACK- is asserted, CS0- and CS1- shall not be asserted and transfers shall be 16 bits wide. 5.2.8 DMARQ (DMA request) This signal, used for DMA data transfers between host and device, shall be asserted by the device when the device is ready to transfer data to or from the host. For Mulitword DMA transfers, the direction of data transfer Page 17 T13/1410D revision 3b is controlled by DIOR- and DIOW-. This signal is used in a handshake manner with DMACK-, i.e., the device shall wait until the host asserts DMACK- before negating DMARQ, and re-asserting DMARQ if there is more data to transfer. For Multiword DMA transfers, the DMARQ/DMACK- handshake is used to provide flow control during the transfer. For Ultra DMA, the DMARQ/DMACK- handshake is used to indicate when the function of interface signals changes. This signal shall be released when the device is not selected. See 6.5 and 6.6. 5.2.9 INTRQ (Device interrupt) This signal is used by the selected device to interrupt the host system when interrupt pending is set. When the nIEN bit is cleared to zero and the device is selected, INTRQ shall be enabled through a driver capacle of a high-impedance output state. When the nIEN bit is set to one or the device is not selected, the INTRQ signal shall be released. When asserted, this signal shall be negated by the device within 400 ns of the negation of DIOR- that reads the Status register to clear interrupt pending. When asserted, this signal shall be negated by the device within 400 ns of the negation of DIOW- that writes the Command register to clear interrupt pending. When the device is selected by writing to the Device register while interrupt pending is set, INTRQ shall be asserted within 400 ns of the negation of DIOW- that writes the Device register. When the device is deselected by writing to the Device register while interrupt pending is set, INTRQ shall be released within 400 ns of the negation of DIOW- that writes the Device register. For devices implementing the Overlapped feature set, if INTRQ assertion is being disabled using nIEN at the same instant that the device asserts INTRQ, the minimum pulse width shall be at least 40 ns. This signal shall be released when the device is not selected. 5.2.10 IORDY:DDMARDY-:DSTROBE (I/O channel ready:Ultra DMA ready:Ultra DMA data strobe) IORDY is negated to extend the host transfer cycle of any host register access (read or write) when the device is not ready to respond to a data transfer request. If the device requires that the host transfer cycle time be extended for PIO modes 3 and above, the device shall use IORDY. Hosts that use PIO modes 3 and above shall support IORDY. DDMARDY- is a flow control signal for Ultra DMA data-out bursts. This signal is asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data-out bursts. The device may negate DDMARDY- to pause an Ultra DMA data-out burst. DSTROBE is the data-in strobe signal from the device for an Ultra DMA data-in burst. Both the rising and falling edge of DSTROBE latch the data from DD(15:0) into the host. The device may stop generating DSTROBE edges to pause an Ultra DMA data-in burst. This signal shall be released when the device is not selected. 5.2.11 PDIAG-:CBLID- (Passed diagnostics:Cable assembly type identifier) PDIAG- shall be asserted by Device 1 to indicate to Device 0 that Device 1 has completed diagnostics (see clause 9). Page 18 T13/1410D revision 3b The host may sample CBLID- after a power-on or hardware reset in order to detect the presence of an 80conductor cable assembly by performing the following steps: a) Wait until the power-on or hardware reset protocol is complete for all devices on the cable; remember which devices are present for the last step. b) If Device 1 is not present, go to step d. c) Issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE to Device 1. From the information returned, save word 80 and word 93 for the last step. NOTE − Word 80 bit 3 indicates compliance with ATA-3 or subsequent standards and word 93 bits (15:13) indicate support of and results from sampling CBLID- at the device. d) Issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE to Device 0. From the information returned, save Word 93 for the last step. NOTE − Word 93 bits (15:13) indicate support of and results from sampling CBLID- at the device. e) Detect the state of the CBLID- signal at the host connector and save the result for the last step. NOTE − Any device compliant with ATA-3 or subsequent standards releases PDIAG- no later than after the first command following a power-on or hardware reset sequence and will not interfere with host detection of CBLID- in this step. Some devices claiming compliance with ATA-3 or subsequent standards are known to continue to assert CBLID-:PDIAG- which sometimes causes a 40-conductor cable assembly to be detected as an 80-conductor cable assembly. f) Look up the output in Table 8 based on the inputs saved from steps a, c, d, and e. Page 19 T13/1410D revision 3b Table 8 – Cable type identification Inputs Device 1 Word 80 Device 1 Word 93 Device 0 Word 93 bit 3 bits (15:13) bits (15:13) X XXX XXX Device absent Device absent 00X or 1XX Device absent Device absent 010 Device absent Device absent 011 0 00X or 1XX Device absent 0 00X or 1XX 00X or 1XX 0 00X or 1XX 010 0 00X or 1XX 011 0 010 Device absent 0 010 XXX 0 011 Device absent 0 011 00X or 1XX 0 011 010 0 011 011 1 00X or 1XX Device absent 1 00X or 1XX 00X or 1XX 1 00X or 1XX 010 1 00X or 1XX 011 1 010 Device absent 1 010 XXX 1 011 Device absent 1 011 00X or 1XX 1 011 010 1 011 011 Output Sensed Cable CBLIDconductors High 40 Low 80 Low Note 2 Low 80 Low Note 1 Low Note 1 Low Note 2 Low 80 Low Note 2 Low Note 2 Low 80 Low 80 Low Note 2 Low 80 Low 80 Low 80 Low Note 2 Low 80 Low Note 2 Low Note 2 Low 80 Low 80 Low Note 2 Low 80 NOTES − 1 Host cannot determine cable type due to insufficient information. For these cases, host should not use Ultra DMA modes higher than mode 2 without using other means to confirm presence of 80-conductor cable. 2 Host cannot determine cable type due to conflicting information. For these cases, host should not use Ultra DMA modes higher than mode 2 without using other means to confirm presence of 80-conductor cable. 3 X represents a don’t-care input. See Annex B for a description of the non-standard device determination of cable type. 5.2.12 RESET- (Hardware reset) This signal, referred to as hardware reset, shall be used by the host to reset the device (see 9.1). 5.2.13 CSEL (Cable select) If CSEL is enabled in the device, the device is configured as either Device 0 or Device 1 depending upon the value of CSEL: − − If CSEL is negated, the device number is 0; If CSEL is asserted, the device number is 1. The state of this signal may be sampled at any time by the device. CSEL shall be grounded by the host. Page 20 T13/1410D revision 3b 5.2.13.1 CSEL with 40-conductor cable Special cabling may be used to selectively ground CSEL. CSEL of Device 0 is connected to the CSEL conductor in the cable, and is grounded, thus allowing the device to recognize itself as Device 0. CSEL of Device 1 is not connected to the CSEL conductor, thus the device recognizes itself as Device 1. If a single device is configured at the end of the cable using CSEL, a Device 1 only configuration results. See Figure 3 and Figure 4. CSEL conductor Open Ground Host Device 0 Device 1 CSEL conductor Open Ground Host Device 1 Figure 3 − Cable select example 5.2.13.2 CSEL with 80-conductor cable For designated cable assemblies (including all 80-conductor cable assemblies): these assemblies are constructed so that CSEL is connected from the host connector to the connector at the opposite end of the cable from the host (see Figure 4). Therefore, Device 0 shall be at the opposite end of the cable from the host. Single device configurations with the device not at the end of the cable shall not be used with Ultra DMA modes. Page 21 T13/1410D revision 3b CSEL conductor Open Ground Host Device 1 Device 0 CSEL conductor Open Ground Host Device 0 Figure 4 − Alternate cable select example 6 General operational requirements 6.1 Command delivery Commands may be delivered in two forms. For devices that do not implement the PACKET Command feature set, all commands and command parameters are delivered by writing the device Command Block registers. Such commands are defined as register delivered commands. Devices that implement the PACKET Command feature set use packet delivered commands as well as some register delivered commands. All register delivered commands and the PACKET command are described in clause 8. NOTE − The content of command packets delivered during execution of the PACKET command are not described in this standard. See clause 2 for standards and specifications that define comand packet content. 6.2 Register delivered data transfer command sector addressing For register delivered data transfer commands all addressing of data sectors recorded on the device's media is by a logical sector address. There is no implied relationship between logical sector addresses and the actual physical location of the data sector on the media. All devices shall support LBA translation. In standards ATA/ATAPI-5 and earlier, a CHS translation was defined. This translation is obsolete but may be implemented as defined in ATA/ATAPI-5. 6.2.1 Definitions and value ranges of IDENTIFY DEVICE words (see 8.12) 1) Words (61:60) shall contain the value one greater than the total number of user-addressable sectors in 28-bit addressing and shall not exceed 0FFFFFFFh. The content of words (61:60) shall be greater than or equal to one and less than or equal to 268,435,455. 2) Words (103:100) shall contain the value one greater than the total number of user-addressable sectors in 48-bit addressing and shall not exceed 0000FFFFFFFFFFFFh. Page 22 T13/1410D revision 3b 3) The contents of words (61:60) and (103:100) may be affected by the host issuing a SET MAX ADDRESS or SET MAX ADDRESS EXT command. 4) The contents of words (61:60) and (103:100) shall not be used to determine if 48-bit addressing is supported. IDENTIFY DEVICE bit 10 word 83 indicates support for 48-bit addressing. 6.2.2 Addressing constraints and error reporting Devices shall set IDNF to one or ABRT to one in the Error register and ERR to one in the Status register in response to any command where the requested LBA number is greater than or equal to the content of words (61:60) for a 28-bit addressing command or greater or equal to the contents of words (103:100) for a 48-bit addressing command. 6.3 Interrupts INTRQ is used by the selected device to notify the host of an event. The device internal interrupt pending state is set when such an event occurs. If nIEN is cleared to zero, INTRQ is asserted (see 5.2.9). The device shall enter the interrupt pending state when: 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) any command except a PIO data-in command reaches command completion successfully; any command reaches command completion with error; the device is ready to send a data block during a PIO data-in command; the device is ready to accept a data block after the first data block during a PIO data-out command; a device implementing the PACKET Command feature set is ready to receive the command packet and bits (6:5) in word 0 of the IDENTIFY PACKET DEVICE response have the value 01b; a device implementing the PACKET Command feature set is ready to transfer a DRQ data block during a PIO transfer; a device implementing the Overlap feature set performs a bus release if the bus release interrupt is enabled; a device implementing the Overlap feature set has performed a bus release and is now ready to continue the command execution; a device implementing the Overlap feature set is ready to transfer data after a SERVICE command if the Service interrupt is enabled; Device 0 completes an EXECUTE DEVICE DIAGNOSTIC command. Device 1 shall not enter the interrupt pending state when completing an EXECUTE DEVICE DIAGNOSTIC command. The device shall not exit the interrupt pending state as a result of the host changing the state of the DEV bit. The device shall exit the interrupt pending state when: 1) the device is selected, BSY is cleared to zero, and the Status register is read; 2) the device is selected, both BSY and DRQ are cleared to zero, and the Command register is written; 3) the RESET- signal is asserted; 4) the SRST bit is set to one. 6.4 General feature set The General feature set defines the common commands implemented by devices. Page 23 T13/1410D revision 3b 6.4.1 General feature set for devices not implementing the PACKET command feature set The following General feature set commands are mandatory for all devices that are capable of both reading and writing their media and do not implement the PACKET command feature set: − − − − − − − − − − − − − EXECUTE DEVICE DIAGNOSTIC FLUSH CACHE IDENTIFY DEVICE READ DMA READ MULTIPLE READ SECTOR(S) READ VERIFY SECTOR(S) SEEK SET FEATURES SET MULTIPLE MODE WRITE DMA WRITE MULTIPLE WRITE SECTOR(S) The following General feature set commands are mandatory for all devices that are capable of only reading their media and do not implement the PACKET command feature set: − − − − − − − − − EXECUTE DEVICE DIAGNOSTIC IDENTIFY DEVICE READ DMA READ MULTIPLE READ SECTOR(S) READ VERIFY SECTOR(S) SEEK SET FEATURES SET MULTIPLE MODE The following General feature set commands are optional for devices not implementing the PACKET command feature set: − − − − DOWNLOAD MICROCODE NOP READ BUFFER WRITE BUFFER The following General feature set command is prohibited for use by devices not implementing the PACKET command feature set: − DEVICE RESET The following resets are mandatory for devices not implementing the PACKET command feature set: − − − Power-on reset: Executed at power-on, the device may execute a series of diagnostics and shall set default values (see 9.1). Hardware reset: Executed in response to the assertion of the RESET- signal the device may execute a series of diagnostics and shall set default values (see 9.1). Software reset: Executed in response to the setting of the SRST bit in the Device Control register the device resets the interface circuitry (see 9.2). Page 24 T13/1410D revision 3b 6.4.2 General feature set for devices implementing the PACKET command feature set The following General feature set commands are mandatory for all devices implementing the PACKET command feature set: − − − − − − − − DEVICE RESET EXECUTE DEVICE DIAGNOSTIC IDENTIFY DEVICE IDENTIFY PACKET DEVICE NOP PACKET READ SECTOR(S) SET FEATURES The following General feature set commands are optional for devices implementing the PACKET command feature set: − FLUSH CACHE The following General command set commands are prohibited for use by devices implementing the PACKET command feature set. − − − − − − − − − − − DOWNLOAD MICROCODE READ BUFFER READ DMA READ MULTIPLE READ VERIFY SEEK SET MULTIPLE MODE WRITE BUFFER WRITE DMA WRITE MULTIPLE WRITE SECTOR(S) The following resets are mandatory for devices implementing the PACKET command feature set: − − − − Power-on reset: Executed at power-on, the device may execute a series of diagnostics and shall set default values (see 9.1). Hardware reset: Executed in response to the assertion of the RESET- signal the device may execute a series of and shall set default values (see 9.1). Software reset: Executed in response to the setting of the SRST bit in the Device Control register the device resets the interface circuitry (see 9.2). DEVICE RESET: Executed in response to the DEVICE RESET command the device resets the interface circuitry (see 8.9). 6.5 Multiword DMA Multiword DMA is a mandatory data transfer protocol used with the READ DMA, READ DMA EXT, WRITE DMA, WRITE DMA EXT, READ DMA QUEUED, READ DMA QUEUED EXT, WRITE DMA QUEUED, WRITE DMA QUEUED EXT, and PACKET commands. When a Multiword DMA transfer is enabled as indicated by IDENTIFY DEVICE (see 8.15) or IDENTIFY PACKET DEVICE (see 8.16) data, this data transfer protocol shall be used for the data transfers associated with these commands. DMA transfer modes may be changed using the SET FEATURES 03h subcommand (see 8.46.11). Signal timing for this protocol is described in 10.2.3. The DMARQ and DMACK- signals are used to signify when a Multiword DMA transfer is to be executed. The DMARQ and DMACK- signals are also used to control the data flow of a Multiword DMA data transfer. Page 25 T13/1410D revision 3b When a device is ready to transfer data associated with a Multiword DMA transfer, the device shall assert DMARQ. The host shall then respond by negating CS0- and CS1-, asserting DMACK-, and begin the data transfer by asserting, then negating, DIOW- or DIOR- for each word transferred. CS0- and CS1- shall remain negated as long as DMACK- is asserted. The host shall not assert DMACK- until DMARQ has been asserted by the device. The host shall initiate DMA read or write cycles only when both DMARQ and DMACK- are asserted. Having asserted DMARQ and DMACK-, these signals shall remain asserted until at least one word of data has been transferred. The device may pause the transfer for flow control purposes by negating DMARQ. The host shall negate DMACK- in response to the negation of DMARQ. The device may then reassert DMARQ to continue the data transfer when the device is ready to transfer more data and DMACK- has been negated by the host. The host may pause the transfer for flow control purposes by either pausing the assertion of DIOW- or DIORpulses or by negating DMACK-. The device may leave DMARQ asserted if DMACK- is negated. The host may then reassert DMACK- when DMARQ is asserted and begin asserting DIOW- or DIOR- pulses to continue the data transfer. When the Multiword DMA data transfer is complete, the device shall negate DMARQ and the host shall negate DMACK- in response. DMARQ shall be driven from the first assertion at the beginning of a DMA transfer until the negation after the last word is transferred. This signal shall be released at all other times. If the device detects an error before data transfer for the command is complete, the device may complete the data transfer or may terminate the data transfer before completion and shall report the error in either case. NOTE − If a data transfer is terminated before completion, the assertion of INTRQ should be passed through to the host software driver regardless of whether all data requested by the command has been transferred. 6.6 Ultra DMA feature set 6.6.1 Overview Ultra DMA is an optional data transfer protocol used with the READ DMA, READ DMA EXT, WRITE DMA, WRITE DMA EXT, READ DMA QUEUED, READ DMA QUEUED EXT, WRITE DMA QUEUED, WRITE DMA QUEUED EXT, and PACKET commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g., Command Block Register access). Several signal lines are redefined to provide different functions during an Ultra DMA burst. These lines assume these definitions when: 1) an Ultra DMA mode is selected, and 2) a host issues a READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED, or a PACKET command requiring data transfer, and 3) the host asserts DMACK-. These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of DMACKby the host at the termination of an Ultra DMA burst. With the Ultra DMA protocol, the STROBE signal that latches data from DD(15:0) is generated by the same agent (either host or device) that drives the data onto the bus. Ownership of DD(15:0) and this data strobe Page 26 T13/1410D revision 3b signal are given either to the device during an Ultra DMA data-in burst or to the host for an Ultra DMA data-out burst. During an Ultra DMA burst a sender shall always drive data onto the bus, and, after a sufficient time to allow for propagation delay, cable settling, and setup time, the sender shall generate a STROBE edge to latch the data. Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data. Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA modes the device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to select the Ultra DMA mode at which the system operates. The Ultra DMA mode selected by a host shall be less than or equal to the fastest mode of which the device is capable. Only one Ultra DMA mode shall be selected at any given time. All timing requirements for a selected Ultra DMA mode shall be satisfied. Devices supporting any Ultra DMA mode shall also support all slower Ultra DMA modes. An Ultra DMA capable device shall retain the previously selected Ultra DMA mode after executing a software reset sequence or the sequence caused by receipt of a DEVICE RESET command if a SET FEATURES disable reverting to defaults command has been issued. The device may revert to a Multiword DMA mode if a SET FEATURES enable reverting to default has been issued. An Ultra DMA capable device shall clear any previously selected Ultra DMA mode and revert to the default non-Ultra DMA modes after executing a power-on or hardware reset. Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the host sends its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two values do not match, the device reports an error in the error register. If an error occurs during one or more Ultra DMA bursts for any one command, the device shall report the first error that occurred. If the device detects that a CRC error has occurred before data transfer for the command is complete, the device may complete the transfer and report the error or abort the command and report the error. NOTE − If a data transfer is terminated before completion, the assertion of INTRQ should be passed through to the host software driver regardless of whether all data requested by the command has been transferred. 6.6.2 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data-in or data-out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data transfer phase (see 9.13 and 9.14 for the detailed protocol descriptions for each of these phases, 10.2.4 defines the specific timing requirements). In the following rules DMARDY- is used in cases that could apply to either DDMARDY- or HDMARDY-, and STROBE is used in cases that could apply to either DSTROBE or HSTROBE. The following are general Ultra DMA rules. 1) An Ultra DMA burst is defined as the period from an assertion of DMACK- by the host to the subsequent negation of DMACK-. 2) When operating in Ultra DMA modes 2, 1, or 0 a recipient shall be prepared to receive up to two data words whenever an Ultra DMA burst is paused. When operating in Ultra DMA modes 5, 4, or 3 a recipient shall be prepared to receive up to three data words whenever an Ultra DMA burst is paused. 6.6.2.1 Ultra DMA burst initiation phase rules 1) An Ultra DMA burst initiation phase begins with the assertion of DMARQ by a device and ends when the sender generates a STROBE edge to transfer the first data word. 2) An Ultra DMA burst shall always be requested by a device asserting DMARQ. 3) When ready to initiate the requested Ultra DMA burst, the host shall respond by asserting DMACK-. Page 27 T13/1410D revision 3b 4) A host shall never assert DMACK- without first detecting that DMARQ is asserted. 5) For Ultra DMA data-in bursts: a device may begin driving DD(15:0) after detecting that DMACK- is asserted, STOP negated, and HDMARDY- is asserted. 6) After asserting DMARQ or asserting DDMARDY- for an Ultra DMA data-out burst, a device shall not negate either signal until the first STROBE edge is generated. 7) After negating STOP or asserting HDMARDY- for an Ultra DMA data-in burst, a host shall not change the state of either signal until the first STROBE edge is generated. 6.6.2.2 Data transfer phase rules 1) The data transfer phase is in effect from after Ultra DMA burst initiation until Ultra DMA burst termination. 2) A recipient pauses an Ultra DMA burst by negating DMARDY- and resumes an Ultra DMA burst by reasserting DMARDY-. 3) A sender pauses an Ultra DMA burst by not generating STROBE edges and resumes by generating STROBE edges. 4) A recipient shall not signal a termination request immediately when the sender stops generating STROBE edges. In the absence of a termination from the sender the recipient shall always negate DMARDY- and wait the required period before signaling a termination request. 5) A sender may generate STROBE edges at greater than the minimum period specified by the enabled Ultra DMA mode. The sender shall not generate STROBE edges at less than the minimum period specified by the enabled Ultra DMA mode. A recipient shall be able to receive data at the minimum period specified by the enabled Ultra DMA mode. 6.6.2.3 Ultra DMA burst termination phase rules 1) Either a sender or a recipient may terminate an Ultra DMA burst. 2) Ultra DMA burst termination is not the same as command completion. If an Ultra DMA burst termination occurs before command completion, the command shall be completed by initiation of a new Ultra DMA burst at some later time or aborted by the host issuing a hardware or software reset or DEVICE RESET command if implemented by the device. 3) An Ultra DMA burst shall be paused before a recipient requests a termination. 4) A host requests a termination by asserting STOP. A device acknowledges a termination request by negating DMARQ. 5) A device requests a termination by negating DMARQ. A host acknowledges a termination request by asserting STOP. 6) Once a sender requests a termination, the sender shall not change the state of STROBE until the recipient acknowledges the request. Then, if STROBE is not in the asserted state, the sender shall return STROBE to the asserted state. No data shall be transferred on this transition of STROBE. 7) A sender shall return STROBE to the asserted state whenever the sender detects a termination request from the recipient. No data shall be transferred nor CRC calculated on this edge of DSTROBE. 8) Once a recipient requests a termination, the responder shall not change DMARDY from the negated state for the remainder of an Ultra DMA burst. 9) A recipient shall ignore a STROBE edge when DMARQ is negated or STOP is asserted. 6.7 Host determination of cable type by detecting CBLIDIn a system using a cable, hosts shall determine that an 80-conductor cable is installed in a system before operating with transfer modes faster than Ultra DMA mode 2. Hosts shall detect that CBLID- is connected to ground to determine the cable type. See Annex B. For detecting that CBLID- is connected to ground, the host shall test to see if CBLID- is below VIL or above VIH. If the signal is below VIL, then an 80-conductor cable assembly is installed in the system because this signal is grounded in the 80-conductor cable assembly’s host connector. If the signal is above VIH, then a 40-conductor cable assembly is installed because this signal is connected to the device(s) and is pulled up through a 10 kΩ resistor at each device. Page 28 T13/1410D revision 3b Host connector Device 0 connector Host PCB N/C Device 1 connector PDIAG-:CBLIDconductor Device 0 PCB Device 1 PCB NOTES − 1 For this configuration hosts shall not set devices to operate at Ultra DMA modes greater than 2. 2 N/C indicates that there is no connection from the host to this signal conductor. Figure 5 – Example configuration of a system with a 40-conductor cable Host PCB Host connector Device 0 connector Device 1 connector PDIAG-:CBLIDconductor Device 0 PCB Device 1 PCB Figure 6 – Example configuration of a system where the host detects a 40-conductor cable Page 29 T13/1410D revision 3b Host connector Host PCB N/C Device 1 connector Device 0 connector PDIAG-:CBLIDconductor Device 1 PCB Device 0 PCB NOTE − N/C indicates that there is no connection from the host to this signal conductor. Figure 7 – Example configuration of a system where the host detects an 80-conductor cable Table 9 – Host detection of CBLIDCable Device 1 Electrical state Host-determined Determination assembly releases of CBLID- at cable type correct? type PDIAGhost 40-conductor Yes 1 40-conductor Yes 80-conductor Yes 0 80-conductor Yes 40-conductor No 0 80-conductor No (see note) 80-conductor No 0 80-conductor Yes NOTE − Ultra DMA mode 3 or 4 may be set incorrectly resulting in ICRC errors. 6.8 PACKET Command feature set The optional PACKET Command feature set provides for devices that require command parameters that are too extensive to be expressed in the Command Block registers. Devices implementing the PACKET Command feature set exhibit responses different from those exhibited by devices not implementing this feature set. The commands unique to the PACKET Command feature set are: − − − PACKET DEVICE RESET IDENTIFY PACKET DEVICE 6.8.1 Identification of PACKET Command feature set devices When executing a power-on, hardware, DEVICE RESET, or software reset, a device implementing the PACKET Command feature set performs the same reset protocol as other devices but leaves the registers with a signature unique to PACKET Command feature set devices (see 9.12). In addition, the IDENTIFY DEVICE command shall not be executed but shall be command aborted and shall return a signature unique to devices implementing the PACKET Command feature set. The IDENTIFY PACKET DEVICE command is used by the host to get identifying parameter information for a device implementing the PACKET Command feature set (see 8.15.5.2 and 8.16). Page 30 T13/1410D revision 3b 6.8.2 PACKET Command feature set resets Devices implementing the PACKET Command feature set respond to power-on, hardware, and software resets as any other device except for the resulting contents in the device registers as described above. However, software reset should not be issued while a PACKET command is in progress. PACKET commands used by some devices do not terminate if a software reset is issued. The DEVICE RESET command is provided to allow the device to be reset without affecting the other device on the bus. 6.8.3 The PACKET command The PACKET command allows a host to send a command to the device via a command packet. The command packet contains the command and command parameters that the device is to execute (see clause 2). Upon receipt of the PACKET command the device sets BSY to one and prepares to receive the command packet. When ready, the device sets DRQ to one and clears BSY to zero. The command packet is then transferred to the device by PIO transfer. When the last word of the command packet is transferred, the device sets BSY to one, and clears DRQ to zero (see 8.23 and 9.8). 6.9 Overlapped feature set The optional Overlap feature set allows devices that require extended command time to perform a bus release so that the other device on the bus may be used. To perform a bus release the device shall clear both DRQ and BSY to zero. When selecting the other device during overlapped operations, the host shall disable assertion of INTRQ via the nIEN bit on the currently selected device before writing the Device register to select the other device and then may re-enable interrupts. The only commands that may be overlapped are: − − − − − − − NOP (with a subcommand code other than 00h) PACKET READ DMA QUEUED READ DMA QUEUED EXT SERVICE WRITE DMA QUEUED WRITE DMA QUEUED EXT For the PACKET command, overlap is specified by the OVL bit in the Features register when the PACKET command is issued. If the device supports PACKET command overlap, the OVL bit is set to one in the Features register and the Release interrupt has been enabled via the SET FEATURES command, then the device shall perform a bus release when the command packet has been received. This allows the host to select the other device to execute commands. When the device is ready to continue the command, the device sets SERV to one, and asserts INTRQ if selected and nIEN is cleared to zero. The host then issues the SERVICE command to continue the execution of the command If the device supports PACKET command overlap, the OVL bit is set to one in the Features register and the Release interrupt has been disabled via the SET FEATURES command, then the device may or may not perform a bus release. If the device is ready to complete execution of the command, the device may complete the command immediately as described in the non-overlap case. If the device is not ready to complete execution of the command, the device may perform a bus release and complete the command as described in the previous paragraph. Page 31 T13/1410D revision 3b For the READ DMA QUEUED and WRITE DMA QUEUED commands, the device may or may not perform a bus release. If the device is ready to complete execution of the command, the device may complete the command immediately. If the device is not ready to complete execution of the command, the device may perform a bus release and complete the command via a service request. If a device has an outstanding command that has been released, the device can only indicate that service is required when the device is selected. This implies that the host has to poll each device to determine if a device is requesting service. The polling can be performed at the host either by hardware or by a software routine. The latter implies a considerable host processor overhead. Hardware polling is initiated by the NOP Auto Poll command. The NOP Poll command is a host adapter function and is ignored by the device. The host software can test for the support of this feature by issuing the NOP Auto Poll subcommand and examining the Status register. If the host adapter does not support this feature, the response received by the host will be from the device with the ERR bit set to one. If the host adapter does support the command, the response will be from the host adapter with the ERR bit cleared to zero. The only action taken by a device supporting the Overlapped feature set will be to return the error indication in the Status register and to not abort any outstanding commands. 6.10 Queued feature set The Queued feature set allows the host to issue concurrent commands to the same device. The Queued feature set is optional if the Overlap feature set is supported. Only commands included in the Overlapped feature set may be queued. The queue contains all commands for which command acceptance has occurred but command completion has not occurred. If a queue exists when a non-queued command is received, the nonqueued command shall be command aborted and the commands in the queue shall be discarded. The ending status shall be command aborted and the results are indeterminate. The maximum queue depth supported by a device shall be indicated in word 75 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. A queued command shall have a Tag provided by the host in the Sector Count register to uniquely identify the command. When the device restores register parameters during the execution of the SERVICE command, this Tag shall be restored so that the host may identify the command for which status is being presented. A Tag value may be any value between 0 and 31, regardless of the queue depth supported. If a queued command is issued with a Tag value that is identical to the Tag value for a command already in the queue, the entire queue shall be aborted including the new command. The ending status shall be command aborted and the results are indeterminate. If any error occurs, the command queue shall be aborted. When the device is ready to continue the processing of a bus released command and BSY and DRQ are both cleared to zero, the device requests service by setting SERV to one, setting a pending interrupt, and asserting INTRQ if selected and if nIEN is cleared to zero. SERV shall remain set until all commands ready for service have been serviced. A read of the Status register or a write of the Command register shall clear the interrupt pending. When the device is ready to continue the processing of a bus released command and BSY or DRQ is set to one (i.e., the device is processing another command on the bus), the device requests service by setting SERV to one. SERV shall remain set until all commands ready for service have been serviced. At command completion of the current command processing (i.e., when both BSY and DRQ are cleared to zero), the device shall process interrupt pending and INTRQ per the protocol for the command being completed. No additional INTRQ assertion shall occur due to other commands ready for service until after the device’s SERV bit has been cleared to zero. When the device receives a new command while queued commands are ready for service, the device shall execute the new command and process interrupt pending and INTRQ per the protocol for the new command. If the queued commands ready for service still exist at command completion of this command, SERV remains set to one but no additional INTRQ assertion shall occur due to commands ready for service. Page 32 T13/1410D revision 3b When queuing commands, the host shall disable INTRQ assertion via the nIEN bit before writing a new command to the Command register and may re-enable INTRQ assertion after writing the command. When reading status at command completion of a command, the host shall check the SERV bit since the SERV bit may be set because the device is ready for service associated with another command. The host receives no additional INTRQ assertion to indicate that a queued command is ready for service. 6.11 Power Management feature set A device shall implement power management. A device implementing the PACKET Command feature set may implement the power management as defined by the packet command set implemented by the device. Otherwise, the device shall implement the Power Management feature set as described in this standard. The Power Management feature set permits a host to modify the behavior of a device in a manner that reduces the power required to operate. The Power Management feature set provides a set of commands and a timer that enable a device to implement low power consumption modes. A register delivered command device that implements the Power Management feature set shall implement the following minimum set of functions: − − − − − − − A Standby timer CHECK POWER MODE command IDLE command IDLE IMMEDIATE command SLEEP command STANDBY command STANDBY IMMEDIATE command A device that implements the PACKET Command feature set and implements the Power Management feature set shall implement the following minimum set of functions: − − − − CHECK POWER MODE command IDLE IMMEDIATE command SLEEP command STANDBY IMMEDIATE command 6.11.1 Power management commands The CHECK POWER MODE command allows a host to determine if a device is currently in, going to or leaving Standby or Idle mode. The CHECK POWER MODE command shall not change the power mode or affect the operation of the Standby timer. The IDLE and IDLE IMMEDIATE commands move a device to Idle mode immediately from the Active or Standby modes. The IDLE command also sets the Standby timer count and enables or disables the Standby timer. The STANDBY and STANDBY IMMEDIATE commands move a device to Standby mode immediately from the Active or Idle modes. The STANDBY command also sets the Standby timer count and enables or disables the Standby timer. The SLEEP command moves a device to Sleep mode. The device's interface becomes inactive at command completion of the SLEEP command. A hardware or software reset or DEVICE RESET command is required to move a device out of Sleep mode. Page 33 T13/1410D revision 3b 6.11.2 Standby timer The Standby timer provides a method for the device to automatically enter Standby mode from either Active or Idle mode following a host programmed period of inactivity. If the Standby timer is enabled and if the device is in the Active or Idle mode, the device waits for the specified time period and if no command is received, the device automatically enters the Standby mode. If the Standby timer is disabled, the device may automatically enter Standby mode. 6.11.3 Power modes Figure 8 shows the set of mode transitions that shall be implemented. PM0: Active reset Power-up with Power-up in Standby feature not implemented or not enabled PM0:PM0 SLEEP command PM0:PM3 PM1: Idle PM2: Standby Power-up with Power-up in Standby implemented and enabled STANDBY or STANDBY IMMEDIATE command, vendor specific implementation, or Standby timer expiration PM0:PM2 reset IDLE or IDLE IMMEDIATE command, or vendor specific implementation PM1:PM1 PM0:PM1 Media access required PM2:PM0 Media access required reset PM1:PM0 PM2:PM2 STANDBY or STANDBY IMMEDIATE command, vendor specific implementation, or Standby timer expiration PM1:PM2 IDLE or IDLE IMMEDIATE command PM2:PM1 PM3: Sleep SLEEP command SLEEP command PM2:PM3 PM1:PM3 reset PM3:PM2 Figure 8 − Power management state diagram PM0: Active: This mode shall be entered when the device receives a media access command while in Idle or Standby mode. This mode shall also be entered when the device is powered-up with the Power-Up In Standby feature not implemented or not enabled (see 6.18). Page 34 T13/1410D revision 3b In Active mode the device is capable of responding to commands. During the execution of a media access command a device shall be in Active mode. Power consumption is greatest in this mode. Transition PM0:PM0: When hardware reset, software reset, or DEVICE RESET command is received, the device shall make a transition to the PM0: Active mode when the reset protocol is completed. Transition PM0:PM1: When an IDLE or IDLE IMMEDIATE command is received or when a vendor specific implementation determines a transition is required, then the device shall make a transition to the PM1:Idle mode. Transition PM0:PM2: When a STANDBY or STANDBY IMMEDIATE command is received, the Standby timer expires, or a vendor specific implementation determines a transition is required, then the device shall make a transition to the PM2:Standby mode. Transition PM0:PM3: When a SLEEP command is received, the device shall make a transition to the PM3:Sleep mode. PM1: Idle: This mode shall be entered when the device receives an IDLE or IDLE IMMEDIATE command. Some devices may perform vendor specific internal power management and make a transition to the Idle mode without host intervention. In Idle mode the device is capable of responding to commands but the device may take longer to complete commands than when in the Active mode. Power consumption may be reduced from that of Active mode. Transition PM1:PM0: When a media access is required, the device shall make a transition to the PM0:Active mode. Transition PM1:PM1: When hardware reset, software reset, or DEVICE RESET command is received, the device shall make a transition to the PM1:Idle mode when the reset protocol is completed. Transition PM1:PM2: When a STANDBY or STANDBY IMMEDIATE command is received, the Standby timer expires, or a vendor specific implementation determines a transition is required, then the device shall make a transition to the PM2:Standby mode. Transition PM1:PM3: When a SLEEP command is received, the device shall make a transition to the PM3:Sleep mode. PM2: Standby: This mode shall be entered when the device receives a STANDBY command, a STANDBY IMMEDIATE command, or the Standby timer expires. Some devices may perform vendor specific internal power management and make a transition to the Standby mode without host intervention. This mode shall also be entered when the device is powered-up with the Power-Up In Standby feature implemented and enabled. In Standby mode the device is capable of responding to commands but the device may take longer to complete commands than in the Idle mode. The time to respond could be as long as 30 s. Power consumption may be reduced from that of Idle mode. Transition PM2:PM0: When a media access is required, the device shall make a transition to the PM0:Active mode. Transition PM2:PM1: When an IDLE or IDLE IMMEDIATE command is received, or a vendor specific implementation determines a transition is required, then the device shall make a transition to the PM1:Idle mode. Page 35 T13/1410D revision 3b Transition PM2:PM2: When hardware reset, software reset, or DEVICE RESET command is received, the device shall make a transition to the PM2:Standby mode when the reset protocol is completed. Transition PM2:PM3: When a SLEEP command is received, the device shall make a transition to the PM3:Sleep mode. PM3: Sleep: This mode shall be entered when the device receives a SLEEP command. In Sleep mode the device requires a hardware or software reset or a DEVICE RESET command to be activated. The time to respond could be as long as 30 s. Sleep mode provides the lowest power consumption of any mode. In Sleep mode, the device's interface is not active. The content of the Status register is invalid in this mode. Transition PM3:PM2:, When hardware reset, software reset, or DEVICE RESET command is received the device shall make a transition to the PM2:Standby mode. 6.12 Advanced Power Management feature set The Advanced Power Management feature set is an optional feature set that allows the host to select a power management level. The power management level is specified using a scale from the lowest power consumption setting of 01h to the maximum performance level of FEh. Device performance may increase with increasing power management levels. Device power consumption may increase with increasing power management levels. A device may implement one power management method for two or more contiguous power management levels. For example, a device may implement one power management method from level 80h to A0h and a higher performance, higher power consumption method from level A1h to FEh. Advanced power management levels 80h and higher do not permit the device to spin down to save power. The Advanced Power Management feature set uses the following functions: − − A SET FEATURES subcommand to enable Advanced Power Management A SET FEATURES subcommand to disable Advanced Power Management Advanced Power Management is independent of the Standby timer setting. If both Advanced Power Management and the Standby timer are set, the device will go to the Standby state when the timer times out or the device’s Advanced Power Management algorithm indicates that the Standby state should be entered. The IDENTIFY DEVICE indicates that Advanced Power Management is supported, if Advanced Power Management is enabled, and the current advanced power management level if Advanced Power Management is enabled. 6.13 Security Mode feature set The optional Security Mode feature set is a password system that restricts access to user data stored on a device. The system has two passwords, User and Master, and two security levels, High and Maximum. The security system is enabled by sending a user password to the device with the SECURITY SET PASSWORD command. When the security system is enabled, access to user data on the device is denied after a power cycle until the User password is sent to the device with the SECURITY UNLOCK command. A Master password may be set in a addition to the User password. The purpose of the Master password is to allow an administrator to establish a password that is kept secret from the user, and which may be used to unlock the device if the User password is lost. Setting the Master password does not enable the password system. Page 36 T13/1410D revision 3b The security level is set to High or Maximum with the SECURITY SET PASSWORD command. The security level determines device behavior when the Master password is used to unlock the device. When the security level is set to High the device requires the SECURITY UNLOCK command and the Master password to unlock. When the security level is set to Maximum the device requires a SECURITY ERASE PREPARE command and a SECURITY ERASE UNIT command with the master password to unlock. Execution of the SECURITY ERASE UNIT command erases all user data on the device. The SECURITY FREEZE LOCK command prevents changes to passwords until a following power cycle. The purpose of the SECURITY FREEZE LOCK command is to prevent password setting attacks on the security system. A device that implements the Security Mode feature set shall implement the following minimum set of commands: − − − − − − SECURITY SET PASSWORD SECURITY UNLOCK SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY DISABLE PASSWORD Support of the Security Mode feature set is indicated in IDENTIFY DEVICE word 82 and word 128. 6.13.1 Security mode initial setting When the device is shipped by the manufacturerer, the state of the Security Mode feature shall be disabled. The initial Master password value is not defined by this standard. If the Master Password Revision Code feature is supported, the Master Password Revision Code shall be set to FFFEh by the manufacturer. 6.13.2 User password lost If the User password sent to the device with the SECURITY UNLOCK command does not match the user password previously set with the SECURITY SET PASSWORD command, the device shall not allow the user to access data. If the Security Level was set to High during the last SECURITY SET PASSWORD command, the device shall unlock if the Master password is received. If the Security Level was set to Maximum during the last SECURITY SET PASSWORD command, the device shall not unlock if the Master password is received. The SECURITY ERASE UNIT command shall erase all user data and unlock the device if the Master password matches the last Master password previously set with the SECURITY SET PASSWORD command. 6.13.3 Attempt limit for SECURITY UNLOCK command The device shall have an attempt limit counter. The purpose of this counter is to defeat repeated trial attacks. After each failed User or Master password SECURITY UNLOCK command, the counter is decremented. When the counter value reaches zero the EXPIRE bit (bit 4) of word 128 in the IDENTIFY DEVICE information is set to one, and the SECURITY UNLOCK and SECURITY UNIT ERASE commands are command aborted until the device is powered off or hardware reset. The EXPIRE bit shall be cleared to zero after power-on or hardware reset. The counter shall be set to five after a power-on or hardware reset. Page 37 T13/1410D revision 3b 6.13.4 Security mode states Figure 8 decribes security mode states and state transitions. SEC2:Security disabled/Frozen SEC0:Powered down / Security disabled Power-down SEC2:SEC0 SEC1:Security disabled/not Frozen RESET- asserted SEC2:SEC1 Power-up SEC0:SEC1 Power-down SEC1:SEC0 SECURITY FREEZE LOCK command SEC1:SEC2 SEC5:Unlocked/not Frozen RESET- asserted SEC1:SEC1 SECURITY SET PASSWORD command SEC1:SEC5 SECURITY DISABLE PASSWORD command SEC5a:SEC1 SECURITY ERASE UNIT command SEC5b:SEC1 SEC4: Security enabled / Locked SEC3:Powered down / Security enabled Power-up SEC3:SEC4 SECURITY ERASE SECURITY UNLOCK command UNIT command SEC4:SEC5 SEC4:SEC1 RESET- asserted SEC5:SEC4 Power-down SEC4:SEC3 RESET- asserted SEC4:SEC4 SEC6:Unlocked/Frozen RESET- asserted SEC6:SEC4 Power-down SEC6:SEC3 SECURITY FREEZE LOCK command SEC5:SEC6 Power-down SEC5:SEC3 Figure 9 − Security mode state diagram SEC0: Powered down/Security disabled: This mode shall be entered when the device is powereddown with the Security Mode feature set disabled. Page 38 T13/1410D revision 3b Transition SEC0:SEC1: When the device is powered-up, the device shall make a transition to the SEC1: Security disabled/not Frozen state. SEC1: Security disabled/not Frozen: This mode shall be entered when the device is powered-up or a hardware reset is received with the Security Mode feature set disabled or when the Security Mode feature set is disabled by a SECURITY DISABLE PASSWORD or SECURITY ERASE UNIT command. In this state, the device is capable of responding to all commands (see Table 10 Unlocked column). Transition SEC1:SEC0: When the device is powered-down, the device shall make a transition to the SEC0: Powered down/Security disabled state. Transition SEC1:SEC1: When the device receives a hardware reset, the device shall make a transition to the SEC1: Security disabled/not Frozen state. Transition SEC1:SEC2: When a SECURITY FREEZE LOCK command is received, the device shall make a transition to the SEC2: Security disabled/Frozen state. Transition SEC1:SEC5: When a SECURITY SET PASSWORD command is received, the device shall make a transition to the SEC5: Unlocked/not frozen state SEC2: Security disabled/Frozen: This mode shall be entered when the device receives a SECURITY FREEZE LOCK command while in Security disabled/not Frozen state. In this state, the device is capable of responding to all commands except those indicated in Table 10 Frozen column. Transition SEC2:SEC0: When the device is powered-down, the device shall make a transition to the SEC0: Powered down/Security disabled state. Transition SEC2:SEC1: When the device receives a hardware reset, the device shall make a transition to the SEC1: Security disabled/not Frozen state. SEC3: Powered down/Security enabled: This mode shall be entered when the device is powereddown with the Security Mode feature set enabled. Transition SEC3:SEC4: When the device is powered-up, the device shall make a transition to the SEC4: Security enabled/locked state. SEC4: Security enabled/Locked: This mode shall be entered when the device is powered-up or a hardware reset is received with the Security Mode feature set enabled. In this state, the device shall only respond to commands that do not access data in the user data area of the media (see Table 10 Locked column). Transition SEC4:SEC3: When the device is powered-down, the device shall make a transition to the SEC3: Powered down/Security enabled state. Transition SEC4:SEC4: When the device receives a hardware reset, the device shall make a transition to the SEC4: Security enabled/locked state. Transition SEC4:SEC5: When a valid SECURITY UNLOCK command is received, the device shall make a transition to the SEC5: Unlocked/not Frozen state. Page 39 T13/1410D revision 3b Transition SEC4:SEC1: When a SECURITY ERASE PREPARE command is received and is followed by a SECURITY ERASE UNIT command, the device shall make a transition to the SEC1: Security disabled/not Frozen state. SEC5: Unlocked/not Frozen: This mode shall be entered when the device receives a SECURITY SET PASSWORD command to enable the lock or a SECURITY UNLOCK command. In this state, the device shall respond to all commands (see Table 10 Unlocked column). Transition SEC5a:SEC1: When a valid SECURITY DISABLE PASSWORD command is received, the device shall make a transition to the SEC1: Security disabled/not Frozen state. Transition SEC5b:SEC1: When a SECURITY ERASE PREPARE command is received and is followed by a SECURITY ERASE UNIT command, the device shall make a transition to the SEC1: Security disabled/not Frozen state. Transition SEC5:SEC6: When a SECURITY FREEZE LOCK command is received, the device shall make a transition to the SEC6: Unlocked/Frozen state. Transition SEC5:SEC3: When the device is powered-down, the device shall make a transition to the SEC3: Powered down/Security enabled state. Transition SEC5:SEC4: When the device receives a hardware reset, the device shall make a transition to the SEC4: Security enabled/Locked state. SEC6: Unlocked/ Frozen: This mode shall be entered when the device receives a SECURITY FREEZE LOCK command while in Unlocked/Locked state. In this state, the device is capable of responding to all commands except those indicated in Table 10 Frozen column. Transition SEC6:SEC3: When the device is powered-down, the device shall make a transition to the SEC3: Powered down/Security enabled state. Transition SEC6:SEC4: When the device receives a hardware reset, the device shall make a transition to the SEC4: Security enabled/Locked state. Page 40 T13/1410D revision 3b Table 10 − Security mode command actions Command CFA ERASE SECTORS CFA REQUEST EXTENDED ERROR CODE CFA TRANSLATE SECTOR CFA WRITE MULTIPLE WITHOUT ERASE CFA WRITE SECTORS WITHOUT ERASE CHECK MEDIA CARD TYPE CHECK POWER MODE DEVICE CONFIGURATION DEVICE RESET DOWNLOAD MICROCODE EXECUTE DEVICE DIAGNOSTIC FLUSH CACHE FLUSH CACHE EXT GET MEDIA STATUS IDENTIFY DEVICE IDENTIFY PACKET DEVICE IDLE IDLE IMMEDIATE MEDIA EJECT MEDIA LOCK MEDIA UNLOCK NOP PACKET READ BUFFER READ DMA READ DMA EXT READ DMA QUEUED READ DMA QUEUED EXT READ LOG EXT READ MULTIPLE READ MULTIPLE EXT READ NATIVE MAX ADDRESS READ NATIVE MAX ADDRESS EXT READ SECTORS READ SECTORS EXT READ VERIFY SECTORS READ VERIFY SECTORS EXT SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY SET PASSWORD SECURITY UNLOCK SEEK SERVICE SET FEATURES SET MAX ADDRESS SET MAX ADDRESS EXT SET MULTIPLE MODE SLEEP SMART DISABLE OPERATIONS SMART ENABLE/DISABLE AUTOSAVE Locked Command aborted Executable Executable Command aborted Command aborted Command aborted Executable Command aborted Executable Executable Executable Command aborted Command aborted Command aborted Executable Executable Executable Executable Command aborted Command aborted Command aborted Executable Command aborted Executable Command aborted Command aborted Command aborted Command aborted Command aborted Command aborted Command aborted Executable Executable Command aborted Command aborted Command aborted Command aborted Command aborted Executable Executable Command aborted Command aborted Executable Executable Command aborted Executable Command aborted Command aborted Executable Executable Executable Executable Unlocked Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Frozen Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Command aborted Command aborted Command aborted Executable Command aborted Command aborted Executable Executable Executable Executable Executable Executable Executable Executable Executable (continued) Page 41 T13/1410D revision 3b Table 10 − Security mode command actions (continued) Command SMART ENABLE OPERATIONS SMART EXECUTE OFF-LINE IMMEDIATE SMART READ DATA SMART READ LOG SMART RETURN STATUS SMART WRITE LOG STANDBY STANDBY IMMEDIATE WRITE BUFFER WRITE DMA WRITE DMA EXT WRITE DMA QUEUED WRITE DMA QUEUED EXT WRITE LOG EXT WRITE MULTIPLE WRITE MULTIPLE EXT WRITE SECTORS WRITE SECTORS EXT Locked Executable Executable Executable Executable Executable Executable Executable Executable Executable Command aborted Command aborted Command aborted Command aborted Command aborted Command aborted Command aborted Command aborted Command aborted Unlocked Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Frozen Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable Executable (concluded) 6.14 Self-monitoring, analysis, and reporting technology feature set The intent of self-monitoring, analysis, and reporting technology (the SMART feature set) is to protect user data and minimize the likelihood of unscheduled system downtime that may be caused by predictable degradation and/or fault of the device. By monitoring and storing critical performance and calibration parameters, SMART feature set devices attempt to predict the likelihood of near-term degradation or fault condition. Providing the host system the knowledge of a negative reliability condition allows the host system to warn the user of the impending risk of a data loss and advise the user of appropriate action. Support of this feature set is indicated in the IDENTIFY DEVICE response. Devices that implement the PACKET Command feature set shall not implement the SMART feature set as described in thisstandard. Devices that implement the PACKET Command feature set and SMART shall implement SMART as defined by the command packet set implemented by the device. This feature set is optional if the PACKET Command feature set is not supported. 6.14.1 Device SMART data structure SMART feature set capability and status information for the device are stored in the device SMART data structure. The off-line data collection capability and status data stored herein may be useful to the host if the SMART EXECUTE OFF-LINE IMMEDIATE command is implemented (see 8.51.4). 6.14.2 On-line data collection Collection of SMART data in an “on-line” mode shall have no impact on device performance. The SMART data that is collected or the methods by which data is collected in this mode may be different than those in the offline data collection mode for any particular device and may vary from one device to another. 6.14.3 Off-line data collection The device shall use off-line mode for data collection and self-test routines that have an impact on performance if the device is required to respond to commands from the host while performing that data collection. This impact on performance may vary from device to device. The data that is collected or the methods by which the data is collected in this mode may be different than those in the on-line data collection mode for any particular device and may vary from one device to another. Page 42 T13/1410D revision 3b 6.14.4 Threshold exceeded condition This condition occurs when the device’s SMART reliability status indicates an impending degrading or fault condition. 6.14.5 SMART feature set commands These commands use a single command code and are differentiated from one another by the value placed in the Features register (see 8.51). If the SMART feature set is implemented, the following commands shall be implemented. − − − − SMART DISABLE OPERATIONS SMART ENABLE/DISABLE AUTOSAVE SMART ENABLE OPERATIONS SMART RETURN STATUS If the SMART feature set is implemented, the following commands may be implemented. − − − − − − SMART EXECUTE OFF-LINE IMMEDIATE SMART READ DATA SMART READ LOG SMART WRITE LOG READ LOG EXT WRITE LOG EXT 6.14.6 SMART operation with power management modes When used with a host that has implemented the Power Management feature set, a SMART enabled device should automatically save the device accumulated SMART data upon receipt of an IDLE IMMEDIATE, STANDBY IMMEDIATE, or SLEEP command or upon return to an Active or Idle mode from a Standby mode (see 8.51.5). If a SMART feature set enabled device has been set to use the Standby timer, the device should automatically save the device accumulated SMART data prior to going from an Idle mode to the Standby mode or upon return to an Active or Idle mode from a Standby mode. A device shall not execute any routine to automatically save the device accumulated SMART data while the device is in a Standby or Sleep mode. 6.14.7 SMART device error log reporting Logging of reported errors is an optional SMART feature. If error logging is supported by a device, it is indicated in byte 370 of the SMART READ DATA command response and bit 0 of word 84 of the IDENTIFY DEVICE response. If error logging is supported, the device shall provide information on the last five errors that the device reported as described in the SMART READ LOG command (see 8.51.6). The device may also provide additional vendor specific information on these reported errors. If error logging is supported, it shall not be disabled when SMART is disabled. Error log information shall be gathered when the device is powered-on except that logging of errors when in a reduced power mode is optional. If errors are logged when in a reduced power mode, the reduced power mode shall not change. Disabling SMART shall disable the delivering of error log information via the SMART READ LOG command. If a device receives a firmware modification, all error log data shall be discarded and the device error count for the life of the device shall be reset to zero. Page 43 T13/1410D revision 3b 6.15 Host Protected Area feature set A reserved area for data storage outside the normal operating system file system is required for several specialized applications. Systems may wish to store configuration data or save memory to the device in a location that the operating systems cannot change. The optional Host Protected Area feature set allows a portion of the device to be reserved for such an area when the device is initially configured. A device that implements the Host Protected Area feature set shall implement the following minimum set of commands: − READ NATIVE MAX ADDRESS − SET MAX ADDRESS A device that implements the Host Protected Area feature set and supports the 48-bit Address feature set shall implement the following additional set of commands: − READ NATIVE MAX ADDRESS EXT − SET MAX ADDRESS EXT Devices supporting this feature set shall set bit 10 of word 82 to one in the data returned by the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command. In addition, a device supporting the Host Protected Area feature set may optionally include the security extensions. The Host Protected Area security commands use a single command code and are differentiated from one another by the value placed in the Features register. − − − − SET MAX SET PASSWORD SET MAX LOCK SET MAX FREEZE LOCK SET MAX UNLOCK Devices supporting these extensions shall set bit 10 of word 82 and bit 8 of word 83 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response to one. The READ NATIVE MAX ADDRESS or READ NATIVE MAX ADDRESS EXT command allows the host to determine the maximum native address space of the device even when a protected area has been allocated. The SET MAX ADDRESS or SET MAX ADDRESS EXT command allows the host to redefine the maximum address of the user accessible address space. That is, when the SET MAX ADDRESS or SET MAX ADDRESS EXT command is issued with a maximum address less than the native maximum address, the device reduces the user accessible address space to the maximum specified by the command, providing a protected area above that maximum address. The SET MAX ADDRESS or SET MAX ADDRESS EXT command shall be immediately preceded by a READ NATIVE MAX ADDRESS or READ NATIVE MAX ADDRESS EXT command. After the SET MAX ADDRESS or SET MAX ADDRESS EXT command has been issued, the device shall report only the reduced user address space in response to an IDENTIFY DEVICE command in words 60, 61, 100, 101, 102, and 103. Any read or write command to an address above the maximum address specified by the SET MAX ADDRESS or SET MAX ADDRESS EXT command shall cause command completion with the IDNF bit set to one and ERR set to one, or command aborted. A volatility bit in the Sector Count register allows the host to specify if the maximum address set is preserved across power-on or hardware reset cycles. On poweron or hardware reset the device maximum address returns to the last non-volatile address setting regardless of subsequent volatile SET MAX ADDRESS or SET MAX ADDRESS EXT commands. If the SET MAX ADDRESS or SET MAX ADDRESS EXT command is issued with a value that exceeds the native maximum address command aborted shall be returned. Page 44 T13/1410D revision 3b Typical use of these commands would be: On reset a) BIOS receives control after a system reset; b) BIOS issues a READ NATIVE MAX ADDRESS or READ NATIVE MAX ADDRESS EXT command to find the max capacity of the device; c) BIOS issues a SET MAX ADDRESS or SET MAX ADDRESS EXT command to the values returned by READ NATIVE MAX ADDRESS or READ NATIVE MAX ADDRESS EXT; d) BIOS reads configuration data from the highest area on the disk; e) BIOS issues a READ NATIVE MAX ADDRESS or READ NATIVE MAX ADDRESS EXT command followed by a SET MAX ADDRESS or SET MAX ADDRESS EXT command to reset the device to the size of the file system. On save to disk a) BIOS receives control prior to shut down; b) BIOS issues a READ NATIVE MAX ADDRESS or READ NATIVE MAX ADDRESS EXT command to find the max capacity of the device; c) BIOS issues a volatile SET MAX ADDRESS or SET MAX ADDRESS EXT command to the values returned by READ NATIVE MAX ADDRESS or READ NATIVE MAX ADDRESS EXT; d) Memory is copied to the reserved area; e) Shut down completes; f) On power-on or hardware reset the device max address returns to the last non-volatile setting. These commands are intended for use only by system BIOS or other low-level boot time process. Using these commands outside BIOS controlled boot or shutdown may result in damage to file systems on the device. Devices should return command aborted if a subsequent non-volatile SET MAX ADDRESS or SET MAX ADDRESS EXT command is received after a power-on or hardware reset. The SET MAX SET PASSWORD command allows the host to define the password to be used during the current power-on cycle. The password does not persist over a power cycle but does persist over a hardware or software reset. This password is not related to the password used for the Security Mode Feature set. When the password is set the device is in the Set_Max_Unlocked mode. The SET MAX LOCK command allows the host to disable the SET MAX commands (except SET MAX UNLOCK) until the next power cycle or the issuance and acceptance of the SET MAX UNLOCK command. When this command is accepted the device is in the Set_Max_Locked mode. The SET MAX UNLOCK command changes the device from the Set_Max_Locked mode to the Set_Max_Unlocked mode. The SET MAX FREEZE LOCK command allows the host to disable the SET MAX commands (including SET MAX UNLOCK) until the next power cycle. When this command is accepted the device is in the Set_Max_Frozen mode. 6.15.1 BIOS determination of SET MAX security exension status When the device is locked bit 8 of word 86 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response shall be set to one. 6.15.2 BIOS locking SET MAX To allow for multiple BIOSs to gain access to the protected area the host BIOS should only lock the protected area immediately prior to booting the operating system. Page 45 T13/1410D revision 3b SM1:Set_Max_Unlocked SM0:Set_Max_Security_Inactive SET MAX ADDRESS command SET MAX SET PASSWORD command SM0:SM1 SET MAX SET PASSWORD command SM1b:SM1 SM0a:SM0 SET MAX ADDRESS command SET MAX LOCK, SET MAX UNLOCK, or SET MAX FREEZE LOCK command SM0b:SM0 SET MAX UNLOCK command SM1a:SM1 SM1c:SM1 Power on SET MAX LOCK command SM1:SM2 SM2:Set_Max_Locked SET MAX ADDRESS or SET MAX SET PASSWORD command SM2a:SM2 SET MAX LOCK command SET MAX UNLOCK command SM2:SM1 SET MAX FREEZE LOCK command (optional) SM2:SM3 SM2b:SM2 SET MAX FREEZE LOCK command SM1:SM3 SM3:Set_Max_Frozen SET MAX ADDRESS, SET MAX SET PASSWORD, SET MAX UNLOCK, SET MAX FREEZE LOCK or SET MAX LOCK command SM3:SM3 Figure 10 − SET MAX security state diagram SM0: Set_Max_Security_Inactive: This state shall be entered when the device is powered-on. When in this state, SET MAX security is disabled. Transition SM0a:SM0: When a SET MAX ADDRESS command is received, the command shall be executed and the device shall make a transition to the SM0: Set_MAX_Security_Inactive state. Transition SM0b:SM0: When a SET MAX LOCK, SET MAX UNLOCK, or SET MAX FREEZE LOCK command is received, the device shall abort the command and make a transition to the SM0: Set_MAX_Security_Inactive state. Transition SM0:SM1: When a SET MAX SET PASSWORD command is received, the device shall make a transition to the SM1: Set_Max_Unlocked state. SM1: Set_Max_Unlocked: This state is entered when a SET MAX SET PASSWORD or a SET MAX UNLOCK command is received. When in this state, a SET MAX security password has been established and the SET MAX security is unlocked. Bit 8 of word 86 of the identify device data shall be set to one. Page 46 T13/1410D revision 3b Transition SM1a:SM1: When a SET MAX ADDRESS command is received, the command shall be executed and the device shall make a transition to the SM1: Set_MAX_Unlocked state. Transition SM1b:SM1: When a SET MAX SET PASSWORD is received, the password stored by the device shall be changed to the new value and the device shall make a transition to the SM1: Set_MAX_Unlocked state. Transition SM1c:SM1: When a SET MAX UNLOCK command is received, the command shall not be executed and the device shall make a transition to the SM1: Set_MAX_Unlocked state. Transition SM1:SM2: When a SET MAX LOCK command is received, the device shall make a transition to the SM2: Set_Max_Locked state. Transition SM1:SM3: When a SET MAX FREEZE LOCK command is received, the device shall make a transition to the SM3: Set_Max_Frozen state. SM2: Set_Max_Locked: This state is entered when a SET MAX LOCK command is received. When in this state, a SET MAX security password has been established and the SET MAX security is locked. Bit 8 of word 86 of the identify device data shall be set to one. Transition SM2a:SM2: When a SET MAX ADDRESS or SET MAX SET PASSWORD command is received, the command shall be aborted and the device shall make a transition to the SM2: Set_Max_Locked state. Transition SM2b:SM2: When a SET MAX LOCK command is received, the command shall be executed and the device shall make a transition to the SM2: Set_Max_Locked state. Transition SM2:SM1: When a SET MAX UNLOCK command is received, the device shall make a transition to the SM1: Set Max Unlocked state. Transition SM2:SM3: When a SET MAX FREEZE LOCK command is received, the device may make a transition to the SM3: Set_Max_Frozen state. Hosts should not issue the SET MAX FREEZE LOCK command when in this state. SM3: Set_Max_Frozen: This state is entered when a SET MAX FREEZE LOCK command is received. In this state, the device may not transition to any other state except by a power cycling. When in this mode bit 8 of word 86 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data shall be set to one. Transition SM3:SM3: When a SET MAX ADDRESS, SET MAX SET PASSWORD, SET MAX UNLOCK, SET MAX FREEZE LOCK, or SET MAX LOCK command is received, the command shall be aborted and the device shall make a transition to the SM3: Set_Max_Frozen state. 6.16 CFA feature set The optional CompactFlash Association (CFA) feature set provides support for solid state memory devices. A device that implements the CFA feature set shall implement the following minimum set of commands: − − − − − − CFA REQUEST EXTENDED ERROR CODE CFA WRITE SECTORS WITHOUT ERASE CFA ERASE SECTORS CFA WRITE MULTIPLE WITHOUT ERASE CFA TRANSLATE SECTOR SET FEATURES Enable/Disable 8-bit transfer Page 47 T13/1410D revision 3b Devices reporting the value 848Ah in IDENTIFY DEVICE data word 0 or devices having bit 2 of IDENTIFY DEVICE data word 83 set to one shall support the CFA feature Set. If the CFA feature set is implemented, all five commands shall be implemented. Support of DMA commands is optional for devices that support the CFA feature set. The CFA ERASE SECTORS command preconditions the sector for a subsequent CFA WRITE SECTORS WITHOUT ERASE or CFA WRITE MULTIPLE WITHOUT ERASE command to achieve higher performance during the write operation. The CFA TRANSLATE SECTOR command provides information about a sector such as the number of write cycles performed on that sector and an indication of the sector’s erased precondition. The CFA REQUEST EXTENDED ERROR CODE command provides more detailed error information. Command codes B8h through BFh are reserved for assignment by the CompactFlash Association. 6.17 Removable Media Status Notification and Removable Media feature sets This section describes two feature sets that secure the media in removable media storage devices using the ATA/ATAPI interface protocols. The Removable Media Status Notification feature set is intended for use in both devices implementing the PACKET Command feature set and those not implementing the PACKET Command feature set. The Removable Media feature set is intended for use only in devices not implementing the PACKET Command feature set. Only one of these feature sets shall be enabled at any time. If the Removable Media Status Notification feature set is in use then the Removable Media feature set is disabled and vice versa. The reasons for implementing the Removable Media Status Notification feature Set or the Removable Media feature set are: − to prevent data loss caused by writing to new media while still referencing the previous media’s information. − to prevent data loss by locking the media until completion of a cached write. − to prevent removal of the media by unauthorized persons. 6.17.1 Removable Media Status Notification feature set The Removable Media Status Notification feature set is the preferred feature set for securing the media in removable media storage devices. This feature set uses the SET FEATURES command to enable Removable Media Status Notification. Removable Media Status Notification gives the host system maximum control of the media. The host system determines media status by issuing the GET MEDIA STATUS command and controls the device eject mechanism via the MEDIA EJECT command (for devices not implementing the PACKET Command feature set) or the START/STOP UNIT command (for devices implementing the PACKET Command feature set, see clause 2). While Removable Media Status Notification is enabled devices not implementing the PACKET Command feature set execute MEDIA LOCK and MEDIA UNLOCK commands without changing the media lock state (no-operation). While Removable Media Status Notification is enabled the eject button does not eject the media. Removable Media Status Notification is persistent through medium removal and insertion and is only disabled via the SET FEATURES command, hardware reset, software reset, the DEVICE RESET command, the EXECUTE DEVICE DIAGNOSTIC command, or power-on reset. Removable Media Status Notification shall be re-enabled after any of the previous reset conditions occur. All media status is reset when Removable Media Status Notification is disabled because a reset condition occurred. Any pending media change or media change request is cleared when the Removable Media Status Notification reset condition occurs. The following commands are defined to implement the Removable Media Status Notification feature set. − − GET MEDIA STATUS MEDIA EJECT Page 48 T13/1410D revision 3b − − SET FEATURES (Enable media status notification) SET FEATURES (Disable media status notification) NOTE − Devices implementing the PACKET Command feature set control the media eject mechanism via the START/STOP UNIT command packet. The preferred sequence of events to use the Removable Media Status Notification feature set is as follows: a) Host system checks whether or not the device implements the PACKET Command feature set via the device signature in the Command Block registers. b) Host system issues the IDENTIFY DEVICE command or the IDENTIFY PACKET DEVICE command and checks that the device is a removable media device and that the Removable Media Status Notification feature set is supported. c) Host system uses the SET FEATURES command to enable Media Status Notification that gives control of the media to the host. At this time the host system checks the LBA High register to determine if: − the device is capable of locking the media. − the device is capable of power ejecting the media. − Media Status Notification was enabled prior to this command. d) Host system periodically checks media status using the GET MEDIA STATUS command to determine if any of the following events occurred: − no media is present in the device (NM). − media was changed since the last command (MC). − a media change request has occurred (MCR). − media is write protected (WP). 6.17.2 Removable Media feature set The Removable Media feature set is intended only for devices not implementing the PACKET Command feature set. This feature set operates with Media Status Notification disabled. The MEDIA LOCK and MEDIA UNLOCK commands are used to secure the media and the MEDIA EJECT command is used to remove the media. While the media is locked, the eject button does not eject the media. Media status is determined by checking the media status bits returned by the MEDIA LOCK and MEDIA UNLOCK commands. Power-on reset, hardware reset, and the EXECUTE DEVICE DIAGNOSTIC command clear the Media Lock (LOCK) state and the Media Change Request (MCR) state. Software reset clears the Media Lock (LOCK) state, clears the Media Change Request (MCR) state, and preserves the Media Change (MC) state. The following commands are defined to implement the Removable Media feature set. − − − MEDIA EJECT MEDIA LOCK MEDIA UNLOCK The preferred sequence of events to use the Removable Media feature set is as follows: a) Host system checks whether or not the device implements the PACKET Command feature set via the device signature in the Command Block registers. b) Host system issues the IDENTIFY DEVICE command and checks that the device is a removable media device and that the Removable Media feature set is supported. c) Host system periodically issues MEDIA LOCK commands to determine if: − no media is present in the device (NM) – media is locked if present. − a media change request has occurred (MCR). Page 49 T13/1410D revision 3b 6.18 Power-Up In Standby feature set The optional Power-Up In Standby feature set allows devices to be powered-up into the Standby power management state to minimize inrush current at power-up and to allow the host to sequence the spin-up of devices. This optional feature set may be enabled or disabled via the SET FEATURES command or may be enabled by use of a jumper or similar means, or both. When enabled by a jumper, the feature set shall not be disabled via the SET FEATURES command. The IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response indicates whether this feature set is implemented and/or enabled. The enabling of this feature set shall be persistent after power-down and power-up. When this feature set is enabled, the device shall power-up into Standby. A device may implement a SET FEATURES subcommand that notifies the device to spin-up to the Active state when the device has powered-up into Standby. If the device implements this SET FEATURES subcommand and power-up into Standby is enabled, the device shall remain in Standby until the SET FEATURES subcommand is received. If the device implements this SET FEATURES subcommand, the fact that the feature is implemented is reported in the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. If the device: − − − implements the Enable/disable Power-up in Standby subcommand, power-up into Standby is enabled, and an IDENTIFY DEVICE or IDENTIFY PACKET DEVICE is received while the device is in Standby as a result of powering up into Standby, the device shall respond to the command and remain in Standby without spinning-up. If the device has IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response that requires access to the media, the device shall set word 0 bit 2 to one to indicate that the response is incomplete. At a minimum, word 0 and word 2 shall be correctly reported. Those fields that cannot be provided shall be filled with zeros. Once the full IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response data has been accessed, a full response shall be returned until the next power-down/power-up sequence has taken place. If the device does not implement the SET FEATURES subcommand to spin-up the device after power-up and power-up into Standby is enabled, the device shall spin-up upon receipt of the first command that requires the device to access the media. 6.19 Automatic Acoustic Management feature set The Automatic Acoustic Management feature set is an optional feature set that allows the host to select an acoustic management level. The acoustic management level may range from the setting of 00h to FFh, although many levels are currently reserved (see Table 46). Device performance and acoustic emanation may increase with increasing acoustic management levels. The acoustic management levels may contain discrete bands. For example, a device may implement one acoustic management method from level 80h to A0h, and a higher performance, higher acoustic emanation method from level A1h to FEh. The Automatic Acoustic Management feature set uses the following functions: − − A SET FEATURES subcommand to enable the Automatic Acoustic Management feature set A SET FEATURES subcommand to disable the Automatic Acoustic Management feature set The IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data indicates if the Automatic Acoustic Management feature set is supported, if the Automatic Acoustic Management feature set is enabled, and the current automatic acoustic management level if the Automatic Acoustic Management feature set is enabled. Page 50 T13/1410D revision 3b 6.20 48-bit Address feature set The optional 48-bit Address feature set allows devices with capacities up to 281,474,976,710,655 sectors or approximately 281 tera sectors. This allows device capacity up to 144,115,188,075,855,360 bytes or approximately 144 peta bytes. In addition, the number of sectors that may be transferred by a single command are increased by increasing the allowable sector count to 16 bits. Commands unique to the 48-bit Address feature set are: − − − − − − − − − − − − FLUSH CACHE EXT READ DMA EXT READ DMA QUEUED EXT READ MULTIPLE EXT READ NATIVE MAX ADDRESS EXT READ SECTOR(S) EXT READ VERIFY SECTOR(S) SET MAX ADDRESS EXT WRITE DMA EXT WRITE DMA QUEUED EXT WRITE MULTIPLE EXT WRITE SECTOR(S) EXT The 48-bit Address feature set operates in LBA only. Devices implementing the 48-bit Address feature set shall also implement commands that use 28-bit addressing. 28-bit and 48-bit commands may be intermixed. Support of the 48-bit Address feature set is indicated in the IDENTIFY DEVICE response. In a device implementing the 48-bit Address feature set, the Features register, the Sector Count register, the LBA Low register, the LBA Mid register, and the LBA High register are each a two byte deep FIFO. Each time one of these registers is written, the new content written is placed into the “most recently written” location and the previous content of the register is moved to “previous content” location. For example, when a 48-bit Address feature set READ SECTOR(S) EXT command is written to the device Command register, the address used by the command is as described in Table 11. Register Features Sector Count LBA Low LBA Mid LBA High Device register Table 11 − 48-bit addresses “most recently written” Reserved Sector count (7:0) LBA (7:0) LBA (15:8) LBA (23:16) Bits 7 and 5 are obsolete, the LBA bit shall be set to one, the DEV bit shall indicate the selected device, bits (3:0) are reserved “previous content” Reserved Sector count (15:8) LBA (31:24) LBA (39:32) LBA (47:40) Reserved When a READ SECTOR(S) command utilizing 28-bit addressing is written to the device Command register, the address used by the command is as described in Table 12. Thus commands utilizing 28-bit addressing still function as described in the command descriptions. Page 51 T13/1410D revision 3b Register Features Sector Count LBA Low LBA Mid LBA High Device register Table 12 − 28-bit addresses “most recently written” na Sector count (7:0) LBA (7:0) LBA (15:8) LBA (23:16) LBA (27:24) “previous content” na na na na na na The host may read the “previous content” of the Features, Sector Count, LBA Low, LBA Mid, and LBA High registers by first setting the High Order Bit (HOB, bit 7) of the Device Control register to one and then reading the desired register. If HOB (bit 7) in the Device Control register is cleared to zero the host reads the “most recently written” content when the register is read. A write to any Command Block register shall cause the device to clear the HOB bit to zero in the Device Control register. The “most recently written” content always gets written by a register write regardless of the state of HOB (bit 7) in the Device Control register. Registers are written and read as described in 7.1. The device shall indicate support of the 48-bit Address feature set in the IDENTIFY DEVICE response. In addition, IDENTIFY DEVICE response words (103:100) contain the maximum user LBA + 1 that is accessible by 48-bit addressable commands . If the value contained in IDENTIFY DEVICE response words (103:100) is equal to or less than 268,435,455, then the content of words (61:60) shall be as described in 6.2.1. If the value in contained IDENTIFY DEVICE response words (103:100) is greater than 268,435,455, then the maximum value in words (61:60) shall be 268,435,455. That is, if the device contains greater than the capacity addressable with 28-bit commands, words (61:60) shall describe the maximum capacity that can be addressed by 28-bit commands. When the 48-bit Address feature set is implemented, the native maximum address is the highest address accepted by the device in the factory default condition using a 48-bit Address feature set command. The native maximum address is the value returned by a READ NATIVE MAX ADDRESS EXT command. If the native maximum address of a device is equal to or less than 268,435,455, a READ NATIVE MAX ADDRESS shall return the native maximum address. If the native maximum address is greater than 268,435,455, a READ NATIVE MAX ADDRESS command shall cause the device to return a maximum value of 268,435,454. When the 48-bit Address feature set is implemented, the SET MAX ADDRESS command shall execute as described in 8.47.1. However, in addition to modifying the content of words (61:60), the new content of (61:60) shall also be placed in words (103:100). When a SET MAX ADDRESS EXT command is issued and the address requested is greater than 268,435,455, words (103:100) shall be modified to reflect the requested value but words 60, and 61 shall not be modified. When a SET MAX ADDRESS EXT command is issued and the address requested is equal to or less than 268,435,455, words (103:100) shall be modified to reflect the requested value and words 60, and 61 shall be modified as described in 8.47.1.8. If a Host Protected Area has been created using the SET MAX ADDRESS command, all SET MAX ADDRESS EXT commands shall result in command aborted until the Host Protected Area is eliminated by use of the SET MAX ADDRESS command with the address value returned by the READ NATIVE MAX ADDRESS command. If a Host Protected Area has been created using the SET MAX ADDRESS EXT command, all SET MAX ADDRESS commands shall result in command aborted until the Host Protected Area is eliminated by use of the SET MAX ADDRESS EXT command with the address value returned by the READ NATIVE MAX ADDRESS EXT command. Page 52 T13/1410D revision 3b 6.21 Device Configuration Overlay feature set The optional Device Configuration Overlay feature set allows a utility program to modify some of the optional commands, modes, and feature sets that a device reports as supported in the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command response as well as the capacity reported. Commands unique to the Device Configuration Overlay feature set use a single command code and are differentiated from one another by the value placed in the Features register. These commands are: − − − − DEVICE CONFIGURATION FREEZE LOCK DEVICE CONFIGURATION IDENTIFY DEVICE CONFIGURATION RESTORE DEVICE CONFIGURATION SET The Device Configuration Overlay feature set may affect words (61:60), 63, (88:82), and(103:100) of the IDENTIFY DEVICE and IDENTIFY PACKET DEVICE command responses. Certain bits in these words that indicate that a command, mode, capacity, or feature set is supported and enabled may be cleared by a DEVICE CONFIGURATION SET command. For a particular command, mode, capacity, or feature set, when a bit is cleared indicating that the device does not support the feature, the device shall not provide the feature. Also, the maximum capacity of the device may be reduced. Since a Host Protected Area may be lost if the capacity of the device is reduced, when a Host Protected Area is set the DEVICE CONFIGURATION SET command shall cause the device to return command aborted. The address value returned by a READ NATIVE MAX ADDRESS or READ NATIVE MAX ADDRESS EXT command is modified by the DEVICE CONFIGURATION SET command modifying the maximum capacity of the device. If a DEVICE CONFIGURATION FREEZE LOCK command has been issued since the device powered-up, the DEVICE CONFIGURATION SET command shall cause the device to return command aborted. The settings made by a DEVICE CONFIGURATION SET command are maintained over power-down and power-up. A DEVICE CONFIGURATION IDENTIFY command specifies the selectable commands, modes, capacity, and feature sets that the device is capable of supporting. After the execution of a DEVICE CONFIGURATION SET command this information is no longer available from an IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command. A DEVICE CONFIGURATION RESTORE command disables an overlay that has been set by a DEVICE CONFIGURATION SET command and returns the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command response to that indicated by the DEVICE CONFIGURATION IDENTIFY command. Since a Host Protected Area may be lost if the capacity of the device is reduced, when a Host Protected Area is set the DEVICE CONFIGURATION RESTORE command shall cause the device to return command aborted. If a DEVICE CONFIGURATION FREEZE LOCK command has been issued since the device powered-up, the DEVICE CONFIGURATION RESTORE command shall cause the device to return command aborted. A DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the state of the Device Configuration Overlay feature set. A device always powers-up with configuration freeze lock not set. After a successful DEVICE CONFIGURATION FREEZE LOCK command is executed, all DEVICE CONFIGURATION SET, DEVICE CONFIGURATION IDENTIFY, and DEVICE CONFIGURATION RESTORE commands are aborted by the device until the device is powered-down and powered-up again. The freeze locked state is not affected by hardware or software reset. Figure 11 and the text following the figure describes the operation of the Device Configuration Overlay feature set. Page 53 T13/1410D revision 3b DCO0: Factory_config Power-up with factory configuration set DCO1: DCO_locked DEVICE CONFIGURATION FREEZE LOCK command DCO0:DCO1 DEVICE CONFIGURATION FREEZE LOCK, DEVICE CONFIGURATION IDENTIFY, DEVICE CONFIGURATION RESTORE, or DEVICE CONFIGURATION SET command DEVICE CONFIGURATION RESTORE or Invalid DEVICE CONFIGURATION SET command (see text) DCO0:DCO0 Valid DEVICE CONFIGURATION SET command (see text) DCO1:DCO1 DCO2: Reduced_config DCO0:DCO2 Valid DEVICE CONFIGURATION RESTORE command (see text) DCO2:DCO0 Power-up with reduced configuration set DEVICE CONFIGURATION FREEZE LOCK command DCO2:DCO1 DEVICE CONFIGURATION SET or Invalid DEVICE CONFIGURATION RESTORE command (see text) DCO2:DCO2 Figure 11 − Device Configuration Overlay state diagram DCO0: Factory_config State: This state is entered when the device powers-up with the factory configuration set or a valid DEVICE CONFIGURATION RESTORE command is received. When in this state, the device shall support all commands, modes, features sets, and the capacity indicated by the response to a DEVICE CONFIGURATION IDENTIFY command. Transition DCO0:DCO1: When a DEVICE CONFIGURATION FREEZE LOCK command is received, the device shall return successful command completion and make a transition to the DCO1: DCO_locked state. Transition DCO0:DCO2: When a valid DEVICE CONFIGURATION SET command is received, the device shall return successful command completion and make a transition to the DCO2: Reduced_config state. See Transition DCO0:DCO0 for the definition of conditions that make a DEVICE CONFIGURATION SET command invalid. This transition is made even if the configuration described by the DEVICE SET CONFIGURATION SET command is the same as the factory configuration. Transition DCO0:DCO0: When a DEVICE CONFIGURATION RESTORE command is received, the device shall return command aborted and make a transition to the DCO0: Factory_config state. When an invalid DEVICE CONFIGURATION SET command is received, the device shall return command aborted and make a transition to the DCO0: Factory_config state. A DEVICE CONFIGURATION SET command is invalid if the DEVICE CONFIGURATION SET command requests: − − a Host Protected Area has been established using the SET MAX ADDRESS command. the elimination of support of a Multiword or Ultra DMA mode if that mode is currently selected or a higher numbered mode is currently selected. Page 54 T13/1410D revision 3b − − − − the elimination of support of the Host Protected Area feature set if a Host Protected Area has been established using a SET MAX ADDRESS command. the elimination of support of the Power-up in Standby feature set if the feature set has been enables by a jumper. the elimination of support of the Security feature set if the feature set has been enabled. the elimination of support of the SMART feature set if bits (2:1) of word 7 are not cleared to zero or if the SMART feature set has been enabled by use of the SMART ENABLE OPERATIONS command. DCO1: DCO_locked State: This state is entered when a DEVICE CONFIGURATION RESTORE command is received. When in this state, all DEVICE CONFIGURATION FREEZE LOCK, DEVICE CONFIGURATION IDENTIFY, DEVICE CONFIGURATION SET, or DEVICE CONFIGURATION RESTORE commands shall return command abort and shall remain in the locked state. Transition DCO1:DCO1: When a DEVICE CONFIGURATION FREEZE LOCK, DEVICE CONFIGURATION IDENTIFY, DEVICE CONFIGURATION SET, or DEVICE CONFIGURATION RESTORE command is received, the device shall return command aborted and make a transition to the DCO1: DCO_locked state. DCO2: Reduced_config State: This state is entered when the device powers-up with a reduced configuration set or a valid DEVICE CONFIGURATION SET command is received. When in this state, the device shall support all commands, modes, features sets, and the capacity specified by the DEVICE CONFIGURATION SET command that caused this state to be entered. Transition DCO2:DCO1: When a DEVICE CONFIGURATION FREEZE LOCK command is received, the device shall return successful command completion and make a transition to the DCO1: DCO_locked state. Transition DCO2:DCO0: When a valid DEVICE CONFIGURATION RESTORE command is received, the device shall return successful command completion and make a transition to the DCO0: Factory_config state. See Transition DCO2:DCO2 for the definition of conditions that make a DEVICE CONFIGURATION RESTORE command invalid. Transition DCO2:DCO2: When a DEVICE CONFIGURATION SET command is received, the device shall return command aborted and make a transition to the DCO2: Reduced_config state. When an invalid DEVICE CONFIGURATION RESTORE command is received, the device shall return command aborted and make a transition to the DCO2: Reduced_config state. A DEVICE CONFIGURATION RESTORE command is invalid if a Host Protected Area has been established using the SET MAX ADDRESS command. 6.22 Media Card Pass Through Command feature set The Media Card Pass Through commands are implemented by a Media Pass Through device. A device implementing the Media Card Pass Through Command feature set is a bridge to one or more types of media card storage devices. The bridge device responds to the same command set as described in 6.4.1 and to the commands included in this feature set. The Media Card Pass Through Command feature set uses the command codes D1h, D2h, D3h, and D4h and bits in word 84 and word 87 of the IDENTIFY DEVICE response. The command codes D2h through D4h are reserved for the Media Card Pass Through Command feature set if this feature set is enabled by the CHECK MEDIA CARD TYPE command (D1h). This feature set embeds small-format flash memory card commands inside the ATA commands. The adapter’s firmware passes the embedded memory card’s command to the memory card as is from the ATA command. The Media Card Pass Through Command feature set reduces the number of commands required for this feature set regardless of the number or type of memory card commands. It also reduces the adapter’s firmware overhead in processing them. As new memory cards types are defined in the market, they can all be supported within this one feature. Page 55 T13/1410D revision 3b The commands unique to the Media Card Pass Through Command feature set are: − − CHECK MEDIA CARD TYPE Command codes D2h through D4h The CHECK MEDIA CARD TYPE command returns the supporting status of the device to this feature set. It also enables and disables the device from running the Media Card Pass Through Command feature set. When the Media Card Pass Through Command feature set is disabled, the command codes D2h through D4h shall not be interpreted as Media Card Pass Through Command feature set commands and the device shall return command aborted. Power-on, hardware, or software reset shall disable the Media Card Pass Through Command feature set. The definitions of the commands D2h-D4h are media card type dependent. Table 13 lists the Media card types and their associated reference document: Media Card Type SD Card Smart Media Table 13 – Media Card type references Reference Document SD Card ATA Command Extension (SDA 3C) Smart Media ATA Command Extension (SSFDC Forum) 6.23 General Purpose Logging feature set The General Purpose Logging feature set provides a mechanism for accessing logs in a device. These logs are associated with specific feature sets such as SMART. Support of the individual logs is determined by support of the associated feature set. If the device supports a particular feature set, support for any associated log(s) is mandatory. Support for the General Purpose Logging feature set shall not be disabled. If the feature set associated with a requested log is disabled, the device shall return command abort. If the General Purpose Logging feature set is implemented, the following commands shall be supported: -- READ LOG EXT -- WRITE LOG EXT 7 Interface register definitions and descriptions 7.1 Device addressing considerations In traditional controller operation, only the selected device receives commands from the host following selection. In this standard, when a register is written the value is written to the register of both devices. The host discriminates between the two by using the DEV bit in the Device register. Data is transferred in parallel either to or from host memory to the device’s buffer under the direction of commands previously transferred from the host. The device performs all of the operations necessary to properly write data to, or read data from, the media. Data read from the media is stored in the device’s buffer pending transfer to the host memory and data is transferred from the host memory to the device’s buffer to be written to the media. The devices using this interface shall be programmed by the host computer to perform commands and return status to the host at command completion. When two devices are connected on the cable, commands are written in parallel to both devices, and for all except the EXECUTE DEVICE DIAGNOSTIC command, only the selected device executes the command. Both devices shall execute an EXECUTE DEVICE DIAGNOSTIC command regardless of which device is selected, and Device 1 shall post status to Device 0 via PDIAG-. Page 56 T13/1410D revision 3b When the Device Control register is written, both devices respond to the write regardless of which device is selected (see 7.8.5). Devices are selected by the DEV bit in the Device register (see 7.7). When the DEV bit is cleared to zero, Device 0 is selected. When the DEV bit is set to one, Device 1 is selected. When two devices are connected to the cable, one shall be set as Device 0 and the other as Device 1. For register access protocols and timing see clauses 9 and 10. When the host initiates a register or Data port read or write cycle by asserting then negating either DIOW- or DIOR-, the device(s) shall determine how to respond and what action(s), if any, are to be taken. The following text and tables describe this decision process. The device response begins with these steps: 1) For a device that is not in Sleep mode, see Table 14. 2) If DMACK- is asserted, a device in Sleep mode shall ignore all DIOW-/DIOR- activity. If DMACK- is not asserted, a device in Sleep mode shall respond as described in Table 19 if the device does not implement the PACKET Command feature set or Table 20 if the device does implement the PACKET Command feature set. Table 14 − Device response to DIOW-/DIORIs the device selected? Is DMACK- asserted? Action/Response (see note 1) No No See Table 15 No Yes DIOW-/DIOR- cycle is ignored (possible DMA transfer with the other device) Yes No See Table 16 Yes Yes See Table 17 (see note 2) Device 1 is selected but there No See Table 18 and 9.16.1 is no Device 1 and Device 0 responds for Device 1. Device 1 is selected but there Yes DIOW-/DIOR- cycle is ignored is no Device 1 and Device 0 (possible malfunction of the host) responds for Device 1. NOTES − 1 Device selected means that the DEV bit in the Device register matches the logical device number of the device. 2 Applicable only to Multiword DMA, not applicable to Ultra DMA. Page 57 T13/1410D revision 3b Table 15 − Device is not selected, DMACK- is not asserted CS0N N N N CS1N A A A DA2 X N A A DA1 X X N A DA0 X X X N DIOxX X X W DMARQ Z Z Z Z BSY X X X X DRQ X X X X N N A A A A A A A N N N N N A A N N N N N A A N N N N A N A N A A A N R X X W W R W Z Z Z Z Z Z Z X X X 0 1 X 0 X X X X X X X A A A A A A A A A A A A N N N N N N N N N N N N N N N N N A A A A A A A A A A A A N N N N N N A N N A A A N N N A A A N W R W W R W W R W W R W Z Z Z Z Z Z Z Z Z Z Z Z 1 X 0 1 X 0 1 X 0 1 X 0 X X X X X X X X X X X X A A A N N N A A A A A A N N A W R W Z Z Z 1 X 0 X X X Device Response DIOW-/DIOR- cycle is ignored. Place new data into the Device Control register and respond to the new values of the nIEN and SRST bits. DIOW-/DIOR- cycle is ignored. Place new data into the Feature register. DIOW-/DIOR- cycle is ignored. Place new data into the Sector Count register. DIOW-/DIOR- cycle is ignored. Place new data into the LBA Low register. DIOW-/DIOR- cycle is ignored. Place new data into the LBA Mid register. DIOW-/DIOR- cycle is ignored. Place new data into the LBA High register. DIOW-/DIOR- cycle is ignored. Place new data into the Device register. Respond to the new value of the DEV bit. DIOW-/DIOR- cycle is ignored. Place new data into the Command register. Do not respond unless the command is EXECUTE DEVICE DIAGNOSTICS. DIOW-/DIOR- cycle is ignored. A N A A A W Z 1 X A N A A A R Z X X A A X X X X Z X X DIOW-/DIOR- cycle is ignored. NOTE − 1. Except in the DIOx- column, A = asserted, N = negated, Z = released, X = don’t care. 2. In the DIOx- column, R = DIOR- asserted, W = DIOW- asserted, X = either DIOR- or DIOW- is asserted. 3. Device is selected if the DEV bit in the Device register is the logical device number of the device. Page 58 T13/1410D revision 3b Table 16 − Device is selected, DMACK- is not asserted CS0N N N N CS1N A A A DA2 X N A A DA1 X X N A DA0 X X X N DIOxX X X W DMARQ X X X X BSY X X X X DRQ X X X X N A A A N R X X X N A A A N N A N N A N N A N N X X X X X X X 0 0 X 0 1 A N N N N X X 1 X A A N N N N N N A A W W X X 0 0 0 1 A N N N A W X 1 X A N N N A R X 0 X A N N N A R X 1 X A N N A N W X 0 0 A N N A N W X 0 1 A N N A N W X 1 X A N N A N R X 0 X A N N A N R X 1 X A A N N N N A A A A W W X X 0 0 0 1 A N N A A W X 1 X A N N A A R X 0 X A N N A A R X 1 X A A N N A A N N N N W W X X 0 0 0 1 A N A N N W X 1 X A N A N N R X 0 X A N A N N R X 1 X A N A N A W X 0 0 Device Response DIOW-/DIOR- cycle is ignored. Place new data into the Device Control register and respond to the new values of the nIEN and SRST bits. Place Status register contents on the data bus (do not change the Interrupt Pending state). DIOW-/DIOR- cycle is ignored. PIO data transfer for this device, a 16-bit data word is transferred via the Data register. Result of DIOW-/DIOR- cycle is indeterminate. Place new data into the Features register. DIOW- is ignored, this is a malfunction of the host. Result of DIOW-/DIOR- cycle is indeterminate. Place the contents of the Error register on the data bus. Place the contents of the Status register on the data bus. Place new data into the Sector Count register. DIOW- is ignored, this is a malfunction of the host. Result of DIOW-/DIOR- cycle is indeterminate. Place the contents of the Sector Count register on the data bus. Place the contents of the Status register on the data bus. Place new data into the LBA Low register. DIOW- is ignored, this is a malfunction of the host. Result of DIOW-/DIOR- cycle is indeterminate. Place the contents of the LBA Low register on the data bus. Place the contents of the Status register on the data bus. Place new data into the LBA Mid register. DIOW- is ignored, this is a malfunction of the host. Result of DIOW-/DIOR- cycle is indeterminate. Place the contents of the LBA Mid register on the data bus. Place the contents of the Status register on the data bus. Place new data into the LBA High register. (continued) Page 59 T13/1410D revision 3b Table 16 − Device is selected, DMACK- is not asserted (continued) CS0A CS1N DA2 A DA1 N DA0 A DIOxW DMARQ X BSY 0 DRQ 1 A N A N A W X 1 X A N A N A R X 0 X A N A N A R X 1 X A N A A N W X 0 0 A N A A N W X 0 1 A N A A N W X 1 X A N A A N R X 0 X A N A A N R X 1 X A N A A A W X 0 0 A A N N A A A A A A W W X X 0 1 1 X A N A A A R X X X Device Response DIOW- is ignored, this is a malfunction of the host. Result of DIOW-/DIOR- cycle is indeterminate. Place the contents of the LBA High register on the data bus. Place the contents of the Status register on the data bus. Place new data into the Device register. Respond to the new value of the DEV bit. DIOW- is ignored, this is a malfunction of the host. Result of DIOW-/DIOR- cycle is indeterminate. Place the contents of the Device register on the data bus. Place the contents of the Status register on the data bus. Place new data into the Command register and respond to the new command (exit the interrupt pending State). Result of DIOW-/DIOR- cycle is indeterminate, unless the device supports DEVICE RESET. If the device supports the DEVICE RESET command, exit the interrupt pending state. Place contents of Status register on the data bus and exit the interrupt pending state. DIOW-/DIOR- cycle is ignored. A A X X X X X X X NOTE − 1. Except in the DIOx- column, A = asserted, N = negated, X = don’t care. 2. In the DIOx- column, R = DIOR- asserted, W = DIOW- asserted, X = either DIOR- or DIOW- is asserted. 3. Device is selected if the DEV bit in the Device register is the logical device number of the device. 4. For devices implementing the 48-bit Address feature set, the HOB bit in the Device Control register defines whether the current or previous content of the registers is placed on DD(7:0). (concluded) Table 17 − Device is selected, DMACK- is asserted (for Multiword DMA only) CS0N N CS1N N DA2 X X DA1 X X DA0 X X DIOxX X DMARQ N N BSY 1 0 DRQ X X Device Response This could be the final DIOW-/DIOR- of a Multiword DMA transfer burst, or a possible malfunction of the host that is ignored. DMA transfer for this device, a 16-bit word of data is transferred via the Data Port. DIOW-/DIOR- cycle is ignored (possible malfunction of the host). N N X X X X A 1 X N N X X X X A 0 1 X A X X X X X X X A X X X X X X X X NOTE − 1. Except in the DIOx- column, A = asserted, N = negated, Z = released, X = don’t care. 2. In the DIOx- column, R = DIOR- asserted, W = DIOW- asserted, X = either DIOR- or DIOW- is asserted. 3. Device is selected if the DEV bit in the Device register is the logical device number of the device. Page 60 T13/1410D revision 3b Table 18 − Device 1 is selected and Device 0 is responding for Device 1 CS0N N N N CS1N A A A DA2 X N A A DA1 X X N A DA0 X X X N DIOxX X X W DMARQ Z Z X X BSY 0 0 0 0 DRQ 0 0 0 0 N N A A A A N N A A N N A A N N N A N A R X X W X X X X 0 0 0 0 0 0 0 0 A N N N A R X 0 0 A N N A N W X 0 0 A N N A N R X 0 0 A N N A A W X 0 0 A N N A A R X 0 0 A N A N N W X 0 0 A N A N N R X 0 0 A N A N A W X 0 0 A N A N A R X 0 0 A N A A N W X 0 0 Device Response DIOW-/DIOR- cycle is ignored. Place new data into the Device 0 Device Control register and respond to the new values of the nIEN and SRST bits. Place 00H on the data bus. DIOW-/DIOR- cycle is ignored. Place new data into the Device 0 Feature register. Place the contents of the Device 0 Error register on the data bus. Place new data into Device 0 Sector Count register. If the device does not implement the PACKET Command feature set, the device shall place the contents of the Device 0 Sector Count register on the data bus. If the device implements the PACKET Command feature set, the device shall place 00h on the data bus. Place new data into Device 0 LBA Low register. If the device does not implement the PACKET Command feature set, the device shall place the contents of the Device 0 LBA Low register on the data bus. If the device implements the PACKET Command feature set, the device shall place 00h on the data bus. Place new data into Device 0 LBA Mid register. If the device does not implement the PACKET Command feature set, the device shall place the contents of the Device 0 LBA Mid register on the data bus. If the device implements the PACKET Command feature set, the device shall place 00h on the data bus. Place new data into Device 0 LBA High register. If the device does not implement the PACKET Command feature set, the device shall place the contents of the Device 0 LBA High register on the data bus. If the device implements the PACKET Command feature set, the device shall place 00h on the data bus. Place new data into the Device 0 Device register. Respond to the new value of the DEV bit. (continued) Page 61 T13/1410D revision 3b Table 18 − Device 1 is selected and Device 0 is responding for Device 1 (continued) CS0A CS1N DA2 A DA1 A DA0 N DIOxR DMARQ X BSY 0 DRQ 0 A N A A A W X 0 0 Device Response If the device does not implement the PACKET Command feature set, the device shall place the contents of the Device 0 Device register, with the DEV bit set to one, on the data bus. If the device implements the PACKET Command feature set, the device shall place 00h on the data bus. Place new data into the Command register of Device 0. Do not respond unless the command is EXECUTE DEVICE DIAGNOSTICS. Place 00H on the data bus. DIOW-/DIOR- cycle is ignored. A N A A A R X 0 0 A A X X X X X 0 0 NOTE − 1. Except in the DIOx- column, A = asserted, N = negated, Z = released, X = don’t care. 2. In the DIOx- column, R = DIOR- asserted, W = DIOW- asserted, X = either DIOR- or DIOW- is asserted. 3. Device is selected if the DEV bit in the Device register is the logical device number of the device. (concluded) Table 19 − Device is in Sleep mode, DEVICE RESET is not implemented, DMACK- is not asserted CS0N N N N CS1N A A A DA2 X N A A DA1 X X N A DA0 X X X N DIOxX X X W DMARQ Z Z Z Z BSY X X X X DRQ X X X X Device Response DIOW-/DIOR- cycle is ignored. Place new data into the Device Control register SRST bit and respond only if SRST bit is 1. DIOW-/DIOR- cycle is ignored. N A A A N R Z X X N A A A A X Z X X A N X X X X Z X X A A X X X X Z X X NOTE − 1. Except in the DIOx- column, A = asserted, N = negated, Z = released, X = don’t care. 2. In the DIOx- column, R = DIOR- asserted, W = DIOW- asserted, X = either DIOR- or DIOW- is asserted. 3. Device is selected if the DEV bit in the Device register is the logical device number of the device. Page 62 T13/1410D revision 3b Table 20 − Device is in Sleep mode, DEVICE RESET is implemented, DMACK- is not asserted CS0N N N N CS1N A A A DA2 X N A A DA1 X X N A DA0 X X X N DIOxX X X W DMARQ Z Z Z Z BSY X X X X DRQ X X X X N N A A A A A N N N A A N A A A A X N A N A X X N R X X X W Z Z Z Z Z X X X X X X X X X X A A N N A A A A N A R W Z Z X X X X Device Response DIOW-/DIOR- cycle is ignored. Place new data into the Device Control register SRST bit and respond only if SRST bit is 1. DIOW-/DIOR- cycle is ignored. Place new data into the Device register DEV bit. DIOR- cycle is ignored. DIOW- cycle is ignored unless the device is selected and the command is DEVICE RESET. DIOR- cycle is ignored. DIOW-/DIOR- cycle is ignored A N A A A R Z X X A A X X X X Z X X NOTE − 1. Except in the DIOx- column, A = asserted, N = negated, Z = released, X = don’t care. 2. In the DIOx- column, R = DIOR- asserted, W = DIOW- asserted, X = either DIOR- or DIOW- is asserted. 3. Device is selected if the DEV bit in the Device register is the logical device number of the device. 7.2 I/O register descriptions The Command Block registers are used for sending commands to the device or posting status from the device. These registers include the LBA High, LBA Mid, Device, Sector Count, Command, Status, Features, Error, and Data registers. The Control Block registers are used for device control and to post alternate status. These registers include the Device Control and Alternate Status registers. Each register description in the following clauses contain the following format: Address – the CS and DA address of the register. Direction –specifies if the register is read/write, read only, or write only from the host. Access restrictions –specifies when the register may be accessed. Effect –specifies the effect of accessing the register. Functional description – describes the function of the register. Field/bit description – describes the content of the register. 7.3 Alternate Status register 7.3.1 Address CS1 CS0 DA2 DA1 A N A A A = asserted, N = negated DA0 N Page 63 T13/1410D revision 3b 7.3.2 Direction This register is read only. If this address is written to by the host, the Device Control register is written. 7.3.3 Access restrictions When the BSY bit is set to one, the other bits in this register shall not be used. The contents of this register are not valid while the device is in Sleep mode. 7.3.4 Effect Reading this register shall not clear a pending interrupt. 7.3.5 Functional description This register contains the same information as the Status register in the Command Block. See 7.15 for definitions of the bits in this register. 7.4 Command register 7.4.1 Address CS1 CS0 DA2 DA1 N A A A A = asserted, N = negated DA0 A 7.4.2 Direction This register is write only. If this address is read by the host, the Status register is read. 7.4.3 Access restrictions For all commands except DEVICE RESET, this register shall only be written when BSY and DRQ are both cleared to zero and DMACK- is not asserted. If written when BSY or DRQ is set to one, the results of writing the Command register are indeterminate except for the DEVICE RESET command. For a device in the Sleep mode, writing of the Command register shall be ignored except for writing of the DEVICE RESET command to a device that implements the PACKET Command feature set. 7.4.4 Effect Command processing begins when this register is written. The content of the Command Block registers become parameters of the command when this register is written. Writing this register clears any pending interrupt condition. 7.4.5 Functional description This register contains the command code being sent to the device. Command execution begins immediately after this register is written. The executable commands, the command codes, and the necessary parameters for each command are summarized in the tables in informative annex E. Page 64 T13/1410D revision 3b 7.4.6 Field/bit description 7 6 5 4 3 Command Code 2 1 0 7.5 Data port 7.5.1 Address When DMACK- is asserted, CS0- and CS1- shall be negated and transfers shall be 16 bits wide. CS1 CS0 DA2 DA1 DA0 N N X X X A = asserted, N = negated, X = don’t care 7.5.2 Direction This port is read/write. 7.5.3 Access restrictions This port shall be accessed for host DMA data transfers only when DMACK- and DMARQ are asserted. 7.5.4 Effect DMA data-out transfers are processed by a series of reads to this port, each read transferring the data that follows the previous read. DMA data-in transfers are processed by a series of writes to this port, each write transferring the data that follows the previous write. The results of a read during a DMA in or a write during a DMA out are indeterminate. 7.5.5 Functional description The data port is 16-bits in width. 7.5.6 Field/bit description 15 14 13 7 6 5 12 11 Data(15:8) 4 3 Data(7:0) 10 9 8 2 1 0 7.6 Data register 7.6.1 Address CS1 CS0 DA2 DA1 N A N N A = asserted, N = negated DA0 N Page 65 T13/1410D revision 3b 7.6.2 Direction This register is read/write. 7.6.3 Access restrictions This register shall be accessed for host PIO data transfer only when DRQ is set to one and DMACK- is not asserted. The contents of this register are not valid while a device is in the Sleep mode. 7.6.4 Effect PIO data-out transfers are processed by a series of reads to this register, each read transferring the data that follows the previous read. PIO data-in transfers are processed by a series of writes to this register, each write transferring the data that follows the previous write. The results of a read during a PIO in or a write during a PIO out are indeterminate. 7.6.5 Functional description The data register is 16 bits wide. When a CFA device is in 8-bit PIO data transfer mode this register is 8 bits wide using only DD7 to DD0. 7.6.6 Field/bit description 15 14 13 7 6 5 12 11 Data(15:8) 4 3 Data(7:0) 10 9 8 2 1 0 7.7 Device register 7.7.1 Address CS1 CS0 DA2 DA1 N A A A A = asserted, N = negated DA0 N 7.7.2 Direction This register is read/write. 7.7.3 Access restrictions This register shall be written only when both BSY and DRQ are cleared to zero and DMACK- is not asserted. The contents of this register are valid only when BSY is cleared to zero. If this register is written when BSY or DRQ is set to one, the result is indeterminate. For devices not implementing the PACKET Command feature set, the contents of this register are not valid while a device is in the Sleep mode. For devices implementing the PACKET Command feature set, the contents of this register are valid while the device is in Sleep mode. 7.7.4 Effect The DEV bit becomes effective when this register is written by the host or the signature is set by the device. All other bits in this register become a command parameter when the Command register is written. Page 66 T13/1410D revision 3b 7.7.5 Functional description Bit 4, DEV, in this register selects the device. Other bits in this register are command dependent (see clause 8). 7.7.6 Field/bit description 7 Obsolete − 6 # 5 Obsolete 4 DEV 3 # 2 # 1 # 0 # Obsolete – These bits are obsolete. NOTE − Some hosts set these bits to one. Devices shall ignore these bits. − − # - The content of these bits is command dependent (see clause 8). DEV – Device select. Cleared to zero selects Device 0. Set to one selects Device 1. 7.8 Device Control register 7.8.1 Address CS1 CS0 DA2 DA1 A N A A A = asserted, N = negated DA0 N 7.8.2 Direction This register is write only. If this address is read by the host, the Alternate Status register is read. 7.8.3 Access restrictions This register shall only be written when DMACK- is not asserted. 7.8.4 Effectiveness The content of this register shall take effect when written. 7.8.5 Functional description This register allows a host to software reset attached devices and to enable or disable the assertion of the INTRQ signal by a selected device. When the Device Control register is written, both devices respond to the write regardless of which device is selected. When the SRST bit is set to one, both devices shall perform the software reset protocol. The device shall respond to the SRST bit when in the SLEEP mode. 7.8.6 Field/bit description 7 HOB 6 r 5 r 4 r 3 r 2 SRST 1 nIEN 0 0 − HOB (high order byte) is defined by the 48-bit Address feature set (see 6.20). A write to any Command Block register shall clear the HOB bit to zero. − Bits (6:3) are reserved. − SRST is the host software reset bit (see 9.2). Page 67 T13/1410D revision 3b − nIEN is the enable bit for the device assertion of INTRQ to the host. When the nIEN bit is cleared to zero, and the device is selected, INTRQ shall be enabled through a driver capable of a high-impedance output state and shall be asserted or negated by the device as appropriate. When the nIEN bit is set to one, or the device is not selected, the device shall release the INTRQ signal. − Bit 0 shall be cleared to zero. 7.9 Error register 7.9.1 Address CS1 CS0 DA2 DA1 N A N N A = asserted, N = negated DA0 A 7.9.2 Direction This register is read only. If this address is written to by the host, the Features register is written. 7.9.3 Access restrictions The contents of this register shall be valid when BSY and DRQ are cleared to zero and ERR is set to one. The contents of this register shall be valid upon completion of power-on, or after a hardware or software reset, or after command completion of an EXECUTE DEVICE DIAGNOSTICS or DEVICE RESET command. The contents of this register are not valid while a device is in the Sleep mode. 7.9.4 Effect None. 7.9.5 Functional description At command completion of any command except EXECUTE DEVICE DIAGNOSTIC or DEVICE RESET, the contents of this register are valid when the ERR bit is set to one in the Status register. Following a power-on, a hardware or software reset (see 9.1), or command completion of an EXECUTE DEVICE DIAGNOSTIC (see 8.11) or DEVICE RESET command (see 8.9), this register contains a diagnostic code . 7.9.6 Field/bit description 7 # 6 # 5 # 4 # 3 # 2 ABRT 1 # 0 # − Bit 2 – ABRT (command aborted) is set to one to indicate the requested command has been command aborted because the command code or a command parameter is invalid, the command is not supported, a prerequisite for the command has not been met, or some other error has occurred. − # -The content of this bit is command dependent (see clause 8). Page 68 T13/1410D revision 3b 7.10 Features register 7.10.1 Address CS1 CS0 DA2 DA1 N A N N A = asserted, N = negated DA0 A 7.10.2 Direction This register is write only. If this address is read by the host, the Error register is read. 7.10.3 Access restrictions This register shall be written only when BSY and DRQ equal zero and DMACK- is not asserted. If this register is written when BSY or DRQ is set to one, the result is indeterminate. 7.10.4 Effect The content of this register becomes a command parameter when the Command register is written. 7.10.5 Functional description The content of this register is command dependent (see clause 8). 7.11 LBA High register 7.11.1 Address CS1 CS0 DA2 DA1 N A A N A = asserted, N = negated DA0 A 7.11.2 Direction This register is read/write. 7.11.3 Access restrictions This register shall be written only when both BSY and DRQ are cleared to zero and DMACK- is not asserted. The contents of this register are valid only when BSY and DRQ are cleared to zero. If this register is written when BSY or DRQ is set to one, the result is indeterminate. The contents of this register are not valid while a device is in the Sleep mode. 7.11.4 Effect The content of this register becomes a command parameter when the Command register is written. 7.11.5 Functional description The content of this register is command dependent (see clause 8). Page 69 T13/1410D revision 3b 7.12 LBA Low register 7.12.1 Address CS1 CS0 DA2 DA1 N A N A A = asserted, N = negated DA0 A 7.12.2 Direction This register is read/write. 7.12.3 Access restrictions This register shall be written only when both BSY and DRQ are cleared to zero and DMACK- is not asserted. The contents of this register are valid only when both BSY and DRQ are cleared to zero. If this register is written when BSY or DRQ is set to one, the result is indeterminate. The contents of this register are not valid while a device is in the Sleep mode. 7.12.4 Effect The content of this register becomes a command parameter when the Command register is written. 7.12.5 Functional description The content of this register is command dependent (see clause 8). 7.13 LBA Mid register 7.13.1 Address CS1 CS0 DA2 DA1 N A A N A = asserted, N = negated DA0 N 7.13.2 Direction This register is read/write. 7.13.3 Access restrictions This register shall be written only when both BSY and DRQ are cleared to zero and DMACK- is not asserted. The contents of this register are valid only when BSY and DRQ are cleared to zero. If this register is written when BSY or DRQ is set to one, the result is indeterminate. The contents of this register are not valid while a device is in the Sleep mode. 7.13.4 Effect The content of this register becomes a command parameter when the Command register is written. 7.13.5 Functional description The content of this register is command dependent (see clause 8). Page 70 T13/1410D revision 3b 7.14 Sector Count register 7.14.1 Address CS1 CS0 DA2 DA1 N A N A A = asserted, N = negated DA0 N 7.14.2 Direction This register is read/write. 7.14.3 Access restrictions This register shall be written only when both BSY and DRQ are cleared to zero and DMACK- is not asserted. The contents of this register are valid only when both BSY and DRQ are cleared to zero. If this register is written when BSY or DRQ is set to one, the result is indeterminate. The contents of this register are not valid while a device is in the Sleep mode. 7.14.4 Effect The content of this register becomes a command parameter when the Command register is written. 7.14.5 Functional description The content of this register is command dependent (see clause 8). 7.15 Status register 7.15.1 Address CS1 CS0 DA2 DA1 N A A A A = asserted, N = negated DA0 A 7.15.2 Direction This register is read only. If this address is written to by the host, the Command register is written. 7.15.3 Access restrictions The contents of this register, except for BSY, shall be ignored when BSY is set to one. The contents of this register are not valid while a device is in the Sleep mode. 7.15.4 Effect Reading this register when an interrupt is pending causes the interrupt pending to be cleared (see 5.2.9). The host should not read the Status register when an interrupt is expected as this may clear the interrupt pending before the INTRQ can be recognized by the host. 7.15.5 Functional description This register contains the device status. The contents of this register are updated to reflect the current state of the device. Page 71 T13/1410D revision 3b 7.15.6 Field/bit description 7 BSY 6 DRDY 5 DF 4 # 3 DRQ 2 1 Obsolete Obsolete 0 ERR 7.15.6.1 BSY (Busy) BSY is set to one to indicate that the device is busy. After the host has written the Command register the device shall have either the BSY bit set to one, or the DRQ bit set to one, until command completion or the device has performed a bus release for an overlapped command. The BSY bit shall be set to one by the device only when one of the following events occurs: 1) after either the negation of RESET- or the setting of the SRST bit to one in the Device Control register; 2) after writing the Command register if the DRQ bit is not set to one; 3) between blocks of a data transfer during PIO data-in commands before the DRQ bit is cleared to zero; 4) after the transfer of a data block during PIO data-out commands before the DRQ bit is cleared to zero; 5) during the data transfer of DMA commands either the BSY bit, the DRQ bit, or both shall be set to one; 6) after the command packet is received during the execution of a PACKET command. NOTE − The BSY bit may be set to one and then cleared to zero so quickly, that host detection of the BSY bit being set to one is not certain. When BSY is set to one, the device has control of the Command Block Registers and: 1) a write to a Command Block register by the host shall cause indeterminate behavior except for writing DEVICE RESET command; 2) a read from a Command Block register by the host may yield invalid contents except for the BSY bit itself. The BSY bit shall be cleared to zero by the device: 1) 2) 3) 4) after setting DRQ to one to indicate the device is ready to transfer data; at command completion; upon releasing the bus for an overlapped command; when the device is ready to accept commands that do not require DRDY during a poweron, hardware or software reset. When BSY is cleared to zero, the host has control of the Command Block registers, the device shall: 1) 2) 3) 4) not set DRQ to one; not change ERR bit; not change the content of any other Command Block register; set the SERVbit to one when ready to continue an overlapped command that has been bus released. 5) clear the DSC bit to zero when an action that uses this bit is completed. Page 72 T13/1410D revision 3b 7.15.6.2 DRDY (Device ready) The DRDY bit shall be cleared to zero by the device: 1) when power-on, hardware, or software reset or DEVICE RESET or EXECUTE DEVICE DIAGNOSTIC commands for devices implementing the PACKET command feature set. When the DRDY bit is cleared to zero, the device shall accept and attempt to execute commands as described in clause 8. The DRDY bit shall be set to one by the device: 1) when the device is capable of accepting all commands for devices not implementing the PACKET command feature set; 2) prior to command completion except the DEVICE RESET or EXECUTE DEVICE DIAGNOSTIC command for devices implementing the PACKET feature set. When the DRDY bit is set to one: 1) the device shall accept and attempt to execute all implemented commands; 2) devices that implement the Power Management feature set shall maintain the DRDY bit set to one when they are in the Idle or Standby modes. 7.15.6.3 DF (Device fault) Device Fault is implemented by many but not all commands (see clause 8). A Device Fault is any event that prevents the device from completing a command that is not the result of an error described in the Error register. Recovery from a Device Fault is device specific. 7.15.6.4 Command dependent The use of bits marked with # are command dependent (see clause 8). Bit 4 was formerly the DSC (Device Seek Complete) bit. 7.15.6.5 DRQ (Data request) DRQ indicates that the device is ready to transfer data between the host and the device. After the host has written the Command register the device shall either set the BSY bit to one or the DRQ bit to one, until command completion or the device has performed a bus release for an overlapped command. The DRQ bit shall be set to one by the device: 1) when BSY is set to one and data is ready for PIO transfer; 2) during the data transfer of DMA commands either the BSY bit, the DRQ bit, or both shall be set to one. When the DRQ bit is set to one, the host may: 1) transfer data via PIO mode; 2) transfer data via DMA mode if DMARQ and DMACK- are asserted. The DRQ bit shall be cleared to zero by the device: 1) when the last word of the data transfer occurs; 2) when the last word of the command packet transfer occurs for a PACKET command. Page 73 T13/1410D revision 3b When the DRQ bit is cleared to zero, the host may: 1) transfer data via DMA mode if DMARQ and DMACK- are asserted and BSY is set to one. 7.15.6.6 Obsolete bits Some bits in this register were defined in previous ATA standards but have been declared obsolete in this standard. 7.15.6.7 ERR (Error) ERR indicates that an error occurred during execution of the previous command. For the PACKET and SERVICE commands, this bit is defined as CHK and indicates that an exception condition exists (see 2.1). The ERR bit shall be set to one by the device: 1) when BSY or DRQ is set to one and an error occurs in the executing command. When the ERR bit is set to one: 1) the bits in the Error register shall be valid; 2) the device shall not change the contents of the following registers until a new command has been accepted, the SRST bit is set to one or RESET- is asserted: − Error register; − LBA High/Mid/Low registers; − Sector Count register; − Device register. The ERR bit shall be cleared to zero by the device: 1) when a new command is written to the Command register; 2) when the SRST bit is set to one; 3) when the RESET- signal is asserted. When the ERR bit is cleared to zero at the end of a command: 1) the content of the Error register shall be ignored by the host. 8 Command descriptions Commands are issued to the device by loading the required registers in the command block with the needed parameters and then writing the command code to the Command register. Required registers are those indicated by a specific content in the Inputs table for the command, i.e., not noted as na or obs. Each command description in the following clauses contains the following subclauses: Command code –Specifies the command code for this command. Feature set –Specifies feature set and if the command is mandatory or optional. Protocol –Specifies which protocol is used by the command (see clause 9). Inputs – Describes the Command Block register data that the host shall supply. Page 74 T13/1410D revision 3b Register 7 6 5 4 3 2 1 0 Features Sector Count LBA Low LBA Mid LBA High Device Command Command Code NOTE − na specifies the content of a bit or field is not applicable to the particular command. Obs specifies that the use of this bit is obsolete. Normal outputs – Describes the Command Block register data returned by the device at the end of a command. Register 7 6 5 4 3 2 1 0 Error Sector Count LBA Low LBA Mid LBA High Device Status NOTE − na indicates the content of a bit or field is not applicable to the particular command. Obs indicates that the use of this bit is obsolete. Error outputs – Describes the Command Block register data that shall be returned by the device at command completion with an unrecoverable error. Register 7 6 5 4 3 2 1 0 Error Sector Count LBA Low LBA Mid LBA High Device Status NOTE − na indicates the content of a bit or field is not applicable to the particular command. Obs indicates that the use of this bit is obsolete. Prerequisites – Any prerequisite commands or conditions that shall be met before the command is issued. Description – The description of the command function(s). 8.1 CFA ERASE SECTORS 8.1.1 Command code C0h 8.1.2 Feature set CFA feature set. − If the CFA feature set is implemented this command shall be implemented. Page 75 T13/1410D revision 3b This command code is Vendor Specific for devices not implementing the CFA feature Set. 8.1.3 Protocol Non-data (see 9.4). 8.1.4 Inputs The LBA High, LBA Mid, LBA Low, and Device registers specify the starting sector address to be erased. The Sector Count register specifies the number of sectors to be erased. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs LBA obs 4 3 na Sector count LBA (7:0) LBA (15:8) LBA (23:16) DEV C0h 2 1 0 LBA (27:24) Sector Count – number of sectors to be erased. A value of 00h specifies that 256 sectors are to be erased. LBA Low – starting LBA bits (7:0). LBA Mid – starting LBA bits (15:8). LBA High – starting LBA bits (23:16). Device – the LBA bit shall be set to one to specify the address is an LBA, starting LBA bits (27:24). 8.1.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na na na na na na na ERR na na na na na obs BSY na DRDY obs na DEV na Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. ERR shall be cleared to zero. 8.1.6 Error outputs The device shall return command aborted if the command is not supported. An unrecoverable error encountered during execution of this command results in the termination of the command. The command block registers contain the address of the sector where the first unrecovered error occurred. Page 76 T13/1410D revision 3b Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na obs BSY 6 na na DRDY 5 na obs DF 4 IDNF 3 na na LBA (7:0) LBA (15:8) LBA (23:16) DEV na na 2 ABRT 1 na 0 MED LBA (27:24) na na ERR Error Register – IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. ABRT shall be set to one if the command is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. MED shall be set to one if a media error is detected. LBA Low, LBA Mid, LBA High, Device– shall be written with the address of first unrecoverable error. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. ERR shall be set to one if an Error register bit is set to one. 8.1.7 Prerequisites DRDY set to one. 8.1.8 Description This command pre-erases and conditions from 1 to 256 sectors as specified in the Sector Count register. This command should be issued in advance of a CFA WRITE SECTORS WITHOUT ERASE or a CFA WRITE MULTIPLE WITHOUT ERASE command to increase the execution speed of the write operation. 8.2 CFA REQUEST EXTENDED ERROR CODE 8.2.1 Command code 03h 8.2.2 Feature set CFA feature set. − If the CFA feature set is implemented this command shall be implemented. 8.2.3 Protocol Non-data (see 9.4). Page 77 T13/1410D revision 3b 8.2.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na na obs na obs DEV na 03h 8.2.5 Normal outputs The extended error code written into the Error register is an 8-bit code. Table 21 defines these values. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 obs BSY na DRDY obs na 4 3 Extended error code Vendor specific Vendor specific Vendor specific Vendor specific DEV na na Error register – Extended error code. LBA Low, LBA Mid, LBA High, Device – May contain additional information. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. ERR shall be cleared to zero. Page 78 2 1 Vendor specific na na 0 ERR T13/1410D revision 3b Extended error code 00h 01h 03h 05h 09h 0Bh 0Ch 0D-0Fh 10h 11h 14h 18h 1Dh, 1Eh 1Fh 20h 21h 22-23h 27h 2Fh 30-34h 35h, 36h 37h, 3Eh 38h 39h 3Ah 3Bh 3Ch, 3Fh 3Dh All other values Table 21 − Extended error codes Description No error detected / no additional information Self-test passed Write / Erase failed Self-test or diagnostic failed Miscellaneous error Vendor specific Corrupted media format Vendor specific ID Not Found / ID Error Uncorrectable ECC error ID Not Found Corrected ECC error Vendor specific Data transfer error / command aborted Invalid command Invalid address Vendor specific Write protect violation Address overflow (address too large) Self-test or diagnostic failed Supply or generated voltage out of tolerance Self-test or diagnostic failed Corrupted media format Vendor specific Spare sectors exhausted Corrupted media format Vendor specific Reserved 8.2.6 Error outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT na na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Error Register – ABRT shall be set to one if the command is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. ERR shall be set to one if an Error register bit is set to one. Page 79 T13/1410D revision 3b 8.2.7 Prerequisites DRDY set to one. 8.2.8 Description This command provides an extended error code which identifies the cause of an error condition in more detail than is available with Status and Error register values. The CFA REQUEST EXTENDED ERROR CODE command shall return an extended error code if the previous command completed with an error or a no error detected extended error code if the previous command completed without error. 8.3 CFA TRANSLATE SECTOR 8.3.1 Command code 87h 8.3.2 Feature set CFA feature set. − If the CFA feature set is implemented this command shall be implemented. This command code is Vendor Specific for devices not implementing the CFA feature Set. 8.3.3 Protocol PIO data-in (see 9.5). 8.3.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs LBA obs 4 3 na na LBA (7:0) LBA (15:8) LBA (23:16) DEV 87h 2 LBA (27:24) LBA Low – LBA bits (7:0). LBA Mid – LBA bits (15:8). LBA High – LBA bits (23:16). Device– the LBA bit shall be set to one to specify the address is an LBA, LBA bits (27:24). 8.3.5 Normal outputs A 512 byte information table is transferred to the host. Table 22 defines these values. Page 80 1 0 T13/1410D revision 3b Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 na na 1 0 na ERR 1 na 0 na na ERR na na na na na obs BSY na DRDY obs na DEV na na Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. ERR shall be cleared to zero. Byte 00h 01h 02h 03h 04h 05h 06h 07-12h 13h 14-17h 18h 19h 1Ah 1B-FFh Table 22 − CFA TRANSLATE SECTOR Information Description Obsolete Obsolete Obsolete Obsolete LBA bits (23:16) LBA bits (15:8) LBA bits (7:0) Reserved Sector erased flag (FFh = erased; 00h = not erased) Reserved Sector write cycles count bits (23:16) Sector write cycles count bits (15:8) Sector write cycles count bits (7:0) Reserved 8.3.6 Error outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT na na na na na na obs BSY na DRDY obs DF DEV na na Error Register – ABRT shall be set to one if the command is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. ERR shall be set to one if an Error register bit is set to one. Page 81 T13/1410D revision 3b 8.3.7 Prerequisites DRDY set to one. 8.3.8 Description This command provides information related to a specific sector. The data indicates the erased or not erased status of the sector, and the number of erase and write cycles performed on that sector. Devices may return zero in fields that do not apply or that are not supported by the device. 8.4 CFA WRITE MULTIPLE WITHOUT ERASE 8.4.1 Command code CDh 8.4.2 Feature set CFA feature set. − If the CFA feature set is implemented this command shall be implemented. 8.4.3 Protocol PIO data-out (see 9.6). 8.4.4 Inputs The LBA Mid, LBA High, Device, and LBA Low specify the starting sector address to be written. The Sector Count register specifies the number of sectors to be transferred. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs LBA obs 4 3 na Sector count LBA (7:0) LBA (15:8) LBA (23:16) DEV CDh 2 1 0 LBA (27:24) Sector Count – number of sectors to be transferred. A value of 00h specifies that 256 sectors are to be transferred. LBA Low – starting LBA bits (7:0). LBA Mid – starting LBA bits (15:8). LBA High – starting LBA bits (23:16). Device/Head – the LBA bit shall be set to one to specify the address is an LBA, starting LBA bits (27:24). Page 82 T13/1410D revision 3b 8.4.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na na na na na na na ERR na na na na na obs BSY na DRDY obs na DEV na Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. ERR shall be cleared to zero. 8.4.6 Error outputs The device shall return command aborted if the command is not supported. An unrecoverable error encountered during execution of this command results in the termination of the command. The command block registers contain the address of the sector where the first unrecovered error occurred. The amount of data transferred is indeterminate. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na obs BSY 6 na na DRDY 5 na obs DF 4 IDNF 3 na na LBA (7:0) LBA (15:8) LBA (23:16) DEV na DRQ 2 ABRT 1 na 0 MED LBA (27:24) na na ERR Error Register – IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. ABRT shall be set to one if the command is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. MED shall be set to one if a media error is detected LBA Low, LBA Mid, LBA High, Device– shall be written with the address of first unrecoverable error. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. Page 83 T13/1410D revision 3b 8.4.7 Prerequisites DRDY set to one. If bit 8 of IDENTIFY DEVICE word 59 is cleared to zero, a successful SET MULTIPLE MODE command shall precede a CFA WRITE MULTIPLE WITHOUT ERASE command. 8.4.8 Description This command is similar to the WRITE MULTIPLE command. Interrupts are not generated on every sector, but on the transfer of a block that contains the number of sectors defined by the SET MULTIPLE MODE. Command execution is identical to the WRITE MULTIPLE operation except that the sectors are written without an implied erase operation. The sectors should be pre-erased by a preceding CFA ERASE SECTORS command. 8.5 CFA WRITE SECTORS WITHOUT ERASE 8.5.1 Command code 38h 8.5.2 Feature set CFA feature set. − If the CFA feature set is implemented this command shall be implemented. 8.5.3 Protocol PIO data-out (see 9.6). 8.5.4 Inputs The LBA Mid, LBA High, Device, and LBA Low specify the starting sector address to be written. The Sector Count register specifies the number of sectors to be transferred. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs LBA obs 4 3 na Sector count LBA (7:0) LBA (15:8) LBA (23:16) DEV 38h 2 1 0 LBA (27:24) Sector Count – number of sectors to be transferred. A value of 00h specifies that 256 sectors are to be transferred. LBA Low – starting LBA bits (7:0). LBA Mid – starting LBA bits (15:8). LBA High – starting LBA bits (23:16). Device – the LBA bit shall be set to one to specify the address is an LBA, starting LBA bits (27:24). Page 84 T13/1410D revision 3b 8.5.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na na na na na na na ERR na na na na na obs BSY na DRDY obs na DEV na Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. ERR shall be cleared to zero. 8.5.6 Error outputs The device shall return command aborted if the command is not supported. An unrecoverable error encountered during execution of this command results in the termination of the command. The command block registers contain the address of the sector where the first unrecovered error occurred. The amount of data transferred is indeterminate. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na obs BSY 6 na na DRDY 5 na obs DF 4 IDNF 3 na na LBA (7:0) LBA (15:8) LBA (23:16) DEV na DRQ 2 ABRT 1 na 0 MED LBA (27:24) na na ERR Error Register – IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. ABRT shall be set to one if the command is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. MED shall be set to one if a media error is detected LBA Low, LBA Mid, LBA High, Device– shall be written with the address of first unrecoverable error. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.5.7 Prerequisites DRDY set to one. Page 85 T13/1410D revision 3b 8.5.8 Description This command is similar to the WRITE SECTORS command. Command execution is identical to the WRITE SECTORS operation except that the sectors are written without an implied erase operation. The sectors should be pre-erased by a preceding CFA ERASE SECTORS command. 8.6 CHECK MEDIA CARD TYPE 8.6.1 Command code D1h 8.6.2 Feature set − Mandatory when the Media Card Pass Through Command feature set is implemented 8.6.3 Protocol Non-data (see 9.4) 8.6.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 na 3 2 1 0 ENB na na na na obs na obs DEV na D1h Feature register – ENB shall be set to one to enable the Media Card Pass Through Command feature set. ENB cleared to zero shall disable the Media Card Pass Through Command feature set. NOTE – Power-on, hardware, or software reset disables the Media Card Pass Through Command feature set. Device register – DEV shall specify the selected device. 8.6.5 Normal Outputs The device shall return 55H in Sector Count register and AAH in LBA Low register. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 obs BSY 6 na DRDY Sector Count register – shall contain 55H Page 86 5 obs DF 4 3 na 55h AAh Card specific data Card specific data DEV WP na DRQ 2 0 1 0 Media Type 0 ERR T13/1410D revision 3b LBA Low register – shall contain AAH LBA Mid register – shall contain card-specific data LBA High register – shall contain card-specific data Device register – DEV shall indicate the selected device WP shall be set to one if the device is write protected, WP shall be cleared to zero if the device is not write protected. Media Type shall be set as follows: 001b 010b 011b 100b 000b, 101b-111b SD Memory Card MMC SD IO Card Smart Media card Reserved Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.6.6 Error Outputs If this command is not supported or there is an error in processing this command, the device shall return command aborted. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT DRQ na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Error register – ABRT shall be set to one If the command is not supported or if an error occurred during the execution of the command. Device/Head register – DEV shall indicate the selected device Status register ERR (B0) shall be set to 1 to indicate error occurred BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. Page 87 T13/1410D revision 3b 8.6.7 Description The CHECK MEDIA CARD TYPE command allows the host to determine if the device supports the Media Card Pass Through Command feature set. If the ENB bit in the Features register is set to one, IDENTIFY DEVICE response bit 3 word 87 shall be set to one upon successful command completion. If the adapter supports the Media Card Pass Through Command feature set and the ENB bit of the Features register is set to one, the adapter shall process any further Media Card Pass Through Command feature set commands. If the ENB bit is cleared to zero, the adapter shall not interpret the command codes D2 through D4 as the Media Card Pass Through Command feature set commands. If the adapter does not support the Media Card Pass Through Command feature set, or the host has disabled the Media Card Pass Through Command feature set mode by clearing the ENB bit to zero, the host shall not send any further Media Card Pass Through Command feature set commands to the adapter. 8.7 CHECK POWER MODE 8.7.1 Command code E5h 8.7.2 Feature set Power Management feature set. − This command is mandatory for devices not implementing the PACKET Command feature set. − Power Management feature set is mandatory when power management is not implemented by the PACKET command set implemented by the device. − This command is mandatory when the Power Management feature set is implemented. 8.7.3 Protocol Non-data command (see 9.4). 8.7.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 4 3 2 1 0 na na na na na na na na na obs na Device register – DEV shall specify the selected device. Page 88 5 obs DEV E5h T13/1410D revision 3b 8.7.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 obs BSY na DRDY obs DF 4 3 na Result value na na na DEV na na DRQ 2 1 0 na na na na na ERR Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. Device register – DEV shall indicate the selected device. Sector Count result value – 00h – device is in Standby mode. 80h – device is in Idle mode. FFh – device is in Active mode or Idle mode. 8.7.6 Error outputs The device shall return command aborted if the device does not support the Power Management feature set. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT 1 na 0 na na DRQ na na na na na ERR na na na na obs BSY na DRDY obs DF DEV na Error register – ABRT shall be set to one if Power Management feature set is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. Page 89 T13/1410D revision 3b 8.7.7 Prerequisites DRDY set to one. 8.7.8 Description The CHECK POWER MODE command allows the host to determine the current power mode of the device. The CHECK POWER MODE command shall not cause the device to change power or affect the operation of the Standby timer. 8.8 DEVICE CONFIGURATION Individual Device Configuration Overlay feature set commands are identified by the value placed in the Features register. Table 23 shows these Features register values. Table 23 − Device Configuration Overlay Features register values Value Command C0h DEVICE CONFIGURATION RESTORE C1h DEVICE CONFIGURATION FREEZE LOCK C2h DEVICE CONFIGURATION IDENTIFY C3h DEVICE CONFIGURATION SET 00h-BFh, Reserved C4h-FFh 8.8.1 DEVICE CONFIGURATION RESTORE 8.8.1.1 Command code B1h with a Features register value of C0h. 8.8.1.2 Feature set Device Configuration Overlay feature set. − Mandatory when the Device Configuration Overlay feature set is implemented. 8.8.1.3 Protocol Non-data (see 9.4) 8.8.1.4 Inputs The Features register shall be set to C0h. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 4 3 2 1 C0h na na na na na Device DEV shall specify the selected device. Page 90 5 DEV na B1h 0 T13/1410D revision 3b 8.8.1.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 DRQ na na ERR 3 na 2 ABRT 1 na 0 na na ERR na na na na na obs BSY na DRDY obs DF DEV na na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.8.1.6 Error outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na na na na na obs BSY na DRDY obs DF DEV na na DRQ na Error register ABRT shall be set to one if the device does not support this command, if a Host Protected Area has been set by a SET MAX ADDRESS command, or if DEVICE CONFIGURATION FREEZE LOCK is set. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.8.1.7 Prerequisites DRDY set to one. 8.8.1.8 Description The DEVICE CONFIGURATION RESTORE command disables any setting previously made by a DEVICE CONFIGURATION SET command and returns the content of the IDENTIFY DEVICE or IDENTIFY PACKET Page 91 T13/1410D revision 3b DEVICE command response to the original settings as indicated by the data returned from the execution of a DEVICE CONFIGURATION IDENTIFY command. 8.8.2 DEVICE CONFIGURATION FREEZE LOCK 8.8.2.1 Command code B1h with a Features register value of C1h. 8.8.2.2 Feature set Device Configuration Overlay feature set. − Mandatory when the Device Configuration Overlay feature set is implemented. 8.8.2.3 Protocol Non-data (see 9.4) 8.8.2.4 Inputs The Features register shall be set to C1h. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 1 0 na ERR C1h na na na na na DEV na B1h Device DEV shall specify the selected device. 8.8.2.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. Page 92 2 na na na na na na DRQ na T13/1410D revision 3b 8.8.2.6 Error outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT DRQ na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Error register ABRT shall be set to one if the device does not support this command or the device has executed a previous DEVICE CONFIGURATION FREEZE LOCK command since power-up. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.8.2.7 Prerequisites DRDY set to one. 8.8.2.8 Description The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings. After successful execution of a DEVICE CONFIGURATION FREEZE LOCK command, all DEVICE CONFIGURATION SET, DEVICE CONFIGURATION FREEZE LOCK, DEVICE CONFIGURATION IDENTIFY, and DEVICE CONFIGURATION RESTORE commands shall be aborted by the device. The DEVICE CONFIGURATION FREEZE LOCK condition shall be cleared by a power-down. The DEVICE CONFIGURATION FREEZE LOCK condition shall not be cleared by hardware or software reset. 8.8.3 DEVICE CONFIGURATION IDENTIFY 8.8.3.1 Command code B1h with a Features register value of C2h. 8.8.3.2 Feature set Device Configuration Overlay feature set. − Mandatory when the Device Configuration Overlay feature set is implemented. 8.8.3.3 Protocol PIO data-in (see 9.5) 8.8.3.4 Inputs The Features register shall be set to C2h. Page 93 T13/1410D revision 3b Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 1 0 C2h na na na na na DEV na B1h Device DEV shall specify the selected device. 8.8.3.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 na na na na na obs BSY na DRDY obs DF DEV na na DRQ na na ERR 3 na 2 ABRT 1 na 0 na DRQ na na ERR Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.8.3.6 Error outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na na na na na obs BSY na DRDY obs DF DEV na na Error register ABRT shall be set to one if the device does not support this command or the device has executed a previous DEVICE CONFIGURATION FREEZE LOCK command since power-up. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. Page 94 T13/1410D revision 3b 8.8.3.7 Prerequisites DRDY set to one. 8.8.3.8 Description The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure via PIO data-in transfer. The content of this data structure indicates the selectable commands, modes, and feature sets that the device is capable of supporting. If a DEVICE CONFIGURATION SET command has been issued reducing the capabilities, the response to an IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command will reflect the reduced set of capabilities, while the DEVICE CONFIGURATION IDENTIFY command will reflect the entire set of selectable capabilities. The format of the Device Configuration Overlay data structure is shown in Table 24. Word 0 1 2 3-6 7 8-254 255 Table 24 − Device Configuration Identify data structure Content Data structure revision Multiword DMA modes supported 15-3 Reserved 2 1 = Multiword DMA mode 2 and below are supported 1 1 = Multiword DMA mode 1 and below are supported 0 1 = Multiword DMA mode 0 is supported Ultra DMA modes supported 15-6 Reserved 5 1 = Ultra DMA mode 5 and below are supported 4 1 = Ultra DMA mode 4 and below are supported 3 1 = Ultra DMA mode 3 and below are supported 2 1 = Ultra DMA mode 2 and below are supported 1 1 = Ultra DMA mode 1 and below are supported 0 1 = Ultra DMA mode 0 is supported Maximum LBA Command set/feature set supported 15-9 Reserved 8 1 = 48-bit Addressing feature set supported 7 1 = Host Protected Area feature set supported 6 1 = Automatic acoustic management supported 5 1 = READ/WRITE DMA QUEUED commands supported 4 1 = Power-up in Standby feature set supported 3 1 = Security feature set supported 2 1 = SMART error log supported 1 1 = SMART self-test supported 0 1 = SMART feature set supported Reserved Integrity word 15-8 Checksum 7-0 Signature 8.8.3.8.1 Word 0: Data structure revision Word 0 shall contain the value 0001h. Page 95 T13/1410D revision 3b 8.8.3.8.2 Word 1: Multiword DMA modes supported Word 1 bits (2:0) contain the same information as contained in word 63 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command response (see 8.15.31). Bits (15:3) of word 1 are reserved. 8.8.3.8.3 Word 2: Ultra DMA modes supported Word 2 bits (5:0) contain the same information as contained in word 88 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command response (see 8.15.44). Bits (15:6) of word 2 are reserved. 8.8.3.8.4 Words (6:3): Maximum LBA Words (7:4) define the maximum LBA. This is the highest address accepted by the device in the factory default condition. If no DEVICE CONFIGURATION SET command has been executed modifying the factory default condition, this is the same value as that returned by a READ NATIVE MAX ADDRESS or READ NATIVE MAX ADDRESS EXT command. 8.8.3.8.5 Word 7: Command/features set supported Word 7 bit 0 if set to one indicates that the device is capable of supporting the SMART feature set. Word 7 bit 1 if set to one indicates that the device is capable of supporting SMART self-test including the selftest log. Word 7 bit 2 if set to one indicates that the device is capable of supporting SMART error logging. Word 7 bit 3 if set to one indicates that the device is capable of supporting the Security feature set. Word 7 bit 4 if set to one indicates that the device is capable of supporting the Power-up in Standby feature set. Word 7 bit 5 if set to one indicates that the device is capable of supporting the READ DMA QUEUED and WRITE DMA QUEUED commands. Word 7 bit 6 if set to one indicates that the device is capable of supporting the Automatic Acoustic Management feature set. Word 7 bit 7 if set to one indicates that the device is capable of supporting the Host Protected Area feature set. Word 7 bit 8 if set to one indicates that the device is capable of supporting the 48-bit Addressing feature set. Word 7 bits (15:9) are reserved. 8.8.3.8.6 Words (254:8): Reserved 8.8.3.8.7 Word 255: Integrity word Bits (7:0) of this word shall contain the value A5h. Bits (15:8) of this word shall contain the data structure checksum. The data structure checksum shall be the two’s complement of the sum of all byte in words (154:0) and the byte consisting of bits (7:0) of word 255. Each byte shall be added with unsigned arithmetic, and overflow shall be ignored. The sum of all bytes is zero when the checksum is correct. Page 96 T13/1410D revision 3b 8.8.4 DEVICE CONFIGURATION SET 8.8.4.1 Command code B1h with a Features register value of C3h. 8.8.4.2 Feature set Device Configuration Overlay feature set. − Mandatory when the Device Configuration Overlay feature set is implemented. 8.8.4.3 Protocol PIO data out (see 9.6) 8.8.4.4 Inputs The Features register shall be set to C3h. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 1 0 na ERR C3h na na na na na DEV na B1h Device DEV shall specify the selected device. 8.8.4.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 na na na na na obs BSY na DRDY obs DF DEV na na DRQ na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. Page 97 T13/1410D revision 3b 8.8.4.6 Error outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na obs BSY na DRDY obs DF 4 3 na na Vendor specific Bit location low Bit location high Word location DEV na DRQ 2 ABRT 1 na 0 na na ERR na na Error register ABRT shall be set to one if the device does not support this command, if a DEVICE CONFIGURATION SET command has already modified the original settings as reported by a DEVICE CONFIGURATION IDENTIFY command, if DEVICE CONFIGURATION FREEZE LOCK is set, if any of the bit modification restrictions described in 8.8.4.8 are violated, or if a Host Protected Area has been established by the execution of a SET MAX ADDRESS or SET MAX ADDRESS EXT command. Sector Count – This register may contain a vendor specific value. LBA Low – If the command was aborted because an attempt was made to modify a mode or feature that cannot be modified with the device in its current state, this register shall contain bits (7:0) set in the bit positions that correspond to the bits in the device configuration overlay data structure words 1, 2, or 7 for each mode or feature that cannot be changed. If not, the value shall be 00h. LBA Mid – If the command was aborted because an attempt was made to modify a mode or feature that cannot be modified with the device in its current state, this register shall contain bits (15:8) set in the bit positions that correspond to the bits in the device configuration overlay data structure words 1, 2, or 7 for each mode or feature that cannot be changed. If not, the value shall be 00h. LBA High – If the command was aborted because an attempt was made to modify a bit that cannot be modified with the device in its current state, this register shall contain the offset of the first word encountered that cannot be changed. If an illegal maximum LBA is encountered, the offset of word 3 shall be entered. If a checksum error occurred, the value FFh shall be entered. A value of 00h indicates that the Data Structure Revision was invalid. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.8.4.7 Prerequisites DRDY set to one. 8.8.4.8 Description The DEVICE CONFIGURATION SET command allows a device manufacturer or a personal computer system manufacturer to reduce the set of optional commands, modes, or feature sets supported by a device as indicated by a DEVICE CONFIGURATION IDENTIFY command. The DEVICE CONFIGURATION SET command transfers an overlay that modifies some of the bits set in words 63, 82, 83, 84, and 88 of the Page 98 T13/1410D revision 3b IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command response. When the bits in these words are cleared, the device shall no longer support the indicated command, mode, or feature set. If a bit is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command, no action is taken for that bit. Modifying the maximum LBA of the device also modifies the address value returned by a READ NATIVE MAX ADDRESS or READ NATIVE MAX ADDRESS EXT command. The format of the overlay transmitted by the device is described in Table 25. The restrictions on changing these bits is described in the text following Table 25. If any of the bit modification restrictions described are violated, the device shall return command aborted. Word 0 1 2 3-6 7 8-254 255 Table 25 − Device Configuration Overlay data structure Content Data structure revision Multiword DMA modes supported 15-3 Reserved 2 1 = Multiword DMA mode 2 and below are supported 1 1 = Multiword DMA mode 1 and below are supported 0 1 = Multiword DMA mode 0 is supported Ultra DMA modes supported 15-6 Reserved 5 1 = Ultra DMA mode 5 and below are supported 4 1 = Ultra DMA mode 4 and below are supported 3 1 = Ultra DMA mode 3 and below are supported 2 1 = Ultra DMA mode 2 and below are supported 1 1 = Ultra DMA mode 1 and below are supported 0 1 = Ultra DMA mode 0 is supported Maximum LBA Command set/feature set supported 15-9 Reserved 8 1 = 48-bit Addressing feature set supported 7 1 = Host Protected Area feature set supported 6 1 = Automatic acoustic management supported 5 1 = READ/WRITE DMA QUEUED commands supported 4 1 = Power-up in Standby feature set supported 3 1 = Security feature set supported 2 1 = SMART error log supported 1 1 = SMART self-test supported 0 1 = SMART feature set supported Reserved Integrity word 15-8 Checksum 7-0 Signature 8.8.4.8.1 Word 0: Data structure revision Word 0 shall contain the value 0001h. 8.8.4.8.2 Word 1: Multiword DMA modes supported Word 1 bits (15:3) are reserved. Word 1 bit 2 is cleared to disable support for Multiword DMA mode 2 and has the effect of clearing bit 2 in word 63 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. This bit shall not be cleared to zero if Multiword DMA mode 2 is currently selected. Page 99 T13/1410D revision 3b Word 1 bit 1 is cleared to disable support for Multiword DMA mode 1 and has the effect of clearing bit 1 to zero in word 63 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. This bit shall not be cleared to zero if Multiword DMA mode 2 is supported or Multiword DMA mode 1 or 2 is selected. Word 1 bit 0 shall not be cleared to zero. 8.8.4.8.3 Word 2: Ultra DMA modes supported Word 2 bits (15:6) are reserved. Word 2 bit 5 is cleared to zero to disable support for Ultra DMA mode 5 and has the effect of clearing bit 5 to zero in word 88 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. This bit shall not be cleared to zero if Ultra DMA mode 5 is currently selected. Word 2 bit 4 is cleared to zero to disable support for Ultra DMA mode 4 and has the effect of clearing bit 4 to zero in word 88 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. This bit shall not be cleared to zero if Ultra DMA mode 5 is supported or if Ultra DMA mode 5 or 4 is selected. Word 2 bit 3 is cleared to zero to disable support for Ultra DMA mode 3 and has the effect of clearing bit 3 to zero in word 88 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. This bit shall not be cleared to zero if Ultra DMA mode 5 or 4 is supported or if Ultra DMA mode 5, 4, or 3 is selected. Word 2 bit 2 is cleared to zero to disable support for Ultra DMA mode 2 and has the effect of clearing bit 2 to zero in word 88 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. This bit shall not be cleared to zero if Ultra DMA mode 5, 4, or 3 is supported or if Ultra DMA mode 5, 4, 3, or 2 is selected. Word 2 bit 1 is cleared to zero to disable support for Ultra DMA mode 1 and has the effect of clearing bit 1 to zero in word 88 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. This bit shall not be cleared to zero if Ultra DMA mode 5, 4, 3, or 2 is supported or if Ultra DMA mode 5, 4, 3, 2, or 1 is selected. Word 2 bit 0 is cleared to zero to disable support for Ultra DMA mode 0 and has the effect of clearing bit 0 to zero in word 88 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. This bit shall not be cleared to zero if Ultra DMA mode 5, 4, 3, 2, or 1 is supported or if Ultra DMA mode 5, 4, 3, 2, 1, or 0 is selected. 8.8.4.8.4 Words (6:3): Maximum LBA Words (6:3) define the maximum LBA. This shall be the highest address accepted by the device after execution of the command. When this value is changed, the content of IDENTIFY DEVICE words (61:60) and (103:100) shall be changed as described in the SET MAX ADDRESS and SET MAX ADDRESS EXT command descriptions to reflect the maximum address set with this command. This value shall not be changed and command aborted shall be returned if a Host Protected Area has been established by the execution of a SET MAX ADDRESS or SET MAX ADDRESS EXT command with an address value less than that returned by a READ NATIVE MAX ADDRESS or READ NATIVE MAX ADDRESS EXT command. Any data contained in the Host Protected Area is not affected. 8.8.4.8.5 Word 7: Command/features set supported Word 7 bits (15:9) are reserved. Word 7 bit 8 is cleared to zero to disable support for the 48-bit Addressing feature set and has the effect of clearing bit 10 to zero in word 83 and word 86 and clearing the value in words (103:100) of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. Page 100 T13/1410D revision 3b Word 7 bit 7 is cleared to zero to disable support for the Host Protected Area feature set and has the effect of clearing bit 10 to zero in word 82 and word 85 and clearing bit 8 to zero in word 83 and word 86 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. If a Host Protected Area has been established by use of the SET MAX ADDRESS or SET MAX ADDRESS EXT command, these bits shall not be cleared to zero and the device shall return command aborted. Word 7 bit 6 is cleared to zero to disable for the Automatic Acoustic Management feature set and has the effect of clearing bit 9 to zero in word 83 and word 94 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. Word 7 bit 5 is cleared to zero to disable support for the READ DMA QUEUED and WRITE DMA QUEUED commands and has the effect of clearing bit 1 to zero in word 83 and word 86 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. Word 7 bit 4 is cleared to zero to disable support for the Power-up in Standby feature set and has the effect of clearing bits (6:5) to zero in word 83 and word 86 and clearing the value in word 94 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. If Power-up in Standby has been enabled by a jumper, these bits shall not be cleared. Word 7 bit 3 is cleared to zero to disable support for the Security feature set and has the effect of clearing bit 1 to zero in word 82 and word 85 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. These bits shall not be cleared if the Security feature set has been enabled. Word 7 bit 2 is cleared to zero to disable support for the SMART error logging and has the effect of clearing bit 0 to zero in word 84 and word 87 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. Word 7 bit 1 is cleared to zero to disable support for the SMART self-test and has the effect of clearing bit 1 to zero in word 84 and word 87 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. Word 7 bit 0 is cleared to zero to disable support for the SMART feature set and has the effect of clearing bit 0 to zero in word 82 and word 85 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. If bits (2:1) of word 7 are not cleared to zero or if the SMART feature set has been enabled by use of the SMART ENABLE OPERATIONS command, these bits shall not be cleared and the device shall return command aborted. 8.8.4.8.6 Words (254:8): Reserved 8.8.4.8.7 Word 255: Integrity word Bits (7:0) of this word shall contain the value A5h. Bits (15:8) of this word shall contain the data structure checksum. The data structure checksum shall be the two’s complement of the sum of all byte in words (254:0) and the byte consisting of bits (7:0) of word 255. Each byte shall be added with unsigned arithmetic, and overflow shall be ignored. The sum of all bytes is zero when the checksum is correct. 8.9 DEVICE RESET 8.9.1 Command code 08h 8.9.2 Feature set General feature set − Use prohibited when the PACKET Command feature set is not implemented. − Mandatory when the PACKET Command feature set is implemented. Page 101 T13/1410D revision 3b 8.9.3 Protocol Device reset (see 9.11). 8.9.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na 2 1 0 0 0 0 na na na na na obs na obs DEV 08h Device register – DEV shall specify the selected device. 8.9.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 0 0 0 4 3 Diagnostic results signature signature signature signature DEV 0 see 9.11 Error register – The diagnostic code as described in 8.11 is placed in this register. Sector Count, LBA Low, LBA Mid, LBA High – Signature (see 9.12). Device register – DEV shall indicate the selected device. Status register – see 9.11. 8.9.6 Error outputs If supported, this command shall not end in an error condition. If this command is not supported and the device has the BSY bit or the DRQ bit set to one when the command is written, the results of this command are indeterminate. If this command is not supported and the device has the BSY bit and the DRQ bit cleared to zero when the command is written, the device shall respond with command aborted. 8.9.7 Prerequisites This command shall be accepted when BSY or DRQ is set to one, DRDY is cleared to zero, or DMARQ is asserted. This command shall be accepted when in Sleep mode. 8.9.8 Description The DEVICE RESET command enables the host to reset an individual device without affecting the other device. Page 102 T13/1410D revision 3b 8.10 DOWNLOAD MICROCODE 8.10.1 Command code 92h 8.10.2 Feature set General feature set − Optional for devices not implementing the PACKET Command feature set. − Use prohibited for devices implementing the PACKET Command feature set. 8.10.3 Protocol PIO data-out (see 9.6). 8.10.4 Inputs Bits (3:0) of the Device register shall always be cleared to zero. The LBA High and LBA Mid registers shall be cleared to zero. The LBA Low and Sector Count registers are used together as a 16-bit sector count value. The Feature register specifies the subcommand code. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 obs na 5 4 3 Subcommand code Sector count (low order) Sector count (high order) 00h 00h obs DEV 0 92h 2 1 0 0 0 0 3 2 1 0 na DRQ na na na na na ERR Device register – DEV shall specify the selected device. 8.10.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 na na na na na obs BSY na DRDY obs DF DEV na Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. Page 103 T13/1410D revision 3b 8.10.6 Error outputs The device shall return command aborted if the device does not support this command or did not accept the microcode data. The device shall return command aborted if subcommand code is not a supported value. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT 1 na 0 na na DRQ na na na na na ERR na na na na obs BSY na DRDY obs DF DEV na Error register – ABRT shall be set to one if the device does not support this command or did not accept the microcode data. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.10.7 Prerequisites DRDY set to one. 8.10.8 Description This command enables the host to alter the device’s microcode. The data transferred using the DOWNLOAD MICROCODE command is vendor specific. All transfers shall be an integer multiple of the sector size. The size of the data transfer is determined by the contents of the LBA Low register and the Sector Count register. The LBA Low register shall be used to extend the Sector Count register to create a 16-bit sector count value. The LBA Low register shall be the most significant eight bits and the Sector Count register shall be the least significant eight bits. A value of zero in both the LBA Low register and the Sector Count register shall specify no data is to be transferred. This allows transfer sizes from 0 bytes to 33,553,920 bytes, in 512 byte increments. The Features register shall be used to determine the effect of the DOWNLOAD MICROCODE command. The values for the Features register are: − − 01h – download is for immediate, temporary use. 07h – save downloaded code for immediate and future use. Either or both values may be supported. All other values are reserved. Page 104 T13/1410D revision 3b 8.11 EXECUTE DEVICE DIAGNOSTIC 8.11.1 Command code 90h 8.11.2 Feature set General feature set − Mandatory for all devices. 8.11.3 Protocol Device diagnostic (see 9.10). 8.11.4 Inputs Only the command code (90h). All other registers shall be ignored. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na na na na na na obs na obs na 90h Device register – DEV shall be ignored. 8.11.5 Normal outputs The diagnostic code written into the Error register is an 8-bit code. Table 26 defines these values. The values of the bits in the Error register are not as defined in 7.9.6. Both Device 0 and Device 1 shall provide these register contents. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 Diagnostic code Signature Signature Signature Signature Signature see 9.10 2 1 0 Error register – Diagnostic code. Sector Count, LBA Low, LBA Mid, LBA High, Device registers – device signature (see 9.12). Device register – DEV shall be cleared to zero. Status register – see 9.10. Page 105 T13/1410D revision 3b Table 26 − Diagnostic codes Code (see note 1) Description When this code is in the Device 0 Error register 01h Device 0 passed, Device 1 passed or not present 00h, 02h-7Fh Device 0 failed, Device 1 passed or not present 81h Device 0 passed, Device 1 failed 80h, 82h-FFh Device 0 failed, Device 1 failed When this code is in the Device 1 Error register 01h Device 1 passed (see note 2) 00h, 02h-7Fh Device 1 failed (see note 2) NOTE − 1 Codes other than 01h and 81h may indicate additional information about the failure(s). 2 If Device 1 is not present, the host may see the information from Device 0 even though Device 1 is selected. 8.11.6 Error outputs Table 26 shows the error information that is returned as a diagnostic code in the Error register. 8.11.7 Prerequisites This command shall be accepted regardless of the state of DRDY. 8.11.8 Description This command shall cause the devices to perform the internal diagnostic tests. Both devices, if present, shall execute this command regardless of which device is selected. If the host issues an EXECUTE DEVICE DIAGNOSTIC command while a device is in or going to a power management mode except Sleep, then the device shall execute the EXECUTE DEVICE DIAGNOSTIC sequence. 8.12 FLUSH CACHE 8.12.1 Command code E7h 8.12.2 Feature set General feature set − Mandatory for all devices not implementing the PACKET Command feature set. − Optional for devices implementing the PACKET Command feature set. 8.12.3 Protocol Non-data (see 9.4). Page 106 T13/1410D revision 3b 8.12.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na 3 2 1 0 na DRQ na na na na na ERR na na na na na obs na obs DEV E7h Device register – DEV shall specify the selected device. 8.12.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 na na na na na obs BSY na DRDY obs DF DEV na Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.12.6 Error outputs An unrecoverable error encountered during execution of writing data results in the termination of the command and the Command Block registers contain the sector address of the sector where the first unrecoverable error occurred. Subsequent FLUSH CACHE commands continue the process of flushing the cache starting with the first sector after the sector in error. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na obs BSY 6 na na DRDY 5 na obs DF 4 na 3 na na LBA (7:0) LBA (15:8) LBA (23:16) DEV na DRQ 2 ABRT 1 na LBA (27:24) na na 0 na ERR Error register – ABRT may be set to one if the device is not able to complete the action requested by the command. LBA Low, LBA Mid, LBA High, Device – Page 107 T13/1410D revision 3b shall be written with the address of the first unrecoverable error. If the device supports the 48-bit Address feature set and the error occurred in an address greater than FFFFFFFh, the value set in the LBA Low, LBA Mid, and LBA High registers shall be FFh and the value set in bits (3:0) of the Device register shall be Fh. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.12.7 Prerequisites DRDY set to one. 8.12.8 Description This command is used by the host to request the device to flush the write cache. If there is data in the write cache, that data shall be written to the media. The BSY bit shall remain set to one until all data has been successfully written or an error occurs. NOTE − This command may take longer than 30 s to complete. 8.13 FLUSH CACHE EXT 8.13.1 Command code EAh 8.13.2 Feature set 48-bit Address feature set − Mandatory for all devices implementing the 48-bit Address feature. − Prohibited for devices implementing the PACKET Command feature set. 8.13.3 Protocol Non-data (see 9.4). Page 108 T13/1410D revision 3b 8.13.4 Inputs Register 7 6 5 4 3 2 1 0 Features Current Reserved Previous Reserved Sector Count Current Reserved Previous Reserved LBA Low Current Reserved Previous Reserved LBA Mid Current Reserved Previous Reserved LBA High Current Reserved Previous Reserved Device obs na obs DEV na Command EAh NOTE − The value indicated as Current is the value most recently written to the register. The value indicated as Previous is the value that was in the register before the most recent write to the register. Device register – DEV shall specify the selected device. 8.13.5 Normal outputs Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. Page 109 T13/1410D revision 3b 8.13.6 Error outputs An unrecoverable error encountered while writing data results in the termination of the command and the Command Block registers contain the sector address of the sector where the first unrecoverable error occurred. Subsequent FLUSH CACHE EXT commands continue the process of flushing the cache starting with the first sector after the sector in error. Register 7 6 5 4 3 2 1 0 Error na na na na na ABRT na na Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 LBA (7:0) HOB = 1 LBA (31:24) LBA Mid HOB = 0 LBA (15:8) HOB = 1 LBA (39:32) LBA High HOB = 0 LBA (23:16) HOB = 1 LBA (47:40) Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Error register ABRT shall be set to one if the device is not able to complete the action requested by the command. LBA Low LBA (7:0) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (31:24) of the address of the first unrecoverable error when read with Device Control register HOB set to one. LBA Mid LBA (15:8) of the address of the first unrecoverable error when read with Device Control register HOB cleared to zero. LBA (39:32) of the address of the first unrecoverable error when read with Device Control register HOB set to one. LBA High LBA (23:16) of the address of the first unrecoverable error when read with Device Control register HOB cleared to zero. LBA (47:40) of the address of the first unrecoverable error when read with Device Control register HOB is set to one. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.13.7 Prerequisites DRDY set to one. Page 110 T13/1410D revision 3b 8.13.8 Description This command is used by the host to request the device to flush the write cache. If there is data in the write cache, that data shall be written to the madia.The BSY bit shall remain set to one until all data has been successfully written or an error occurs. NOTE − This command may take longer than 30 s to complete. 8.14 GET MEDIA STATUS 8.14.1 Command code DAh 8.14.2 Feature set Removable Media Status Notification feature set − Mandatory for devices implementing the Removable Media Status Notification feature set. Removable Media feature set − Optional for devices implementing the Removable Media feature set. 8.14.3 Protocol Non-data (see 9.4). 8.14.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na na na na na na obs na obs DEV DAh Device register – DEV shall specify the selected device. 8.14.5 Normal outputs Normal outputs are returned if Media Status Notification is disabled or if no bits are set to one in the Error register. Page 111 T13/1410D revision 3b Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na DRQ na na na na na ERR na na na na na obs BSY na DRDY obs DF DEV na Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.14.6 Error outputs If the device does not support this command, the device shall return command aborted. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 WP 5 MC 4 na 3 MCR 2 ABRT 1 NM 0 obs na DRQ na na na na na ERR na na na na obs BSY na DRDY obs DF DEV na Error register – ABRT shall be set to one if device does not support this command. ABRT may be set to one if the device is not able to complete the action requested by the command. NM (No Media) shall be set to one if no media is present in the device. This bit shall be set to one for each execution of GET MEDIA STATUS until media is inserted into the device. MCR (Media Change Request) shall be set to one if the eject button is pressed by the user and detected by the device. The device shall reset this bit after each execution of the GET MEDIA STATUS command and only set the bit again for subsequent eject button presses. MC (Media Change) shall be set to one when the device detects media has been inserted. The device shall reset this bit after each execution of the GET MEDIA STATUS command and only set the bit again for subsequent media insertions. WP (Write Protect) shall be set to one for each execution of GET MEDIA STATUS while the media is write protected. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. Page 112 T13/1410D revision 3b 8.14.7 Prerequisites DRDY set to one. 8.14.8 Description This command returns media status bits WP, MC, MCR, and NM, as defined above. When Media Status Notification is disabled this command returns zeros in the WP, MC, MCR, and NM bits. 8.15 IDENTIFY DEVICE 8.15.1 Command code ECh 8.15.2 Feature set General feature set − − Mandatory for all devices. Devices implementing the PACKET Command feature set (see 8.15.5.2). 8.15.3 Protocol PIO data-in (see 9.5). 8.15.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na na obs na obs DEV na ECh Device register – DEV shall specify the selected device. 8.15.5 Outputs 8.15.5.1 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na DRQ na na na na na ERR na na na na na obs BSY na DRDY obs DF DEV na Device register – Page 113 T13/1410D revision 3b DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.15.5.2 Outputs for PACKET Command feature set devices In response to this command, devices that implement the PACKET Command feature set shall post command aborted and place the PACKET Command feature set signature in the Command Block registers (see 9.12). 8.15.6 Error outputs Devices not implementing the PACKET Command feature set shall not report an error. 8.15.7 Prerequisites DRDY set to one. 8.15.8 Description The IDENTIFY DEVICE command enables the host to receive parameter information from the device. Some devices may have to read the media in order to complete this command. When the command is issued, the device sets the BSY bit to one, prepares to transfer the 256 words of device identification data to the host, sets the DRQ bit to one, clears the BSY bit to zero, and asserts INTRQ if nIEN is cleared to zero. The host may then transfer the data by reading the Data register. Table 27 defines the arrangement and meaning of the parameter words in the buffer. All reserved bits or words shall be zero. Some parameters are defined as a 16-bit value. A word that is defined as a 16-bit value places the most significant bit of the value on signal line DD15 and the least significant bit on signal line DD0 (see 3.2.9). Some parameters are defined as 32-bit values (e.g., words (61:60)). Such fields are transferred using two successive word transfers. The device shall first transfer the least significant bits, bits (15:0) of the value, on signal lines DD(15:0) respectively. After the least significant bits have been transferred, the most significant bits, bits (31:16) of the value, shall be transferred on DD(15:0) respectively (see 3.2.9). Some parameters are defined as a string of ACSII characters. Such fields are transferred as defined in 3.2.9. Page 114 T13/1410D revision 3b Table 27 − IDENTIFY DEVICE information Word 0 1 2 3 4-5 6 7-8 9 10-19 20-21 22 23-26 27-46 47 48 49 O/M M O O M M M M F/V F X F X X V X F X V X X X V X F X X F F F F F F M F F F F F F F X 50 51-52 53 M M F F F X F X F F F X Description General configuration bit-significant information: 15 0 = ATA device 14-8 Retired 7 1 = removable media device 6 Obsolete 5-3 Retired 2 Response incomplete 1 Retired 0 Reserved Obsolete Specific configuration Obsolete Retired Obsolete Reserved for assignment by the CompactFlash Association Retired Serial number (20 ASCII characters) Retired Obsolete Firmware revision (8 ASCII characters) Model number (40 ASCII characters) 15-8 80h 7-0 00h = Reserved 01h-FFh = Maximum number of sectors that shall be transferred per interrupt on READ/WRITE MULTIPLE commands Reserved Capabilities 15-14 Reserved for the IDENTIFY PACKET DEVICE command. 13 1 = Standby timer values as specified in this standard are supported 0 = Standby timer values shall be managed by the device 12 Reserved for the IDENTIFY PACKET DEVICE command. 11 1 = IORDY supported 0 = IORDY may be supported 10 1 = IORDY may be disabled 9 1 = LBA supported 8 1 = DMA supported. 7-0 Retired Capabilities 15 Shall be cleared to zero. 14 Shall be set to one. 13-2 Reserved. 1 Obsolete 0 Shall be set to one to indicate a device specific Standby timer value minimum. Obsolete 15-3 Reserved 2 1 = the fields reported in word 88 are valid 0 = the fields reported in word 88 are not valid 1 1 = the fields reported in words (70:64) are valid 0 = the fields reported in words (70:64) are not valid 0 Obsolete (continued) Page 115 T13/1410D revision 3b Table 27 − IDENTIFY DEVICE information (continued) Word 54-58 59 O/M 60-61 62 63 M M M F/V X F V V F X F V V V 64 M 65 M 66 M 67 M 68 M F F F F F F F F F 69-70 71-74 75 76-79 80 F F F O F F F M F F F F F F F F F F F F F X X F Description Obsolete 15-9 Reserved 8 1 = Multiple sector setting is valid 7-0 xxh = Current setting for number of sectors that shall be transferred per interrupt on R/W Multiple command Total number of user addressable sectors Obsolete 15-11 Reserved 10 1 = Multiword DMA mode 2 is selected 0 = Multiword DMA mode 2 is not selected 9 1 = Multiword DMA mode 1 is selected 0 = Multiword DMA mode 1 is not selected 8 1 = Multiword DMA mode 0 is selected 0 = Multiword DMA mode 0 is not selected 7-3 Reserved 2 1 = Multiword DMA mode 2 and below are supported 1 1 = Multiword DMA mode 1 and below are supported 0 1 = Multiword DMA mode 0 is supported 15-8 Reserved 7-0 PIO modes supported Minimum Multiword DMA transfer cycle time per word 15-0 Cycle time in nanoseconds Manufacturer’s recommended Multiword DMA transfer cycle time 15-0 Cycle time in nanoseconds Minimum PIO transfer cycle time without flow control 15-0 Cycle time in nanoseconds Minimum PIO transfer cycle time with IORDY flow control 15-0 Cycle time in nanoseconds Reserved (for future command overlap and queuing) Reserved for IDENTIFY PACKET DEVICE command. Queue depth 15-5 Reserved 4-0 Maximum queue depth – 1 Reserved Major version number 0000h or FFFFh = device does not report version 15 Reserved 14 Reserved for ATA/ATAPI-14 13 Reserved for ATA/ATAPI-13 12 Reserved for ATA/ATAPI-12 11 Reserved for ATA/ATAPI-11 10 Reserved for ATA/ATAPI-10 9 Reserved for ATA/ATAPI-9 8 Reserved for ATA/ATAPI-8 7 Reserved for ATA/ATAPI-7 6 1 = supports ATA/ATAPI-6 5 1 = supports ATA/ATAPI-5 4 1 = supports ATA/ATAPI-4 3 1 = supports ATA-3 2 Obsolete 1 Obsolete 0 Reserved (continued) Page 116 T13/1410D revision 3b Table 27 − IDENTIFY DEVICE information (continued) Word 81 O/M M 82 M F/V F X F F F X F F F F F F F F F F F 83 M F F F F F F F F F F F F F F F F 84 M F F F F F F F F F Description Minor version number 0000h or FFFFh = device does not report version 0001h-FFFEh = see 8.15.41 Command set supported. 15 Obsolete 14 1 = NOP command supported 13 1 = READ BUFFER command supported 12 1 = WRITE BUFFER command supported 11 Obsolete 10 1 = Host Protected Area feature set supported 9 1 = DEVICE RESET command supported 8 1 = SERVICE interrupt supported 7 1 = release interrupt supported 6 1 = look-ahead supported 5 1 = write cache supported 4 Shall be cleared to zero to indicate that the PACKET Command feature set is not supported. 3 1 = mandatory Power Management feature set supported 2 1 = Removable Media feature set supported 1 1 = Security Mode feature set supported 0 1 = SMART feature set supported Command sets supported. 15 Shall be cleared to zero 14 Shall be set to one 13 1 = FLUSH CACHE EXT command supported 12 1 = mandatory FLUSH CACHE command supported 11 1 = Device Configuration Overlay feature set supported 10 1 = 48-bit Address feature set supported 9 1 = Automatic Acoustic Management feature set supported 8 1 = SET MAX security extension supported 7 See Address Offset Reserved Area Boot, NCITS TR27:2001 6 1 = SET FEATURES subcommand required to spinup after power-up 5 1 = Power-Up In Standby feature set supported 4 1 = Removable Media Status Notification feature set supported 3 1 = Advanced Power Management feature set supported 2 1 = CFA feature set supported 1 1 = READ/WRITE DMA QUEUED supported 0 1 = DOWNLOAD MICROCODE command supported Command set/feature supported extension. 15 Shall be cleared to zero 14 Shall be set to one 13-6 Reserved 5 1 = General Purpose Logging feature set supported 4 Reserved 3 1 = Media Card Pass Through Command feature set supported 2 1 = Media serial number supported 1 1 = SMART self-test supported 0 1 = SMART error logging supported (continued) Page 117 T13/1410D revision 3b Table 27 − IDENTIFY DEVICE information (continued) Word 85 O/M M F/V X F F F X V F V V V V F F F V V 86 M F F F F F V F F F V V V F F F 87 M F F F F V V V F F Description Command set/feature enabled. 15 Obsolete 14 1 = NOP command enabled 13 1 = READ BUFFER command enabled 12 1 = WRITE BUFFER command enabled 11 Obsolete 10 1 = Host Protected Area feature set enabled 9 1 = DEVICE RESET command enabled 8 1 = SERVICE interrupt enabled 7 1 = release interrupt enabled 6 1 = look-ahead enabled 5 1 = write cache enabled 4 Shall be cleared to zero to indicate that the PACKET Command feature set is not supported. 3 1 = Power Management feature set enabled 2 1 = Removable Media feature set enabled 1 1 = Security Mode feature set enabled 0 1 = SMART feature set enabled Command set/feature enabled. 15-14 Reserved 13 1 = FLUSH CACHE EXT command supported 12 1 = FLUSH CACHE command supported 11 1 = Device Configuration Overlay supported 10 1 = 48-bit Address features set supported 9 1 = Automatic Acoustic Management feature set enabled 8 1 = SET MAX security extension enabled by SET MAX SET PASSWORD 7 See Address Offset Reserved Area Boot, NCITS TR27:2001 6 1 = SET FEATURES subcommand required to spin-up after power-up 5 1 = Power-Up In Standby feature set enabled 4 1 = Removable Media Status Notification feature set enabled 3 1 = Advanced Power Management feature set enabled 2 1 = CFA feature set enabled 1 1 = READ/WRITE DMA QUEUED command supported 0 1 = DOWNLOAD MICROCODE command supported Command set/feature default. 15 Shall be cleared to zero 14 Shall be set to one 13-6 Reserved 5 General Purpose Logging feature set supported 4 Reserved 3 1 = Media Card Pass Through Command feature set enabled 2 1 = Media serial number is valid 1 1 = SMART self-test supported 0 1 = SMART error logging supported (continued) Page 118 T13/1410D revision 3b Table 27 − IDENTIFY DEVICE information (continued) Word 88 O/M O F/V F V V V V V V 89 90 91 92 O O O O F F F F F F F F F V V Description 15-14 Reserved 13 1 = Ultra DMA mode 5 is selected 0 = Ultra DMA mode 5 is not selected 12 1 = Ultra DMA mode 4 is selected 0 = Ultra DMA mode 4 is not selected 11 1 = Ultra DMA mode 3 is selected 0 = Ultra DMA mode 3 is not selected 10 1 = Ultra DMA mode 2 is selected 0 = Ultra DMA mode 2 is not selected 9 1 = Ultra DMA mode 1 is selected 0 = Ultra DMA mode 1 is not selected 8 1 = Ultra DMA mode 0 is selected 0 = Ultra DMA mode 0 is not selected 7-6 Reserved 5 1 = Ultra DMA mode 5 and below are supported 4 1 = Ultra DMA mode 4 and below are supported 3 1 = Ultra DMA mode 3 and below are supported 2 1 = Ultra DMA mode 2 and below are supported 1 1 = Ultra DMA mode 1 and below are supported 0 1 = Ultra DMA mode 0 is supported Time required for security erase unit completion Time required for Enhanced security erase completion Current advanced power management value Master Password Revision Code (continued) Page 119 T13/1410D revision 3b Table 27 − IDENTIFY DEVICE information (continued) Word 93 O/M * F/V F F V F V V F F V V V V F Description Hardware reset result. The contents of bits (12:0) of this word shall change only during the execution of a hardware reset. 15 Shall be cleared to zero. 14 Shall be set to one. 13 1 = device detected CBLID- above ViH 0 = device detected CBLID- below ViL 12-8 Device 1 hardware reset result. Device 0 shall clear these bits to zero. Device 1 shall set these bits as follows: 12 Reserved. 11 0 = Device 1 did not assert PDIAG-. 1 = Device 1 asserted PDIAG-. 10-9 These bits indicate how Device 1 determined the device number: 00 = Reserved. 01 = a jumper was used. 10 = the CSEL signal was used. 11 = some other method was used or the method is unknown. 8 Shall be set to one. 7-0 Device 0 hardware reset result. Device 1 shall clear these bits to zero. Device 0 shall set these bits as follows: 7 Reserved. 6 0 = Device 0 does not respond when Device 1 is selected. 1 = Device 0 responds when Device 1 is selected. 5 0 = Device 0 did not detect the assertion of DASP-. 1 = Device 0 detected the assertion of DASP-. 4 0 = Device 0 did not detect the assertion of PDIAG-. 1 = Device 0 detected the assertion of PDIAG-. 3 0 = Device 0 failed diagnostics. 1 = Device 0 passed diagnostics. 2-1 These bits indicate how Device 0 determined the device number: 00 = Reserved. 01 = a jumper was used. 10 = the CSEL signal was used. 11 = some other method was used or the method is unknown. 0 Shall be set to one. (continued) Page 120 T13/1410D revision 3b Table 27 − IDENTIFY DEVICE information (continued) Word 94 95-99 100-103 104-126 127 O/M O O F/V V V F V F O F F 128 129-159 160 O F V F F V V V V F X O F F F 161-175 176-205 206-254 255 O M V F X V F X Description 15-8 Vendor’s recommended acoustic management value. 7-0 Current automatic acoustic management value. Reserved Maximum user LBA for 48-bit Address feature set. Reserved Removable Media Status Notification feature set support 15-2 Reserved 1-0 00 = Removable Media Status Notification feature set not supported 01 = Removable Media Status Notification feature supported 10 = Reserved 11 = Reserved Security status 15-9 Reserved 8 Security level 0 = High, 1 = Maximum 7-6 Reserved 5 1 = Enhanced security erase supported 4 1 = Security count expired 3 1 = Security frozen 2 1 = Security locked 1 1 = Security enabled 0 1 = Security supported Vendor specific CFA power mode 1 15 Word 160 supported 14 Reserved 13 CFA power mode 1 is required for one or more commands implemented by the device 12 CFA power mode 1 disabled 11-0 Maximum current in ma Reserved for assignment by the CompactFlash Association Current media serial number Reserved Integrity word 15-8 Checksum 7-0 Signature Key: O/M = Mandatory/optional requirement. M = Support of the word is mandatory. O = Support of the word is optional. * = see 8.15.49. F/V = Fixed/variable content F = the content of the word is fixed and does not change. For removable media devices, these values may change when media is removed or changed. V = the contents of the word is variable and may change depending on the state of the device or the commands executed by the device. X = the content of the word may be fixed or variable. (concluded) 8.15.9 Word 0: General configuration Devices that conform to this standard shall clear bit 15 to zero. If bit 7 is set to one, the device is a removable media device. Page 121 T13/1410D revision 3b Bit 6 is obsolete. If bit 2 is set to one it indicates that the content of the IDENTIFY DEVICE response is incomplete. This will occur if the device supports the Power-up in Standby feature set and required data is contained on the device media. In this case the content of at least word 0 and word 2 shall be valid. Devices supporting the CFA feature set shall place the value 848Ah in word 0. definitions for the bits in word 0 are not valid. In this case, the above 8.15.10 Word 1: Obsolete 8.15.11 Word 2: Specific configuration. Word 2 shall be set as follows: Value 37C8h 738Ch 8C73h C837h All other values Description Device requires SET FEATURES subcommand to spin-up after power-up and IDENTIFY DEVICE response is incomplete (see 6.18). Device requires SET FEATURES subcommand to spin-up after power-up and IDENTIFY DEVICE response is complete (see 6.18). Device does not require SET FEATURES subcommand to spin-up after power-up and IDENTIFY DEVICE response is incomplete (see 6.18). Device does not require SET FEATURES subcommand to spin-up after power-up and IDENTIFY DEVICE response is complete (see 6.18). Reserved. 8.15.12 Word 3: Obsolete 8.15.13 Word (5:4): Retired. 8.15.14 Word 6: Obsolete 8.15.15 Words (8:7): Reserved for assignment by the CompactFlash Association 8.15.16 Word 9: Retired. 8.15.17 Words (19:10): Serial number This field contains the serial number of the device. The contents of this field is an ASCII character string of twenty bytes. The device shall pad the character string with spaces (20h), if necessary, to ensure that the string is the proper length. The combination of Serial number (words (19:10)) and Model number (words (46:27)) shall be unique for a given manufacturer. 8.15.18 Word (21:20): Retired. 8.15.19 Word 22: Obsolete. 8.15.20 Word (26:23): Firmware revision This field contains the firmware revision number of the device. The contents of this field is an ASCII character string of eight bytes. The device shall pad the character string with spaces (20h), if necessary, to ensure that the string is the proper length. Page 122 T13/1410D revision 3b 8.15.21 Words (46:27): Model number This field contains the model number of the device. The contents of this field is an ASCII character string of forty bytes. The device shall pad the character string with spaces (20h), if necessary, to ensure that the string is the proper length. The combination of Serial number (words (19:10)) and Model number (words (46:27)) shall be unique for a given manufacturer. 8.15.22 Word 47: READ/WRITE MULTIPLE support. Bits (7:0) of this word define the maximum number of sectors per block that the device supports for READ/WRITE MULTIPLE commands. 8.15.23 Word 48: Reserved. 8.15.24 Word (50:49): Capabilities Bits (15:14) of word 49 are reserved for use in the IDENTIFY PACKET DEVICE command response. Bit 13 of word 49 is used to determine whether a device uses the Standby timer values as defined in this standard. Table 30 specifies the Standby timer values used by the device if bit 13 is set to one. If bit 13 is cleared to zero, the timer values shall be vendor specific. Bit 12 of word 49 is reserved for use in the IDENTIFY PACKET DEVICE command response. Bit 11 of word 49 indicates whether a device supports IORDY. If this bit is set to one, then the device supports IORDY operation. All devices except CFA and PCMCIA devices shall support PIO mode 3 or higher, shall support IORDY, and shall set this bit to one. Bit 10 of word 49 is used to indicate a device’s ability to enable or disable the use of IORDY. If this bit is set to one, then the device supports the disabling of IORDY. Disabling and enabling of IORDY is accomplished using the SET FEATURES command. Bit 9 of word 49 shall be set to one to indicate that an LBA transition is supported. Bits 8 of word 49 Shall be set to one to indicate that DMA is supported. For devices not implementing the CompactFlash feature set this bit shall be set to one. Bits (7:0) of word 49 are retired. Bit 15 of word 50 shall be cleared to zero to indicate that the contents of word 50 are valid. Bit 14 of word 50 shall be set to one to indicate that the contents of word 50 are valid. Bits (13:2) of word 50 are reserved. Bit 1 of word 50 is obsolete. Bit 0 of word 50 set to one indicates that the device has a minimum Standby timer value that is device specific. 8.15.25 Words (52:51): Obsolete 8.15.26 Word 53: Field validity Bit 0 of word 53 is obsolete. If bit 1 of word 53 is set to one, the values reported in words (70:64) are valid. If this bit is cleared to zero, the values reported in words (70:64) are not valid. All devices except CFA and PCMCIA devices shall support PIO mode 3 or above and shall set bit 1 of word 53 to one and support the fields Page 123 T13/1410D revision 3b contained in words (70:64). If the device supports Ultra DMA and the values reported in word 88 are valid, then bit 2 of word 53 shall be set to one. If the device does not support Ultra DMA and the values reported in word 88 are not valid, then this bit is cleared to zero. 8.15.27 Word (58:54): Obsolete 8.15.28 Word 59: Multiple sector setting If bit 8 is set to one, bits (7:0) reflect the number of sectors currently set to transfer on a READ/WRITE MULTIPLE command. This field may default to the preferred value for the device (see 8.49). 8.15.29 Word (61:60): Total number of user addressable sectors This field contains a value that is one greater than the total number of user addressable sectors (see 6.2). The maximum value that shall be placed in this field is 0FFFFFFFh. 8.15.30 Word 62: Obsolete 8.15.31 Word 63: Multiword DMA transfer Word 63 identifies the Multiword DMA transfer modes supported by the device and indicates the mode that is currently selected. Only one DMA mode shall be selected at any given time. If an Ultra DMA mode is enabled, then no Multiword DMA mode shall be enabled. If a Multiword DMA mode is enabled then no Ultra DMA mode shall be enabled. 8.15.31.1 Reserved Bits (15:11) of word 63 are reserved. 8.15.31.2 Multiword DMA mode 2 selected If bit 10 of word 63 is set to one, then Multiword DMA mode 2 is selected. If this bit is cleared to zero, then Multiword DMA mode 2 is not selected. If bit 9 is set to one or if bit 8 is set to one, then this bit shall be cleared to zero. 8.15.31.3 Multiword DMA mode 1 selected If bit 9 of word 63 is set to one, then Multiword DMA mode 1 is selected. If this bit is cleared to zero then Multiword DMA mode 1 is not selected. If bit 10 is set to one or if bit 8 is set to one, then this bit shall be cleared to zero. 8.15.31.4 Multiword DMA mode 0 selected If bit 8 of word 63 is set to one, then Multiword DMA mode 0 is selected. If this bit is cleared to zero then Multiword DMA mode 0 is not selected. If bit 10 is set to one or if bit 9 is set to one, then this bit shall be cleared to zero. 8.15.31.5 Reserved Bits (7:3) of word 63 are reserved. Page 124 T13/1410D revision 3b 8.15.31.6 Multiword DMA mode 2 supported If bit 2 of word 63 is set to one, then Multiword DMA modes 2 and below are supported. If this bit is cleared to zero, then Multiword DMA mode 2 is not supported. If Multiword DMA mode 2 is supported, then Multiword DMA modes 1 and 0 shall also be supported. If this bit is set to one, bits (1:0) shall be set to one. 8.15.31.7 Multiword DMA mode 1 supported If bit 1 of word 63 is set to one, then Multiword DMA modes 1 and below are supported. If this bit is cleared to zero, then Multiword DMA mode 1 is not supported. If Multiword DMA mode 1 is supported, then Multiword DMA mode 0 shall also be supported. If this bit is set to one, bit 0 shall be set to one. 8.15.31.8 Multiword DMA mode 0 supported If bit 0 of word 63 is set to one, then Multiword DMA mode 0 is supported. 8.15.32 Word 64: PIO transfer modes supported Bits (7:0) of word 64 of the Identify Device parameter information is defined as the PIO data and register transfer supported field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant. Any number of bits may be set to one in this field by the device to indicate the PIO modes the device is capable of supporting. Of these bits, bits (7:2) are Reserved for future PIO modes. Bit 0, if set to one, indicates that the device supports PIO mode 3. All devices except CFA and PCMCIA devices shall support PIO mode 3 and shall set bit 0 to one. Bit 1, if set to one, indicates that the device supports PIO mode 4. 8.15.33 Word 65: Minimum Multiword DMA transfer cycle time per word Word 65 of the parameter information of the IDENTIFY DEVICE command is defined as the minimum Multiword DMA transfer cycle time per word. This field defines, in nanoseconds, the minimum cycle time that the device supports when performing Multiword DMA transfers on a per word basis. If this field is supported, bit 1 of word 53 shall be set to one. Any device that supports Multiword DMA mode 1 or above shall support this field, and the value in word 65 shall not be less than the minimum cycle time for the fastest DMA mode supported by the device. If bit 1 of word 53 is set to one because a device supports a field in words (70:64) other than this field and the device does not support this field, the device shall return a value of zero in this field. 8.15.34 Word 66: Device recommended Multiword DMA cycle time Word 66 of the parameter information of the IDENTIFY DEVICE command is defined as the device recommended Multiword DMA transfer cycle time. This field defines, in nanoseconds, the minimum cycle time per word during a single sector host transfer while performing a multiple sector READ DMA or WRITE DMA command for any location on the media under nominal conditions. If a host runs at a faster cycle rate by operating at a cycle time of less than this value, the device may negate DMARQ for flow control. The rate at which DMARQ is negated could result in reduced throughput despite the faster cycle rate. Transfer at this rate does not ensure that flow control will not be used, but implies that higher performance may result. If this field is supported, bit 1 of word 53 shall be set to one. Any device that supports Multiword DMA mode 1 or above shall support this field, and the value in word 66 shall not be less than the value in word 65. If bit 1 of word 53 is set to one because a device supports a field in words (70:64) other than this field and the device does not support this field, the device shall return a value of zero in this field. Page 125 T13/1410D revision 3b 8.15.35 Word 67: Minimum PIO transfer cycle time without IORDY flow control Word 67 of the parameter information of the IDENTIFY DEVICE command is defined as the minimum PIO transfer without IORDY flow control cycle time. This field defines, in nanoseconds, the minimum cycle time that, if used by the host, the device guarantees data integrity during the transfer without utilization of IORDY flow control. If this field is supported, Bit 1 of word 53 shall be set to one. Any device that supports PIO mode 3 or above shall support this field, and the value in word 67 shall not be less than the value reported in word 68. If bit 1 of word 53 is set to one because a device supports a field in words (70:64) other than this field and the device does not support this field, the device shall return a value of zero in this field. 8.15.36 Word 68: Minimum PIO transfer cycle time with IORDY flow control Word 68 of the parameter information of the IDENTIFY DEVICE command is defined as the minimum PIO transfer with IORDY flow control cycle time. This field defines, in nanoseconds, the minimum cycle time that the device supports while performing data transfers while utilizing IORDY flow control. If this field is supported, Bit 1 of word 53 shall be set to one. All devices except CFA and PCMCIA devices shall support PIO mode 3 and shall support this field, and the value in word 68 shall be the fastest defined PIO mode supported by the device. The maximum value reported in this field shall be 180 to indicate support for PIO mode 3 or above. If bit 1 of word 53 is set to one because a device supports a field in words (70:64) other than this field and the device does not support this field, the device shall return a value of zero in this field. 8.15.37 Words (74:69): Reserved 8.15.38 Word 75: Queue depth Bits (4:0) of word 75 indicate the maximum queue depth supported by the device. The queue depth includes all commands for which command acceptance has occured and command completion has not occurred. The value in this field equals (maximum queue depth – 1), e.g., a value of zero indicates a queue depth of one, a value of 31 indicates a queue depth of 32. If bit 1 of word 83 is cleared to zero indicating that the device does not support READ/WRITE DMA QUEUED commands, the value in this field shall be zero. A device may support READ/WRITE DMA QUEUED commands to provide overlap only (i.e., queuing not supported), in this case, bit 1 of word 83 shall be set to one and the queue depth shall be set to zero. Support of this word is mandatory if the Queuing feature set is supported. 8.15.39 Words (79:76): Reserved 8.15.40 Word 80: Major version number If not 0000h or FFFFh, the device claims compliance with the major version(s) as indicated by bits (6:3) being set to one. Values other than 0000h and FFFFh are bit significant. Since ATA standards maintain downward compatibility, a device may set more than one bit. Page 126 T13/1410D revision 3b 8.15.41 Word 81: Minor version number If an implementor claims that the revision of the standard they used to guide their implementation does not need to be reported or if the implementation was based upon a standard prior to the ATA-3 standard, word 81 shall be 0000h or FFFFh. Table 28 defines the value that may optionally be reported in word 81 to indicate the revision of the standard that guided the implementation. Value 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh-FFFFh Table 28 − Minor version number Minor revision Obsolete Obsolete Obsolete Obsolete Obsolete ATA-3 X3T10 2008D revision 1 Obsolete ATA-3 X3T10 2008D revision 0 Obsolete ATA-3 published, ANSI X3.298-199x ATA-3 X3T10 2008D revision 6 ATA-3 X3T13 2008D revision 7 and 7a ATA/ATAPI-4 X3T13 1153D revision 6 ATA/ATAPI-4 T13 1153D revision 13 ATA/ATAPI-4 X3T13 1153D revision 7 ATA/ATAPI-4 T13 1153D revision 18 ATA/ATAPI-4 T13 1153D revision 15 ATA/ATAPI-4 published, ANSI NCITS 317-1998 ATA/ATAPI-5 T13 1321D revision 3 ATA/ATAPI-4 T13 1153D revision 14 ATA/ATAPI-5 T13 1321D revision 1 ATA/ATAPI-5 published, ANSI NCITS 340-2000 ATA/ATAPI-4 T13 1153D revision 17 ATA/ATAPI-6 T13 1410D revision 0 ATA/ATAPI-6 T13 1410D revision 3a Reserved ATA/ATAPI-6 T13 1410D revision 2 ATA/ATAPI-6 T13 1410D revision 1 Reserved 8.15.42 Words (84:82): Features/command sets supported Words (84:82) shall indicate features/command sets supported. If a defined bit is cleared to zero, the indicated features/command set is not supported. If bit 14 of word 83 is set to one and bit 15 of word 83 is cleared to zero, the contents of words (83:82) contain valid support information. If not, support information is not valid in these words. If bit 14 of word 84 is set to one and bit 15 of word 84 is cleared to zero, the contents of word 84 contains valid support information. If not, support information is not valid in this word. If bit 0 of word 82 is set to one, the SMART feature set is supported. If bit 1 of word 82 is set to one, the Security Mode feature set is supported. If bit 2 of word 82 is set to one, the Removable Media feature set is supported. Page 127 T13/1410D revision 3b Bit 3 of word 82 shall be set to one indicating the mandatory Power Management feature set is supported. Bit 4 of word 82 shall be cleared to zero to indicate that the PACKET Command feature set is not supported. If bit 5 of word 82 is set to one, write cache is supported. If bit 6 of word 82 is set to one, look-ahead is supported. If bit 7 of word 82 is set to one, release interrupt is supported. If bit 8 of word 82 is set to one, SERVICE interrupt is supported. If bit 9 of word 82 is set to one, the DEVICE RESET command is supported. If bit 10 of word 82 is set to one, the Host Protected Area feature set is supported. Bit 11 of word 82 is obsolete. If bit 12 of word 82 is set to one, the device supports the WRITE BUFFER command. If bit 13 of word 82 is set to one, the device supports the READ BUFFER command. If bit 14 of word 82 is set to one, the device supports the NOP command. Bit 15 of word 82 is obsolete. If bit 0 of word 83 is set to one, the device supports the DOWNLOAD MICROCODE command. If bit 1 of word 83 is set to one, the device supports the READ DMA QUEUED and WRITE DMA QUEUED commands. If bit 2 of word 83 is set to one, the device supports the CFA feature set. If bit 3 of word 83 is set to one, the device supports the Advanced Power Management feature set. If bit 4 of word 83 is set to one, the device supports the Removable Media Status feature set. If bit 5 of word 83 is set to one, the device supports the Power-Up In Standby feature set. If bit 6 of word 83 is set to one, the device requires the SET FEATURES subcommand to spin-up after power-up if the Power-Up In Standby feature set is enabled (see 8.46.15). Bit 7 is defined in Address Offset Reserved Area Boot, NCITS TR27:2001. If bit 8 of word 83 is set to one, the device supports the SET MAX security extension. If bit 9 of word 83 is set to one, the device supports the Automatic Acoustic Management feature set. If bit 10 of word 83 is set to one, the 48-bit Address feature set is supported. If bit 11 of word 83 is set to one, the device supports the Device Configuration Overlay feature set. Bit 12 of word 83 shall be set to one indicating the device supports the mandatory FLUSH CACHE command. If bit 13 of word 83 is set to one, the device supports the FLUSH CACHE EXT command. Page 128 T13/1410D revision 3b If bit 0 of word 84 is set to one, the device supports SMART error logging. If bit 1 of word 84 is set to one, the device supports SMART self-test. If bit 2 of word 84 is set to one, the device supports the media serial number field words (205:176). If bit 3 of word 84 is set to one, the device supports the Media Card Pass Through Command feature set. If bit 4 of word 84 is reserved. If bit 5 of word 84 is set to one, the device supports the General Purpose Logging feature set. 8.15.43 Words (87:85): Features/command sets enabled Words (87:85) shall indicate features/command sets enabled. If a defined bit is cleared to zero, the indicated features/command set is not enabled. If a supported features/command set is supported and cannot be disabled, it is defined as supported and the bit shall be set to one. If bit 14 of word 87 is set to one and bit 15 of word 87 is cleared to zero, the contents of words (87:85) contain valid information. If not, information is not valid in these words. If bit 0 of word 85 is set to one, the SMART feature set has been enabled via the SMART ENABLE OPERATIONS command. If bit 0 of word 85 is cleared to zero, the SMART feature set has been disabled via the SMART DISABLE OPERATIONS command. If bit 1 of word 85 is set to one, the Security Mode feature set has been enabled via the SECURITY SET PASSWORD command. If bit 1 of word 85 is cleared to zero, the Security Mode feature set has been disabled via the SECURITY DISABLE PASSWORD command. If bit 2 of word 85 is set to one, the Removable Media feature set is supported. Bit 3 of word 85 shall be set to oneindicating the mandatory Power Management feature set is supported. Bit 4 of word 85 shall be cleared to zero to indicate that the PACKET Command feature set is not supported. If bit 5 of word 85 is set to one, write cache has been enabled via the SET FEATURES command (see 8.46.10). If bit 5 of word 85 is cleared to zero, write cache has been disabled via the SET FEATURES command. If bit 6 of word 85 is set to one, look-ahead has been enabled via the SET FEATURES command (see 8.46.18). If bit 6 of word 85 is cleared to zero, look-ahead has been disabled via the SET FEATURES command. If bit 7 of word 85 is set to one, release interrupt has been enabled via the SET FEATURES command (see 8.46.19). If bit 7 of word 85 is cleared to zero, release interrupt has been disabled via the SET FEATURES command. If bit 8 of word 85 is set to one, SERVICE interrupt has been enabled via the SET FEATURES command (see 8.46.20). If bit 8 of word 85 is cleared to zero, SERVICE interrupt has been disabled via the SET FEATURES command. If bit 9 of word 85 is set to one, the DEVICE RESET command is supported. If bit 10 of word 85 is set to one, the Host Protected Area feature set is supported. Bit 11 of word 85 is obsolete. If bit 12 of word 85 is set to one, the device supports the WRITE BUFFER command. Page 129 T13/1410D revision 3b If bit 13 of word 85 is set to one, the device supports the READ BUFFER command. If bit 14 of word 85 is set to one, the device supports the NOP command. Bit 15 of word 85 is obsolete. If bit 0 of word 86 is set to one, the device supports the DOWNLOAD MICROCODE command. If bit 1 of word 86 is set to one, the device supports the READ DMA QUEUED and WRITE DMA QUEUED commands. If bit 2 of word 86 is set to one, the device supports the CFA feature set. If bit 3 of word 86 is set to one, the Advanced Power Management feature set has been enabled via the SET FEATURES command. If bit 3 of word 86 is cleared to zero, the Advanced Power Management feature set has been disabled via the SET FEATURES command. If bit 4 of word 86 is set to one, the Removable Media Status feature set has been enabled via the SET FEATURES command. If bit 4 of word 86 is cleared to zero, the Removable Media Status feature set has been disabled via the SET FEATURES command. If bit 5 of word 86 is set to one, the Power-Up In Standby feature set has been enabled via the SET FEATURES command (see 8.46.13). If bit 5 of word 86 is cleared to zero, the Power-Up In Standby feature set has been disabled via the SET FEATURES command If bit 6 of word 86 is set to one, the device requires the SET FEATURES subcommand to spin-up after power-up (see 8.46.15). Bit 7 of word 86 is defined in Address Offset Reserved Area Boot, NCITS TR27:2001. If bit 8 of word 86 is set to one, the device has had the SET MAX security extension enabled via a SET MAX SET PASSWORD command. If bit 9 of word 86 is set to one, the device has had the Automatic Acoustic Management feature set enabled via a SET FEATURES command and the value in word 94 is valid. If bit 10 of word 86 is set to one, the 48-bit Address feature set is supported. If bit 11 of word 86 is set to one, the device supports the Device Configuration Overlay feature set. Bit 12 of word 86 shall be set to oneindicating the device supports the mandatory FLUSH CACHE command. If bit 13 of word 86 is set to one, the device supports the FLUSH CACHE EXT command. If bit 0 of word 87 is set to one, the device supports SMART error logging. If bit 1 of word 87 is set to one, the device supports SMART self-test. If bit 2 of word 87 is set to one, the media serial number field in words (205:176) is valid. This bit shall be cleared to zero if the media does not contain a valid serial number or if no media is present. If bit 3 of word 87 is set to one, the Media Card Pass Through feature set has been enabled. If bit 4 of word 87 is reserved. Page 130 T13/1410D revision 3b If bit 5 of word 87 is set to one, the device supports the General Purpose Logging feature set. 8.15.44 Word 88: Ultra DMA modes Word 88 identifies the Ultra DMA transfer modes supported by the device and indicates the mode that is currently selected. Only one DMA mode shall be selected at any given time. If an Ultra DMA mode is selected, then no Multiword DMA mode shall be selected. If a Multiword DMA mode is selected, then no Ultra DMA mode shall be selected. Support of this word is mandatory if Ultra DMA is supported. 8.15.44.1 Reserved Bits (15:14) of word 88 are reserved. 8.15.44.2 Ultra DMA mode 5 selected If bit 13 of word 88 is set to one, then Ultra DMA mode 5 is selected. If this bit is cleared to zero, then Ultra DMA mode 5 is not selected. If bit 12 or bit 11 or bit 10 or bit 9 or bit 8 is set to one, then this bit shall be cleared to zero. 8.15.44.3 Ultra DMA mode 4 selected If bit 12 of word 88 is set to one, then Ultra DMA mode 4 is selected. If this bit is cleared to zero, then Ultra DMA mode 4 is not selected. If bit 13 or 11 or bit 10 or bit 9 or bit 8 is set to one, then this bit shall be cleared to zero. 8.15.44.4 Ultra DMA mode 3 selected If bit 11 of word 88 is set to one, then Ultra DMA mode 3 is selected. If this bit is cleared to zero, then Ultra DMA mode 3 is not selected. If bit 13 or 12 or bit 10 or bit 9 or bit 8 is set to one, then this bit shall be cleared to zero. 8.15.44.5 Ultra DMA mode 2 selected If bit 10 of word 88 is set to one, then Ultra DMA mode 2 is selected. If this bit is cleared to zero, then Ultra DMA mode 2 is not selected. If bit 13 or 12 or bit 11 or bit 9 or bit 8 is set to one, then this bit shall be cleared to zero. 8.15.44.6 Ultra DMA mode 1 selected If bit 9 of word 88 is set to one, then Ultra DMA mode 1 is selected. If this bit is cleared to zero then Ultra DMA mode 1 is not selected. If bit 13 or 12 or bit 11 or bit 10 or bit 8 is set to one, then this bit shall be cleared to zero. 8.15.44.7 Ultra DMA mode 0 selected If bit 8 of word 88 is set to one, then Ultra DMA mode 0 is selected. If this bit is cleared to zero then Ultra DMA mode 0 is not selected. If bit 13 or 12 or bit 11 or bit 10 or bit 9 is set to one, then this bit shall be cleared to zero. 8.15.44.8 Reserved Bits (7:6) of word 88 are reserved. Page 131 T13/1410D revision 3b 8.15.44.9 Ultra DMA mode 5 supported If bit 5 of word 88 is set to one, then Ultra DMA modes 5 and below are supported. If this bit is cleared to zero, then Ultra DMA mode 5 is not supported. If Ultra DMA mode 5 is supported, then Ultra DMA modes 4, 3, 2, 1 and 0 shall also be supported. If this bit is set to one, then bits (4:0) shall be set to one. 8.15.44.10 Ultra DMA mode 4 supported If bit 4 of word 88 is set to one, then Ultra DMA modes 4 and below are supported. If this bit is cleared to zero, then Ultra DMA mode 4 is not supported. If Ultra DMA mode 4 is supported, then Ultra DMA modes 3, 2, 1 and 0 shall also be supported. If this bit is set to one, then bits (3:0) shall be set to one. 8.15.44.11 Ultra DMA mode 3 supported If bit 3 of word 88 is set to one, then Ultra DMA modes 3 and below are supported. If this bit is cleared to zero, then Ultra DMA mode 3 is not supported. If Ultra DMA mode 3 is supported, then Ultra DMA modes 2, 1 and 0 shall also be supported. If this bit is set to one, then bits (2:0) shall be set to one. 8.15.44.12 Ultra DMA mode 2 supported If bit 2 of word 88 is set to one, then Ultra DMA modes 2 and below are supported. If this bit is cleared to zero, then Ultra DMA mode 2 is not supported. If Ultra DMA mode 2 is supported, then Ultra DMA modes 1 and 0 shall also be supported. If this bit is set to one, bits (1:0) shall be set to one. 8.15.44.13 Ultra DMA mode 1 supported If bit 1 of word 88 is set to one, then Ultra DMA modes 1 and below are supported. If this bit is cleared to zero, then Ultra DMA mode 1 is not supported. If Ultra DMA mode 1 is supported, then Ultra DMA mode 0 shall also be supported. If this bit is set to one, bit 0 shall be set to one. 8.15.44.14 Ultra DMA mode 0 supported If bit 0 of word 88 is set to one, then Ultra DMA mode 0 is supported. If this bit is cleared to zero, then Ultra DMA is not supported. 8.15.45 Word 89: Time required for Security erase unit completion Word 89 specifies the time required for the SECURITY ERASE UNIT command to complete. Support of this word is mandatory if the Security feature set is supported. Value 0 1-254 255 Time Value not specified (Value∗2) minutes >508 minutes 8.15.46 Word 90: Time required for Enhanced security erase unit completion Word 90 specifies the time required for the ENHANCED SECURITY ERASE UNIT command to complete. Support of this word is mandatory if support of the Enhanced Security feature set is supported. Value 0 1-254 255 Page 132 Time Value not specified (Value∗2) minutes >508 minutes T13/1410D revision 3b 8.15.47 Word 91: Advanced power management level value Bits (7:0) of word 91 contain the current Advanced Power Management level setting. Support of this word is mandatory if advanced power management is supported. 8.15.48 Word 92: Master Password Revision Code Word 92 contains the value of the Master Password Revision Code set when the Master Password was last changed. Valid values are 0001h through FFFEh. A value of 0000h or FFFFh indicates that the Master Password Revision is not supported. Support of this word is mandatory if the Security feature set is supported. 8.15.49 Word 93: Hardware configuration test results If bit 14 of word 93 is set to one and bit 15 of word 93 is cleared to zero, the content of word 93 contains valid information. During hardware reset execution, Device 0 shall clear bits (12:8) of this word to zero and shall set bits (7:0) of the word as indicated to show the result of the hardware reset execution. During hardware reset execution, Device 1 shall clear bits (7:0) of this word to zero and shall set bits (12:8) as indicated to show the result of the hardware reset execution. Support of bits (15:13) are mandatory. Support of bits (12:0) is optional. Bit 13 shall be set or cleared by the selected device to indicate whether the device detected CBLID- above VIH or below VIL at any time during execution of each IDENTIFY DEVICE routine after receiving the command from the host but before returning data to the host. This test may be repeated as desired by the device during command execution (see Annex B). 8.15.50 Word 94: Current automatic acoustic management value Bits (15:8) contain the device vendor’s recommended acoustic management level (see Table 47 for an enumeration of all of the possible acoustic management levels). If the host desires the drive to perform with highest performance, it should set the automatic acoustic management level to FEh. If the OEM host desires the vendor’s recommended acoustic management level as defined by the device’s vendor, the host should set the automatic acoustic management level to the value returned to the host in these 8 bits of the IDENTIFY DEVICE data. The use of this setting may not provide the lowest acoustics, or the best tradeoff of acoustics and performance, in all configurations. Support of this word is mandatory if the Acoustic Management feature set is supported. Bits (7:0) contain the current automatic acoustic management level. If the Automatic Acoustic Management feature set is supported by the device, but the level has not been set by the host, this byte shall contain the drive’s default setting. If the Automatic Acoustic Management feature set is not supported by the device, the value of this byte shall be zero. 8.15.51 Word (99:95): Reserved 8.15.52 Words (103:100): Maximum user LBA for 48-bit Address feature set Words (103:100) contain a value that is one greater than the maximum LBA in used addressable space when the 48-bit Addressing feature set is supported. The maximum value that shall be placed in this field is 0000FFFFFFFFFFFFh. Support of these words is mandatory if the 48-bit Address feature set is supported. 8.15.53 Words (126:104): Reserved 8.15.54 Word 127: Removable Media Status Notification feature set support If bit 0 of word 127 is set to one and bit 1 of word 127 is cleared to zero, the device supports the Removable Media Status Notification feature set. Bits (15:2) shall be cleared to zero. Support of this word is mandatory if the Removable Media Status Notification feature set is supported. Page 133 T13/1410D revision 3b 8.15.55 Word 128: Security status Support of this word is mandatory if the Security feature set is supported. Bit 8 of word 128 indicates the security level. If security mode is enabled and the security level is high, bit 8 shall be cleared to zero. If security mode is enabled and the security level is maximum, bit 8 shall be set to one. When security mode is disabled, bit 8 shall be cleared to zero. Bit 5 of word 128 indicates the Enhanced security erase unit feature is supported. If bit 5 is set to one, the Enhanced security erase unit feature set is supported. Bit 4 of word 128 indicates that the security count has expired. If bit 4 is set to one, the security count is expired and SECURITY UNLOCK and SECURITY ERASE UNIT are command aborted until a power-on reset or hardware reset. Bit 3 of word 128 indicates security Frozen. If bit 3 is set to one, the security is Frozen. Bit 2 of word 128 indicates security locked. If bit 2 is set to one, the security is locked. Bit 1 of word 128 indicates security enabled. If bit 1 is set to one, the security is enabled. Bit 0 of word 128 indicates the Security Mode feature set supported. If bit 0 is set to one, security is supported. 8.15.56 Words (159:129): Vendor specific. 8.15.57 Word 160: CFA power mode Word 160 indicates the presence and status of a CFA feature set device that supports CFA Power Mode 1. Support of this word is mandatory if CFA Power Mode 1 is supported. If bit 13 of word 160 is set to one then the device shall be in CFA Power Mode 1 to perform one or more commands implemented by the device. If bit 12 of word 160 is set to one the device is in CFA Power Mode 0 (see 8.46.14). Bits (11:0) indicate the maximum average RMS current in Milliamperes required during 3.3V or 5V device operation in CFA Power Mode 1. 8.15.58 Words (175:161): Reserved for assignment by the CompactFlash Association 8.15.59 Words (205:176): Current media serial number Words (205:176) contain the current media serial number. Serial numbers shall consist of 60 bytes. The first 40 bytes shall indicate the media serial number and the remaining 20 bytes shall indicate the media manufacturer. For removable ATA devices (e.g., flash media with native ATA interfaces) that do not support removable media, the first 20 words of this field shall be the same as words (46:27) of the IDENTIFY DEVICE response and the next ten words shall be the same as words (19:10) of the IDENTIFY DEVICE response. 8.15.60 Words (254:206): Reserved. 8.15.61 Word 255: Integrity word The use of this word is optional. If bits (7:0) of this word contain the signature A5h, bits (15:8) contain the data structure checksum. The data structure checksum is the two’s complement of the sum of all bytes in words Page 134 T13/1410D revision 3b (254:0) and the byte consisting of bits (7:0) in word 255. Each byte shall be added with unsigned arithmetic, and overflow shall be ignored. The sum of all 512 bytes is zero when the checksum is correct. 8.16 IDENTIFY PACKET DEVICE 8.16.1 Command code A1h 8.16.2 Feature set PACKET Command feature set − Use prohibited for devices not implementing the PACKET Command feature set. − Mandatory for devices implementing the PACKET Command feature set. 8.16.3 Protocol PIO data-in (see 9.5). 8.16.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na 3 2 1 0 na DRQ na na na na na ERR na na na na na obs na obs DEV A1h Device register DEV shall specify the selected device. 8.16.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. Page 135 T13/1410D revision 3b 8.16.6 Error outputs The device shall return command aborted if the device does not implement this command, otherwise, the device shall not report an error. 8.16.7 Prerequisites This command shall be accepted regardless of the state of DRDY. 8.16.8 Description The IDENTIFY PACKET DEVICE command enables the host to receive parameter information from a device that implements the PACKET Command feature set. Some devices may have to read the media in order to complete this command. When the command is issued, the device sets the BSY bit to one, prepares to transfer the 256 words of device identification data to the host, sets the DRQ bit to one, clears the BSY bit to zero, and asserts INTRQ if nIEN is cleared to zero. The host may then transfer the data by reading the Data register. Table 29 defines the arrangement and meanings of the parameter words in the buffer. All reserved bits or words shall be zero. Some parameters are defined as a group of bits. A word that is defined as a set of bits is transmitted with indicated bits on the respective data bus bit (e.g., bit 15 appears on DD15). Some parameters are defined as a 16-bit value. A word that is defined as a 16-bit value places the most significant bit of the value on bit DD15 and the least significant bit on bit DD0 (see 3.2.9). Some parameters are defined as 32-bit values (e.g., words (61:60)). Such fields are transferred using two word transfers. The device shall first transfer the least significant bits, bits (15:0) of the value, on bits DD(15:0) respectively. After the least significant bits have been transferred, the most significant bits, bits (31:16) of the value, shall be transferred on DD(15:0) respectively (see 3.2.9). Some parameters are defined as a string of ASCII characters (see 3.2.9). Page 136 T13/1410D revision 3b Table 29 − IDENTIFY PACKET DEVICE information Word 0 O/M M F/V F F F F F F F V F 1 2 3-9 10-19 20-22 23-26 27-46 47-48 49 M M M F V F F F F F F M F F F F F F F F X 50 51-52 53 O M F F F X F X F F F 54-62 X F Description General configuration bit-significant information: 15-14 10 = ATAPI device 11 = Reserved 13 Reserved 12-8 Field indicates command packet set used by device 7 1 = removable media device 6-5 00 = Device shall set DRQ to one within 3 ms of receiving PACKET command. 01 = Obsolete. 10 = Device shall set DRQ to one within 50 µs of receiving PACKET command. 11 = Reserved 4-3 Reserved 2 Incomplete response 1-0 00 = 12 byte command packet 01 = 16 byte command packet 1x = Reserved Reserved Unique configuration Reserved Serial number (20 ASCII characters) Reserved Firmware revision (8 ASCII characters) Model number (40 ASCII characters) Reserved Capabilities 15 1 = interleaved DMA supported 14 1 = command queuing supported 13 1 = overlap operation supported 12 1 = ATA software reset required (Obsolete) 11 1 = IORDY supported 10 1 = IORDY may be disabled 9 Shall be set to one. 8 1 = DMA supported 7-0 Vendor specific Capabilities 15 Shall be cleared to zero. 14 Shall be set to one. 13-2 Reserved 1 Obsolete 0 Shall be set to one to indicate a device specific Standby timer value minimum. Obsolete 15-3 Reserved 2 1 = the fields reported in word 88 are valid 0 = the fields reported in word 88 are not valid 1 1 = the fields reported in words (70:64) are valid 0 = the fields reported in words (70:64) are not valid 0 Obsolete Reserved (continued) Page 137 T13/1410D revision 3b Table 29 − IDENTIFY PACKET DEVICE information (continued) Word 63 O/M M F/V F V V V 64 M 65 M 66 M 67 M 68 M F F F F F F F F F 69-70 71 72 73-74 75 76-79 80 O O F F F F F O F F R M F F F F F F F F F F F F F X X F 81 M Description 15-11 Reserved 10 1 = Multiword DMA mode 2 is selected 0 = Multiword DMA mode 2 is not selected 9 1 = Multiword DMA mode 1 is selected 0 = Multiword DMA mode 1 is not selected 8 1 = Multiword DMA mode 0 is selected 0 = Multiword DMA mode 0 is not selected 7-3 Reserved 2 1 = Multiword DMA mode 2 and below are supported 1 1 = Multiword DMA mode 1 and below are supported 0 1 = Multiword DMA mode 0 is supported Multiword DMA mode selected 15-8 Reserved 7-0 PIO transfer modes supported Minimum Multiword DMA transfer cycle time per word 15-0 Cycle time in nanoseconds Manufacturer’s recommended Multiword DMA transfer cycle time 15-0 Cycle time in nanoseconds Minimum PIO transfer cycle time without flow control 15-0 Cycle time in nanoseconds Minimum PIO transfer cycle time with IORDY flow control 15-0 Cycle time in nanoseconds Reserved (for future command overlap and queuing) Typical time in ns from receipt of PACKET command to bus release. Typical time in ns from receipt of SERVICE command to BSY cleared to zero Reserved Queue depth 15-5 Reserved 4-0 Maximum queue depth supported - 1 Reserved Major version number 0000h or FFFFh = device does not report version 15 Reserved 14 Reserved for ATA/ATAPI-14 13 Reserved for ATA/ATAPI-13 12 Reserved for ATA/ATAPI-12 11 Reserved for ATA/ATAPI-11 10 Reserved for ATA/ATAPI-10 9 Reserved for ATA/ATAPI-9 8 Reserved for ATA/ATAPI-8 7 Reserved for ATA/ATAPI-7 6 1 = supports ATA/ATAPI-6 5 1 = supports ATA/ATAPI-5 4 1 = supports ATA/ATAPI-4 3 1 = supports ATA-3 2 Obsolete 1 Obsolete 0 Reserved Minor version number 0000h or FFFFh=device does not report version 0001h-FFFEh=see 8.15.41 (continued) Page 138 T13/1410D revision 3b Table 29 − IDENTIFY PACKET DEVICE information (continued) Word 82 O/M M F/V X F F F X F F F F F F F F F F F 83 M F F F F F F F F F F F F F F 84 M F F F Description Command set supported. If words (83:82) = 0000h or FFFFh command set notification not supported. 15 Obsolete 14 1 = NOP command supported 13 1 = READ BUFFER command supported 12 1 = WRITE BUFFER command supported 11 Obsolete 10 1 = Host Protected Area feature set supported 9 1 = DEVICE RESET command supported 8 1 = SERVICE interrupt supported 7 1 = release interrupt supported 6 1 = look-ahead supported 5 1 = write cache supported 4 Shall be set to one indicating the PACKET Command feature set is supported. 3 1 = Power Management feature set supported 2 1 = Removable Media feature set supported 1 1 = Security Mode feature set supported 0 1 = SMART feature set supported Command sets supported. If words (83:82) = 0000h or FFFFh command set notification not supported. 15 Shall be cleared to zero 14 Shall be set to one 13 Reserved 12 1 = FLUSH CACHE command supported 11 1 = Device Configuration Overlay feature set supported 10 Reserved 9 1 = Automatic Acoustic Management feature set supported 8 1 = SET MAX security extension supported 7 See Address Offset Reserved Area Boot, NCITS TR27:2001 6 1 = SET FEATURES subcommand required to spinup after power-up 5 1 = Power-Up In Standby feature set supported 4 1 = Removable Media Status Notification feature set supported 3-1 Reserved 0 1 = DOWNLOAD MICROCODE command supported Command set/feature supported extension. If words 82, 83, and 84 = 0000h or FFFFh command set notification extension is not supported. 15 Shall be cleared to zero 14 Shall be set to one 13-0 Reserved (continued) Page 139 T13/1410D revision 3b Table 29 − IDENTIFY PACKET DEVICE information (continued) Word 85 O/M M F/V X F F F X V F V V V V F F V V V 86 M F V F F V V V F V V F F 87 M F F F Description Command set/feature enabled. If words 85, 86, and 87 = 0000h or FFFFh command set enabled notification is not supported. 15 Obsolete 14 1 = NOP command enabled 13 1 = READ BUFFER command enabled 12 1 = WRITE BUFFER command enabled 11 Obsolete 10 1 = Host Protected Area feature set enabled 9 1 = DEVICE RESET command enabled 8 1 = SERVICE interrupt enabled 7 1 = release interrupt enabled 6 1 = look-ahead enabled 5 1 = write cache enabled 4 Shall be set to one indicating the PACKET Command feature set is supported. 3 1 = Power Management feature set enabled 2 1 = Removable Media feature set enabled 1 1 = Security Mode feature set enabled 0 1 = SMART feature set enabled Command set/feature enabled. If words 85, 86, and 87 = 0000h or FFFFh command set enabled notification is not supported. 15-13 Reserved 12 1 = FLUSH CACHE command supported 11 1 = Device Configuration Overlay feature set supported 10 Reserved 9 1 = Automatic Acoustic Management feature set enabled 8 1 = SET MAX security extension enabled by a SET MAX SET PASSWORD 7 See Address Offset Reserved Area Boot, NCITS TR27:2001 6 1 = SET FEATURES subcommand required to spinup after power-up 5 1 = Power-Up In Standby feature set enabled 4 1 = Removable Media Status Notification feature set enabled via the SET FEATURES command. 3-1 Reserved 0 1 = DOWNLOAD MICROCODE command enabled Command set/feature default. If words 85, 86, and 87 = 0000h or FFFFh command set default notification is not supported. 15 Shall be cleared to zero 14 Shall be set to one 13-0 Reserved (continued) Page 140 T13/1410D revision 3b Table 29 − IDENTIFY PACKET DEVICE information (continued) Word 88 O/M M F/V F V V V V V V 89-92 F F F F F F F F Description 15-14 Reserved 13 1 = Ultra DMA mode 5 is selected 0 = Ultra DMA mode 5 is not selected 12 1 = Ultra DMA mode 4 is selected 0 = Ultra DMA mode 4 is not selected 11 1 = Ultra DMA mode 3 is selected 0 = Ultra DMA mode 3 is not selected 10 1 = Ultra DMA mode 2 is selected 0 = Ultra DMA mode 2 is not selected 9 1 = Ultra DMA mode 1 is selected 0 = Ultra DMA mode 1 is not selected 8 1 = Ultra DMA mode 0 is selected 0 = Ultra DMA mode 0 is not selected 7-6 Reserved 5 1 = Ultra DMA mode 5 and below are supported 4 1 = Ultra DMA mode 4 and below are supported 3 1 = Ultra DMA mode 3 and below are supported 2 1 = Ultra DMA mode 2 and below are supported 1 1 = Ultra DMA mode 1 and below are supported 0 1 = Ultra DMA mode 0 is supported Reserved (continued) Page 141 T13/1410D revision 3b Table 29 − IDENTIFY PACKET DEVICE information (continued) Word 93 O/M * F/V F F V F V V F F F V V V 94-124 125 126 127 M F V V V F F F X O F F Description Hardware reset result. The contents of bits (12:0) of this word shall change only during the execution of a hardware reset. 15 Shall be cleared to zero. 14 Shall be set to one. 13 1 = device detected CBLID- above ViH 0 = device detected CBLID- below ViL 12-8 Device 1 hardware reset result. Device 0 shall clear these bits to zero. Device 1 shall set these bits as follows: 12 Reserved. 11 0 = Device 1 did not assert PDIAG-. 1 = Device 1 asserted PDIAG-. 10-9 These bits indicate how Device 1 determined the device number: 00 = Reserved. 01 = a jumper was used. 10 = the CSEL signal was used. 11 = some other method was used or the method is unknown. 8 Shall be set to one. 7-0 Device 0 hardware reset result. Device 1 shall clear these bits to zero. Device 0 shall set these bits as follows: 7 Reserved. 6 0 = Device 0 does not respond when Device 1 is selected. 1 = Device 0 responds when Device 1 is selected. 5 0 = Device 0 did not detect the assertion of DASP-. 1 = Device 0 detected the assertion of DASP-. 4 0 = Device 0 did not detect the assertion of PDIAG-. 1 = Device 0 detected the assertion of PDIAG-. 3 0 = Device 0 failed diagnostics. 1 = Device 0 passed diagnostics. 2-1 These bits indicate how Device 0 determined the device number: 00 = Reserved. 01 = a jumper was used. 10 = the CSEL signal was used. 11 = some other method was used or the method is unknown. 0 Shall be set to one. Reserved ATAPI byte count = 0 behavior Obsolete Removable Media Status Notification feature set support 15-2 Reserved 1-0 00 = Removable Media Status Notification feature set not supported 01 = Removable Media Status Notification feature set supported 10 = Reserved 11 = Reserved (continued) Page 142 T13/1410D revision 3b Word 128 O/M O 129-159 160-175 176-254 255 O Table 29 − IDENTIFY PACKET DEVICE information (concluded) F/V Description Security status F 15-9 Reserved V 8 Security level 0 = High, 1 = Maximum F 7-6 Reserved F 5 1 = Enhanced security erase supported V 4 1 = Security count expired V 3 1 = Security frozen V 2 1 = Security locked V 1 1 = Security enabled F 0 1 = Security supported X Vendor specific F Reserved for assignment by the CompactFlash Association F Reserved X Integrity word 15-8 Checksum 7-0 Signature Key: O/M = Mandatory/optional requirement. M = Support of the word is mandatory. O = Support of the word is optional. * = see 8.15.49. F/V = Fixed/variable content. F = the content of the word is fixed and does not change. For removable media devices, these values may change when media is removed or changed. V = the contents of the word is variable and may change depending on the state of the device or the commands executed by the device. X = the content of the word may be fixed or variable. 8.16.9 Word 0: General configuration Bits (15:14) of word 0 indicate the type of device. Bit 15 shall be set to one and bit 14 shall be cleared to zeroto indicate the device implements the PACKET Command feature set. Bits (12:8) of word 0 indicate the command packet set implemented by the device. This value follows the peripheral device type value as defined in SCSI Primary Commands, ANSI NCITS 301:1997. Page 143 T13/1410D revision 3b Value 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0A-0Bh 0Ch 0Dh 0Eh 0Fh 10-1Eh 1Fh Description Direct-access device Sequential-access device Printer device Processor device Write-once device CD-ROM device Scanner device Optical memory device Medium changer device Communications device Reserved for ACS IT8 (Graphic arts pre-press devices) Array controller device Enclosure services device Reduced block command devices Optical card reader/writer device Reserved Unknown or no device type Bit 7 if set to one indicates that the device has removable media. Bits (6:5) of word 0 indicate the DRQ response time when a PACKET command is received. A value of 00b indicates a maximum time of 3 ms from receipt of PACKET to the setting of DRQ to one. A value of 10b indicates a maximum time of 50 µs from the receipt of PACKET to the setting of DRQ to one. The value 11b is reserved. If bit 2 is set to one it indicates that the content of the IDENTIFY DEVICE response is incomplete. This will occur if the device supports the Power-up in Standby feature set and required data is contained on the device media. In this case the content of at least word 0 and word 2 shall be valid. Bits (1:0) of word 0 indicate the packet size the device supports. A value of 00b indicates that a 12-byte packet is supported; a value of 01b indicates a 16 byte packet. The values 10b and 11b are reserved. 8.16.10 Word 1: Reserved 8.16.11 Word 2: Specific configuration Word 2 shall have the same content described for word 2 of the IDENTIFY DEVICE command. 8.16.12 Words (9:3): Reserved 8.16.13 Words (19:10): Serial number The use of these words is optional. If not implemented, the content shall be zeros. If implemented, the content shall be as described in words (19:10) of the IDENTIFY DEVICE command (see 8.15). 8.16.14 Words (22:20): Reserved 8.16.15 Words (26:23): Firmware revision Words (26:23) shall have the content described for words (26:23) of the IDENTIFY DEVICE command. Page 144 T13/1410D revision 3b 8.16.16 Words (46:27): Model number Words (46:27) shall have the content described for words (46:27) of the IDENTIFY DEVICE command. 8.16.17 Words (48:47): Reserved 8.16.18 Word 49: Capabilities Bit 15 of word 49 is used to indicate that the device supports interleaved DMA data transfer for overlapped DMA commands. Bit 14 of word 49 is used to indicate that the device supports command queuing for overlapped commands. If bit 14 is set to one, bit 13 shall be set to one. Bit 13 of word 49 is used to indicate that the device supports command overlap operation. Bit 12 of word 49 is obsolete. Bit 11 of word 49 is used to determine whether a device supports IORDY. If this bit is set to one, then the device supports IORDY operation. If this bit is zero, the device may support IORDY. This ensures backward compatibility. If a device supports PIO mode 3 or higher, then this bit shall be set to one. Bit 10 of word 49 is used to indicate a device’s ability to enable or disable the use of IORDY. If this bit is set to one, then the device supports the disabling of IORDY. Disabling and enabling of IORDY is accomplished using the SET FEATURES command. Bit 9 of word 49 shall be set to one. Bit 8 of word 49 indicates that DMA is supported. 8.16.19 Word 50: Capabilities Word 50 shall have the content described for word 50 of the IDENTIFY DEVICE command. Support of this word is mandatory if the STANDBY command is supported. 8.16.20 Word 51: Obsolete 8.16.21 Word 52: Reserved 8.16.22 Word 53: Field validity Word 53 shall have the content described for word 53 of the IDENTIFY DEVICE command. 8.16.23 Words (62:54): Reserved 8.16.24 Word 63: Multiword DMA transfer Word 63 shall have the content described for word 63 of the IDENTIFY DEVICE command. 8.16.25 Word 64: PIO transfer mode supported Word 64 shall have the content described for word 64 of the IDENTIFY DEVICE command. Page 145 T13/1410D revision 3b 8.16.26 Word 65: Minimum multiword DMA transfer cycle time per word Word 65 shall have the content described for word 65 of the IDENTIFY DEVICE command. 8.16.27 Word 66: Device recommended multiword DMA cycle time Word 66 shall have the content described for word 66 of the IDENTIFY DEVICE command. 8.16.28 Word 67: Minimum PIO transfer cycle time without flow control Word 67 shall have the content described for word 67 of the IDENTIFY DEVICE command. 8.16.29 Word 68: Minimum PIO transfer cycle time with IORDY Word 68 shall have the content described for word 68 of the IDENTIFY DEVICE command. 8.16.30 Word (70:69): Reserved 8.16.31 Word 71: PACKET to bus release time Word 71 shall contain the time (for 99.7% of the occurances) in microseconds from the receipt of a PACKET command until the device performs a bus release. Support of this word is mandatory if the Overlap or Queuing feature set is supported. 8.16.32 Word 72: SERVICE to bus release time Word 72 shall contain the time (for 99.7% of the occurances) in microseconds from the receipt of a SERVICE command until the device performs a bus release. Support of this word is mandatory if the Overlap or Queuing feature set is supported. 8.16.33 Word (74:73): Reserved 8.16.34 Word 75: Queue depth Bits (4:0) of word 75 shall have the content described for word 75 of the IDENTIFY DEVICE command. Support of this word is mandatory if the Queuing feature set is supported. 8.16.35 Words (79:76): Reserved 8.16.36 Word 80: Major revision number Word 80 shall have the content described for word 80 of the IDENTIFY DEVICE command. 8.16.37 Word 81: Minor revision number Word 81 shall have the content described for word 81 of the IDENTIFY DEVICE command. 8.16.38 Words (84:82): Features/command sets supported Words (84:82) shall have the content described for words (84:82) of the IDENTIFY DEVICE command except that bit 4 of word 82 shall be set to one to indicate that the PACKET Command feature set is supported. Page 146 T13/1410D revision 3b 8.16.39 Words (87:85): Features/command sets enabled Words (87:85) shall have the content described for words (87:85) of the IDENTIFY DEVICE command except that bit 4 of word 85 shall be set to one to indicate that the PACKET Command feature set is supported. 8.16.40 Word 88:Ultra DMA modes Word 88 shall have the content described for word 88 of the IDENTIFY DEVICE command. 8.16.41 Word 89: Time required for Security erase unit completion Word 89 shall have the content described for word 89 of the IDENTIFY DEVICE command. 8.16.42 Word 90: Time required for Enhanced security erase unit completion Word 90 shall have the content described for word 90 of the IDENTIFY DEVICE command. 8.16.43 Word (92:91): Reserved 8.16.44 Word 93: Hardware reset results Word 93 shall have the content described for word 93 of the IDENTIFY DEVICE command. Support of bits (13:15) is mandatory. Support of bits (12:0) is optional. 8.16.45 Word (124:94): Reserved 8.16.46 Word 125 ATAPI byte count=0 behavior. If the contents of word 125 are 0000h and the value of the byte count limit is zero, the device shall return command aborted. If the contents of word 125 are non-zero and the value of the byte count limit is zero, the device shall use the contents of word 125 as the actual byte count limit for the current command and shall not abort. The device may be reconfigured to report a new value. However, after the device is reconfigured, the content of word 125 reported shall not change until after the next hardware reset or power-on reset event. 8.16.47 Word 126: Obsolete 8.16.48 Word 127: Removable Media Status Notification feature set support Word 127 shall have the content described for word 127 of the IDENTIFY DEVICE command. Support of this word is mandatory if the Removable Media Status Notification feature set is supported. 8.16.49 Word 128: Security status Word 128 shall have the content described for word 128 of the IDENTIFY DEVICE command. Support of this word is mandatory if the Security feature set is supported. 8.16.50 Words (160:129): Reserved 8.16.51 Words (175:161): Reserved for assignment by the CompactFlash Association 8.16.52 Words (254:176): Reserved Page 147 T13/1410D revision 3b 8.16.53 Word 255: Integrity Word Word 255 shall have the content described for word 255 of the IDENTIFY DEVICE command. Word 255 should be implemented. 8.17 IDLE 8.17.1 Command code E3h 8.17.2 Feature set Power Management feature set. − This command is mandatory for devices not implementing the PACKET Command feature set. − Power Management feature set is mandatory when power management is not implemented by the PACKET command set implemented by the device. − This command is mandatory when the Power Management feature set is implemented. 8.17.3 Protocol Non-data (see 9.4). 8.17.4 Inputs Values other than zero in the Sector Count register when the IDLE command is issued shall determine the time period programmed into the Standby timer. Table 30 defines these values. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs na obs 4 3 na Timer period value na na na DEV na E3h 2 1 0 na na na Device register DEV shall indicate the selected device. Table 30 − Automatic Standby timer periods Sector Count register Corresponding timeout period contents 0 (00h) Timeout disabled 1-240 (01h-F0h) (value ∗ 5) s 241-251 (F1h-FBh) ((value - 240) ∗30) min 252 (FCh) 21 min 253 (FDh) Period between 8 and 12 hrs 254 (FEh) Reserved 255 (FFh) 21 min 15 s NOTE − Times are approximate. Page 148 T13/1410D revision 3b 8.17.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na DRQ na na na na na ERR na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.17.6 Error outputs The device shall return command aborted if the device does not support the Power Management feature set. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT 1 na 0 na na DRQ na na na na na ERR na na na na obs BSY na DRDY obs DF DEV na Error register ABRT shall be set to one if Power Management feature set is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.17.7 Prerequisites DRDY set to one. 8.17.8 Description The IDLE command allows the host to place the device in the Idle mode and also set the Standby timer. INTRQ may be asserted even though the device may not have fully transitioned to Idle mode. Page 149 T13/1410D revision 3b If the Sector Count register is non-zero then the Standby timer shall be enabled. The value in the Sector Count register shall be used to determine the time programmed into the Standby timer (see 6.11). If the Sector Count register is zero then the Standby timer is disabled. 8.18 IDLE IMMEDIATE 8.18.1 Command code E1h 8.18.2 Feature set Power Management feature set. − − − This command is mandatory for devices not implementing the PACKET Command feature set. Power Management feature set is mandatory when power management is not implemented by the PACKET command set implemented by the device. This command is mandatory when the Power Management feature set is implemented. 8.18.3 Protocol Non-data (see 9.4). 8.18.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na 3 2 1 0 na DRQ na na na na na ERR na na na na na obs na obs DEV E1h Device register DEV shall specify the selected device. 8.18.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. Page 150 T13/1410D revision 3b DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.18.6 Error outputs The device shall return command aborted if the device does not support the Power Management feature set. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT 1 na 0 na na DRQ na na na na na ERR na na na na obs BSY na DRDY obs DF DEV na Error register ABRT shall be set to one if Power Management feature set is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.18.7 Prerequisites DRDY set to one. 8.18.8 Description The IDLE IMMEDIATE command allows the host to immediately place the device in the Idle mode. INTRQ may be asserted even though the device may not have fully transitioned to Idle mode (see 6.11). 8.19 MEDIA EJECT 8.19.1 Command code EDh 8.19.2 Feature set Removable Media Status Notification feature set − − Mandatory for devices not implementing the PACKET command feature set and implementing the Removable Media Status Notification feature set. Prohibited for devices implementing the PACKET command feature set. Removable Media feature set − Mandatory for devices not implementing the PACKET command feature set and implementing the Removable Media feature set. Page 151 T13/1410D revision 3b − Prohibited for devices implementing the PACKET command feature set. 8.19.3 Protocol Non-data (see 9.4). 8.19.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na 3 2 1 0 na DRQ na na na na na ERR na na na na na obs na obs DEV EDh Device register DEV shall specify the selected device. 8.19.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.19.6 Error outputs If the device does not support this command, the device shall return command aborted. Register Error Sector Count LBA Low LBA Mid LBA High Device Status Page 152 7 na 6 na 5 na 4 na 3 na 2 ABRT 1 NM 0 obs na DRQ na na na na na ERR na na na na obs BSY na DRDY obs DF DEV na T13/1410D revision 3b Error register ABRT shall be set to one if device does not support this command. ABRT may be set to one if the device is not able to complete the action requested by the command. NM (No Media) shall be set to one if no media is present in the device. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.19.7 Prerequisites DRDY set to one. 8.19.8 Description This command causes any pending operations to complete, spins down the device if needed, unlocks the media if locked, and ejects the media. The device keeps track of only one level of media lock. 8.20 MEDIA LOCK 8.20.1 Command code DEh 8.20.2 Feature set Removable Media Status Notification feature set − − Optional for devices not implementing the PACKET command feature set and implementing the Removable Media Status Notification feature set. Prohibited for device implementing the PACKET command feature set. Removable Media feature set − Mandatory for devices not implementing the PACKET command feature set and implementing the Removable Media feature set. − Prohibited for devices implementing the PACKET command feature set. 8.20.3 Protocol Non-data (see 9.4). Page 153 T13/1410D revision 3b 8.20.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na 3 2 1 0 na DRQ na na na na na ERR na na na na na obs na obs DEV DEh Device register DEV shall specify the selected device. 8.20.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.20.6 Error outputs If the device does not support this command, the device shall return command aborted. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 MCR 2 ABRT 1 NM 0 obs na DRQ na na na na na ERR na na na na obs BSY na DRDY obs DF DEV na Error register ABRT shall be set to one if device does not support this command. ABRT may be set to one if the device is not able to complete the action requested by the command. NM (No Media) shall be set to one if no media is present in the device. MCR (Media Change Request) shall be set to one if the device is locked and a media change request has been detected by the device. Device register Page 154 T13/1410D revision 3b DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.20.7 Prerequisites DRDY set to one. 8.20.8 Description This command shall be used to lock the media, if Media Status Notification is disabled. If Media Status Notification is enabled, this command shall return good status (no ERR bit in the Status register) and perform no action. If the media is unlocked and media is present, the media shall be set to the LOCKED state and no Error register bit shall be set to one. The device keeps track of only one level of media lock. Subsequent MEDIA LOCK commands, while the media is in the LOCKED state, do not set additional levels of media locks. If the media is locked, the status returned shall indicate whether a media change request has been detected by the device. If a media change request has been detected, the MCR bit in the Error register and the ERR bit in the Status register shall be set to one. When media is in the LOCKED state, the device shall respond to the media change request button, by setting the MCR bit in the Error register and the ERR bit in the Status register to one, until the media LOCKED condition is cleared. 8.21 MEDIA UNLOCK 8.21.1 Command code DFh 8.21.2 Feature set Removable Media Status Notification feature set − − Optional for devices not implementing the PACKET command feature set and implementing the Removable Media Status Notification feature set. Prohibited for devices implementing the PACKET command feature set. Removable Media feature set − Mandatory for devices not implementing the PACKET command feature set and implementing the Removable Media feature set. − Prohibited for devices implementing the PACKET command feature set. 8.21.3 Protocol Non-data (see 9.4). Page 155 T13/1410D revision 3b 8.21.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na 3 2 1 0 na DRQ na na na na na ERR na na na na na obs na obs DEV DFh Device register DEV shall specify the selected device. 8.21.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.21.6 Error outputs If the device does not support this command, the device shall return command aborted. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT 1 NM 0 obs na DRQ na na na na na ERR na na na na obs BSY na DRDY obs DF DEV na Error register ABRT shall be set to one if device does not support this command. ABRT may be set to one if the device is not able to complete the action requested by the command. NM (No Media) shall be set to one if no media is present in the device. Device register DEV shall indicate the selected device. Status register Page 156 T13/1410D revision 3b BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.21.7 Prerequisites DRDY set to one. 8.21.8 Description This command can be used to unlock the device, if Media Status Notification is disabled. If Media Status Notification is enabled, this command will return good status (no ERR bit in the Status register) and perform no action. If the media is present, the media shall be set to the UNLOCKED state and no Error register bit shall be set to one. The device keeps track of only one level of media lock. A single MEDIA UNLOCK command unlocks the media. If a media change request has been detected by the device prior to the issuance of this command, the media shall be ejected at MEDIA UNLOCK command completion. 8.22 NOP 8.22.1 Command code 00h 8.22.2 Feature set General feature set − − − Optional for devices not implementing the PACKET Command feature set. Mandatory for devices implementing the PACKET Command feature set. Mandatory for devices implementing the Overlapped feature set. 8.22.3 Protocol Non-data (see 9.4). 8.22.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs na obs 4 3 Subcommand code na na na na DEV na 00h 2 1 0 na na na Page 157 T13/1410D revision 3b Features register Subcommand code 00h Description 01h NOP Auto Poll 02h-FFh Reserved NOP Action Return command aborted and abort any outstanding queued commands. Return command aborted and do not abort any outstanding queued commands. Return command aborted and do not abort any outstanding queued commands. Device register DEV shall specify the selected device. 8.22.5 Normal outputs This command always fails with an error. 8.22.6 Error outputs The Command Block registers, other than the Error and Status registers, are not changed by this command. This command always fails with the device returning command aborted. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na BSY DRDY DF 4 3 na na Initial value Initial value Initial value Initial value Initial value na DRQ 2 ABRT 1 na 0 na na na ERR Error register ABRT shall be set to one. Sector Count, LBA Low, LBA Mid, LBA High, Device value set by host is not changed. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one. 8.22.7 Prerequisites DRDY set to one. 8.22.8 Description The device shall respond with command aborted. For devices implementing the Overlapped feature set, subcommand code 00h in the Features register shall abort any outstanding queue. Subcommand codes 01h through FFh in the Features register shall not affect the status of any outstanding queue. Page 158 T13/1410D revision 3b 8.23 PACKET 8.23.1 Command code A0h 8.23.2 Feature set PACKET Command feature set − − Use prohibited for devices not implementing the PACKET Command feature set. Mandatory for devices implementing the PACKET Command feature set. 8.23.3 Protocol Packet (see 9.8). 8.23.4 Inputs Register Features Sector Count LBA Low Byte Count low (LBA Mid) Byte Count high (LBA High) Device Command 7 na 6 na 5 na Tag 4 na 3 na 2 na 1 OVL na na na 0 DMA na Byte Count limit (7:0) Byte Count limit (15:8) obs na obs DEV na na A0h Features register OVL - This bit is set to one to inform the device that the PACKET command is to be overlapped. DMA - This bit is set to one to inform the device that the data transfer (not the command packet transfer) associated with this command is via Multiword DMA or Ultra DMA mode. Sector Count register Tag - If the device supports command queuing, this field contains the command Tag for the command being delivered. A Tag may have any value between 0 and 31 regardless of the queue depth supported. If queuing is not supported, this field is not applicable. Byte Count low and Byte Count high registers These registers are written by the host with the maximum byte count that is to be transferred in any single DRQ assertion for PIO transfers. The byte count does not apply to the command packet transfer. If the PACKET command does not transfer data, the byte count is ignored. If the PACKET command results in a data transfer: 1) the host should not set the byte count limit to zero. If the host sets the byte count limit to zero, the contents of IDENTIFY PACKET DEVICE word 125 determines the expected behavior; 2) the value set into the byte count limit shall be even if the total requested data transfer length is greater than the byte count limit; 3) the value set into the byte count limit may be odd if the total requested data transfer length is equal to or less than the byte count limit; 4) the value FFFFh is interpreted by the device as though the value were FFFEh. Device register DEV shall specify the selected device. Page 159 T13/1410D revision 3b 8.23.5 Normal outputs 8.23.5.1 Awaiting command When the device is ready to accept the command packet from the host the register content shall be as shown below. Register Error Interrupt reason (Sector Count) LBA Low Byte Count low (LBA Mid) Byte Count high (LBA High) Device Status 7 6 5 4 3 2 1 0 REL I/O C/D na na na na na CHK na Tag na Byte Count (7:0) Byte Count (15:8) obs BSY na na obs DMRD DEV SERV na DRQ Byte Count High/Low - shall reflect the value set by the host when the command was issued. Interrupt reason register Tag - If the device supports command queuing and overlap is enabled, this field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this field is not applicable. REL - Shall be cleared to zero. I/O - Shall be cleared to zero indicating transfer to the device. C/D - Shall be set to one indicating the transfer of a command packet. Device register DEV shall indicate the selected device. Status register BSY - Shall be cleared to zero. DMRD (DMA ready) - Shall be cleared to zero. SERV (Service) - Shall be set to one if another command is ready to be serviced. If overlap is not supported, this bit is command specific. DRQ - Shall be set to one. CHK - Shall be cleared to zero. 8.23.5.2 Data transmission If overlap is not supported or not specified by the command, data transfer shall occur after the receipt of the command packet. If overlap is supported and the command specifies that the command may be overlapped, data transfer may occur after receipt of the command packet or may occur after the receipt of a SERVICE command. When the device is ready to transfer data requested by a data transfer command, the device sets the following register content to initiate the data transfer. Page 160 T13/1410D revision 3b Register Error Interrupt reason (Sector Count) LBA Low Byte Count low (LBA Mid) Byte Count high (LBA High) Device Status 7 6 5 4 3 2 1 0 REL I/O C/D na na na na na CHK na Tag na Byte Count (7:0) Byte Count (15:8) obs BSY na na obs DMRD DEV SERV na DRQ Byte Count High/Low - If the transfer is to be in PIO mode, the byte count of the data to be transferred for this DRQ assertion shall be presented. Valid byte count values are as follows: 1) 2) 3) 4) 5) the byte count shall be less than or equal to the byte count limit value from the host; the byte count shall not be zero; the byte count shall be less than or equal to FFFEh; the byte count shall be even except for the last transfer of a command; if the byte count is odd, the last valid byte transferred is on DD(7:0) and the data on DD(15:8) is a pad byte of undefined value; 6) if the last transfer of a command has a pad byte, the byte count shall be odd. Interrupt reason register Tag - If the device supports command queuing and overlap is enabled, this field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this field is not applicable. REL - Shall be cleared to zero. I/O - Shall be cleared to zero if the transfer is to the device. Shall be set to one if the transfer is to the host. C/D - Shall be cleared to zero indicating the transfer of data. Device register DEV shall indicate the selected device. Status register BSY - Shall be cleared to zero. DMRD (DMA ready) - Shall be set to one if the transfer is to be a DMA or Ultra DMA transfer and the device supports overlap DMA. SERV (Service) - Shall be set to one if another command is ready to be serviced. If overlap is not supported, this bit is command specific. DRQ - Shall be set to one. CHK - Shall be cleared to zero. 8.23.5.3 Bus release (overlap feature set only) After receiving the command packet, the device sets BSY to one and clears DRQ to zero. If the command packet requires a data transfer, the OVL bit is set to one, the Release interrupt is disabled, and the device is not prepared to immediately transfer data, the device may perform a bus release by placing the following register content in the Command Block registers. If the command packet requires a data transfer, the OVL bit is set to one, and the Release interrupt is enabled, the device shall perform a bus release by setting the register content as follows. Page 161 T13/1410D revision 3b Register Error Interrupt reason (Sector Count) LBA Low Byte Count low (LBA Mid) Byte Count high (LBA High) Device Status 7 6 5 4 3 2 1 0 REL I/O C/D na na na na na CHK na Tag na na na obs BSY na DRDY obs DMRD DEV SERV na DRQ Byte Count High/Low - na. Interrupt reason register Tag - If the device supports command queuing and overlap is enabled, this field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this field is not applicable. REL - Shall be set to one. I/O - Shall be cleared to zero. C/D - Shall be cleared to zero. Device register DEV shall indicate the selected device. Status register BSY - Shall be cleared to zero indicating bus release. DRDY - na. DMRD (DMA ready) - Shall be cleared to zero. SERV (Service) - Shall be set to one if another command is ready to be serviced. If overlap is not supported, this bit is command specific. DRQ - Shall be cleared to zero. CHK - Shall be cleared to zero. 8.23.5.4 Service request (overlap feature set only) When the device is ready to transfer data or complete a command after the command has performed a bus release, the device shall set the SERV bit and not change the state of any other register bit (see 6.9). When the SERVICE command is received, the device shall set outputs as described in data transfer, successful command completion, or error outputs depending on the service the device requires. 8.23.5.5 Successful command completion When the device has command completion without error, the device sets the following register content. Page 162 T13/1410D revision 3b Register Error Interrupt reason (Sector Count) LBA Low Byte Count low (LBA Mid) Byte Count high (LBA High) Device Status 7 6 5 4 3 2 1 0 REL I/O C/D na na na na na CHK na Tag na na na obs BSY na DRDY obs DMRD DEV SERV na DRQ Byte Count High/Low -na. Interrupt reason register Tag - If the device supports command queuing and overlap is enabled, this field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this field is not applicable. REL - Shall be cleared to zero. I/O - Shall be set to one. C/D - Shall be set to one. Device register DEV shall indicate the selected device. Status register BSY - Shall be cleared to zero indicating command completion. DRDY - Shall be set to one. DMRD (DMA ready) - na. SERV (Service) - Shall be set to one if another command is ready to be serviced. If overlap is not supported, this bit is command specific. DRQ - Shall be cleared to zero. CHK - Shall be cleared to zero. 8.23.6 Error outputs The device shall not terminate the PACKET command with an error before the last byte of the command packet has been written (see 9.8). Register Error Interrupt reason (Sector Count) LBA Low LBA Mid LBA High Device Status 7 6 5 Sense key Tag 4 3 na 2 ABRT REL 1 EOM I/O 0 ILI C/D na DRQ na na na na na CHK na na na obs BSY na DRDY obs DF DEV SERV Error register Sense Key is a command packet set specific error indication. ABRT shall be set to one if the requested command has been command aborted because the command code or a command parameter is invalid. ABRT may be set to one if the device is not able to complete the action requested by the command. EOM - the meaning of this bit is command set specific. See the appropriate command set standard for the definition of this bit. Page 163 T13/1410D revision 3b ILI - the meaning of this bit is command set specific. See the appropriate command set standard for the definition of this bit. Interrupt reason register Tag - If the device supports command queuing and overlap is enabled, this field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this field is not applicable. REL - Shall be cleared to zero. I/O - Shall be set to one. C/D - Shall be set to one. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. SERV (Service) - Shall be set to one if another command is ready to be serviced. If overlap is not supported, this bit is command specific. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. CHK shall be set to one if an Error register sense key or code bit is set. 8.23.7 Prerequisites This command shall be accepted regardless of the state of DRDY. 8.23.8 Description The PACKET command is used to transfer a device command via a command packet. If the native form of the encapsulated command is shorter than the packet size reported in bits (1:0) of word 0 of the IDENTIFY PACKET DEVICE response, the encapsulated command shall begin at byte 0 of the packet. Packet bytes beyond the end of the encapsulated command are reserved. If the device supports overlap, the OVL bit is set to one in the Features register and the Release interrupt has been disabled via the SET FEATURES command, the device may or may not perform a bus release. If the device is ready for the data transfer, the device may begin the transfer immediately as described in the nonoverlapped protocol (see 9.8). If the data is not ready, the device may perform a bus release and complete the transfer after the execution of a SERVICE command. 8.24 READ BUFFER 8.24.1 Command code E4h 8.24.2 Feature set General feature set − − Optional for devices not implementing the PACKET Command feature set. Use prohibited for devices implementing the PACKET Command feature set. 8.24.3 Protocol PIO data-in (see 9.5). Page 164 T13/1410D revision 3b 8.24.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na 3 2 1 0 na DRQ na na na na na ERR 3 na 2 ABRT 1 na 0 na na DRQ na na na na na ERR na na na na na obs na obs DEV E4h Device register DEV shall specify the selected device. 8.24.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.24.6 Error outputs The device shall return command aborted if the command is not supported. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na na na na na obs BSY na DRDY obs DF DEV na Error register ABRT shall be set to one if this command is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. Page 165 T13/1410D revision 3b DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.24.7 Prerequisites DRDY set to one. The command prior to a READ BUFFER command shall be a WRITE BUFFER command. 8.24.8 Description The READ BUFFER command enables the host to read the current contents of the device’s sector buffer. The READ BUFFER and WRITE BUFFER commands shall be synchronized such that sequential WRITE BUFFER and READ BUFFER commands access the same 512 bytes within the buffer. 8.25 READ DMA 8.25.1 Command code C8h 8.25.2 Feature set General feature set − − Mandatory for devices not implementing the PACKET Command feature set. Use prohibited for devices implementing the PACKET Command feature set. 8.25.3 Protocol DMA (see 9.7). 8.25.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs LBA obs 4 3 na Sector count LBA (7:0) LBA (15:8) LBA (23:16) DEV C8h 2 1 0 LBA (27:24) Sector Count number of sectors to be transferred. A value of 00h specifies that 256 sectors are to be transferred. LBA Low starting LBA bits (7:0). LBA Mid starting LBA bits (15:8). LBA High starting LBA bits (23:16). Device the LBA bit shall be set to one to specify the address is an LBA, DEV shall specify the selected device. Page 166 T13/1410D revision 3b bits (3:0) shall be starting LBA bits (27:24). 8.25.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na DRQ na na na na na ERR na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.25.6 Error outputs An unrecoverable error encountered during the execution of this command results in the termination of the command. The Command Block registers contain the address of the sector where the first unrecoverable error occurred. The amount of data transferred is indeterminate. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 ICRC obs BSY 6 UNC na DRDY 5 MC 4 IDNF 3 MCR obs DF na LBA (7:0) LBA (15:8) LBA (23:16) DEV na DRQ 2 ABRT 1 NM 0 obs LBA (27:24) na na ERR Error register ICRC shall be set to one if an interface CRC error has occurred during an Ultra DMA data transfer. The content of this bit is not applicable for Multiword DMA transfers. UNC shall be set to one if data is uncorrectable MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported or if an error, including an ICRC error, has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. LBA Low, LBA Mid, LBA High, Device Page 167 T13/1410D revision 3b shall be written with the address of first unrecoverable error. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.25.7 Prerequisites DRDY set to one. The host shall initialize the DMA channel. 8.25.8 Description The READ DMA command allows the host to read data using the DMA data transfer protocol. 8.26 READ DMA EXT 8.26.1 Command code 25h 8.26.2 Feature set 48-bit Address feature set − − Mandatory for devices implementing the 48-bit Address feature set. Use prohibited for devices implementing the PACKET Command feature set. 8.26.3 Protocol DMA (see 9.7). 8.26.4 Inputs Register 7 6 5 4 3 2 1 0 Features Current Reserved Previous Reserved Sector Count Current Sector count (7:0) Previous Sector count (15:8) LBA Low Current LBA (7:0) Previous LBA (31:24) LBA Mid Current LBA (15:8) Previous LBA (39:32) LBA High Current LBA (23:16) Previous LBA (47:40) Device obs LBA obs DEV Reserved Command 25h NOTE − The value indicated as Current is the value most recently written to the register. The value indicated as Previous is the value that was in the register before the most recent write to the register. Sector Count Current number of sectors to be transferred low order, bits (7:0). Page 168 T13/1410D revision 3b Sector Count Previous number of sectors to be transferred high order, bits (15:8). 0000h in the Sector Count register specifies that 65,536 sectors are to be transferred. LBA Low Current LBA (7:0). LBA Low Previous LBA (31:24). LBA Mid Current LBA (15:8). LBA Mid Previous LBA (39:32). LBA High Current LBA (23:16). LBA High Previous LBA (47:40). Device . DEV shall specify the selected device. 8.26.5 Normal outputs Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.26.6 Error outputs An unrecoverable error encountered during the execution of this command results in the termination of the command. The Command Block registers contain the address of the sector where the first unrecoverable error occurred. The amount of data transferred is indeterminate. Page 169 T13/1410D revision 3b Register 7 6 5 4 3 2 1 0 Error ICRC UNC MC IDNF MCR ABRT NM obs Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 LBA (7:0) HOB = 1 LBA (31:24) LBA Mid HOB = 0 LBA (15:8) HOB = 1 LBA (39:32) LBA High HOB = 0 LBA (23:16) HOB = 1 LBA (47:40) Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Error register ICRC shall be set to one if an interface CRC error has occurred during an Ultra DMA data transfer. The content of this bit is not applicable for Multiword DMA transfers. UNC shall be set to one if data is uncorrectable. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported or if an error, including an ICRC error, has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. LBA Low LBA (7:0) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (31:24) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA Mid LBA (15:8) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (39:32) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA High LBA (23:16) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (47:40) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. Page 170 T13/1410D revision 3b 8.26.7 Prerequisites DRDY set to one. The host shall initialize the DMA channel. 8.26.8 Description The READ DMA EXT command allows the host to read data using the DMA data transfer protocol. 8.27 READ DMA QUEUED 8.27.1 Command code C7h 8.27.2 Feature set Overlapped feature set − Mandatory for devices implementing the Overlapped feature set and not implementing the PACKET Command feature set. − Use prohibited for devices implementing the PACKET command feature set. 8.27.3 Protocol DMA QUEUED (see 9.9). 8.27.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 Sector Count Tag obs LBA obs LBA (7:0) LBA (15:8) LBA (23:16) DEV C7h 2 1 0 na na na LBA (27:24) Features number of sectors to be transferred. A value of 00h specifies that 256 sectors are to be transferred. Sector count if the device supports command queuing, bits (7:3) contain the Tag for the command being delivered. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If queuing is not supported, this register shall be set to the value 00h. LBA Low starting LBA bits (7:0). LBA Mid starting LBA bits (15:8). LBA High starting LBA bits (23:16). Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. bits (3:0) starting LBA bits (27:24). Page 171 T13/1410D revision 3b 8.27.5 Normal outputs 8.27.5.1 Data transmission Data transfer may occur after receipt of the command or may occur after the receipt of a SERVICE command. When the device is ready to transfer data requested by a data transfer command, the device sets the following register content to initiate the data transfer. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 REL I/O C/D na na na na na CHK na Tag na na na obs BSY na DRDY obs DF DEV SERV na DRQ Sector Count register Tag -This field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this register shall be set to the value 00h. REL - Shall be cleared to zero. I/O - Shall be set to one indicating the transfer is to the host. C/D - Shall be cleared to zero indicating the transfer of data. Device register DEV shall indicate the selected device. Status register BSY - Shall be cleared to zero. DRDY - Shall be set to one. DF (Device Fault) - Shall be cleared to zero. SERV (Service) - Shall be set to one if another command is ready to be serviced. DRQ - Shall be set to one. CHK - Shall be cleared to zero. 8.27.5.2 Bus release If the device performs a bus release before transferring data for this command, the register content upon performing a bus release shall be as shown below. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 REL I/O C/D na ERR na Tag na na na obs BSY na DRDY obs DF DEV SERV na DRQ na Sector Count register Tag - If the device supports command queuing, this field shall contain the Tag of the command being bus released. If the device does not support command queuing, this field shall be set to the value 00h. REL shall be set to one. I/O shall be zero. Page 172 T13/1410D revision 3b C/D shall be zero. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating bus release. DRDY shall be set to one. SERV (Service) shall be cleared to zero when no other queued command is ready for service. SERV shall be set to one when another queued command is ready for service. SERV shall be set to one when the device has prepared this command for service. DF (Device Fault) shall be cleared to zero DRQ bit shall be cleared to zero. ERR bit shall be cleared to zero. 8.27.5.3 Service request When the device is ready to transfer data or complete a command after the command has performed a bus release, the device shall set the SERV bit and not change the state of any other register bit (see 6.9). When the SERVICE command is received, the device shall set outputs as described in data transfer, command completion, or error outputs depending on the service the device requires. 8.27.5.4 Command completion When the transfer of all requested data has occurred without error, the register content shall be as shown below. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 REL I/O C/D na ERR 00h Tag na na na obs BSY na DRDY obs DF DEV SERV na DRQ na Sector Count register Tag - If the device supports command queuing, this field shall contain the Tag of the completed command. If the device does not support command queuing, this field shall be set to the value 00h. REL shall be cleared to zero. I/O shall be set to one. C/D shall be set to one. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. SERV (Service) shall be cleared to zero when no other queued command is ready for service. SERV shall be set to one when another queued command is ready for service. DF (Device Fault) shall be cleared to zero. DRQ bit shall be cleared to zero. ERR bit shall be cleared to zero. Page 173 T13/1410D revision 3b 8.27.6 Error outputs The Sector Count register contains the Tag for this command if the device supports command queuing. The device shall return command aborted if the command is not supported or if the device has not had overlapped interrupt enabled. The device shall return command aborted if the device supports command queuing and the Tag is invalid. An unrecoverable error encountered during the execution of this command results in the termination of the command and the Command Block registers contain the sector where the first unrecoverable error occurred. If a queue existed, the unrecoverable error shall cause the queue to abort. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 ICRC obs BSY 6 UNC na DRDY 5 MC Tag obs DF 4 IDNF 3 MCR LBA (7:0) LBA (15:8) LBA (23:16) DEV SERV DRQ 2 ABRT REL 1 NM I/O 0 obs C/D LBA (27:24) na na ERR Error register ICRC shall be set to one if an interface CRC error has occurred during an Ultra DMA data transfer. The content of this bit is not applicable for Multiword DMA transfers. UNC shall be set to one if data is uncorrectable. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if ABRT is not set to one. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported or if an error, including an ICRC error, has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. Sector Count register Tag - If the device supports command queuing, this field shall contain the Tag of the completed command. If the device does not support command queuing, this field shall be set to the value 00h. REL shall be cleared to zero. I/O shall be set to one. C/D shall be set to one. LBA Low, LBA Mid, LBA High, Device shall be written with the address of first unrecoverable error. DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. SERV (Service) shall be cleared to zero when no other queued command is ready for service. SERV shall be set to one when another queued command is ready for service. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. Page 174 T13/1410D revision 3b 8.27.7 Prerequisites DRDY set to one. The host shall initialize the DMA channel. 8.27.8 Description This command executes in a similar manner to a READ DMA command. The device may perform a bus release or may execute the data transfer without performing a bus release if the data is ready to transfer. 8.28 READ DMA QUEUED EXT 8.28.1 Command code 26h 8.28.2 Feature set 48-bit Address feature set − Mandatory for devices implementing the Overlapped feature set and the 48-bit Address feature set and not implementing the PACKET Command feature set. − Use prohibited for devices implementing the PACKET command feature set. 8.28.3 Protocol DMA QUEUED (see 9.9). 8.28.4 Inputs Register 7 6 5 4 3 2 1 0 Features Current Sector count (7:0) Previous Sector count (15:8) Sector Count Current Tag Reserved Previous Reserved LBA Low Current LBA (7:0) Previous LBA (31:24) LBA Mid Current LBA (15:8) Previous LBA (39:32) LBA High Current LBA (23:16) Previous LBA (47:40) Device obs LBA obs DEV Reserved Command 26h NOTE − The value indicated as Current is the value most recently written to the register. The value indicated as Previous is the value that was in the register before the most recent write to the register. Features Current number of sectors to be transferred low order, bits (7:0). Features Previous number of sectors to be transferred high order, bits (15:8). 0000h in the Features register specifies that 65,536 sectors are to be transferred. Sector Count Current if the device supports command queuing, bits (7:3) contain the Tag for the command being delivered. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If queuing is not supported, this register shall be set to the value 00h. Sector Count Previous – Reserved Page 175 T13/1410D revision 3b LBA Low Current LBA (7:0). LBA Low Previous LBA (31:24). LBA Mid Current LBA (15:8). LBA Mid Previous LBA (39:32). LBA High Current LBA (23:16). LBA High Previous LBA (47:40). Device . DEV shall specify the selected device. 8.28.5 Normal outputs 8.28.5.1 Data transmission Data transfer may occur after receipt of the command or may occur after the receipt of a SERVICE command. When the device is ready to transfer data requested by a data transfer command, the device sets the following register content to initiate the data transfer. Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Tag REL I/O C/D HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Sector Count (when the HOB bit of the Device Control register is cleared to zero) Tag -This field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this register shall be set to the value 00h. REL - Shall be cleared to zero. I/O - Shall be set to one indicating the transfer is to the host. C/D - Shall be cleared to zero indicating the transfer of data. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. Page 176 T13/1410D revision 3b 8.28.5.2 Bus release If the device performs a bus release before transferring data for this command, the register content upon performing a bus release shall be as shown below. Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Tag REL I/O C/D HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY DF SERV DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Sector Count (when the HOB bit of the Device Control register is cleared to zero) Tag -This field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this register shall be set to the value 00h. REL - Shall be set to one. I/O - Shall be set to one indicating the transfer is to the host. C/D - Shall be cleared to zero indicating the transfer of data. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. SERV (Service) shall be cleared to zero when no other queued command is ready for service. SERV shall be set to one when another queued command is ready for service. SERV shall be set to one when the device has prepared this command for service. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.28.5.3 Service request When the device is ready to transfer data or complete a command after the command has performed a bus release, the device shall set the SERV bit and not change the state of any other register bit (see 6.9). When the SERVICE command is received, the device shall set outputs as described in data transfer, command completion, or error outputs depending on the service the device requires. 8.28.5.4 Command completion When the transfer of all requested data has occurred without error, the register content shall be as shown below. Page 177 T13/1410D revision 3b Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Tag REL I/O C/D HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY DF SERV DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Sector Count (when the HOB bit of the Device Control register is cleared to zero) Tag -This field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this register shall be set to the value 00h. REL - Shall be cleared to zero. I/O - Shall be set to one. C/D - Shall be set to one. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. SERV (Service) shall be cleared to zero when no other queued command is ready for service. SERV shall be set to one when another queued command is ready for service. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.28.6 Error outputs The Sector Count register contains the Tag for this command if the device supports command queuing. The device shall return command aborted if the command is not supported or if the device has not had overlapped interrupt enabled. The device shall return command aborted if the device supports command queuing and the Tag is invalid. An unrecoverable error encountered during the execution of this command results in the termination of the command and the Command Block registers contain the sector where the first unrecoverable error occurred. If a queue existed, the unrecoverable error shall cause the queue to abort. Page 178 T13/1410D revision 3b Register 7 6 5 4 3 2 1 0 Error ICRC UNC MC IDNF MCR ABRT NM obs Sector Count HOB = 0 Tag REL I/O C/D HOB = 1 Reserved LBA Low HOB = 0 LBA (7:0) HOB = 1 LBA (31:24) LBA Mid HOB = 0 LBA (15:8) HOB = 1 LBA (39:32) LBA High HOB = 0 LBA (23:16) HOB = 1 LBA (47:40) Device obs na obs DEV Reserved Status BSY DRDY DF SERV DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Error register ICRC shall be set to one if an interface CRC error has occurred during an Ultra DMA data transfer. The content of this bit is not applicable for Multiword DMA transfers. UNC shall be set to one if data is uncorrectable. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported or if an error, including an ICRC error, has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. Sector Count (when the HOB bit of the Device Control register is cleared to zero) Tag -This field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this register shall be set to the value 00h. REL - Shall be cleared to zero. I/O - Shall be set to one. C/D - Shall be set to one. LBA Low LBA (7:0) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (31:24) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA Mid LBA (15:8) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (39:32) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA High LBA (23:16) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (47:40) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. Device register Page 179 T13/1410D revision 3b DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.28.7 Prerequisites DRDY set to one. The host shall initialize the DMA channel. 8.28.8 Description This command executes in a similar manner to a READ DMA command. The device may perform a bus release or may execute the data transfer without performing a bus release if the data is ready to transfer. 8.29 READ LOG EXT 8.29.1 Command code 2Fh 8.29.2 Feature set General Purpose Logging feature set -- Mandatory for devices implementing the General Purpose Logging feature set 8.29.3 Protocol PIO data-in (see 9.5) 8.29.4 Inputs Register 7 6 5 4 3 2 1 0 Features Current Reserved Previous Reserved Sector Count Current Sector count (7:0) Previous Sector count (15:8) LBA Low Current Log address Previous Reserved LBA Mid Current Sector offset (7:0) Previous Sector offset (15:8) LBA High Current Reserved Previous Reserved Device/Head obs na obs DEV Reserved Command 2Fh NOTE – The value indicated as Current is the value most recently written to the register. The value indicated as Previous is the value that was in the register before the most recent write to the register. Sector Count – Specifies the number of sectors to be read from the specified log. The log transferred by the drive shall start at the sector in the specified log at the specified offset, regardless of the sector count requested. LBA Low - Specifies the log to be returned as described in Table 31. A device may support a subset of the available logs. Support for individual logs is determined by support for the associated feature set. Page 180 T13/1410D revision 3b Support of the associated log(s) is mandatory for devices implementing the associated feature set. The host vendor specific logs may be used by the host to store any data desired. If a host vendor specific log has never been written by the host, when read the content of the log shall be zeros. Device vendor specific logs may be used by the device vendor to store any data and need only be implemented if used. LBA Mid – Specifies the first sector of the log to be read. Device/Head register DEV shall indicate the selected device. Log address 00h 01h 02h 03h 04h-05h 06h 07h 08h-7Fh 80h-9Fh A0h-BFh Table 31 − Log address definition Content Feature set Log directory na Reserved na Comprehensive SMART error logging SMART error log Extended SMART error logging Comprehensive SMART error log Reserved na SMART self-test log SMART self-test Extended SMART SMART self-test self-test log Reserved na Host vendor specific SMART Device vendor SMART specific Reserved na C0h-FFh Key − RO – Log is read only by the host. R/W – Log is read or written by the host. VS – Log is vendor specific thus read/write ability is vendor specific. R/W RO Reserved See note RO Reserved See note RO Reserved R/W VS Reserved NOTE − If log address 02h or log address 06h are accessed using the READ LOG EXT or WRITE LOG EXT commands, command abort shall be returned. The Comprehensive SMART error log and the SMART self-test log are defined in 8.51.6 and 8.51.8. If log address 02h or log address 06h are accessed using the READ LOG EXT or WRITE LOG EXT commands, command abort shall be returned. All 28-bit entries contained in the Comprehensive SMART log shall also be included in the Extended Comprehensive SMART error log with the 48-bit entries. The Extended SMART self-test log sector shall support 48-bit and 28-bit addressing. All 28-bit entries contained in the SMART self-test log sector shall also be included in the Comprehensive SMART self-test log sector with the 48-bit entries. Page 181 T13/1410D revision 3b 8.29.5 Normal outputs Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device/Head obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Device/Head register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one indicating that the device is capable of receiving any command. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.29.6 Error outputs If the device does not support this command, if the feature set associated with the log specified in the LBA Low register is not supported or enabled, or if the values in the Features, Sector Count, LBA Mid, or LBA High registers are invalid, the device shall return command aborted. Register 7 6 5 4 3 2 1 0 Error na UNC na IDNF na ABRT na obs Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device/Head obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Error register UNC shall be set to one if the log contains one or more sectors that are uncorrectable. IDNF shall be set to one if the log sector’s ID field was not found or data structure checksum error occurred. Page 182 T13/1410D revision 3b ABRT shall be set to one if this command is not supported, if the feature associated with the log specified in the LBA Low register is not supported, or if other register values are invalid. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if the Sector Count register contains a count larger than the log size reported in the Log Directory. ABRT shall be set to one if the host issues a READ LOG EXT or WRITE LOG EXT command with a value of zero in the Sector Count register. Device/Head register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one indicating that the device is capable of receiving any command. DF (Device Fault) shall be set to one indicating that a device fault has occurred. DRQ shall be cleared to zero indicating that there is no data to be transferred. ERR shall be set to one if any Error register bit is set to one. 8.29.7 Prerequisites DRDY set to one. 8.29.8 Description This command returns the specified log to the host. The device shall interrupt for each DRQ block transferred. 8.29.8.1 General Purpose Log Directory Table 32 defines the 512 bytes that make up the General Purpose Log Directory. Byte 0-1 2 3 4 5 … 256 257 … 510-511 Table 32 − General Purpose Log Directory Descriptions General Purpose Logging Version Number of sectors in the log at log address 01h (7:0) Number of sectors in the log at log address 01h (15:8) Number of sectors in the log at log address 02h (7:0) Number of sectors in the log at log address 02h (15:8) 10h sectors in the log at log address 80h 00h sectors in the log at log address 80h Number of sectors in the log at log address FFh The value of the General Purpose Logging Version word shall be 0001h. A value of 0000h indicates that no General Purpose log Directory exists. The logs at log addresses 80-9Fh shall each be defined as 16 sectors long. Page 183 T13/1410D revision 3b 8.29.8.2 Extended Comprehensive SMART Error log Table 33 defines the format of each of the sectors that comprise the Extended Comprehensive SMART error log. The maximum size of the Extended Comprehensive SMART error log is 65,536 sectors. Devices may support fewer than 65,535 sectors. All multi-byte fields shown in this structure follow the byte ordering described in 3.2.9. Error log data structures shall include UNC errors, IDNF errors for which the address requested was valid, servo errors, write fault errors, etc. Error log data structures shall not include errors attributed to the receipt of faulty commands such as command codes not implemented by the device or requests with invalid parameters or invalid addresses. All 28-bit entries contained in the Comprehensive SMART log, defined under section 8.51.6.8.3, shall also be included in the Extended Comprehensive SMART error log with the 48-bit entries. Table 33 − Extended Comprehensive SMART error log Byte First sector Subsequent sectors 0 SMART error log version Reserved 1 Reserved Reserved 2 Error log index (7:0) Reserved 3 Error log index (15:8) Reserved 4-127 First error log data structure Data structure 4n+1 128-251 Second error log data structure Data structure 4n+2 252-375 Third error log data structure Data structure 4n+3 376-499 Fourth error log data structure Data structure 4n+4 500-501 Device error count Reserved 502-510 Reserved Reserved 511 Data structure checksum Data structure checksum n is the sector number within the log. The first sector is sector zero 8.29.8.2.1 Error log version The value of the SMART error log version byte shall be 01h. 8.29.8.2.2 Error log index The error log index indicates the error log data structure representing the most recent error. If there have been no error log entries, the error log index is cleared to zero. Valid values for the error log index are zero to 65,536. 8.29.8.2.3 Extended Error log data structure The error log is viewed as a circular buffer. When the last supported error log sector has been filled, the next error shall create an error log data structure that replaces the first error log data structure in sector zero. The next error after that shall create an error log data structure that replaces the second error log data structure in sector zero. The sixth error after the log has filled shall replace the first error log data structure in sector one, and so on. The error log index indicates the most recent error log data structure. Unused error log data structures shall be filled with zeros. The content of the error log data structure entries is defined in Table 34. Page 184 T13/1410D revision 3b Table 34 − Extended Error log data structure Byte Descriptions n thru n+17 First command data structure n+18 thru n+35 Second command data structure n+36 thru n+53 Third command data structure n+54 thru n+71 Fourth command data structure n+72 thru n+89 Fifth command data structure n+90 thru n+123 Error data structure 8.29.8.2.3.1 Command data structure The fifth command data structure shall contain the command or reset for which the error is being reported. The fourth command data structure should contain the command or reset that preceded the command or reset for which the error is being reported, the third command data structure should contain the command or reset preceding the one in the fourth command data structure, etc. If fewer than four commands and resets preceded the command or reset for which the error is being reported, the unused command data structures shall be zero filled, for example, if only three commands and resets preceded the command or reset for which the error is being reported, the first command data structure shall be zero filled. In some devices, the hardware implementation may preclude the device from reporting the commands that preceded the command for which the error is being reported or that preceded a reset. In this case, the command data structures are zero filled. If the command data structure represents a command or software reset, the content of the command data structure shall be as shown in Table 35. If the command data structure represents a hardware reset, the content of byte n shall be FFh, the content of bytes n+1 through n+13 are vendor specific, and the content of bytes n+14 through n+17 shall contain the timestamp. Table 35 − Command data structure Byte Descriptions n Content of the Device Control register when the Command register was written. n+1 Content of the Features register (7:0) when the Command register was written. (see note) n+2 Content of the Features register (15:8) when the Command register was written. n+3 Content of the Sector Count register (7:0) when the Command register was written. n+4 Content of the Sector Count register (15:8) when the Command register was written. n+5 Content of the LBA Low register (7:0) when the Command register was written. n+6 Content of the LBA Lowregister (15:8) when the Command register was written. n+7 Content of the LBA Mid register (7:0) when the Command register was written. n+8 Content of the LBA Mid register (15:8) when the Command register was written. n+9 Content of the LBA High register (7:0) when the Command register was written. n+10 Content of the LBA High register (15:8) when the Command register was written. n+11 Content of the Device/Head register when the Command register was written. n+12 Content written to the Command register. n+13 Reserved n+14 Timestamp (least significant byte) n+15 Timestamp (next least significant byte) n+16 Timestamp (next most significant byte) n+17 Timestamp (most significant byte) NOTE – bits (7:0) refer to the most recently written contents of the register. Bits (15:8) refer to the contents of the register prior to the most recent write to the register. Timestamp shall be the time since power-on in milliseconds when command acceptance occurred. This timestamp may wrap around. Page 185 T13/1410D revision 3b 8.29.8.2.3.2 Error data structure The error data structure shall contain the error description of the command for which an error was reported as described in Table 36. If the error was logged for a hardware reset, the content of bytes n+1 through n+11 shall be vendor specific and the remaining bytes shall be as defined in Table 36. Table 36 − Error data structure Byte Descriptions n Reserved n+1 Content of the Error register after command completion occurred. n+2 Content of the Sector Count register (7:0) after command completion occurred. (see note) n+3 Content of the Sector Count register (15:8) after command completion occurred. (see note) n+4 Content of the LBA Low register (7:0) after command completion occurred. n+5 Content of the LBA Low register (15:8) after command completion occurred. n+6 Content of the LBA Mid register (7:0) after command completion occurred. n+7 Content of the LBA Mid register (15:8) after command completion occurred. n+8 Content of the LBA High register (7:0) after command completion occurred. n+9 Content of the LBA High register (15:8) after command completion occurred. n+10 Content of the Device/Head register after command completion occurred. n+11 Content written to the Status register after command completion occurred. n+12 Extended error information through n+30 n+31 State n+32 Life timestamp (least significant byte) n+33 Life timestamp (most significant byte) NOTE – bits (7:0) refer to the contents if the register were read with bit 7 of the Device Control register cleared to zero. Bits (15:8) refer to the contents if the register were read with bit 7 of the Device Control register set to one. Extended error information shall be vendor specific. State shall contain a value indicating the state of the device when the command was written to the Command register or the reset occurred as described in Table 37. Table 37 − State field values Value State x0h Unknown x1h Sleep x2h Standby x3h Active/Idle with BSY cleared to zero x4h Executing SMART off-line or self-test x5h-xAh Reserved xBh-xFh Vendor unique The value of x is vendor specific and may be different for each state. Sleep indicates the reset for which the error is being reported was received when the device was in the Sleep mode. Standby indicates the command or reset for which the error is being reported was received when the device was in the Standby mode. Active/Idle with BSY cleared to zero indicates the command or reset for which the error is being reported was received when the device was in the Active or Idle mode and BSY was cleared to zero. Page 186 T13/1410D revision 3b Executing SMART off-line or self-test indicates the command or reset for which the error is being reported was received when the device was in the process of executing a SMART off-line or self-test. Life timestamp shall contain the power-on lifetime of the device in hours when command completion occurred. 8.29.8.2.4 Device error count The device error count field shall contain the total number of errors attributable to the device that have been reported by the device during the life of the device. These errors shall include UNC errors, IDNF errors for which the address requested was valid, servo errors, write fault errors, etc. This count shall not include errors attributed to the receipt of faulty commands such as commands codes not implemented by the device or requests with invalid parameters or invalid addresses. If the maximum value for this field is reached, the count shall remain at the maximum value when additional errors are encountered and logged. 8.29.8.2.5 Data structure checksum The data structure checksum is the two’s complement of the sum of the first 511 bytes in the data structure. Each byte shall be added with unsigned arithmetic, and overflow shall be ignored. The sum of all 512 bytes will be zero when the checksum is correct. The checksum is placed in byte 511. 8.29.8.3 Extended Self-test log sector Table 38 defines the format of each of the sectors that comprise the Extended SMART Self-test log. The maximum size of the self-test log is 65,535 sectors. Devices may support fewer than 65,536 sectors. All multi-byte fields shown in this structure follow the byte ordering described in 3.2.9. The Extended SMART self-test log sector shall support 48-bit and 28-bit addressing. All 28-bit entries contained in the SMART self-test log, defined under section 8.51.6.8.4 shall also be included in the Extended SMART self-test log with all 48-bit entries. Table 38 − Extended Self-test log data structure Byte First sector Subsequent sectors 0 Self-test log data structure Reserved revision number 1 Reserved Reserved 2 Self-test descriptor index (7:0) Reserved 3 Self-test descriptor index (15:8) Reserved 4-29 Descriptor entry 1 Descriptor entry 18n+1 30-55 Descriptor entry 2 Descriptor entry 18n+2 .... .... .... 472-497 Descriptor entry 18 Descriptor entry 18n+18 498-499 Vendor specific Vendor specific 500-510 Reserved Reserved 511 Data structure checksum Data structure checksum n is the sector number within the log. The first sector is sector zero This log is viewed as a circular buffer. When the last supported Self-test log sector has been filled, the next self-test shall create a descriptor that replaces descriptor entry 1 in sector 0. The next self-test after that shall create a descriptor that replaces descriptor entry 2 in sector 0, and so on. All unused self-test descriptors shall be filled with zeros. Page 187 T13/1410D revision 3b 8.29.8.3.1 Self-test descriptor index The Self-test descriptor index indicates the most recent self-test descriptor. If there have been no self-tests, the Self-test descriptor index is set to zero. Valid values for the Self-test descriptor index are zero to 65,535. 8.29.8.3.2 Self-test log data structure revision number The value of the self-test log data structure revision number shall be 01h. 8.29.8.3.3 Extended Self-test log descriptor entry The content of the self-test descriptor entry is shown in Table 39. Table 39 − Extended Self-test log descriptor entry Byte Descriptions n Content of the LBA Low register. n+1 Content of the self-test execution status byte. n+2 Life timestamp (least significant byte). n+3 Life timestamp (most significant byte). n+4 Content of the self-test failure checkpoint byte. n+5 Failing LBA (7:0). n+6 Failing LBA (15:8). n+7 Failing LBA (23:16). n+8 Failing LBA (31:24). n+9 Failing LBA (39:32). n+10 Failing LBA (47:40). n+11 - n+23 Vendor specific. Content of the LBA Low register shall be the content of the LBA Low register when the nth self-test subcommand was issued (see 8.51.4.8). Content of the self-test execution status byte shall be the content of the self-test execution status byte when the nth self-test was completed (see 8.51.5.8.2). Life timestamp shall contain the power-on lifetime of the device in hours when the nth self-test subcommand was completed. Content of the self-test failure checkpoint byte may contain additional information about the self-test that failed. The failing LBA shall be the LBA of the sector that caused the test to fail. If the device encountered more than one failed sector during the test, this field shall indicate the LBA of the first failed sector encountered. If the test passed or the test failed for some reason other than a failed sector, the value of this field is undefined. 8.29.8.3.4 Data structure checksum The data structure checksum is the two's complement of the sum of the first 511 bytes in the data structure. Each byte shall be added with unsigned arithmetic, and overflow shall be ignored. The sum of all 512 bytes is zero when the checksum is correct. The checksum is placed in byte 511. 8.30 READ MULTIPLE 8.30.1 Command code C4h Page 188 T13/1410D revision 3b 8.30.2 Feature set General feature set − − Mandatory for devices not implementing the PACKET Command feature set. Use prohibited for devices implementing the PACKET Command feature set. 8.30.3 Protocol PIO data-in (see 9.5). 8.30.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs LBA obs 4 3 na Sector count LBA (7:0) LBA (15:0) LBA (23:16) DEV C4h 2 1 0 LBA (27:24) Sector Count number of sectors to be transferred. A value of 00h specifies that 256 sectors are to be transferred. LBA Low starting LBA bits (7:0). LBA Mid starting LBA bits (15:8). LBA High starting LBA bits (23:16). Device DEV shall specify the selected device. bits (3:0) starting LBA bits (27:24). 8.30.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na DRQ na na na na na ERR na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. Page 189 T13/1410D revision 3b 8.30.6 Error outputs An unrecoverable error encountered during the execution of this command results in the termination of the command. The Command Block registers contain the address of the sector where the first unrecoverable error occurred. The amount of data transferred is indeterminate. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na obs BSY 6 UNC na DRDY 5 MC 4 IDNF 3 MCR obs DF na LBA (7:0) LBA (15:8) LBA (23:16) DEV na DRQ 2 ABRT 1 NM 0 obs LBA (27:24) na na ERR Error register UNC shall be set to one if data is uncorrectable. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported or if an error, including an ICRC error, has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. LBA Low, LBA Mid, LBA High, Device shall be written with the address of first unrecoverable error. DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.30.7 Prerequisites DRDY set to one. If bit 8 of IDENTIFY DEVICE word 59 is cleared to zero, a successful SET MULTIPLE MODE command shall precede a READ MULTIPLE command. 8.30.8 Description This command reads the number of sectors specified in the Sector Count register. The number of sectors per block is defined by the content of word 59 in the IDENTIFY DEVICE response. When the READ MULTIPLE command is issued, the Sector Count register contains the number of sectors (not the number of blocks) requested. The device shall interrupt for each DRQ block transferred. Page 190 T13/1410D revision 3b If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer shall be for n sectors, where n = remainder (sector count/ block count). If the READ MULTIPLE command is received when READ MULTIPLE commands are disabled, the READ MULTIPLE operation shall be rejected with command aborted. Device errors encountered during READ MULTIPLE commands are posted at the beginning of the block or partial block transfer, but the DRQ bit is still set to one and the data transfer shall take place, including transfer of corrupted data, if any. The contents of the Command Block Registers following the transfer of a data block that had a sector in error are undefined. The host should retry the transfer as individual requests to obtain valid error information. Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the command to stop after transfer of the block that contained the error. 8.31 READ MULTIPLE EXT 8.31.1 Command code 29h 8.31.2 Feature set 48-bit Address feature set − Mandatory for all devices implementing the 48-bit Address feature set. − Use prohibited when the PACKET feature set is implemented 8.31.3 Protocol PIO data-in (see 9.5). 8.31.4 Inputs Register 7 6 5 4 3 2 1 0 Features Current Reserved Previous Reserved Sector Count Current Sector count (7:0) Previous Sector count (15:8) LBA Low Current LBA (7:0) Previous LBA (31:24) LBA Mid Current LBA (15:8) Previous LBA (39:32) LBA High Current LBA (23:16) Previous LBA (47:40) Device obs LBA obs DEV Reserved Command 29h NOTE − The value indicated as Current is the value most recently written to the register. The value indicated as Previous is the value that was in the register before the most recent write to the register. Sector Count Current number of sectors to be transferred low order, bits (7:0). Sector Count Previous - Page 191 T13/1410D revision 3b number of sectors to be transferred high order, bits (15:8). 0000h in the Sector Count register specifies that 65,536 sectors are to be transferred. LBA Low Current LBA (7:0). LBA Low Previous LBA (31:24). LBA Mid Current LBA (15:8). LBA Mid Previous LBA (39:32). LBA High Current LBA (23:16). LBA High Previous LBA (47:40). Device DEV shall specify the selected device. 8.31.5 Normal outputs Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved na Status BSY DRDY DF na DRQ na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.31.6 Error outputs An unrecoverable error encountered during the execution of this command results in the termination of the command. The Command Block registers contain the address of the sector where the first unrecoverable error occurred. The amount of data transferred is indeterminate. Page 192 T13/1410D revision 3b Register 7 6 5 4 3 2 1 0 Error na UNC MC IDNF MCR ABRT NM obs Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 LBA (7:0) HOB = 1 LBA (31:24) LBA Mid HOB = 0 LBA (15:8) HOB = 1 LBA (39:32) LBA High HOB = 0 LBA (23:16) HOB = 1 LBA (47:40) Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Error register UNC shall be set to one if data is uncorrectable MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. LBA Low LBA (7:0) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (31:24) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA Mid LBA (15:8) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (39:32) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA High LBA (23:16) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (47:40) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. Page 193 T13/1410D revision 3b 8.31.7 Prerequisites DRDY set to one. If bit 8 of IDENTIFY DEVICE word 59 is cleared to zero, a successful SET MULTIPLE MODE command shall precede a READ MULTIPLE EXT command. 8.31.8 Description This command reads the number of sectors specified in the Sector Count register. The number of sectors per block is defined by a successful SET MULTIPLE command. If no successful SET MULTIPLE command has been issued, the block is defined by the device’s default value for number of sectors per block as defined in bits (7:0) in word 47 in the IDENTIFY DEVICE information. When the READ MULTIPLE EXT command is issued, the Sector Count register contains the number of sectors (not the number of blocks) requested. The device shall interrupt for each DRQ block transferred. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer shall be for n sectors, where n = remainder (sector count/ block count). If the READ MULTIPLE EXT command is received when READ MULTIPLE commands are disabled, the READ MULTIPLE operation shall be rejected with command aborted. Device errors encountered during READ MULTIPLE EXT commands are posted at the beginning of the block or partial block transfer, but the DRQ bit is still set to one and the data transfer shall take place, including transfer of corrupted data, if any. The contents of the Command Block Registers following the transfer of a data block that had a sector in error are undefined. The host should retry the transfer as individual requests to obtain valid error information. Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the command to stop after transfer of the block that contained the error. 8.32 READ NATIVE MAX ADDRESS 8.32.1 Command code F8h 8.32.2 Feature set Host Protected Area feature set. − − Mandatory when the Host Protected Area feature set is implemented. Use prohibited when Removable feature set is implemented. 8.32.3 Protocol Non-data (see 9.4). Page 194 T13/1410D revision 3b 8.32.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na na obs LBA obs DEV na F8h Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. 8.32.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 obs BSY na DRDY 5 4 3 2 1 0 na na Native max address LBA (7:0) Native max address LBA (15:8) Native max address LBA (23:16) obs DEV Native max address LBA (27:24) DF na DRQ na na ERR LBA Low maximum native LBA bits (7:0) for native max address on the device. LBA Mid maximum native LBA bits (15:8) for native max address on the device. LBA High maximum native LBA bits (23:16) for native max address on device. Device maximum native LBA bits (27:24) for native max address on the device. DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.32.6 Error outputs If this command is not supported the device shall return command aborted. Page 195 T13/1410D revision 3b Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT na na 1 na 0 na na ERR na na na na obs BSY na DRDY obs na DEV na na Error register ABRT shall be set to one if this command is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. ERR shall be set to one if an Error register bit is set to one. 8.32.7 Prerequisites DRDY set to one. 8.32.8 Description This command returns the native maximum address. The native maximum address is the highest address accepted by the device in the factory default condition. The native maximum address is the maximum address that is valid when using the SET MAX ADDRESS command. If the 48-bit Address feature set is supported and the 48-bit native max address is greater than 268,435,455, the READ NATIVE MAX ADDRESS command shall return a maximum value of 268,435,454. 8.33 READ NATIVE MAX ADDRESS EXT 8.33.1 Command code 27h 8.33.2 Feature set Host Protected Area feature set and 48-bit Address feature set. − − Mandatory when the Host Protected Area feature set and the 48-bit Address feature set are implemented. Use prohibited when Removable feature set is implemented. 8.33.3 Protocol Non-data (see 9.4). Page 196 T13/1410D revision 3b 8.33.4 Inputs Register 7 6 5 4 3 2 1 0 Features Current Reserved Previous Reserved Sector Count Current Reserved Previous Reserved LBA Low Current Reserved Previous Reserved LBA Mid Current Reserved Previous Reserved LBA High Current Reserved Previous Reserved Device obs LBA obs DEV na Command 27h NOTE − The value indicated as Current is the value most recently written to the register. The value indicated as Previous is the value that was in the register before the most recent write to the register. Device register – the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. 8.33.5 Normal outputs Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 Native max address LBA (7:0) HOB = 1 Native max address LBA (31:24) LBA Mid HOB = 0 Native max address LBA (15:8) HOB = 1 Native max address LBA (39:32) LBA High HOB = 0 Native max address LBA (23:16) HOB = 1 Native max address LBA (47:40) Device obs na obs DEV Reserved na Status BSY DRDY DF na DRQ na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. LBA Low LBA (7:0) of the address of the Native max address when read with Device Control register HOB cleared to zero. LBA (31:24) of the address of the Native max address when read with Device Control register HOB set to one. LBA Mid LBA (15:8) of the address of the Native max address when read with Device Control register HOB cleared to zero. LBA (39:32) of the address of the Native max address when read with Device Control register HOB set to one. LBA High LBA (23:16) of the address of the Native max address when read with Device Control register HOB cleared to zero. Page 197 bit bit bit bit bit T13/1410D revision 3b LBA (47:40) of the address of the Native max address when read with Device Control register HOB bit set to one. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.33.6 Error outputs If this command is not supported the device shall return command aborted. Register 7 6 5 4 3 2 1 0 Error na na na na na ABRT na obs Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Error register ABRT shall be set to one if this command is not supported. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.33.7 Prerequisites DRDY set to one. 8.33.8 Description This command returns the native maximum address. The native maximum address is the highest address accepted by the device in the factory default condition. The native maximum address is the maximum address that is valid when using the SET MAX ADDRESS EXT command. Page 198 T13/1410D revision 3b 8.34 READ SECTOR(S) 8.34.1 Command code 20h 8.34.2 Feature set General feature set − Mandatory for all devices. − PACKET Command feature set devices (see 8.34.5.2). 8.34.3 Protocol PIO data-in (see 9.5). 8.34.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs LBA obs 4 3 na Sector count LBA (7:0) LBA (15:8) LBA (23:16) DEV 20h 2 1 0 LBA (27:24) Sector Count number of sectors to be transferred. A value of 00h specifies that 256 sectors are to be transferred. LBA Low starting LBA bits (7:0). LBA Mid starting LBA bits (15:8). LBA High starting LBA bits (23:16). Device . DEV shall specify the selected device. bits (3:0) starting LBA bits (27:24). 8.34.5 Outputs 8.34.5.1 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na DRQ na na na na na ERR na na na na na obs BSY na DRDY obs DF DEV na Device register Page 199 T13/1410D revision 3b DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.34.5.2 Outputs for PACKET Command feature set devices In response to this command, devices that implement the PACKET Command feature set shall post command aborted and place the PACKET Command feature set signature in the LBA High and the LBA Mid register (see 9.12). 8.34.6 Error outputs An unrecoverable error encountered during the execution of this command results in the termination of the command. The Command Block registers contain the address of the sector where the first unrecoverable error occurred. The amount of data transferred is indeterminate. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na obs BSY 6 UNC na DRDY 5 MC obs DF 4 IDNF 3 MCR na LBA (7:0) LBA (15:8) LBA (23:16) DEV na DRQ 2 ABRT 1 NM 0 obs LBA (27:24) na na ERR Error register UNC shall be set to one if data is uncorrectable. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported or if an error, including an ICRC error, has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. LBA Low, LBA Mid, LBA High, Device shall be written with the address of first unrecoverable error. DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. Page 200 T13/1410D revision 3b 8.34.7 Prerequisites DRDY set to one. 8.34.8 Description This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer shall begin at the sector specified in the LBA Low, LBA Mid, LBA High, and Device registers. The DRQ bit is always set to one prior to data transfer regardless of the presence or absence of an error condition. The device shall interrupt for each DRQ block transferred. 8.35 READ SECTOR(S) EXT 8.35.1 Command code 24h 8.35.2 Feature set 48-bit Address feature set − Mandatory for all devices implementing the 48-bit Address feature set. − Use prohibited when the PACKET feature set is implemented 8.35.3 Protocol PIO data-in (see 9.5). 8.35.4 Inputs Register 7 6 5 4 3 2 1 0 Features Current Reserved Previous Reserved Sector Count Current Sector count (7:0) Previous Sector count (15:8) LBA Low Current LBA (7:0) Previous LBA (31:24) LBA Mid Current LBA (15:8) Previous LBA (39:32) LBA High Current LBA (23:16) Previous LBA (47:40) Device obs LBA obs DEV Reserved Command 24h NOTE − The value indicated as Current is the value most recently written to the register. The value indicated as Previous is the value that was in the register before the most recent write to the register. Sector Count Current number of sectors to be transferred low order, bits (7:0). Sector Count Previous number of sectors to be transferred high order, bits (15:8). LBA Low Current LBA (7:0). LBA Low Previous Page 201 T13/1410D revision 3b LBA (31:24). LBA Mid Current LBA (15:8). LBA Mid Previous LBA (39:32). LBA High Current LBA (23:16). LBA High Previous LBA (47:40). Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. 8.35.5 Normal outputs Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.35.6 Error outputs An unrecoverable error encountered during the execution of this command results in the termination of the command. The Command Block registers contain the address of the sector where the first unrecoverable error occurred. The amount of data transferred is indeterminate. Page 202 T13/1410D revision 3b Register 7 6 5 4 3 2 1 0 Error na UNC MC IDNF MCR ABRT NM obs Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 LBA (7:0) HOB = 1 LBA (31:24) LBA Mid HOB = 0 LBA (15:8) HOB = 1 LBA (39:32) LBA High HOB = 0 LBA (23:16) HOB = 1 LBA (47:40) Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Error register UNC shall be set to one if data is uncorrectable MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. LBA Low LBA (7:0) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (31:24) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA Mid LBA (15:8) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (39:32) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA High LBA (23:16) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (47:40) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. Page 203 T13/1410D revision 3b 8.35.7 Prerequisites DRDY set to one. 8.35.8 Description This command reads from 1 to 65,536 sectors as specified in the Sector Count register. A sector count of 0000h requests 65,536 sectors. The transfer shall begin at the sector specified in the LBA Low, LBA Mid, and LBA High registers. The DRQ bit is always set to one prior to data transfer regardless of the presence or absence of an error condition. The device shall interrupt for each DRQ block transferred. 8.36 READ VERIFY SECTOR(S) 8.36.1 Command code 40h 8.36.2 Feature set General feature set − − Mandatory for all devices not implementing the PACKET Command feature set. Use prohibited for devices implementing the PACKET Command feature set. 8.36.3 Protocol Non-data (see 9.4). 8.36.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs LBA obs 4 3 na Sector count LBA (7:0) LBA (15:8) LBA (23:16) DEV 40h 2 1 0 LBA (27:24) Sector Count number of sectors to be transferred. A value of 00h specifies that 256 sectors are to be transferred. LBA Low starting LBA bits (7:0). LBA Mid starting LBA bits (15:8). LBA High starting LBA bits (23:16). Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. bits (3:0) starting LBA bits (27:24). Page 204 T13/1410D revision 3b 8.36.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na DRQ na na na na na ERR na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.36.6 Error outputs An unrecoverable error encountered during the execution of this command results in the termination of the command. The Command Block registers contain the address of the sector where the first unrecoverable error occurred. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na obs BSY 6 UNC na DRDY 5 MC 4 IDNF 3 MCR obs DF na LBA (7:0) LBA (15:8) LBA (23:16) DEV na DRQ 2 ABRT 1 NM 0 obs LBA (27:24) na na ERR Error register UNC shall be set to one if data is uncorrectable. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported or if an error, including an ICRC error, has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. LBA Low, LBA Mid, LBA High, Device shall be written with the address of first unrecoverable error. DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. Page 205 T13/1410D revision 3b DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.36.7 Prerequisites DRDY set to one. 8.36.8 Description This command is identical to the READ SECTOR(S) command, except that the device shall have read the data from the media, the DRQ bit is never set to one, and no data is transferred to the host. 8.37 READ VERIFY SECTOR(S) EXT 8.37.1 Command code 42h 8.37.2 Feature set 48-bit Address feature set − Mandatory for all devices implementing the 48-bit Address feature set. − Use prohibited when the PACKET feature set is implemented 8.37.3 Protocol Non-data (see 9.4). 8.37.4 Inputs Register 7 6 5 4 3 2 1 0 Features Current Reserved Previous Reserved Sector Count Current Sector count (7:0) Previous Sector count (15:8) LBA Low Current LBA (7:0) Previous LBA (31:24) LBA Mid Current LBA (15:8) Previous LBA (39:32) LBA High Current LBA (23:16) Previous LBA (47:40) Device obs LBA obs DEV Reserved Command 42h NOTE − The value indicated as Current is the value most recently written to the register. The value indicated as Previous is the value that was in the register before the most recent write to the register. Sector Count Current number of sectors to be transferred low order, bits (7:0). Sector Count Previous number of sectors to be transferred high order, bits (15:8). LBA Low Current LBA (7:0). Page 206 T13/1410D revision 3b LBA Low Previous LBA (31:24). LBA Mid Current LBA (15:8). LBA Mid Previous LBA (39:32). LBA High Current LBA (23:16). LBA High Previous LBA (47:40). Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. 8.37.5 Normal outputs Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.37.6 Error outputs An unrecoverable error encountered during the execution of this command results in the termination of the command. The Command Block registers contain the address of the sector where the first unrecoverable error occurred. Page 207 T13/1410D revision 3b Register 7 6 5 4 3 2 1 0 Error na UNC MC IDNF MCR ABRT NM obs Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 LBA (7:0) HOB = 1 LBA (31:24) LBA Mid HOB = 0 LBA (15:8) HOB = 1 LBA (39:32) LBA High HOB = 0 LBA (23:16) HOB = 1 LBA (47:40) Device obs na obs DEV Reserved na Status BSY DRDY DF na DRQ na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Error register UNC shall be set to one if data is uncorrectable. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. LBA Low LBA (7:0) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (31:24) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA Mid LBA (15:8) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (39:32) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA High LBA (23:16) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (47:40) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. Page 208 T13/1410D revision 3b 8.37.7 Prerequisites DRDY set to one. 8.37.8 Description This command is identical to the READ SECTOR(S) EXT command, except that the device shall have read the data from the media, the DRQ bit is never set to one, and no data is transferred to the host. 8.38 SECURITY DISABLE PASSWORD 8.38.1 Command code F6h 8.38.2 Feature set Security Mode feature set. − Mandatory when the Security Mode feature set is implemented. 8.38.3 Protocol PIO data-out (see 9.6). 8.38.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 1 0 na ERR na na na na na obs na obs DEV na F6h Device register DEV shall specify the selected device. 8.38.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 DRQ na na na na na na obs BSY na DRDY obs DF DEV na na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. Page 209 T13/1410D revision 3b DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.38.6 Error outputs The device shall return command aborted if the command is not supported, the device is in Locked mode, or the device is in Frozen mode. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT DRQ na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Error register ABRT shall be set to one if this command is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.38.7 Prerequisites DRDY set to one. Device shall be in Unlocked mode. 8.38.8 Description The SECURITY DISABLE PASSWORD command transfers 512 bytes of data from the host. Table 40 defines the content of this information. If the password selected by word 0 matches the password previously saved by the device, the device shall disable the Lock mode. This command shall not change the Master password. The Master password shall be reactivated when a User password is set(see 6.13). Word 0 1-16 17-255 Page 210 Table 40 − Security password content Content Control word Bit 0 Identifier 0=compare User password 1=compare Master password Bit (15:1) Reserved Password (32 bytes) Reserved T13/1410D revision 3b 8.39 SECURITY ERASE PREPARE 8.39.1 Command code F3h 8.39.2 Feature set Security Mode feature set. − Mandatory when the Security Mode feature set is implemented. 8.39.3 Protocol Non-data (see 9.4). 8.39.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na na obs na obs DEV na F3h Device register DEV shall specify the selected device. 8.39.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na DRQ na na na na na ERR na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.39.6 Error outputs The device shall return command aborted if the command is not supported or the device is in Frozen mode. Page 211 T13/1410D revision 3b Register Error Sector Count LBA Low LBA Mid LBAHigh Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT DRQ na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Error register ABRT shall be set to one if this command is not supported or device is in Frozen mode. ABRT may be set to one if the device is not able to complete the action requested by the command. NOTE − In a previous revision of this standard, there were conflicting descriptions of the handling of this command when in the Frozen mode. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.39.7 Prerequisites DRDY set to one. 8.39.8 Description The SECURITY ERASE PREPARE command shall be issued immediately before the SECURITY ERASE UNIT command to enable device erasing and unlocking. This command prevents accidental loss of data on the device. 8.40 SECURITY ERASE UNIT 8.40.1 Command code F4h 8.40.2 Feature set Security Mode feature set. − Mandatory when the Security Mode feature set is implemented. 8.40.3 Protocol PIO data-out (see 9.6). Page 212 T13/1410D revision 3b 8.40.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na 3 2 1 0 na DRQ na na na na na ERR na na na na na obs na obs DEV F4h Device register DEV shall specify the selected device. 8.40.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.40.6 Error outputs The device shall return command aborted if the command is not supported, the device is in Frozen mode, not preceded by a SECURITY ERASE PREPARE command, if Enhance Erase is specified but not supported, or if the data area is not successfully overwritten. Register Error Sector Count LBA Low LBA Mid LBAHigh Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT DRQ na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Page 213 T13/1410D revision 3b Error register ABRT shall be set to one if this command is not supported, device is in Frozen mode, not preceded by a SECURITY ERASE PREPARE command, or if the data area is not successfully overwritten. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.40.7 Prerequisites DRDY set to one. This command shall be immediately preceded by a SECURITY ERASE PREPARE command. 8.40.8 Description This command transfers 512 bytes of data from the host. Table 41 defines the content of this information. If the password does not match the password previously saved by the device, the device shall reject the command with command aborted. The SECURITY ERASE PREPARE command shall be completed immediately prior to the SECURITY ERASE UNIT command. If the device receives a SECURITY ERASE UNIT command without an immediately prior SECURITY ERASE PREPARE command, the device shall command abort the SECURITY ERASE UNIT command. When Normal Erase mode isspecified, the SECURITY ERASE UNIT command shall write binary zeroes to all user data areas. The Enhanced Erase mode is optional. When Enhanced Erase mode isspecified, the device shall write predetermined data patterns to all user data areas. In Enhanced Erase mode, all previously written user data shall be overwritten, including sectors that are no longer in use due to reallocation. This command shall disable the device Lock mode, however, the Master password shall still be stored internally within the device and may be reactivated later when a new User password is set. Word 0 1-16 17-255 Table 41 − SECURITY ERASE UNIT password Content Control word Bit 0 Identifier 0=Compare User password 1=Compare Master password Bit 1 Erase mode 0=Normal Erase 1=Enhanced Erase Bit (15:2) Reserved Password (32 bytes) Reserved 8.41 SECURITY FREEZE LOCK 8.41.1 Command code F5h Page 214 T13/1410D revision 3b 8.41.2 Feature set Security Mode feature set. − Mandatory when the Security Mode feature set is implemented. 8.41.3 Protocol Non-data (see 9.4). 8.41.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 1 0 na ERR na na na na na obs na obs DEV na F5h Device register DEV shall specify the selected device. 8.41.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 na na na na na obs BSY na DRDY obs DF DEV na na DRQ na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.41.6 Error outputs The device shall return command aborted if the command is not supported, or the device is in Locked mode. Page 215 T13/1410D revision 3b Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT DRQ na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Error register ABRT shall be set to one if this command is not supported or device is in locked mode. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.41.7 Prerequisites DRDY set to one. 8.41.8 Description The SECURITY FREEZE LOCK command shall set the device to Frozen mode. After command completion any other commands that update the device Lock mode shall be command aborted. Frozen mode shall be disabled by power-off or hardware reset. If SECURITY FREEZE LOCK shall be issued when the device is in Frozen mode, the command executes and the device shall remain in Frozen mode. Commands disabled by SECURITY FREEZE LOCK are: − − − − − SECURITY SET PASSWORD SECURITY UNLOCK SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT 8.42 SECURITY SET PASSWORD 8.42.1 Command code F1h 8.42.2 Feature set Security Mode feature set. − Mandatory when the Security Mode feature set is implemented. Page 216 T13/1410D revision 3b 8.42.3 Protocol PIO data-out (see 9.6). 8.42.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 1 0 na ERR na na na na na obs na obs DEV na F1h Device register DEV shall specify the selected device. 8.42.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 na na na na na obs BSY na DRDY obs DF DEV na na DRQ na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.42.6 Error outputs The device shall return command aborted if the command is not supported, the device is in Locked mode, or the device is in Frozen mode. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT DRQ na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Page 217 T13/1410D revision 3b Error register ABRT shall be set to one if this command is not supported, if device is in Frozen mode, or if device is in locked mode. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.42.7 Prerequisites DRDY set to one. 8.42.8 Description This command transfers 512 bytes of data from the host. Table 42 defines the content of this information. The data transferred controls the function of this command. Table 43 defines the interaction of the identifier and security level bits. The revision code field shall be returned in the IDENTIFY DEVICE word 92. The valid revision codes are 0001h through FFFEh. A value of 0000h or FFFFh indicates that the Master Password Revision Code is not supported. Word 0 1-16 17 18-255 Table 42 − SECURITY SET PASSWORD data content Content Control word Bit 0 Identifier 0=set User password 1=set Master password Bits (7:1) Reserved Bit 8 Security level 0=High 1=Maximum Bits (15:9) Reserved Password (32 bytes) Master Password Revision Code (valid if word 0 bit 0 = 1) Reserved Identifier User Level High User Maximum Master High or Maximum Page 218 Table 43 − Identifier and security level bit interaction Command result The password supplied with the command shall be saved as the new User password. The Lock mode shall be enabled from the next power-on or hardware reset. The device shall then be unlocked by either the User password or the previously set Master password. The password supplied with the command shall be saved as the new User password. The Lock mode shall be enabled from the next power-on or hardware reset. The device shall then be unlocked by only the User password. The Master password previously set is still stored in the device but shall not be used to unlock the device. This combination shall set a Master password but shall not enable or disable the Lock mode. The security level is not changed. Master password revision code set to the value in Master Password Revision Code field. T13/1410D revision 3b 8.43 SECURITY UNLOCK 8.43.1 Command code F2h 8.43.2 Feature set Security Mode feature set. − Mandatory when the Security Mode feature set is implemented. 8.43.3 Protocol PIO data-out (see 9.6). 8.43.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 1 0 na ERR na na na na na obs na obs DEV na F2h Device register DEV shall specify the selected device. 8.43.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 DRQ na na na na na na obs BSY na DRDY obs DF DEV na na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.43.6 Error outputs The device shall return command aborted if the command is not supported, or the device is in Frozen mode. Page 219 T13/1410D revision 3b Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT DRQ na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Error register ABRT shall be set to one if this command is not supported or if device is in Frozen mode. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.43.7 Prerequisites DRDY set to one. 8.43.8 Description This command transfers 512 bytes of data from the host. Table 40 defines the content of this information. If the Identifier bit is set to Master and the device is in high security level, then the password supplied shall be compared with the stored Master password. If the device is in maximum security level then the unlock shall be rejected. If the Identifier bit is set to user then the device shall compare the supplied password with the stored User password. If the password compare fails then the device shall return command aborted to the host and decrements the unlock counter. This counter shall be initially set to five and shall be decremented for each password mismatch when SECURITY UNLOCK is issued and the device is locked. When this counter reaches zero then SECURITY UNLOCK and SECURITY ERASE UNIT commands shall be command aborted until a power-on reset or a hardware reset. SECURITY UNLOCK commands issued when the device is unlocked have no effect on the unlock counter. 8.44 SEEK 8.44.1 Command code 70h Page 220 T13/1410D revision 3b 8.44.2 Feature set General feature set − − Mandatory for devices not implementing the PACKET Command feature set. Use prohibited for devices implementing the PACKET Command feature set. 8.44.3 Protocol Non-data (see 9.4). 8.44.4 Inputs The LBA High register, the LBA Mid register, a portion of Device register, and the LBA Low register contain the address of a sector that the host may request in a subsequent command. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs LBA obs 4 3 na na LBA (7:0) LBA (15:8) LBA (23:16) DEV 70h 2 1 0 LBA (27:24) LBA Low LBA bits (7:0). LBA Mid LBA bits (15:8). LBA High LBA bits (23:16). Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. bits (3:0) LBA bits (27:24). 8.44.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na ERR na na na na na obs BSY na DRDY obs DF DEV DSC na DRQ na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DSC (Device Seek Complete) shall be set to one concurrent with or after the setting of DRDY to one. DF (Device Fault) shall be cleared to zero. Page 221 T13/1410D revision 3b DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.44.6 Error outputs Some devices may not report IDNF because they do not range check the address values requested by the host. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 MC 4 IDNF 3 MCR 2 ABRT DRQ na 1 NM 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Error register MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported or if an error, including an ICRC error, has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.44.7 Prerequisites DRDY set to one. 8.44.8 Description This command allows the host to provide advanced notification that particular data may be requested by the host in a subsequent command. DSC shall be set to one concurrent with or after the setting of DRDY to one when updating the Status register for this command. 8.45 SERVICE 8.45.1 Command code A2h Page 222 T13/1410D revision 3b 8.45.2 Feature set Overlap and Queued feature sets − Mandatory when the PACKET, Overlapped feature set is implemented. 8.45.3 Protocol PACKET or READ/WRITE DMA QUEUED (see 9.8 and 9.9). 8.45.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na na na na na na obs na obs DEV A2h Device register DEV shall specify the selected device. 8.45.5 Outputs Outputs as a result of a SERVICE command are described in the command description for the command for which SERVICE is being requested. 8.45.6 Prerequisites The device shall have performed a bus release for a previous overlap PACKET, READ DMA QUEUED, READ DMA QUEUED EXT, WRITE DMA QUEUED, or WRITE DMA QUEUED EXT command and shall have set the SERV bit to one to request the SERVICE command be issued to continue data transfer and/or provide command status (see 8.46.20). 8.45.7 Description The SERVICE command is used to provide data transfer and/or status of a command that was previously bus released. 8.46 SET FEATURES 8.46.1 Command code EFh Page 223 T13/1410D revision 3b 8.46.2 Feature set General feature set − − − − − Mandatory for all devices. Set transfer mode subcommand is mandatory. Enable/disable write cache subcommands are mandatory when a write cache is implemented. Enable/disable Media Status Notification sub commands are mandatory if the Removable Media feature set is implemented. All other subcommands are optional. 8.46.3 Protocol Non-data (see 9.4). 8.46.4 Inputs Table 44 defines the value of the subcommand in the Feature register. Some subcommands use other registers, such as the Sector Count register to pass additional information to the device. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs na obs 4 3 Subcommand code Subcommand specific Subcommand specific Subcommand specific Subcommand specific DEV na EFh 2 1 0 na na na Device register DEV shall specify the selected device. 8.46.5 Normal outputs See the subcommand descriptions. 8.46.6 Error outputs If any subcommand input value is not supported or is invalid, the device shall return command aborted. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na DRQ na Error register ABRT shall be set to one if this subcommand is not supported or if the value is invalid. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Page 224 T13/1410D revision 3b Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.46.7 Prerequisites DRDY shall be set to one. 8.46.8 Description This command is used by the host to establish parameters that affect the execution of certain device features. Table 44 defines these features. At power-on, or after a hardware reset, the default settings of the functions specified by the subcommands are vendor specific. Page 225 T13/1410D revision 3b Table 44 − SET FEATURES register definitions Value (see note) 01h Enable 8-bit PIO transfer mode (CFA feature set only) 02h Enable write cache 03h Set transfer mode based on value in Sector Count register. Table 45 defines values. 04h Obsolete 05h Enable advanced power management 06h Enable Power-Up In Standby feature set. 07h Power-Up In Standby feature set device spin-up. 09h Reserved for Address offset reserved area boot method technical report 0Ah Enable CFA power mode 1 31h Disable Media Status Notification 33h Obsolete 42h Enable Automatic Acoustic Management feature set 44h Obsolete 54h Obsolete 55h Disable read look-ahead feature 5Dh Enable release interrupt 5Eh Enable SERVICE interrupt 66h Disable reverting to power-on defaults 77h Obsolete 81h Disable 8-bit PIO transfer mode (CFA feature set only) 82h Disable write cache 84h Obsolete 85h Disable advanced power management 86h Disable Power-Up In Standby feature set. 88h Obsolete 89h Reserved for Address offset reserved area boot method technical report 8Ah Disable CFA power mode 1 95h Enable Media Status Notification 99h Obsolete 9Ah Obsolete Aah Enable read look-ahead feature Abh Obsolete BBh Obsolete C2h Disable Automatic Acoustic Management feature set CCh Enable reverting to power-on defaults DDh Disable release interrupt DEh Disable SERVICE interrupt F0h-FFh Reserved for assignment by the CompactFlash Association NOTE − All values not shown are reserved for future definition. 8.46.9 Enable/disable 8-bit PIO data transfer Devices implementing the CFA feature set shall support 8-bit PIO data transfers. Devices not implementing the CFA feature set shall not support 8-bit PIO data transfers. When 8-bit PIO data transfer is enabled the Data register is 8-bits wide using only DD7 to DD0. 8.46.10 Enable/disable write cache Subcommand codes 02h and 82h allow the host to enable or disable write cache in devices that implement write cache. When the subcommand disable write cache is issued, the device shall initiate the sequence to Page 226 T13/1410D revision 3b flush cache to non-volatile memory before command completion (see 8.12). This subcommand does not apply to commands that have a Flush to Disk bit. 8.46.11 Set transfer mode A host selects the transfer mechanism by Set Transfer Mode, subcommand code 03h, and specifying a value in the Sector Count register. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. The host may change the selected modes by the SET FEATURES command. Table 45 − Transfer mode values Mode Bits (7:3) PIO default mode 00000b PIO default mode, disable IORDY 00000b PIO flow control transfer mode 00001b Retired 00010b Multiword DMA mode 00100b Ultra DMA mode 01000b Reserved 10000b mode = transfer mode number Bits (2:0) 000b 001b mode na mode mode na If a device supports this standard, and receives a SET FEATURES command with a Set Transfer Mode parameter and a Sector Count register value of “00000000b”, the device shall set the default PIO mode. If the value is “00000001b” and the device supports disabling of IORDY, then the device shall set the default PIO mode and disable IORDY. A device shall support all PIO modes below the highest mode supported, e.g., if PIO mode 1 is supported PIO mode 0 shall be supported. Support of IORDY is mandatory when PIO mode 3 or above is the current mode of operation. A device shall support all Multiword DMA modes below the highest mode supported, e.g., if Multiword DMA mode 1 is supported Multiword DMA mode 0 shall be supported. A device shall support all Ultra DMA modes below the highest mode supported, e.g., if Ultra DMA mode 1 is supported Ultra DMA mode 0 shall be supported. If an Ultra DMA mode is enabled any previously enabled Multiword DMA mode shall be disabled by the device. If a Multiword DMA mode is enabled any previously enabled Ultra DMA mode shall be disabled by the device. For systems using a cable assembly, the host shall detect that an 80-conductor cable assembly is connecting the host with the device(s) before enabling any Ultra DMA mode greater than 2 in the device(s) (see Annex B). 8.46.12 Enable/disable advanced power management Subcommand code 05h allows the host to enable Advanced Power Management. To enable Advanced Power Management, the host writes the Sector Count register with the desired advanced power management level and then executes a SET FEATURES command with subcommand code 05h. The power management level is a scale from the lowest power consumption setting of 01h to the maximum performance level of FEh. Table 46 shows these values. Page 227 T13/1410D revision 3b Table 46 − Advanced power management levels Level Sector Count value Maximum performance FEh Intermediate power management levels without Standby 81h-FDh Minimum power consumption without Standby 80h Intermediate power management levels with Standby 02h-7Fh Minimum power consumption with Standby 01h Reserved FFh Reserved 00h Device performance may increase with increasing power management levels. Device power consumption may increase with increasing power management levels. The power management levels may contain discrete bands. For example, a device may implement one power management method from 80h to A0h and a higher performance, higher power consumption method from level A1h to FEh. Advanced power management levels 80h and higher do not permit the device to spin down to save power. Subcommand code 85h disables Advanced Power Management. Subcommand 85h may not be implemented on all devices that implement SET FEATURES subcommand 05h. 8.46.13 Enable/disable Power-Up In Standby feature set Subcommand code 06h enables the Power-Up In Standby feature set. When this feature set is enabled, the device shall power-up into Standby mode, i.e., the device shall be ready to receive commands but shall not spinup (see 6.18). Having been enabled, this feature shall remain enabled through power-down, hardware reset and software rest. Subcommand code 86h disables the Power-Up In Standby feature set. When this feature set is disabled, the device shall power-up into Active mode. The factory default for this feature set shall be disabled. 8.46.14 Enable/disable CFA power mode 1 Subcommand code 0Ah enables CFA Power Mode 1. CFA devices may consume up to 500 mA maximum average RMS current for either 3.3 V or 5 V operation in Power Mode 1. CFA devices revert to Power Mode 1 on hardware or power-on reset. CFA devices revert to Power Mode 1 on software reset except when Set Features disable reverting to power-on defaults is set (see 8.15.57). Enabling CFA Power Mode 1 does not spin up rotating media devices. Subcommand 8Ah disables CFA Power Mode 1, placing the device to CFA Power Mode 0. CFA devices may consume up to 75 mA maximum average RMS current for 3.3 V or 100 mA maximum average RMS current for 5 V operation in Power Mode 0. A device in Power Mode 0 the device shall accept the following commands: − − − − − − − − IDENTIFY DEVICE SET FEATURES (function codes 0Ah and 8Ah) STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE EXECUTE DEVICE DIAGNOSTICS CFA REQUEST EXTENDED ERROR A device in Power Mode 0 may accept any command that the device is capable of executing within the Power Mode 0 current restrictions. Commands that require more current than specified for Power Mode 0 shall be rejected with an abort error. Page 228 T13/1410D revision 3b 8.46.15 Power-Up In Standby feature set device spin-up Subcommand code 07h shall cause a device that has powered-up into Standby to go to the Active state (see 6.18 and Figure 8). 8.46.16 Enable/disable Media Status Notification Subcommand code 31h disables Media Status Notification and leaves the media in an unlocked state. If Media Status Notification is disabled when this subcommand is received, the subcommand has no effect. Subcommand code 95h enables Media Status Notification and clears any previous media lock state. This subcommand returns the device capabilities for media eject, media lock, previous state of Media Status Notification and the current version of Media Status Notification supported in the LBA Mid and LBA High registers as described below. Register LBA Mid LBA High 7 6 5 4 3 2 1 0 PEJ LOCK PENA VER Reserved LBA Mid register VER shall contain the Media Status Notification version supported by the device (currently 0x00h). LBA High register PENA shall be set to one if Media Status Notification was enabled prior to the receipt of this command. LOCK shall be set to one if the device is capable of locking the media preventing manual ejection. PEJ shall be set to one if the device has a power eject mechanism that is capable of physically ejecting the media when a MEDIA EJECT command is sent to the device. This bit shall be set to zero if the device only unlocks the media when the device receives a MEDIA EJECT command. 8.46.17 Enable/disable Automatic Acoustic Management Subcommand code 42h allows the host to enable the Automatic Acoustic Management feature set. To enable the Automatic Acoustic Management feature set, the host writes the Sector Count register with the requested automatic acoustic management level and executes a SET FEATURES command with subcommand code 42h. The acoustic management level is selected on a scale from 01h to FEh. Table 47 shows the acoustic management level values. Enabling or disabling of the Automatic Acoustic Management feature set, and the current automatic acoustic management level setting shall be preserved by the device across all forms of reset, i.e. power-on, hardware, and software resets. Table 47 − Automatic acoustic management levels Level Sector Count value Reserved FFh Maximum performance FEh Intermediate acoustic management levels 81h-FDh Minimum acoustic emanation level 80h Retired 01h-7Fh Vendor Specific 00h Device performance may increase with increasing acoustic management levels. Device power consumption may decrease with decreasing acoustic management levels. The acoustic management levels may contain discrete bands. For example, a device may implement one acoustic management method from 80h to BFh and a higher performance, higher acoustic management method from level C0h to FEh. Page 229 T13/1410D revision 3b Upon successful completion of this SET FEATURES subcommand, IDENTIFY DEVICE word 94, bits (7:0) shall be updated by the device. If the command is aborted by the device, the previous automatic acoustic management state shall be retained. Subcommand code C2h disables the Automatic Acoustic Management feature set. Devices that implement SET FEATURES subcommand 42h are not required to implement subcommand C2h. If device successfully completes execution of this subcommand, then the acoustic behavior of the device shall be vendor-specific, and the device shall return zeros in bits (7:0) of word 94 and bit 9 of word 86 of the IDENTIFY DEVICE data. 8.46.18 Enable/disable read look-ahead Subcommand codes AAh and 55h allow the host to request the device to enable or disable read look-ahead. Error recovery performed by the device is vendor specific. 8.46.19 Enable/disable release interrupt Subcommand codes 5Dh and DDh allow a host to enable or disable the asserting of interrupt pending when a device releases the bus for an overlapped PACKET command. 8.46.20 Enable/disable SERVICE interrupt Subcommand codes 5Eh and DEh allow a host to enable or disable the asserting of an interrupt pending when DRQ is set to one in response to a SERVICE command. 8.46.21 Enable/disable reverting to defaults Subcommand codes CCh and 66h allow the host to enable or disable the device from reverting to power-on default values. A setting of 66h allows settings that may have been modified since power-on to remain at the same setting after a software reset. 8.47 SET MAX Individual SET MAX commands are identified by the value placed in the Features register. Table 48 shows these Features register values. Table 48 − SET MAX Features register values Value Command 00h Obsolete 01h SET MAX SET PASSWORD 02h SET MAX LOCK 03h SET MAX UNLOCK 04h SET MAX FREEZE LOCK 05h-FFh Reserved 8.47.1 SET MAX ADDRESS 8.47.1.1 Command code F9h (see 8.47.1.7). Page 230 T13/1410D revision 3b 8.47.1.2 Feature set Host Protected Area feature set. − − Mandatory when the Host Protected Area feature set is implemented. Use prohibited when the Removable feature set is implemented. 8.47.1.3 Protocol Non-data (see 9.4). 8.47.1.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na obs LBA obs na V V SET MAX LBA (7:0) SET MAX LBA (15:8) SET MAX LBA (23:16) DEV SET MAX LBA (27:24) F9h Sector Count V V (Value volatile). If bit 0 is set to one, the device shall preserve the maximum values over power-up or hardware reset. If bit 0 is cleared to zero, the device shall revert to the most recent non-volatile maximum address value setting over power-up or hardware reset. LBA Low contains LBA bits (7:0) value to be set. LBA Mid contains LBA bits (15:8) value to be set. LBA High contains the LBA bits (23:16) value to be set. Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. Bits (3:0) contain the LBA bits (27:24) value to be set. 8.47.1.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 obs BSY na DRDY obs DF 4 3 na na LBA (7:0) LBA (15:8) LBA (23:16) DEV na DRQ 2 1 LBA (27:24) na na 0 ERR LBA LowLBA bits (7:0) set on the device. LBA Mid LBA bits (15:8) set on the device. LBA High LBA bits (23:16) set on device. Page 231 T13/1410D revision 3b Device DEV shall indicate the selected device. LBA bits (27:24) set on the device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.47.1.6 Error outputs If this command is not supported, the maximum value to be set exceeds the capacity of the device, a host protected area has been established by a SET MAX ADDRESS EXT command, or the device is in the Set_Max_Locked or Set_Max_Frozen state, then the device shall return command aborted. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 IDNF 3 na 2 ABRT na na 1 na 0 na na ERR na na na na obs BSY na DRDY obs na DEV na na Error register ABRT shall be set to one if this command is not supported, maximum value requested exceeds the device capacity, a host protected area has been estabished by a SET MAX ADDRESS EXT command, the device is in the Set_Max_Locked or Set_Max_Frozen state, or the command is not immediately preceded by a READ NATIVE MAX ADDRESS command. ABRT may be set to one if the device is not able to complete the action requested by the command. IDNF shall be set to one if the command was the second non-volatile SET MAX ADDRESS command after power-on or hardware reset. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. ERR shall be set to one if an Error register bit is set to one. 8.47.1.7 Prerequisites DRDY set to one. A successful READ NATIVE MAX ADDRESS command shall immediately precede a SET MAX ADDRESS command. 8.47.1.8 Description After successful command completion, all read and write access attempts to addresses greater than specified by the successful SET MAX ADDRESS command shall be rejected with an IDNF error. IDENTIFY DEVICE response words (61:60) shall reflect the maximum address set with this command. If the 48-bit Address feature set is supported, the value placed in IDENTIFY DEVICE response words (103:100) shall be the same as the value placed in words (61:60). Page 232 T13/1410D revision 3b Hosts shall not issue more than one non-volatile SET MAX ADDRESS or SET MAX ADDRESS EXT command after a power-on or hardware reset. Devices should report an IDNF error upon receiving a second non-volatile SET MAX ADDRESS command after a power-on or hardware reset. The contents of IDENTIFY DEVICE words and the max address shall not be changed if a SET MAX ADDRESS command fails. After a successful SET MAX ADDRESS command using a new maximum LBA the content of all IDENTIFY DEVICE words shall comply with 6.2.1 and the content of words (61:60) shall be equal to the new Maximum LBA + 1. 8.47.2 SET MAX SET PASSWORD 8.47.2.1 Command code F9h with the content of the Features register equal to 01h. 8.47.2.2 Feature set Host Protected Area feature set. − − Mandatory when the Host Protected Area feature set security extensions are implemented. Use prohibited when the Removable feature set is implemented. 8.47.2.3 Protocol PIO data-out (see 9.6). 8.47.2.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 1 0 na ERR 01h na na na na obs na obs DEV na F9h Device DEV shall specify the selected device. 8.47.2.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 na na na na na obs BSY na DRDY obs DF DEV na na DRQ na Device Page 233 T13/1410D revision 3b DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.47.2.6 Error outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT na na 1 na 0 na na ERR na na na na obs BSY na DRDY obs na DEV na na Error register ABRT shall be set to one if this command is not supported or the device is in the Set_Max_Locked or Set_Max_Frozen state. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. ERR shall be set to one if an Error register bit is set to one. 8.47.2.7 Prerequisites DRDY set to one. This command shall not be immediately preceded by a READ NATIVE MAX ADDRESS command. If this command is immediately preceded by a READ NATIVE MAX ADDRESS command, it shall be interpreted as a SET MAX ADDRESS command. 8.47.2.8 Description This command requests a transfer of a single sector of data from the host. Table 49 defines the content of this sector of information. The password is retained by the device until the next power cycle. When the device accepts this command the device is in Set_Max_Unlocked state. Table 49 − SET MAX SET PASSWORD data content Word Content 0 Reserved 1-16 Password (32 bytes) 17-255 Reserved 8.47.3 SET MAX LOCK 8.47.3.1 Command code F9h with the content of the Features register equal to 02h. Page 234 T13/1410D revision 3b 8.47.3.2 Feature set Host Protected Area feature set. − − Mandatory when the Host Protected Area feature set security extensions are implemented. Use prohibited when the Removable feature set is implemented. 8.47.3.3 Protocol Non-data (see 9.4). 8.47.3.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 1 0 na ERR 02h na na na na obs na obs DEV na F9h Device DEV shall specify the selected device. 8.47.3.5 Normal outputs Register Error Sector Count LBA low LBA Mid LBA High Device Status 7 6 5 4 3 2 na na na na na obs BSY na DRDY obs DF DEV na na DRQ na Device DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. Page 235 T13/1410D revision 3b 8.47.3.6 Error outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT na na 1 na 0 na na ERR na na na na obs BSY na DRDY obs na DEV na na Error register ABRT shall be set to one if this command is not supported or the device is not in the Set_Max_Locked state. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. ERR shall be set to one if an Error register bit is set to one. 8.47.3.7 Prerequisites DRDY set to one. This command shall not be immediately preceded by a READ NATIVE MAX ADDRESS command. If this command is immediately preceded by a READ NATIVE MAX ADDRESS command, it shall be interpreted as a SET MAX ADDRESS command. 8.47.3.8 Description The SET MAX LOCK command sets the device into Set_Max_Locked state. After this command is completed any other SET MAX commands except SET MAX UNLOCK and SET MAX FREEZE LOCK shall be command aborted. The device shall remain in this state until a power cycle or command completion without error of a SET MAX UNLOCK or SET MAX FREEZE LOCK command. 8.47.4 SET MAX UNLOCK 8.47.4.1 Command code F9h with the content of the Features register equal to 03h. 8.47.4.2 Feature set Host Protected Area feature set. − − Mandatory when the Host Protected Area feature set security extensions are implemented. Use prohibited when the Removable feature set is implemented. 8.47.4.3 Protocol PIO data-out (see 9.6). Page 236 T13/1410D revision 3b 8.47.4.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 1 0 03h na na na na obs na obs DEV na F9h Device DEV shall specify the selected device. 8.47.4.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 na na na na na obs BSY na DRDY obs DF DEV na na DRQ na na ERR 3 na 2 ABRT 1 na 0 na na na na ERR Device DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.47.4.6 Error outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na na na na na obs BSY na DRDY obs na DEV na na Error register ABRT shall be set to one if this command is not supported or the device is not in the Set_Max_Locked state. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. Page 237 T13/1410D revision 3b ERR shall be set to one if an Error register bit is set to one. 8.47.4.7 Prerequisites DRDY set to one. This command shall not be immediately preceded by a READ NATIVE MAX ADDRESS command. If this command is immediately preceded by a READ NATIVE MAX ADDRESS command, it shall be interpreted as a SET MAX ADDRESS command. 8.47.4.8 Description This command requests a transfer of a single sector of data from the host. Table 49 defines the content of this sector of information. The password supplied in the sector of data transferred shall be compared with the stored SET MAX password. If the password compare fails, then the device shall return command aborted and decrement the unlock counter. On the acceptance of the SET MAX LOCK command, this counter is set to a value of five and shall be decremented for each password mismatch when SET MAX UNLOCK is issued and the device is locked. When this counter reaches zero, then the SET MAX UNLOCK command shall return command aborted until a power cycle. If the password compare matches, then the device shall make a transition to the Set_Max_Unlocked state and all SET MAX commands shall be accepted. 8.47.5 SET MAX FREEZE LOCK 8.47.5.1 Command code F9h with the content of the Features register equal to 04h. 8.47.5.2 Feature set Host Protected Area feature set. − − Mandatory when the Host Protected Area feature set security extensions are implemented. Use prohibited when the Removable feature set is implemented. 8.47.5.3 Protocol Non-data (see 9.4). 8.47.5.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 4 3 2 1 04h na na na na obs na Device DEV shall specify the selected device. Page 238 5 obs DEV na F9h 0 T13/1410D revision 3b 8.47.5.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 DRQ na na ERR 3 na 2 ABRT 1 na 0 na na ERR na na na na na obs BSY na DRDY obs DF DEV na na Device DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.47.5.6 Error outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na na na na na obs BSY na DRDY obs na DEV na na na na Error register ABRT shall be set to one if this command is not supported or the device is in the Set_Max_Unlocked state. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. ERR shall be set to one if an Error register bit is set to one. 8.47.5.7 Prerequisites DRDY set to one. A SET MAX SET PASSWORD command shall previously have been successfully completed. This command shall not be immediately preceded by a READ NATIVE MAX ADDRESS command. If this command is immediately preceded by a READ NATIVE MAX ADDRESS command, it shall be interpreted as a SET MAX ADDRESS command. 8.47.5.8 Description The SET MAX FREEZE LOCK command sets the device to Set_Max_Frozen state. After command completion any subsequent SET MAX commands shall be command aborted. Page 239 T13/1410D revision 3b Commands disabled by SET MAX FREEZE LOCK are: − − − − SET MAX ADDRESS SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK 8.48 SET MAX ADDRESS EXT 8.48.1.1 Command code 37h. 8.48.1.2 Feature set Host Protected Area feature set and 48-bit Address feature set. − − Mandatory when the Host Protected Area feature set and the 48-bit Address feature set are implemented. Use prohibited when the Removable Media feature set is implemented. 8.48.1.3 Protocol Non-data (see 9.4). 8.48.1.4 Inputs Register 7 6 5 4 3 2 1 0 Features Current Reserved Previous Reserved Sector Count Current Reserved V V Previous Reserved LBA Low Current SET MAX LBA (7:0) Previous SET MAX LBA (31:24) LBA Mid Current SET MAX LBA (15:8) Previous SET MAX LBA (39:32) LBA High Current SET MAX LBA (23:16) Previous SET MAX LBA (47:40) Device obs LBA obs DEV Reserved Command 37h NOTE − The value indicated as Current is the value most recently written to the register. The value indicated as Previous is the value that was in the register before the most recent write to the register. Sector Count Current V V (Value volatile). If bit 0 is set to one, the device shall preserve the maximum values over power-up or hardware reset. If bit 0 is cleared to zero, the device shall revert to the most recent nonvolatile maximum address value setting over power-up or hardware reset. LBA Low Current SET MAX LBA (7:0). LBA Low Previous SET MAX LBA (31:24). LBA Mid Current SET MAX LBA (15:8). LBA Mid Previous SET MAX LBA (39:32). Page 240 T13/1410D revision 3b LBA High Current SET MAX LBA (23:16). LBA High Previous SET MAX LBA (47:40). Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. 8.48.1.5 Normal outputs Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 SET MAX LBA (7:0) HOB = 1 SET MAX LBA (31:24) LBA Mid HOB = 0 SET MAX LBA (15:8) HOB = 1 SET MAX LBA (39:32) LBA High HOB = 0 SET MAX LBA (23:16) HOB = 1 SET MAX LBA (47:40) Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. LBA Low LBA (7:0) of the address of the SET MAX ADDRESS EXT when read with Device Control register HOB bit cleared to zero. LBA (31:24) of the address of the SET MAX ADDRESS EXT when read with Device Control register HOB bit set to one. LBA Mid LBA (15:8) of the address of the SET MAX ADDRESS EXT when read with Device Control register HOB bit cleared to zero. LBA (39:32) of the address of the SET MAX ADDRESS EXT when read with Device Control register HOB bit set to one. LBA High LBA (23:16) of the address of the SET MAX ADDRESS EXT when read with Device Control register HOB bit cleared to zero. LBA (47:40) of the address of the SET MAX ADDRESS EXT when read with Device Control register HOB bit set to one. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.48.1.6 Error outputs If this command is not supported, the maximum value to be set exceeds the capacity of the device, a host protected area has been established by a SET MAX ADDRESS command, the command is not immediately Page 241 T13/1410D revision 3b preceded by a READ NATIVE MAX ADDRESS EXT command, or the device is in the Set_Max_Locked or Set_Max_Frozen state, then the device shall return command aborted. Register 7 6 5 4 3 2 1 0 Error na na na IDNF na ABRT na obs Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY na na na na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Error register ABRT shall be set to one if this command is not supported, maximum value requested exceeds the device capacity, a host protected area has been established by a SET MAX ADDRESS command, or the command is not immediately preceded by a READ NATIVE MAX ADDRESS EXT command. ABRT may be set to one if the device is not able to complete the action requested by the command. IDNF shall be set to one if the command was the second non-volatile SET MAX ADDRESS or SET MAX ADDRESS EXT command after power-on or hardware reset. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.48.1.7 Prerequisites DRDY set to one. A successful READ NATIVE MAX ADDRESS EXT command shall immediately precede a SET MAX ADDRESS EXT command. 8.48.1.8 Description After successful command completion, all read and write access attempts to addresses greater than specified by the successful SET MAX ADDRESS EXT command shall be rejected with an IDNF error. Hosts shall not issue more than one non-volatile SET MAX ADDRESS or SET MAX ADDRESS EXT command after a power-on or hardware reset. Devices shall report an IDNF error upon receiving a second non-volatile SET MAX ADDRESS EXT command after a power-on or hardware reset. The contents of IDENTIFY DEVICE words and the max address shall not be changed if a SET MAX ADDRESS EXT command fails. After a successful SET MAX ADDRESS EXT command using a new maximum LBA the content of all IDENTIFY DEVICE words shall comply with 6.2.1. Page 242 T13/1410D revision 3b 8.49 SET MULTIPLE MODE 8.49.1 Command code C6h 8.49.2 Feature set General feature set − − Mandatory for devices not implementing the PACKET Command feature set. Use prohibited for devices implementing the PACKET Command feature set. 8.49.3 Protocol Non-data (see 9.4). 8.49.4 Inputs If the content of the Sector Count register is not zero, then the Sector Count register contains the number of sectors per block for the device to be used on all following READ/WRITE MULTIPLE commands. The content of the Sector Count register shall be less than or equal to the value in bits (7:0) in word 47 in the IDENTIFY DEVICE information. The host should set the content of the Sector Count register to 1, 2, 4, 8, 16, 32, 64 or 128. If the content of the Sector Count register is zero and the SET MULTIPLE command completes without error, then the device shall respond to any subsequent READ MULTIPLE or WRITE MULTIPLE command with command aborted until a subsequent successful SET MULTIPLE command completion where the Sector Count register is not set to zero. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs na obs 4 3 na Sectors per block na na na DEV C6h 2 1 0 1 0 na ERR na Device register DEV shall specify the selected device. 8.49.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 DRQ na na na na na na obs BSY na DRDY obs DF DEV na na Page 243 T13/1410D revision 3b Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.49.6 Error outputs If a block count is not supported, the device shall return command aborted. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT DRQ na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Error register ABRT shall be set to one if the block count is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.49.7 Prerequisites DRDY set to one. 8.49.8 Description This command establishes the block count for READ MULTIPLE, READ MULTIPLE EXT, WRITE MULTIPLE, and WRITE MULTIPLE EXT commands. Devices shall support the block size specified in the IDENTIFY DEVICE parameter word 47, bits (7:0), and may also support smaller values. Upon receipt of the command, the device checks the Sector Count register. If the content of the Sector Count register is not zero, the Sector Count register contains a valid value, and the block count is supported, then the value in the Sector Count register is used for all subsequent READ MULTIPLE, READ MULTIPLE EXT, WRITE MULTIPLE, and WRITE MULTIPLE EXT commands and their execution is enabled. If the content of the Sector Count register is zero, the device may: 1) disable multiple mode and respond with command aborted to all subsequent READ MULTIPLE, READ MULTIPLE EXT, WRITE MULTIPLE, and WRITE MULTIPLE EXT commands; 2) respond with command aborted to the SET MULTIPLE MODE command; Page 244 T13/1410D revision 3b 3) retain the previous multiple mode settings. After a successful SET MULTIPLE command the device shall report the valid value set by that command in bits (7:0) in word 59 in the IDENTIFY DEVICE information. After a power-on or hardware reset, if bit 8 is set to one and bits (7:0) are cleared to zero in word 59 of the IDENTIFY DEVICE information, a SET MULTIPLE command is required before issuing a READ MULTIPLE, READ MULTIPLE EXT, WRITE MULTIPLE, or WRITE MULTIPLE EXT command. If bit 8 is set to one and bits (7:0) are not cleared to zero, a SET MULTIPLE command may be issue to change the multiple value required before issuing a READ MULTIPLE, READ MULTIPLE EXT, WRITE MULTIPLE, or WRITE MULTIPLE EXT command. 8.50 SLEEP 8.50.1 Command code E6h 8.50.2 Feature set Power Management feature set. − − − This command is mandatory for devices not implementing the PACKET Command feature set. Power Management feature set is mandatory when power management is not implemented by the PACKET command set implemented by the device. This command is mandatory when the Power Management feature set is implemented. 8.50.3 Protocol Non-data (see 9.4). 8.50.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na na obs na obs DEV na E6h Device register DEV shall specify the selected device. Page 245 T13/1410D revision 3b 8.50.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 DRQ na 1 0 na ERR na na na na na obs BSY na DRDY obs DF DEV na na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.50.6 Error outputs The device shall return command aborted if the device does not support the Power Management feature set. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na DRQ na Error register ABRT shall be set to one if the device does not support the Power Management feature set. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.50.7 Prerequisites DRDY set to one. 8.50.8 Description This command is the only way to cause the device to enter Sleep mode. Page 246 T13/1410D revision 3b This command shall cause the device to set the BSY bit to one, prepare to enter Sleep mode, clear the BSY bit to zero and assert INTRQ. The host shall read the Status register in order to clear the interrupt pending and allow the device to enter Sleep mode. In Sleep mode, the device shall only respond to the assertion of the RESET- signal and the writing of the SRST bit in the Device Control register and shall release the device driven signal lines (see Figure 8). The host shall not attempt to access the Command Block registers while the device is in Sleep mode. Because some host systems may not read the Status register and clear the interrupt pending, a device may release INTRQ and enter Sleep mode after a vendor specific time period of not less than 2 s. The only way to recover from Sleep mode is with a software reset, a hardware reset, or a DEVICE RESET command. A device shall not power-on in Sleep mode nor remain in Sleep mode following a reset sequence. 8.51 SMART Individual SMART commands are identified by the value placed in the Feature register. Table 50 shows these Feature register values. Value 00h-CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh-DFh E0h-FFh Table 50 − SMART Feature register values Command Reserved SMART READ DATA Obsolete SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE Obsolete SMART EXECUTE OFF-LINE IMMEDIATE SMART READ LOG SMART WRITE LOG Obsolete SMART ENABLE OPERATIONS SMART DISABLE OPERATIONS SMART RETURN STATUS Obsolete Reserved vendor specific 8.51.1 SMART DISABLE OPERATIONS 8.51.1.1 Command code B0h with a Feature register value of D9h. 8.51.1.2 Feature set SMART feature set. − − Mandatory when the SMART feature set is implemented. Use prohibited when the PACKET Command feature set is implemented. Page 247 T13/1410D revision 3b 8.51.1.3 Protocol Non-data (see 9.4). 8.51.1.4 Inputs The Features register shall be set to D9h. The LBA Mid register shall be set to 4Fh. The LBA High register shall be set to C2h. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na 3 2 1 0 na DRQ na na na na na ERR D9h na na 4Fh C2h obs na obs DEV B0h Device register DEV shall specify the selected device. 8.51.1.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.51.1.6 Error outputs If the device does not support this command, if SMART is not enabled, or if the values in the Features, LBA Mid, or LBA High registers are invalid, the device shall return command aborted. Page 248 T13/1410D revision 3b Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT DRQ na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Error register ABRT shall be set to one if this command is not supported, if SMART is not enabled, or if input register values are invalid. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.51.1.7 Prerequisites DRDY set to one. SMART enabled. 8.51.1.8 Description This command disables all SMART capabilities within the device including any and all timer and event count functions related exclusively to this feature. After command acceptance the device shall disable all SMART operations. SMART data shall no longer be monitored or saved by the device. The state of SMART, either enabled or disabled, shall be preserved by the device across power cycles. After receipt of this command by the device, all other SMART commands including SMART DISABLE OPERATIONS commands, with the exception of SMART ENABLE OPERATIONS, are disabled and invalid and shall be command aborted by the device. 8.51.2 SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE 8.51.2.1 Command code B0h with a Feature register value of D2h. 8.51.2.2 Feature set SMART feature set. − − Mandatory when the SMART feature set is implemented. Use prohibited when the PACKET Command feature set is implemented. 8.51.2.3 Protocol Non-data (see 9.4). Page 249 T13/1410D revision 3b 8.51.2.4 Inputs The Features register shall be set to D2h. The LBA Mid register shall be set to 4Fh. The LBA High register shall be set to C2h. The Sector Count register shall set to 00h to disable attribute autosave and a value of F1h shall be set to enable attribute autosave. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs na obs 4 3 D2h 00h or F1h na 4Fh C2h DEV na B0h 2 1 0 na na na 3 2 1 0 na DRQ na na na na na ERR Device register DEV shall specify the selected device. 8.51.2.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.51.2.6 Error outputs If the device does not support this command, if SMART is disabled, or if the values in the Features, LBA Mid, or LBA High registers are invalid, the device shall return command aborted. Register Error Sector Count LBA Low LBA Mid LBA High Device Status Page 250 7 na 6 na 5 na 4 na 3 na 2 ABRT DRQ na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na T13/1410D revision 3b Error register ABRT shall be set to one if this command is not supported, if SMART is disabled, or if the input register values are invalid. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.51.2.7 Prerequisites DRDY set to one. SMART enabled. 8.51.2.8 Description This command enables and disables the optional attribute autosave feature of the device. This command may either allow the device, after some vendor specified event, to save the device updated attribute values to nonvolatile memory; or this command may cause the autosave feature to be disabled. The state of the attribute autosave feature (either enabled or disabled) shall be preserved by the device across power cycles. A value of zero written by the host into the device’s Sector Count register before issuing this command shall cause this feature to be disabled. Disabling this feature does not preclude the device from saving SMART data to non-volatile memory during some other normal operation such as during a power-on or power-off sequence or during an error recovery sequence. A value of F1h written by the host into the device’s Sector Count register before issuing this command shall cause this feature to be enabled. Any other meaning of this value or any other non-zero value written by the host into this register before issuing this command may differ from device to device. The meaning of any nonzero value written to this register at this time shall be preserved by the device across power cycles. If this command is not supported by the device, the device shall return command aborted upon receipt from the host. During execution of the autosave routine the device shall not set BSY to one nor clear DRDY to zero. If the device receives a command from the host while executing the autosave routine the device shall begin processing the command within two seconds. 8.51.3 SMART ENABLE OPERATIONS 8.51.3.1 Command code B0h with a Feature register value of D8h. 8.51.3.2 Feature set SMART feature set. − − Mandatory when the SMART feature set is implemented. Use prohibited when the PACKET Command feature set is implemented. Page 251 T13/1410D revision 3b 8.51.3.3 Protocol Non-data (see 9.4). 8.51.3.4 Inputs The Features register shall be set to D8h. The LBA Mid register shall be set to 4Fh. The LBA High register shall be set to C2h. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 1 0 na ERR D8h na na 4Fh C2h obs na obs DEV na B0h Device register DEV shall specify the selected device. 8.51.3.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 na na na na na obs BSY na DRDY obs DF DEV na na DRQ na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.51.3.6 Error outputs If the device does not support this command or if the values in the Features, LBA Mid, or LBA High registers are invalid, the device shall return command aborted. Page 252 T13/1410D revision 3b Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT DRQ na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Error register ABRT shall be set to one if this command is not supported or if the input register values are invalid. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.51.3.7 Prerequisites DRDY set to one. 8.51.3.8 Description This command enables access to all SMART capabilities within the device. Prior to receipt of this command SMART data are neither monitored nor saved by the device. The state of SMART (either enabled or disabled) shall be preserved by the device across power cycles. Once enabled, the receipt of subsequent SMART ENABLE OPERATIONS commands shall not affect any SMART data or functions. 8.51.4 SMART EXECUTE OFF-LINE IMMEDIATE 8.51.4.1 Command code B0h with the content of the Features register equal to D4h 8.51.4.2 Feature set SMART feature set. − − Optional when the SMART feature set is implemented. Use prohibited when the PACKET Command feature set is implemented. 8.51.4.3 Protocol Non-data (see 9.4). Page 253 T13/1410D revision 3b 8.51.4.4 Inputs The Features register shall be set to D4h. The LBA Mid register shall be set to 4Fh. The LBA High register shall be set to C2h. Table 51 defines the subcommand that shall be executed based on the value in the LBA Low register. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs na obs 4 3 D4h na Subcommand specific 4Fh C2h DEV B0h 2 1 0 1 0 na ERR na Device register DEV shall specify the selected device. 8.51.4.5 Normal Outputs Register Features Sector Count LBA Low LBA Mid LBA High Device/Head Status 7 6 5 obs BSY na DRDY obs DF 4 3 na na na na or 4Fh na or C2h DEV na DRQ 2 na na LBA Mid na when the subcommand specified an off-line routine including an off-line self-test routine. 4Fh when the subcommand specified a captive self-test routine (see 8.51.4.8.2) that has executed without failure. LBA High na when the subcommand specified an off-line routine including an off-line self-test routine. C2h when the subcommand specified a captive self-test routine that has executed without failure. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one indicating that the device is capable of receiving any command. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.51.4.6 Error Outputs If the device does not support this command, if SMART is disabled, or if the values in the Features, LBA Mid, or LBA High registers are invalid, the device shall return command aborted. When a failure occurs while executing a test in captive mode, the device shall return command aborted with the LBA Mid register value of F4h and the LBA High value of 2Ch. Page 254 T13/1410D revision 3b Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na obs BSY 6 na na DRDY 5 na obs DF 4 IDNF 3 na na na na or 4Fh or F4h na or C2h or 2Ch DEV na DRQ 2 ABRT 1 na 0 obs na ERR na na Error register IDNF shall be set to one if SMART data sector’s ID field could not be found. ABRT shall be set to one if this command is not supported, if SMART is not enabled, if register values are invalid, or if a self-test fails while executing a sequence in captive mode. ABRT may be set to one if the device is not able to complete the action requested by the command. LBA Mid register – na when the subcommand specified an off-line routine (including an off-line self-test routine). 4Fh when the subcommand specified a captive self-test routine and some error other than a self-test routine failure occurred (i.e., if the sub-command is not supported or register values are invalid) F4h when the subcommand specified a captive self-test routine which has failed during execution. LBA High register – na when the subcommand specified an off-line routine (including an off-line self-test routine). 2Ch when the subcommand specified a captive self-test routine which has failed during execution. C2h when the subcommand specified a captive self-test routine and some error other than a self-test routine failure occurred (i.e., if the sub-command is not supported or register values are invalid) Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one indicating that the device is capable of receiving any command. DF (Device Fault) shall be set to one indicating that a device fault has occurred. DRQ shall be cleared to zero indicating that there is no data to be transferred. ERR shall be set to one if any Error register bit is set to one. 8.51.4.7 Prerequisites DRDY set to one. SMART enabled. 8.51.4.8 Description This command causes the device to immediately initiate the optional set of activities that collect SMART data in an off-line mode and then save this data to the device's non-volatile memory, or execute a self-diagnostic test routine in either captive or off-line mode. Page 255 T13/1410D revision 3b Table 51 − SMART EXECUTE OFF-LINE IMMEDIATE LBA Low register values Value Description of subcommand to be executed 0 Execute SMART off-line routine immediately in off-line mode 1 Execute SMART Short self-test routine immediately in off-line mode 2 Execute SMART Extended self-test routine immediately in off-line mode 3-63 Reserved 64-126 Vendor specific 127 Abort off-line mode self-test routine 128 Reserved 129 Execute SMART Short self-test routine immediately in captive mode 130 Execute SMART Extended self-test routine immediately in captive mode 131-191 Reserved 192-255 Vendor specific 8.51.4.8.1 Off-line mode The following describes the protocol for executing a SMART EXECUTE OFF-LINE IMMEDIATE subcommand routine (including a self-test routine) in the off-line mode. a) The device shall execute command completion before executing the subcommand routine. b) After clearing BSY to zero and setting DRDY to one after receiving the command, the device shall not set BSY nor clear DRDY during execution of the subcommand routine. c) If the device is in the process of performing the subcommand routine and is interrupted by any new command from the host except a SLEEP, SMART DISABLE OPERATIONS, SMART EXECUTE OFF-LINE IMMEDIATE, or STANDBY IMMEDIATE command, the device shall suspend or abort the subcommand routine and service the host within two seconds after receipt of the new command. After servicing the interrupting command from the host the device may immediately re-initiate or resume the subcommand routine without any additional commands from the host (see 8.51.5.8.4). d) If the device is in the process of performing a subcommand routine and is interrupted by a SLEEP command from the host, the device may abort the subcommand routine and execute the SLEEP command. If the device is in the process of performing any self-test routine and is interrupted by a SLEEP command from the host, the device shall abort the subcommand routine and execute the SLEEP command. e) If the device is in the process of performing the subcommand routine and is interrupted by a SMART DISABLE OPERATIONS command from the host, the device shall suspend or abort the subcommand routine and service the host within two seconds after receipt of the command. Upon receipt of the next SMART ENABLE OPERATIONS command the device may, either re-initiate the subcommand routine or resume the subcommand routine from where it had been previously suspended. f) If the device is in the process of performing the subcommand routine and is interrupted by a SMART EXECUTE OFF-LINE IMMEDIATE command from the host, the device shall abort the subcommand routine and service the host within two seconds after receipt of the command. The device shall then service the new SMART EXECUTE OFF-LINE IMMEDIATE subcommand. g) If the device is in the process of performing the subcommand routine and is interrupted by a STANDBY IMMEDIATE or IDLE IMMEDIATE command from the host, the device shall suspend or abort the subcommand routine, and service the host within two seconds after receipt of the command. After receiving a new command that causes the device to exit a power saving mode, the device shall initiate or resume the subcommand routine without any additional commands from the host unless these activities were aborted by the host (see 8.51.5.8). h) While the device is performing the subcommand routine it shall not automatically change power states (e.g., as a result of its Standby timer expiring). i) If a test failure occurs while a device is performing a self-test routine the device may discontinue the testing and place the test results in the Self-test execution status byte (see Table 52). Page 256 T13/1410D revision 3b 8.51.4.8.2 Captive mode When executing a self-test in captive mode, the device sets BSY to one and executes the self-test routine after receipt of the command. At the end of the routine the device places the results of this routine in the Self-test execution status byte (see Table 52) and executes command completion. If an error occurs while a device is performing the routine the device may discontinue its testing, place the results of this routine in the Self-test execution status byte, and complete the command. 8.51.4.8.3 SMART off-line routine This routine shall only be performed in the off-line mode. The results of this routine are placed in the Off-line data collection status byte (see Table 53). 8.51.4.8.4 SMART Short self-test routine Depending on the value in the LBA Low register, this self-test routine may be performed in either the captive or the off-line mode. This self-test routine should take on the order of ones of minutes to complete (see 8.51.5.8). 8.51.4.8.5 SMART Extended self-test routine Depending on the value in the LBA Low register, this self-test routine may be performed in either the captive or the off-line mode. This self-test routine should take on the order of tens of minutes to complete (see 8.51.5.8). 8.51.5 SMART READ DATA 8.51.5.1 Command code B0h with the content of the Features register equal to D0h. 8.51.5.2 Feature set SMART feature set. − Optional when the SMART feature set is implemented. − Use prohibited when the PACKET Command feature set is implemented. 8.51.5.3 Protocol PIO data-in (see 9.5). 8.51.5.4 Inputs The Features register shall be set to D0h. The LBA Mid register shall be set to 4Fh. The LBA High register shall be set to C2h. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 D0h na na 4Fh C2h obs na obs DEV na B0h Device register DEV shall specify the selected device. Page 257 T13/1410D revision 3b 8.51.5.5 Normal outputs Register Features Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 DRQ na 1 0 na ERR na na na na na obs BSY na DRDY obs DF DEV na na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one indicating that the device is capable of receiving any command. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.51.5.6 Error outputs If the device does not support this command, if SMART is disabled, or if the values in the Features, LBA Mid, or LBA High registers are invalid, the device shall return command aborted. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 UNC 5 na 4 IDNF 3 na 2 ABRT 1 na 0 obs na ERR na na na na obs BSY na DRDY obs DF DEV na na DRQ na Error register UNC shall be set to one if SMART data is uncorrectable. IDNF shall be set to one if SMART data sector’s ID field could not be found or data structure checksum occurred. ABRT shall be set to one if this command is not supported, if SMART is not enabled, or if register values are invalid. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one indicating that the device is capable of receiving any command. DF (Device Fault) shall be set to one indicating that a device fault has occurred. DRQ shall be cleared to zero indicating that there is no data to be transferred. ERR shall be set to one if any Error register bit is set to one. Page 258 T13/1410D revision 3b 8.51.5.7 Prerequisites DRDY set to one. SMART enabled. 8.51.5.8 Description This command returns the Device SMART data structure to the host. Table 52 defines the 512 bytes that make up the Device SMART data structure. All multi-byte fields shown in this structure follow the byte ordering described in 3.2.9. Byte 0-361 362 363 364-365 366 367 368-369 370 F/V X V X V X F F F Table 52 − Device SMART data structure Descriptions Vendor specific Off-line data collection status Self-test execution status byte Total time in seconds to complete off-line data collection activity Vendor specific Off-line data collection capability SMART capability Error logging capability 7-1 Reserved 0 1=Device error logging supported Vendor specific Short self-test routine recommended polling time (in minutes) Extended self-test routine recommended polling time (in minutes) Reserved Vendor specific Data structure checksum 371 X 372 F 373 F 374-385 R 386-510 X 511 V Key: F=the content of the byte is fixed and does not change. V=the content of the byte is variable and may change depending on the state of the device or the commands executed by the device. X=the content of the byte is vendor specific and may be fixed or variable. R=the content of the byte is reserved and shall be zero. 8.51.5.8.1 Off-line collection status byte The value of the off-line data collection status byte defines the current status of the off-line activities of the device. Table 53 lists the values and their respective definitions. Page 259 T13/1410D revision 3b Value 00h or 80h 01h 02h or 82h 03h 04h or 84h 05h or 85h 06h or 86h 07h-3Fh 40h-7Fh 81h 83h 87h-BFh C0h-FFh Table 53 − Off-line data collection status byte values Definition Off-line data collection activity was never started. Reserved Off-line data collection activity was completed without error. Reserved Off-line data collection activity was suspended by an interrupting command from host. Off-line data collection activity was aborted by an interrupting command from host. Off-line data collection activity was aborted by the device with a fatal error. Reserved Vendor specific Reserved Reserved Reserved Vendor specific 8.51.5.8.2 Self-test execution status byte The self-test execution status byte reports the execution status of the self-test routine. − − Value 0 1 Bits (3:0) (Percent Self-Test Remaining) The value in these bits indicates an approximation of the percent of the self-test routine remaining until completion in ten percent increments. Valid values are 9 through 0. A value of 0 indicates the self-test routine is complete. A value of 9 indicates 90% of total test time remaining. Bits (7:4) (Self-test Execution Status) The value in these bits indicates the current Self-test Execution Status (see Table 54). Table 54 − Self-test execution status values Description The previous self-test routine completed without error or no self-test has ever been run The self-test routine was aborted by the host 2 The self-test routine was interrupted by the host with a hardware or software reset 3 A fatal error or unknown test error occurred while the device was executing its self-test routineand the device was unable to complete the self-test routine. The previous self-test completed having a test element that failed and the test element that failed is not known. The previous self-test completed having the electrical element of the test failed. The previous self-test completed having the servo (and/or seek) test element of the test failed. The previous self-test completed having the read element of the test failed. Reserved. 4 5 6 7 8-14 15 Self-test routine in progress. 8.51.5.8.3 Total time to complete off-line data collection The total time in seconds to complete off-line data collection activity word specifies how many seconds the device requires to complete the sequence of off-line data collection activity. Valid values for this word are from 0001h to FFFFh. Page 260 T13/1410D revision 3b 8.51.5.8.4 Off-line data collection capabilities The following describes the definition for the off-line data collection capability bits. If the value of all of these bits is cleared to zero, then no off-line data collection is implemented by this device. − Bit 0 (EXECUTE OFF-LINE IMMEDIATE implemented bit) - If this bit is set to one, then the SMART EXECUTE OFF-LINE IMMEDIATE command is implemented by this device. If this bit is cleared to zero, then the SMART EXECUTE OFF-LINE IMMEDIATE command is not implemented by this device. − Bit 1 (vendor specific). − Bit 2 (abort/restart off-line by host bit) - If this bit is set to one, then the device shall abort all off-line data collection activity initiated by an SMART EXECUTE OFF-LINE IMMEDIATE command upon receipt of a new command within 2 seconds of receiving the new command. If this bit is cleared to zero, the device shall suspend off-line data collection activity after an interrupting command and resume off-line data collection activity after some vendor-specified event. − Bit 3 (off-line read scanning implemented bit) - If this bit is cleared to zero, the device does not support offline read scanning. If this bit is set to one, the device supports off-line read scanning. − Bit 4 (self-test implemented bit) – If this bit is cleared to zero, the device does not implement the Short and Extended self-test routines. If this bit is set to one, the device implements the Short and Extended selftest routines. − Bits (7:5) (Reserved). 8.51.5.8.5 SMART capablilities The following describes the definition for the SMART capabilities bits. − Bit 0 - If this bit is set to one, the device saves SMART data prior to going into a power saving mode (Idle, Standby, or Sleep) or immediately upon return to Active or Idle mode from a Standby mode. If this bit is cleared to zero, the device does not save SMART data prior to going into a power saving mode (Idle, Standby, or Sleep) or immediately upon return to Active or Idle mode from a Standby mode. − Bit 1 - This bit shall be set to one to indicate that the device supports the SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE command. − Bits (15:2) (Reserved). 8.51.5.8.6 Self-test routine recommended polling time The self-test routine recommended polling time shall be equal to the number of minutes that is the minimum recommended time before which the host should first poll for test completion status. Actual test time could be several times this value. Polling before this time could extend the self-test execution time or abort the test depending on the state of bit 2 of the off-line data capability bits. 8.51.5.8.7 Data structure checksum The data structure checksum is the two's complement of the sum of the first 511 bytes in the data structure. Each byte shall be added with unsigned arithmetic, and overflow shall be ignored. The sum of all 512 bytes will be zero when the checksum is correct. The checksum is placed in byte 511. Page 261 T13/1410D revision 3b 8.51.6 SMART READ LOG 8.51.6.1 Command code B0h with the content of the Features register equal to D5h. 8.51.6.2 Feature set SMART feature set. − − Optional when the SMART feature set is implemented. Use prohibited when the PACKET Command feature set is implemented. 8.51.6.3 Protocol PIO data-in (see 9.5). 8.51.6.4 Inputs The Features register shall be set to D5h. The Sector Count register shall specify the number of sectors to be read from the log number specified by the LBA Low register. The LBA Mid register shall be set to 4Fh. The LBA High register shall be set to C2h. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 obs na 5 4 3 2 D5h Number of sectors to be read Log address 4Fh C2h obs DEV B0h 1 0 na Sector count –specifies the number of sectors to be read from the specified log. The log transferred by the drive shall start at the first sector in the specified log, regardless of the sector count requested. LBA Low - specifies the log to be returned as described in Table 55. If this command is implemented, all address values for which the contents are defined shall be implemented and all address values defined as host vendor specific shall be implemented. The host vendor specific logs may be used by the host to store any data desired. If a host vendor specific log has never been written by the host, when read the content of the log shall be zeros. Device vendor specific logs may be used by the device vendor to store any data and need only be implemented if used. Page 262 T13/1410D revision 3b Table 55 − Log address definition Content Log directory Summary SMART error log Comprehensive SMART error log Extended Comprehensive SMART error log Reserved SMART self-test log Extended self-test log Reserved Host vendor specific Device vendor specific Reserved Log address 00h 01h 02h 03h 04h-05h 06h 07h 08h-7Fh 80h-9Fh A0h-BFh C0h-FFh R/W RO RO RO See note Reserved RO See note Reserved R/W VS Reserved Key − RO - Log is read only by the host. R/W - Log is read or written by the host. VS - Log is vendor specific thus read/write abiltiy is vendor specific. NOTE – Log addresses 03h, 07h, 20h, 21h , 22h, and 23h are used by the READ LOG EXT and WRITE LOG EXT commands. If these log addresses are used with the SMART READ LOG command, the device shall return command aborted. Device register DEV shall specify the selected device. 8.51.6.5 Normal outputs Register Features Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na ERR na na na na na obs BSY na DRDY obs DF DEV na na DRQ na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one indicating that the device is capable of receiving any command. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.51.6.6 Error outputs If the device does not support this command, if SMART is disabled, or if the values in the Features, LBA Low, Sector Count, LBA Mid, or LBA High registers are invalid, the device shall return command aborted. If the host issues a SMART READ LOG or SMART WRITE LOG command with a Sector Count value of zero, the device shall return command aborted. Page 263 T13/1410D revision 3b Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 UNC 5 na 4 IDNF 3 na 2 ABRT DRQ na 1 na 0 obs na ERR na na na na obs BSY na DRDY obs DF DEV na Na Error register UNC shall be set to one if SMART log sector is uncorrectable. IDNF shall be set to one if SMART log sector’s ID field was not found or data structure checksum error occurred. ABRT shall be set to one if this command is not supported, if SMART is not enabled, if the log sector address is not implemented, if the Sector Count value is zero, or if other register values are invalid. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one indicating that the device is capable of receiving any command. DF (Device Fault) shall be set to one indicating that a device fault has occurred. DRQ shall be cleared to zero indicating that there is no data to be transferred. ERR shall be set to one if any Error register bit is set to one. 8.51.6.7 Prerequisites DRDY set to one. SMART enabled. 8.51.6.8 Description This command returns the specified log to the host. 8.51.6.8.1 SMART Log Directory Table 56 defines the 512 bytes that make up the SMART Log Directory, which is optional. If implemented, the SMART Log Directory is SMART Log address zero, and is defined as one sector long. Byte 0-1 2 3 4 5 … 510 511 Table 56 − SMART Log Directory Descriptions SMART Logging Version Number of sectors in the log at log address 1 Reserved Number of sectors in the log at log address 2 Reserved … Number of sectors in the log at log address 255 Reserved The value of the SMART Logging Version word shall be 01h if the drive supports multi-sector SMART logs. In addition, if the drive supports multi-sector logs, then the logs at log addresses 80-9Fh shall each be defined as 16 sectors long. Page 264 T13/1410D revision 3b If the drive does not support multi-sector SMART logs, then log number zero is defined as reserved, and the drive shall return a command aborted response to the host’s request to read log number zero. 8.51.6.8.2 Summary error log sector Table 57 defines the 512 bytes that make up the SMART summary error log sector. All multi-byte fields shown in this structure follow the byte ordering described in 3.2.9. Summary error log data structures shall include UNC errors, IDNF errors for which the address requested was valid, servo errors, write fault errors, etc. Summary error log data structures shall not include errors attributed to the receipt of faulty commands such as command codes not implemented by the device or requests with invalid parameters or invalid addresses. If the device supports comprehensive error log (address 02h), then the summary error log sector duplicates the last five error entries in the comprehensive error log. The summary error log supports 28-bit addressing only. Byte 0 1 2-91 92-181 182-271 272-361 362-451 452-453 454-510 511 Table 57 − SMART summary error log sector Descriptions SMART error log version Error log index First error log data structure Second error log data structure Third error log data structure Fourth error log data structure Fifth error log data structure Device error count Reserved Data structure checksum 8.51.6.8.2.1 Error log version The value of the SMART summary error log version byte shall be 01h. 8.51.6.8.2.2 Error log index The error log index indicates the error log data structure representing the most recent error. Only values 5 through 0 are valid. If there are no error log entries, the value of the error log index shall be zero. 8.51.6.8.2.3 Error log data structure An error log data structure shall be presented for each of the last five errors reported by the device. These error log data structure entries are viewed as a circular buffer. That is, the first error shall create the first error log data structure; the second error, the second error log structure; etc. The sixth error shall create an error log data structure that replaces the first error log data structure; the seventh error replaces the second error log structure, etc. The error log pointer indicates the most recent error log structure. If fewer than five errors have occurred, the unused error log structure entries shall be zero filled. Table 58 describes the content of a valid error log data structure. Byte n thru n+11 n+12 thru n+23 n+24 thru n+35 n+36 thru n+47 n+48 thru n+59 n+60 thru n+89 Table 58 − Error log data structure Descriptions First command data structure Second command data structure Third command data structure Fourth command data structure Fifth command data structure Error data structure Page 265 T13/1410D revision 3b 8.51.6.8.2.3.1 Command data structure The fifth command data structure shall contain the command or reset for which the error is being reported. The fourth command data structure should contain the command or reset that preceded the command or reset for which the error is being reported, the third command data structure should contain the command or reset preceding the one in the fourth command data structure, etc. If fewer than four commands and resets preceded the command or reset for which the error is being reported, the unused command data structures shall be zero filled, for example, if only three commands and resets preceded the command or reset for which the error is being reported, the first command data structure shall be zero filled. In some devices, the hardware implementation may preclude the device from reporting the commands that preceded the command for which the error is being reported or that preceded a reset. In this case, the command data structures are zero filled. If the command data structure represents a command or software reset, the content of the command data structure shall be as shown in Table 59. If the command data structure represents a hardware reset, the content of byte n shall be FFh, the content of bytes n+1 through n+7 are vendor specific, and the content of bytes n+8 through n+11 shall contain the timestamp. Table 59 − Command data structure Byte n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 Descriptions Content of the Device Control register when the Command register was written. Content of the Features register when the Command register was written. Content of the Sector Count register when the Command register was written. Content of the LBA Low register when the Command register was written. Content of the LBA Mid register when the Command register was written. Content of the LBA High register when the Command register was written. Content of the Device register when the Command register was written. Content written to the Command register. Timestamp (least significant byte) Timestamp (next least significant byte) Timestamp (next most significant byte) Timestamp (most significant byte) Timestamp shall be the time since power-on in milliseconds when command acceptance occurred. This timestamp may wrap around. 8.51.6.8.2.3.2 Error data structure The error data structure shall contain the error description of the command for which an error was reported as described in Table 60. If the error was logged for a hardware reset, the content of bytes n+1 through n+7 shall be vendor specific and the remaining bytes shall be as defined in Table 60. Page 266 T13/1410D revision 3b Table 60 − Error data structure Byte n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 thru n+26 n+27 n+28 n+29 Descriptions Reserved Content of the Error register after command completion occurred. Content of the Sector Count register after command completion occurred. Content of the LBA Low register after command completion occurred. Content of the LBA Mid register after command completion occurred. Content of the LBA High register after command completion occurred. Content of the Device register after command completion occurred. Content written to the Status register after command completion occurred. Extended error information State Life timestamp (least significant byte) Life timestamp (most significant byte) Extended error information shall be vendor specific. State shall contain a value indicating the state of the device when command was written to the Command register or the reset occurred as described in Table 61. Table 61 − State field values Value State x0h Unknown x1h Sleep x2h Standby x3h Active/Idle with BSY cleared to zero x4h Executing SMART off-line or self-test x5h-xAh Reserved xBh-xFh Vendor unique The value of x is vendor specific and may be different for each state. Sleep indicates the reset for which the error is being reported was received when the device was in the Sleep mode. Standby indicates the command or reset for which the error is being reported was received when the device was in the Standby mode. Active/Idle with BSY cleared to zero indicates the command or reset for which the error is being reported was received when the device was in the Active or Idle mode and BSY was cleared to zero. Executing SMART off-line or self-test indicates the command or reset for which the error is being reported was received when the device was in the process of executing a SMART off-line or self-test. Life timestamp shall contain the power-on lifetime of the device in hours when command completion occurred. 8.51.6.8.2.4 Device error count The device error count field shall contain the total number of errors attributable to the device that have been reported by the device during the life of the device. These errors shall include UNC errors, IDNF errors for which the address requested was valid, servo errors, write fault errors, etc. This count shall not include errors attributed to the receipt of faulty commands such as commands codes not implemented by the device or requests with invalid parameters or invalid addresses. If the maximum value for this field is reached, the count shall remain at the maximum value when additional errors are encountered and logged. Page 267 T13/1410D revision 3b 8.51.6.8.2.5 Data structure checksum The data structure checksum is the two's complement of the sum of the first 511 bytes in the data structure. Each byte shall be added with unsigned arithmetic, and overflow shall be ignored. The sum of all 512 bytes will be zero when the checksum is correct. The checksum is placed in byte 511. 8.51.6.8.3 Comprehensive error log Table 62 defines the format of each of the sectors that comprise the SMART comprehensive error log. The SMART Comprehensive error log provides logging for 28-bit addressing only. For 48-bit addressing see 8.29.8.2. The maximum size of the SMART comprehensive error log shall be 51 sectors. Devices may support fewer than 51 sectors. All multi-byte fields shown in this structure follow the byte ordering described in 3.2.9. The comprehensive error log data structures shall include UNC errors, IDNF errors for which the address requested was valid, servo errors, write fault errors, etc. Comprehensive error log data structures shall not include errors attributed to the receipt of faulty commands such as command codes not supported by the device or requests with invalid parameters or invalid addresses. Table 62 − Comprehensive error log Byte First sector Subsequent sectors 0 SMART error log version Reserved 1 Error log index Reserved 2-91 First error log data structure Data structure 5n+1 92-181 Second error log data structure Data structure 5n+2 182-271 Third error log data structure Data structure 5n+3 272-361 Fourth error log data structure Data structure 5n+4 362-451 Fifth error log data structure Data structure 5n+5 452-453 Device error count Reserved 454-510 Reserved Reserved 511 Data structure checksum Data structure checksum n is the sector number within the log. The first sector is sector zero 8.51.6.8.3.1 Error log version The value of the error log version byte shall be set to 01h. 8.51.6.8.3.2 Error log index The error log index indicates the error log data structure representing the most recent error. If there have been no error log entries, the error log index is set to zero. Valid values for the error log index are zero to 255. 8.51.6.8.3.3 Error log data structure The error log is viewed as a circular buffer. The device may support from two to 51 error log sectors. When the last supported error log sector has been filled, the next error shall create an error log data structure that replaces the first error log data structure in sector zero. The next error after that shall create an error log data structure that replaces the second error log data structure in sector zero. The sixth error after the log has filled shall replace the first error log data structure in sector one, and so on. The error log index indicates the most recent error log data structure. Unused error log data structures shall be filled with zeros. The content of the error log data structure entries is defined in 8.51.6.8.2.3. Page 268 T13/1410D revision 3b 8.51.6.8.3.4 Device error count The device error count field is defined in 8.51.6.8.2.4. 8.51.6.8.3.5 Data structure checksum The data structure checksum is defined in 8.51.6.8.2.5. 8.51.6.8.4 Self-test log sector Table 63 defines the 512 bytes that make up the SMART self-test log sector. All multi-byte fields shown in this structure follow the byte ordering described in 3.2.9. The self-test log sector supports 28-bit addressing only. Byte 0-1 2-25 26-49 ..... 482-505 506-507 508 509-510 511 Table 63 − Self-test log data structure Descriptions Self-test log data structure revision number First descriptor entry Second descriptor entry ............ Twenty-first descriptor entry Vendor specific Self-test index Reserved Data structure checksum This log is viewed as a circular buffer. The first entry shall begin at byte 2, the second entry shall begin at byte 26, and so on until the twenty-second entry, that shall replace the first entry. Then, the twenty-third entry shall replace the second entry, and so on. If fewer than 21 self-tests have been performed by the device, the unused descriptor entries shall be filled with zeroes. 8.51.6.8.4.1 Self-test log data structure revision number The value of the self-test log data structure revision number shall be 0001h. 8.51.6.8.4.2 Self-test log descriptor entry The content of the self-test descriptor entry is shown in Table 64. Byte n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 - n+23 Table 64 − Self-test log descriptor entry Descriptions Content of the LBA Low register. Content of the self-test execution status byte. Life timestamp (least significant byte). Life timestamp (most significant byte). Content of the self-test failure checkpoint byte. Failing LBA (least significant byte). Failing LBA (next least significant byte). Failing LBA (next most significant byte). Failing LBA (most significant byte). Vendor specific. Content of the LBA Low register shall be the content of the LBA Low register when the nth self-test subcommand was issued (see 8.51.4.8). Page 269 T13/1410D revision 3b Content of the self-test execution status byte shall be the content of the self-test execution status byte when the nth self-test was completed (see 8.51.5.8.2). Life timestamp shall contain the power-on lifetime of the device in hours when the nth self-test subcommand was completed. Content of the self-test failure checkpoint byte may contain additional information about the self-test that failed. The failing LBA shall be the LBA of the uncorrectable sector that caused the test to fail. If the device encountered more than one uncorrectable sector during the test, this field shall indicate the LBA of the first uncorrectable sector encountered. If the test passed or the test failed for some reason other than an uncorrectable sector, the value of this field is undefined. 8.51.6.8.4.3 Self-test index The self-test index shall point to the most recent entry. Initially, when the log is empty, the index shall be set to zero. It shall be set to one when the first entry is made, two for the second entry, etc., until the 22nd entry, when the index shall be reset to one. 8.51.6.8.4.4 Data structure checksum The data structure checksum is the two's complement of the sum of the first 511 bytes in the data structure. Each byte shall be added with unsigned arithmetic, and overflow shall be ignored. The sum of all 512 bytes is zero when the checksum is correct. The checksum is placed in byte 511. 8.51.7 SMART RETURN STATUS 8.51.7.1 Command code B0h with a Feature register value of DAh. 8.51.7.2 Feature set SMART feature set. − − Mandatory when the SMART feature set is implemented. Use prohibited when the PACKET Command feature set is implemented. 8.51.7.3 Protocol Non-data (see 9.4). 8.51.7.4 Inputs The Features register shall be set to DAh. The LBA Mid register shall be set to 4Fh. The LBA High register shall be set to C2h. Page 270 T13/1410D revision 3b Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na DAh na na 4Fh C2h obs na obs DEV B0h Device register DEV shall specify the selected device. 8.51.7.5 Normal outputs If the device has not detected a threshold exceeded condition, the device sets the LBA Mid register to 4Fh and the LBA High register to C2h. If the device has detected a threshold exceeded condition, the device sets the LBA Mid register to F4h and the LBA High register to 2Ch. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 obs BSY na DRDY obs DF 4 3 na na na 4Fh or F4h C2h or 2Ch DEV na na DRQ 2 1 0 na na na na na ERR LBA Mid 4Fh if threshold not exceeded, F4h if threshold exceeded. LBA High C2h if threshold not exceeded, 2Ch if threshold exceeded. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.51.7.6 Error outputs If the device does not support this command, if SMART is disabled, or if the values in the Features, LBA Mid, or LBA High registers are invalid, the device shall return command aborted. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT DRQ na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Page 271 T13/1410D revision 3b Error register ABRT shall be set to one if this command is not supported, if SMART is disabled, or if the input register values are invalid. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.51.7.7 Prerequisites DRDY set to one. SMART enabled. 8.51.7.8 Description This command causes the device to communicate the reliability status of the device to the host. If a threshold exceeded condition is not detected by the device, the device shall set the LBA Mid register to 4Fh and the LBA High register to C2h. If a threshold exceeded condition is detected by the device, the device shall set the LBA Mid register to F4h and the LBA High register to 2Ch. 8.51.8 SMART WRITE LOG 8.51.8.1 Command code B0h with the content of the Features register equal to D6h. 8.51.8.2 Feature set SMART feature set. − − Optional when the SMART feature set is implemented. Use prohibited when the PACKET Command feature set is implemented. 8.51.8.3 Protocol PIO data-out (see 9.6). 8.51.8.4 Inputs The Features register shall be set to D6h. The Sector Count register shall specify the number of sectors that shall be written to the log number specified by the LBA Low register. The LBA Mid register shall be set to 4Fh. The LBA High register shall be set to C2h. Page 272 T13/1410D revision 3b Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 obs na 5 4 3 2 D6h Number of sectors to be written Log sector address 4Fh C2h obs DEV B0h 1 0 na Sector count –specifies the number of sectors that shall be written to the specified log. The log transferred to the drive shall be stored by the drive starting at the first sector in the specified log. LBA Low - specifies the log to be written as described in Table 55. If this command is implemented, all address values defined as host vendor specific shall be implemented. Device register DEV shall specify the selected device. 8.51.8.5 Normal outputs Register Features Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na ERR na na na na na obs BSY na DRDY obs DF DEV na na DRQ na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one indicating that the device is capable of receiving any command. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.51.8.6 Error outputs If the device does not support this command, if SMART is disabled, or if the values in the Features, LBA Low, Sector Count, LBA Mid, or LBA High registers are invalid, the device shall return command aborted. If the host attempts to write to a read only (RO) log address, the device shall return command aborted. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 IDNF 3 na 2 ABRT DRQ na 1 na 0 obs na ERR na na na na obs BSY na DRDY obs DF DEV na na Error register Page 273 T13/1410D revision 3b IDNF shall be set to one if SMART log sector’s ID field could not be found. ABRT shall be set to one if this command is not supported, if SMART is not enabled, if the log sector address is not implemented, or if other register values are invalid. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one indicating that the device is capable of receiving any command. DF (Device Fault) shall be set to one indicating that a device fault has occurred. DRQ shall be cleared to zero indicating that there is no data to be transferred. ERR shall be set to one if any Error register bit is set to one. 8.51.8.7 Prerequisites DRDY set to one. SMART enabled. 8.51.8.8 Description This command writes an specified number of 512 byte data sectors to the specified log. 8.52 STANDBY 8.52.1 Command code E2h 8.52.2 Feature set Power Management feature set. − − − This command is mandatory for devices not implementing the PACKET Command feature set. Power Management feature set is mandatory when power management is not implemented by the PACKET command set implemented by the device. This command is mandatory when the Power Management feature set is implemented. 8.52.3 Protocol Non-data (see 9.4). 8.52.4 Inputs The value in the Sector Count register when the STANDBY command is issued shall determine the time period programmed into the Standby timer. Table 30 defines these values. Register Features Sector Count LBA Low LBA Mid LBA High Device Command Device register Page 274 7 6 5 obs na obs 4 3 na Time period value na na na DEV na E2h 2 1 0 na na na T13/1410D revision 3b DEV shall specify the selected device. 8.52.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na DRQ na na na na na ERR na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.52.6 Error outputs The device shall return command aborted if the device does not support the Power Management feature set. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na DRQ na Error register ABRT shall be set to one if the Power Management feature set is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.52.7 Prerequisites DRDY set to one. Page 275 T13/1410D revision 3b 8.52.8 Description This command causes the device to enter the Standby mode. If the Sector Count register is non-zero then the Standby timer shall be enabled. The value in the Sector Count register shall be used to determine the time programmed into the Standby timer (see Table 30). If the Sector Count register is zero then the Standby timer is disabled. 8.53 STANDBY IMMEDIATE 8.53.1 Command code E0h 8.53.2 Feature set Power Management feature set. − − − This command is mandatory for devices not implementing the PACKET Command feature set. Power Management feature set is mandatory when power management is not implemented by the PACKET command set implemented by the device. This command is mandatory when the Power Management feature set is implemented. 8.53.3 Protocol Non-data (see 9.4). 8.53.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na 3 2 1 0 na DRQ na na na na na ERR na na na na na obs na obs DEV E0h Device register DEV shall specify the selected device. 8.53.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status Page 276 7 6 5 4 na na na na na obs BSY na DRDY obs DF DEV na T13/1410D revision 3b Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.53.6 Error outputs The device shall return command aborted if the device does not support the Power Management feature set. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na 6 na 5 na 4 na 3 na 2 ABRT DRQ na 1 na 0 na na ERR na na na na obs BSY na DRDY obs DF DEV na na Error register ABRT shall be set to one if the Power Management feature set is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.53.7 Prerequisites DRDY set to one. 8.53.8 Description This command causes the device to immediately enter the Standby mode. 8.54 WRITE BUFFER 8.54.1 Command code E8h 8.54.2 Feature set General feature set − − Optional for devices not implementing the PACKET Command feature set. Use prohibited for devices implementing the PACKET Command feature set. Page 277 T13/1410D revision 3b 8.54.3 Protocol PIO data-out (see 9.6). 8.54.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 na na na na 3 2 1 0 na DRQ na na na na na ERR 3 na 2 ABRT 1 na 0 na DRQ na na ERR na na na na na obs na obs DEV E8h Device register DEV shall specify the selected device. 8.54.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.54.6 Error outputs The device shall return command aborted if the command is not supported. Register Error Sector Count LBA Low LBA Mid LBA High Device Status Page 278 7 na 6 na 5 na 4 na na na na na obs BSY na DRDY obs DF DEV na na T13/1410D revision 3b Error register ABRT shall be set to one if this command is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.54.7 Prerequisites DRDY set to one. 8.54.8 Description This command enables the host to write the contents of one sector in the device’s buffer. The READ BUFFER and WRITE BUFFER commands shall be synchronized within the device such that sequential WRITE BUFFER and READ BUFFER commands access the same 512 bytes within the buffer. 8.55 WRITE DMA 8.55.1 Command code CAh 8.55.2 Feature set General feature set − − Mandatory for devices not implementing the PACKET Command feature set. Use prohibited for devices implementing the PACKET Command feature set. 8.55.3 Protocol DMA (see 9.7). 8.55.4 Inputs The LBA Mid, LBA High, Device, and LBA Low specify the starting sector address to be written. The Sector Count register specifies the number of sectors to be transferred. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs LBA obs 4 3 na Sector count LBA (7:0) LBA (15:8) LBA (23:16) DEV CAh 2 1 0 LBA (27:24) Page 279 T13/1410D revision 3b Sector Count number of sectors to be transferred. A value of 00h specifies that 256 sectors are to be transferred. LBA Low starting LBA bits (7:0). LBA Mid starting LBA bits (15:8). LBA High starting LBA bits (23:16). Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. bits (3:0) starting LBA bits (27:24). 8.55.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na DRQ na na na na na ERR na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.55.6 Error outputs An unrecoverable error encountered during the execution of this command results in the termination of the command. The Command Block registers contain the address of the sector where the first unrecoverable error occurred. The amount of data transferred is indeterminate. Register Error Sector Count LBA Low LBA Mid LBA High Device Status Page 280 7 ICRC obs BSY 6 WP na DRDY 5 MC 4 IDNF 3 MCR obs DF na LBA (7:0) LBA (15:8) LBA (23:16) DEV na DRQ 2 ABRT 1 NM 0 obs LBA (27:24) na na ERR T13/1410D revision 3b Error register ICRC shall be set to one if an interface CRC error has occurred during an Ultra DMA data transfer. The content of this bit is not applicable for Multiword DMA transfers. WP shall be set to one if the media in a removable media device is write protected. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported or if an error, including an ICRC error, has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. LBA Low, LBA Mid, LBA High, Device shall be written with address of first unrecoverable error. DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.55.7 Prerequisites DRDY set to one. The host shall initialize the DMA channel. 8.55.8 Description The WRITE DMA command allows the host to write data using the DMA data transfer protocol. 8.56 WRITE DMA EXT 8.56.1 Command code 35h 8.56.2 Feature set 48-bit Address feature set − − Mandatory for devices implementing the 48-bit Address feature set. Use prohibited for devices implementing the PACKET Command feature set. 8.56.3 Protocol DMA (see 9.7). Page 281 T13/1410D revision 3b 8.56.4 Inputs Register 7 6 5 4 3 2 1 0 Features Current Reserved Previous Reserved Sector Count Current Sector count (7:0) Previous Sector count (15:8) LBA Low Current LBA (7:0) Previous LBA (31:24) LBA Mid Current LBA (15:8) Previous LBA (39:32) LBA High Current LBA (23:16) Previous LBA (47:40) Device obs LBA obs DEV Reserved Command 35h NOTE − The value indicated as Current is the value most recently written to the register. The value indicated as Previous is the value that was in the register before the most recent write to the register. Sector Count Current number of sectors to be transferred low order, bits (7:0). Sector Count Previous number of sectors to be transferred high order, bits (15:8). 0000h in the Sector Count register specifies that 65,536 sectors are to be transferred. LBA Low Current LBA (7:0). LBA Low Previous LBA (31:24). LBA Mid Current LBA (15:8). LBA Mid Previous LBA (39:32). LBA High Current LBA (23:16). LBA High Previous LBA (47:40). Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. Page 282 T13/1410D revision 3b 8.56.5 Normal outputs Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.56.6 Error outputs An unrecoverable error encountered during the execution of this command results in the termination of the command. The Command Block registers contain the address of the sector where the first unrecoverable error occurred. The amount of data transferred is indeterminate. Register 7 6 5 4 3 2 1 0 Error ICRC WP MC IDNF MCR ABRT NM obs Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 LBA (7:0) HOB = 1 LBA (31:24) LBA Mid HOB = 0 LBA (15:8) HOB = 1 LBA (39:32) LBA High HOB = 0 LBA (23:16) HOB = 1 LBA (47:40) Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Page 283 T13/1410D revision 3b Error register ICRC shall be set to one if an interface CRC error has occurred during an Ultra DMA data transfer. The content of this bit is not applicable for Multiword DMA transfers. WP shall be set to one if the media in a removable media device is write protected. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported or if an error, including an ICRC error, has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. LBA Low LBA (7:0) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (31:24) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA Mid LBA (15:8) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (39:32) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA High LBA (23:16) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (47:40) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.56.7 Prerequisites DRDY set to one. The host shall initialize the DMA channel. 8.56.8 Description The WRITE DMA EXT command allows the host to write data using the DMA data transfer protocol. 8.57 WRITE DMA QUEUED 8.57.1 Command code CCh Page 284 T13/1410D revision 3b 8.57.2 Feature set Overlapped feature set − − Mandatory for devices implementing the Overlapped feature set and not implementing the PACKET Command feature set. Use prohibited for devices implementing the PACKET Command feature set. 8.57.3 Protocol DMA QUEUED (see 9.9). 8.57.4 Inputs Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 Sector Count Tag obs LBA obs 2 1 0 na LBA (7:0) LBA (15:8) LBA (23:16) DEV CCh LBA (27:24) Features number of sectors to be transferred. A value of 00h specifies that 256 sectors are to be transferred. Sector count if the device supports command queuing, bits (7:3) contain the Tag for the command being delivered. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If queuing is not supported, this field is not applicable. LBA Low starting LBA bits (7:0). LBA Mid starting LBA bits (15:8). LBA High starting LBA bits (23:16). Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. bits (3:0) starting LBA bits (27:24). 8.57.5 Normal outputs 8.57.5.1 Data transmission Data transfer may occur after receipt of the command or may occur after the receipt of a SERVICE command. When the device is ready to transfer data requested by a data transfer command, the device sets the following register content to initiate the data transfer. Page 285 T13/1410D revision 3b Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 REL I/O C/D na na na na na CHK na Tag na na na obs BSY na DRDY obs DF DEV SERV na DRQ Interrupt reason register Tag -This field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this field is not applicable. REL - Shall be cleared to zero. I/O - Shall be cleared to zero indicating the transfer is from the host. C/D - Shall be cleared to zero indicating the transfer of data. Device register DEV - Shall indicate the selected device. Status register BSY - Shall be cleared to zero. DRDY - Shall be set to one. DF (Device Fault) - Shall be cleared to zero. SERV (Service) - Shall be set to one if another command is ready to be serviced. DRQ - Shall be set to one. CHK - Shall be cleared to zero. 8.57.5.2 Bus release If the device performs a bus release before transferring data for this command, the register content upon performing a bus release shall be as shown below. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 REL I/O C/D na ERR na Tag na na na obs BSY na DRDY obs DF DEV SERV na DRQ na Sector Count register Tag - If the device supports command queuing, this field shall contain the Tag of the command being bus released. If the device does not support command queuing, this field shall be zeros. REL bit shall be set indicating that the device has bus released an overlap command. I/O shall be cleared to zero. C/D shall be cleared to zero. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating bus release. DRDY shall be set to one. SERV (Service) shall be cleared to zero if no other queued command is ready for service. SERV shall be set to one when another queued command is ready for service. This bit shall be set to one when the device has prepared this command for service. Page 286 T13/1410D revision 3b DF (Device Fault) shall be cleared to zero. DRQ bit shall be cleared to zero. ERR bit shall be cleared to zero. 8.57.5.3 Service request When the device is ready to transfer data or complete a command after the command has performed a bus release, the device shall set the SERV bit and not change the state of any other register bit (see 6.9). When the SERVICE command is received, the device shall set outputs as described in data transfer, command completion, or error outputs depending on the service the device requires. 8.57.5.4 Command completion When the transfer of all requested data has occurred without error, the register content shall be as shown below. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 REL I/O C/D na ERR 00h Tag na na na obs BSY na DRDY obs DF DEV SERV na DRQ na Sector Count register Tag - If the device supports command queuing, this field shall contain the Tag of the completed command. If the device does not support command queuing, this field shall be zeros. REL shall be cleared to zero. I/O shall be set to one. C/D shall be set to one. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. SERV (Service) shall be cleared to zero when no other queued command is ready for service. SERV shall be set to one when another queued command is ready for service. DF (Device Fault) shall be cleared to zero. DRQ bit shall be cleared to zero. ERR bit shall be cleared to zero. 8.57.6 Error outputs The Sector Count register contains the Tag for this command if the device supports command queuing. The device shall return command aborted if the command is not supported. The device shall return command aborted if the device supports command queuing and the Tag is invalid. An unrecoverable error encountered during the execution of this command results in the termination of the command and the Command Block registers contain the sector where the first unrecoverable error occurred. If a queue existed, the unrecoverable error shall cause the queue to abort. The device may remain BSY for some time when responding to these errors. Page 287 T13/1410D revision 3b Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 ICRC obs BSY 6 WP na DRDY 5 MC Tag obs DF 4 IDNF 3 MCR LBA (7:0) LBA (15:8) LBA (23:16) DEV SERV DRQ 2 ABRT REL 1 NM I/O 0 na C/D LBA (27:24) na na ERR Error register ICRC shall be set to one if an interface CRC error has occurred during an Ultra DMA data transfer. The content of this bit is not applicable for Multiword DMA transfers. WP shall be set to one if the media in a removable media device is write protected. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported or if an error, including an ICRC error, has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. Sector Count register Tag - If the device supports command queuing, this field shall contain the Tag of the completed command. If the device does not support command queuing, this field shall be zeros. REL shall be cleared to zero. I/O shall be set to one. C/D shall be set to one. LBA Low, LBA Mid, LBA High, Device shall be written with the address of first unrecoverable error. DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. SERV (Service) shall be cleared to zero when no other queued command is ready for service. SERV shall be set to one when another queued command is ready for service. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.57.7 Prerequisites DRDY set to one. The host shall initialize the DMA channel. 8.57.8 Description This command executes in a similar manner to a WRITE DMA command. The device may perform a bus release the bus or may execute the data transfer without performing a bus release if the data is ready to transfer. If the device performs a bus release, the host shall reselect the device using the SERVICE command. Page 288 T13/1410D revision 3b Once the data transfer is begun, the device shall not perform a bus release until the entire data transfer has been completed. 8.58 WRITE DMA QUEUED EXT 8.58.1 Command code 36h 8.58.2 Feature set Overlapped feature set and 48-bit Address feature set − − Mandatory for devices implementing the Overlapped feature set and the 48-bit Address feature set and not implementing the PACKET Command feature set. Use prohibited for devices implementing the PACKET Command feature set. 8.58.3 Protocol DMA QUEUED (see 9.9). 8.58.4 Inputs Register 7 6 5 4 3 2 1 0 Features Current Sector count (7:0) Previous Sector count (15:8) Sector Count Current Tag Reserved Previous Reserved LBA Low Current LBA (7:0) Previous LBA (31:24) LBA Mid Current LBA (15:8) Previous LBA (39:32) LBA High Current LBA (23:16) Previous LBA (47:40) Device obs LBA obs DEV Reserved Command 36h NOTE − The value indicated as Current is the value most recently written to the register. The value indicated as Previous is the value that was in the register before the most recent write to the register. Features Current number of sectors to be transferred low order, bits (7:0). Features Previous number of sectors to be transferred high order, bits (15:8). 0000h in the Features register specifiess that 65,536 sectors are to be transferred. Sector Count Current if the device supports command queuing, bits (7:3) contain the Tag for the command being delivered. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If queuing is not supported, this register shall be set to the value 00h. Sector Count Previous – Reserved LBA Low Current LBA (7:0). LBA Low Previous LBA (31:24). LBA Mid Current LBA (15:8). Page 289 T13/1410D revision 3b LBA Mid Previous LBA (39:32). LBA High Current LBA (23:16). LBA High Previous LBA (47:40). Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. 8.58.5 Normal outputs 8.58.5.1 Data transmission Data transfer may occur after receipt of the command or may occur after the receipt of a SERVICE command. When the device is ready to transfer data requested by a data transfer command, the device sets the following register content to initiate the data transfer. Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Tag REL I/O C/D HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Sector Count (when HOB of the Device Control register is cleared to zero) Tag -This field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this register shall be set to the value 00h. REL - Shall be cleared to zero. I/O - Shall be cleared to zero indicating the transfer is from the host. C/D - Shall be cleared to zero indicating the transfer of data. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.58.5.2 Bus release If the device performs a bus release before transferring data for this command, the register content upon performing a bus release shall be as shown below. Page 290 T13/1410D revision 3b Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Tag REL I/O C/D HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY DF SERV DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Sector Count (when HOB of the Device Control register is cleared to zero) Tag -This field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this register shall be set to the value 00h. REL - Shall be set to one. I/O - Shall be cleared to zero. C/D - Shall be cleared to zero indicating the transfer of data. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. SERV (Service) shall be cleared to zero when no other queued command is ready for service. SERV shall be set to one when another queued command is ready for service. SERV shall be set to one when the device has prepared this command for service. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.58.5.3 Service request When the device is ready to transfer data or complete a command after the command has performed a bus release, the device shall set the SERV bit to one and not change the state of any other register bit (see 6.9). When the SERVICE command is received, the device shall set outputs as described in data transfer, command completion, or error outputs depending on the service the device requires. 8.58.5.4 Command completion When the transfer of all requested data has occurred without error, the register content shall be as shown below. Page 291 T13/1410D revision 3b Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Tag REL I/O C/D HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY DF SERV DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Sector Count (when HOB of the Device Control register is cleared to zero) Tag -This field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this register shall be set to the value 00h. REL - Shall be cleared to zero. I/O - Shall be set to one. C/D - Shall be set to one. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. SERV (Service) shall be cleared to zero when no other queued command is ready for service. SERV shall be set to one when another queued command is ready for service. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.58.6 Error outputs The Sector Count register contains the Tag for this command if the device supports command queuing. The device shall return command aborted if the command is not supported or if the device has not had overlapped interrupt enabled. The device shall return command aborted if the device supports command queuing and the Tag is invalid. An unrecoverable error encountered during the execution of this command results in the termination of the command and the Command Block registers contain the sector where the first unrecoverable error occurred. If a queue existed, the unrecoverable error shall cause the queue to abort. Page 292 T13/1410D revision 3b Register 7 6 5 4 3 2 1 0 Error ICRC WP MC IDNF MCR ABRT NM obs Sector Count HOB = 0 Tag REL I/O C/D HOB = 1 Reserved LBA Low HOB = 0 LBA (7:0) HOB = 1 LBA (31:24) LBA Mid HOB = 0 LBA (15:8) HOB = 1 LBA (39:32) LBA High HOB = 0 LBA (23:16) HOB = 1 LBA (47:40) Device obs na obs DEV Reserved Status BSY DRDY DF SERV DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Error register ICRC shall be set to one if an interface CRC error has occurred during an Ultra DMA data transfer. The content of this bit is not applicable for Multiword DMA transfers. WP shall be set to one if the media in a removable media device is write protected. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported or if an error, including an ICRC error, has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. Sector Count (when HOB of the Device Control register is cleared to zero) Tag -This field contains the command Tag for the command. A Tag value may be any value between 0 and 31 regardless of the queue depth supported. If the device does not support command queuing or overlap is disabled, this register shall be set to the value 00h. REL - Shall be cleared to zero. I/O - Shall be set to one. C/D - Shall be set to one. LBA Low LBA (7:0) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (31:24) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA Mid LBA (15:8) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (39:32) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA High LBA (23:16) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (47:40) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. Device register Page 293 T13/1410D revision 3b DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.58.7 Prerequisites DRDY set to one. The host shall initialize the DMA channel. 8.58.8 Description This command executes in a similar manner to a WRITE DMA EXT command. The device may perform a bus release the bus or may execute the data transfer without performing a bus release if the data is ready to transfer. If the device performs a bus release, the host shall reselect the device using the SERVICE command. Once the data transfer is begun, the device shall not perform a bus release until the entire data transfer has been completed. 8.59 WRITE LOG EXT 8.59.1 Command code 3Fh 8.59.2 Feature set General Purpose Logging feature set. − Mandatory for devices implementing the General Purpose Logging feature set. 8.59.3 Protocol PIO data-out (see 9.6). Page 294 T13/1410D revision 3b 8.59.4 Inputs Register 7 6 5 4 3 2 1 Features Current Reserved Previous Reserved Sector Count Current Sector count (7:0) Previous Sector count (15:8) LBA Low Current Log address Previous Reserved LBA Mid Current Sector offset (7:0) Previous Sector offset (15:8) LBA High Current Reserved Previous Reserved Device/Head obs na obs DEV Reserved Command 3Fh NOTE – The value indicated as Current is the value most recently written to the register. The value indicated as Previous is the value that was in the register before the most recent write to the register. 0 Sector Count – Specifies the number of sectors that shall be written to the specified log. If the number is greater than the number indicated in the Log directory (which is available in Log number zero), the device shall return command aborted. The log transferred to the drive shall be stored by the drive starting at the first sector in the specified log. LBA Low - Specifies the log to be written as described in Table 31. A device may support a subset of the available logs. Support for individual logs is determined by support for the associated feature set. Support of the associated log(s) is mandatory for devices implementing the associated feature set. If this command is implemented, all address values defined as host vendor specific shall be implemented. These host vendor specific logs may be used by the host to store any data desired. Support for device vendor specific logs is optional. If the host attempts to write to a read only (RO) log address, the device shall return command aborted. LBA Mid – Specifies the first sector of the log to be written. Device/Head register DEV shall specify the selected device. 8.59.5 Normal outputs Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device/Head obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Device/Head register DEV shall indicate the selected device. Page 295 T13/1410D revision 3b Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one indicating that the device is capable of receiving any command. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.59.6 Error outputs If the device does not support this command, if the feature set associated with the log specified in the LBA Low register is not supported or enabled, or if the values in the Features, Sector Count, LBA Mid, or LBA High registers are invalid, the device shall return command aborted. If the host attempts to write to a read only (RO) log address, the device shall return command aborted. Register 7 6 5 4 3 2 1 0 Error na na na IDNF na ABRT na obs Sector Count DC 7=0 Reserved DC 7=1 Reserved LBA Low DC 7=0 Reserved DC 7=1 Reserved LBA Mid DC 7=0 Reserved DC 7=1 Reserved LBA High DC 7=0 Reserved DC 7=1 Reserved Device/Head obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Error register IDNF shall be set to one if the log sector’s ID field was not found or data structure checksum error occurred. ABRT shall be set to one if this command is not supported, if the feature associated with the log specified in the LBA Low register is not supported or not enabled, or if other register values are invalid. ABRT may be set to one if the device is not able to complete the action requested by the command. Device/Head register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one indicating that the device is capable of receiving any command. DF (Device Fault) shall be set to one indicating that a device fault has occurred. DRQ shall be cleared to zero indicating that there is no data to be transferred. ERR shall be set to one if any Error register bit is set to one. 8.59.7 Prerequisites DRDY set to one. 8.59.8 Description This command writes a specified number of 512 byte data sectors to the specified log. The device shall interrupt for each DRQ block transferred. Page 296 T13/1410D revision 3b 8.60 WRITE MULTIPLE 8.60.1 Command code C5h 8.60.2 Feature set General feature set − Mandatory for devices not implementing the PACKET Command feature set. − Use prohibited for devices implementing the PACKET Command feature set. 8.60.3 Protocol PIO data-out (see 9.6). 8.60.4 Inputs The LBA Mid, LBA High, Device, and LBA Low specify the starting sector address to be written. The Sector Count register specifies the number of sectors to be transferred. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 obs LBA obs 4 3 na Sector count LBA (7:0) LBA (15:8) LBA (23:16) DEV C5h 2 1 0 LBA (27:24) Sector Count number of sectors to be transferred. A value of 00h specifies that 256 sectors shall be transferred. LBA Low starting LBA bits (7:0). LBA Mid starting LBA bits (15:8). LBA High starting LBA bits (23:16). Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. bits (3:0) starting LBA bits (27:24). Page 297 T13/1410D revision 3b 8.60.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na DRQ na na na na na ERR na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.60.6 Error outputs An unrecoverable error encountered during the execution of this command results in the termination of the command. The Command Block registers contain the address of the sector where the first unrecoverable error occurred. The amount of data transferred is indeterminate. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na obs BSY 6 WP na DRDY 5 MC 4 IDNF 3 MCR obs DF na LBA (7:0) LBA (15:8) LBA (23:16) DEV na DRQ 2 ABRT 1 NM LBA (27:24) na na 0 na ERR Error register WP shall be set to one if the media in a removable media device is write protected. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported or if an error, including an ICRC error, has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is not able to complete action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. LBA Low, LBA Mid, LBA High, Device shall be written with the address of first unrecoverable error. DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. Page 298 T13/1410D revision 3b DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.60.7 Prerequisites DRDY set to one. If bit 8 of IDENTIFY DEVICE word 59 is cleared to zero, a successful SET MULTIPLE MODE command shall proceed a WRITE MULTIPLE command. 8.60.8 Description This command writes the number of sectors specified in the Sector Count register. The number of sectors per block is defined by the content of word 59 of the IDENTIFY DEVICE response. When the WRITE MULTIPLE command is issued, the Sector Count register contains the number of sectors (not the number of blocks) requested. The device shall interrupt for each DRQ block transferred. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where: n = Remainder (sector count/ block count). If the WRITE MULTIPLE command is received when WRITE MULTIPLE commands are disabled, the Write Multiple operation shall be rejected with command aborted. Device errors encountered during WRITE MULTIPLE commands are posted after the attempted device write of the block or partial block transferred. The command ends with the sector in error, even if the error was in the middle of a block. Subsequent blocks are not transferred in the event of an error. The contents of the Command Block Registers following the transfer of a data block that had a sector in error are undefined. The host should retry the transfer as individual requests to obtain valid error information. Interrupt pending is set when the DRQ bit is set to one at the beginning of each block or partial block. 8.61 WRITE MULTIPLE EXT 8.61.1 Command code 39h 8.61.2 Feature set 48-bit Address feature set − − Mandatory for devices implementing the 48-bit Address feature set. Use prohibited for devices implementing the PACKET Command feature set. 8.61.3 Protocol PIO data-out (see 9.6). Page 299 T13/1410D revision 3b 8.61.4 Inputs Register 7 6 5 4 3 2 1 0 Features Current Reserved Previous Reserved Sector Count Current Sector count (7:0) Previous Sector count (15:8) LBA Low Current LBA (7:0) Previous LBA (31:24) LBA Mid Current LBA (15:8) Previous LBA (39:32) LBA High Current LBA (23:16) Previous LBA (47:40) Device obs LBA obs DEV Reserved Command 39h NOTE − The value indicated as Current is the value most recently written to the register. The value indicated as Previous is the value that was in the register before the most recent write to the register. Sector Count Current number of sectors to be transferred low order, bits (7:0). Sector Count Previous number of sectors to be transferred high order, bits (15:8). 0000h in the Sector Count register specifies that 65,536 sectors are to be transferred. LBA Low Current LBA (7:0). LBA Low Previous LBA (31:24). LBA Mid Current LBA (15:8). LBA Mid Previous LBA (39:32). LBA High Current LBA (23:16). LBA High Previous LBA (47:40). Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. Page 300 T13/1410D revision 3b 8.61.5 Normal outputs Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.61.6 Error outputs An unrecoverable error encountered during the execution of this command results in the termination of the command. The Command Block registers contain the address of the sector where the first unrecoverable error occurred. The amount of data transferred is indeterminate. Register 7 6 5 4 3 2 1 0 Error na WP MC IDNF MCR ABRT NM obs Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 LBA (7:0) HOB = 1 LBA (31:24) LBA Mid HOB = 0 LBA (15:8) HOB = 1 LBA (39:32) LBA High HOB = 0 LBA (23:16) HOB = 1 LBA (47:40) Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Page 301 T13/1410D revision 3b Error register WP shall be set to one if the media in a removable media device is write protected. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. LBA Low LBA (7:0) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (31:24) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA Mid LBA (15:8) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (39:32) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA High LBA (23:16) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (47:40) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.61.7 Prerequisites DRDY set to one. If bit 8 of IDENTIFY DEVICE word 59 is cleared to zero, a successful SET MULTIPLE MODE command shall proceed a WRITE MULTIPLE EXT command. 8.61.8 Description This command writes the number of sectors specified in the Sector Count register. The number of sectors per block is defined by the content of word 59 in the IDENTIFY DEVICE response. When the WRITE MULTIPLE EXT command is issued, the Sector Count register contains the number of sectors (not the number of blocks) requested. The device shall interrupt for each DRQ block transferred. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where: n = Remainder (sector count / block count). Page 302 T13/1410D revision 3b If the WRITE MULTIPLE EXT command is received when WRITE MULTIPLE EXT commands are disabled, the Write Multiple operation shall be rejected with command aborted. Device errors encountered during WRITE MULTIPLE EXT commands are posted after the attempted device write of the block or partial block transferred. The command ends with the sector in error, even if the error was in the middle of a block. Subsequent blocks are not transferred in the event of an error. The contents of the Command Block Registers following the transfer of a data block that had a sector in error are undefined. The host should retry the transfer as individual requests to obtain valid error information. Interrupt pending is set when the DRQ bit is set to one at the beginning of each block or partial block. 8.62 WRITE SECTOR(S) 8.62.1 Command code 30h 8.62.2 Feature set General feature set − − Mandatory for devices not implementing the PACKET Command feature set. Use prohibited for devices implementing the PACKET Command feature set. 8.62.3 Protocol PIO data-out (see 9.6). 8.62.4 Inputs The LBA Mid, LBA High, Device, and LBA Low specify the starting sector address to be written. The Sector Count register specifies the number of sectors to be transferred. Register Features Sector Count LBA Low LBA Mid LBA High Device Command 7 obs 6 LBA 5 obs 4 3 na Sector count LBA (7:0) LBA (15:8) LBA (23:16) DEV 30h 2 1 0 LBA (27:24) Sector Count number of sectors to be transferred. A value of 00h specifies that 256 sectors are to be transferred. LBA Low starting LBA bits (7:0). LBA Mid starting LBA bits (15:8). LBA High starting LBA bits (23:16). Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. Page 303 T13/1410D revision 3b bits (3:0) starting LBA bits (27:24). 8.62.5 Normal outputs Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 na DRQ na na na na na ERR na na na na na obs BSY na DRDY obs DF DEV na Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.62.6 Error outputs An unrecoverable error encountered during the execution of this command results in the termination of the command. The Command Block registers contain the address of the sector where the first unrecoverable error occurred. The amount of data transferred is indeterminate. Register Error Sector Count LBA Low LBA Mid LBA High Device Status 7 na obs BSY 6 WP na DRDY 5 MC 4 IDNF 3 MCR obs DF na LBA (7:0) LBA (15:8) LBA (23:16) DEV na DRQ 2 ABRT 1 NM LBA (27:24) na na 0 na ERR Error register WP shall be set to one if the media in a removable media device is write protected. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported or if an error, including an ICRC error, has occurred during an Ultra DMA data transfer. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. LBA Low, LBA Mid, LBA High, Device shall be written with the address of first unrecoverable error. DEV shall indicate the selected device. Page 304 T13/1410D revision 3b Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. 8.62.7 Prerequisites DRDY set to one. 8.62.8 Description This command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The device shall interrupt for each DRQ block transferred. 8.63 WRITE SECTOR(S) EXT 8.63.1 Command code 34h 8.63.2 Feature set 48-bit Address feature set − − Mandatory for devices implementing the 48-bit Address feature set. Use prohibited for devices implementing the PACKET Command feature set. 8.63.3 Protocol PIO data-out (see 9.6). 8.63.4 Inputs Register 7 6 5 4 3 2 1 0 Features Current Reserved Previous Reserved Sector Count Current Sector count (7:0) Previous Sector count (15:8) LBA Low Current LBA (7:0) Previous LBA (31:24) LBA Mid Current LBA (15:8) Previous LBA (39:32) LBA High Current LBA (23:16) Previous LBA (47:40) Device obs LBA obs DEV Reserved Command 34h NOTE − The value indicated as Current is the value most recently written to the register. The value indicated as Previous is the value that was in the register before the most recent write to the register. Sector Count Current number of sectors to be transferred low order, bits (7:0). Sector Count Previous Page 305 T13/1410D revision 3b number of sectors to be transferred high order, bits (15:8). LBA Low Current LBA (7:0). LBA Low Previous LBA (31:24). LBA Mid Current LBA (15:8). LBA Mid Previous LBA (39:32). LBA High Current LBA (23:16). LBA High Previous LBA (47:40). Device the LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the selected device. 8.63.5 Normal outputs Register 7 6 5 4 3 2 1 0 Error na Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 Reserved HOB = 1 Reserved LBA Mid HOB = 0 Reserved HOB = 1 Reserved LBA High HOB = 0 Reserved HOB = 1 Reserved Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Device register – DEV shall indicate the selected device. Status register – BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. 8.63.6 Error outputs An unrecoverable error encountered during the execution of this command results in the termination of the command. The Command Block registers contain the address of the sector where the first unrecoverable error occurred. The amount of data transferred is indeterminate. Page 306 T13/1410D revision 3b Register 7 6 5 4 3 2 1 0 Error na WP MC IDNF MCR ABRT NM obs Sector Count HOB = 0 Reserved HOB = 1 Reserved LBA Low HOB = 0 LBA (7:0) HOB = 1 LBA (31:24) LBA Mid HOB = 0 LBA (15:8) HOB = 1 LBA (39:32) LBA High HOB = 0 LBA (23:16) HOB = 1 LBA (47:40) Device obs na obs DEV Reserved Status BSY DRDY DF na DRQ na na ERR NOTE − HOB = 0 indicates the value read by the host when the HOB bit of the Device Control register is cleared to zero. HOB = 1 Indicates the value read by the host when the HOB bit of the Device Control register is set to one. Error register WP shall be set to one if the media in a removable media device is write protected. MC shall be set to one if the media in a removable media device changed since the issuance of the last command. The device shall clear the device internal media change detected state. IDNF shall be set to one if a user-accessible address could not be found. IDNF shall be set to one if an address outside of the range of user-accessible addresses is requested if command aborted is not returned. MCR shall be set to one if a media change request has been detected by a removable media device. This bit is only cleared by a GET MEDIA STATUS or a media access command. ABRT shall be set to one if this command is not supported. ABRT may be set to one if the device is not able to complete the action requested by the command. ABRT shall be set to one if an address outside of the range of user-accessible addresses is requested if IDNF is not set to one. NM shall be set to one if no media is present in a removable media device. LBA Low LBA (7:0) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (31:24) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA Mid LBA (15:8) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (39:32) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. LBA High LBA (23:16) of the address of the first unrecoverable error when read with Device Control register HOB bit cleared to zero. LBA (47:40) of the address of the first unrecoverable error when read with Device Control register HOB bit set to one. Device register DEV shall indicate the selected device. Status register BSY shall be cleared to zero indicating command completion. DRDY shall be set to one. DF (Device Fault) shall be set to one if a device fault has occurred. DRQ shall be cleared to zero. ERR shall be set to one if an Error register bit is set to one. Page 307 T13/1410D revision 3b 8.63.7 Prerequisites DRDY set to one. 8.63.8 Description This command writes from 1 to 65,536 sectors as specified in the Sector Count register. A sector count value of 0000h requests 65,536 sectors. The device shall interrupt for each DRQ block transferred. 9 Protocol Commands are grouped into different classes according to the protocol followed for command execution. The command classes with their associated protocol are defined in state diagrams in this clause, one state diagram for host actions and a second state diagram for device actions. Figure 12 shows the overall relationship of the host protocol state diagrams. Figure 13 shows the overall relationship of the device protocol state diagrams. State diagrams defining these protocols are not normative descriptions of implementations, they are normative descriptions of externally apparent device or host behavior. Different implementations are allowed. See 3.2.7 for state diagram conventions. A device shall not timeout any activity when waiting for a response from the host. Page 308 T13/1410D revision 3b HHR: Host power on or Hardware Reset Power on HI:HIO: Host bus Idle RESET asserted HSR: Host Software Reset Reset completed Command written Command completed SRST Service return Bus released HND: Host Non-Data command HPIOI: Host PIO dataIn command HPIOO: Host PIO dataOut command HDMA: Host DMA command HED: Host EXECUTE DEVICE DIAGNOSTIC command HDR: Host DEVICE RESET command HP: Host PACKET nondata & PIO data command HPD: Host PACKET DMA command HDMAQ: Host DMA QUEUED command Figure 12 − Overall host protocol state sequence Page 309 T13/1410D revision 3b DHR: Device power on or Hardware Reset Power on DI:DIO: Device bus Idle RESET asserted Reset completed D0SR: Device 0 Software Reset SRST & Device 0 Command written Command completed Service return Bus released D1SR: Device 1 Software Reset SRST & Device 1 DND: Device Non-Data command DPIOO: Device PIO data-Out command D0ED: Device 0 EXECUTE DEVICE DIAGNOSTIC command DDR: Device DEVICE RESET command DPD: Device PACKET DMA command DPIOI: Device PIO data-In command DDMA: Device DMA command D1ED: Device 1 EXECUTE DEVICE DIAGNOSTIC cmnd DP: Device PACKET nondata & PIO data command DDMAQ: Device DMA QUEUED command Figure 13 − Overall device protocol state sequence Page 310 T13/1410D revision 3b 9.1 Power-on and hardware reset protocol This clause describes the protocol for processing of power-on and hardware resets. If the host asserts RESET-, regardless of the power management mode, the device shall execute the hardware reset protocol. If the host reasserts RESET- before a device has completed the power-on or hardware reset protocol, then the device shall restart the protocol from the begining. The host should not set the SRST bit to one in the Device Control register or issue a DEVICE RESET command while the BSY bit is set to one in either device Status register as a result of executing the power-on or hardware reset protocol. If the host sets the SRST bit in the Device Control register to one or issues a DEVICE RESET command before devices have completed execution of the power-on or hardware reset protocol, then the devices shall ignore the software reset or DEVICE RESET command. A host should issue an IDENTIFY DEVICE and/or IDENTIFY PACKET DEVICE command after the power-on or hardware reset protocol has completed to determine the current status of features implemented by the device(s). Figure 14 and the text following the figure decribes the power-on or hardware reset protocol for the host. Figure 15 and the text following the figure decribes the power-on or hardware reset protocol for the devices. HHR0: Assert_RESETPower on or hardware reset required HHR1: Negate_wait RESET- asserted >25 µs (t=0) HHR0:HHR1 HHR2: Check_status t > 2 ms HHR1:HHR2 BSY = 0 HHR2:HI0 Host_idle BSY = 1 xx:HHR0 HHR2:HHR2 Figure 14 − Host power-on or hardware reset state diagram HHR0: Assert_RESET- State: This state is entered at power-on or when the host recognizes that a hardware reset is required. When in this state, the host asserts RESET-. The host shall remain in this state with RESET- asserted for at least 25 µs. The host shall negate CS(1:0), DA(2:0), DMACK-, DIOR-, and DIOW- and release DD(15:0). Transition HHR0:HHR1: When the host has had RESET- asserted for at least 25 µs, the host shall make a transition to the HHR1: Negate_wait state. HHR1: Negate_wait State: This state is entered when RESET- has been asserted for at least 25 µs. When in this state, the host shall negate RESET-. The host shall remain in this state for at least 2 ms after negating RESET-. If the host tests CBLID- it shall do so at this time. Transition HHR1:HHR2: When RESET- has been negated for at least 2 ms, the host shall make a transition to the HHR2: Check_status state. HHR2: Check_status State: This state is entered when RESET- has been negated for at least 2 ms. When in this state the host shall read the Status or Alternate Status register. Page 311 T13/1410D revision 3b Transition HHR2:HHR2: When BSY is set to one, the host shall make a transition to the HHR2: Check_status state. Transition HHR2:HI0: When BSY is cleared to zero, the host shall make a transition to the HI0: Host_idle state (see Figure 19). If status indicates that an error has occurred, the host shall take appropriate error recovery action. DHR0: RESETPDIAG-=X, DASP-=X, BSY=x DHR1: Release_bus PDIAG-=R, DASP-=X, BSY=1 Bus released & Device 1 RESET- negated (t=0) DHR0:DHR1 DHR1:D1HR0 Bus released & Device 0 D0HR0: DASP-_wait DHR1:D0HR0 PDIAG- =R, DASP- =R, BSY=1 D1HR0: Set_DASPt > 1 ms PDIAG- =R, DASP- =R, BSY=1 D0HR0:D0HR1 RESET- asserted xx:DHR0 D0HR1: Sample_DASPPDIAG- =R, DASP- =R, BSY=1 DASP- asserted D1HR0:D1HR1 Sample DASPD0HR1:D0HR1 DASP- asserted D0HR1:D0HR2 D1HR1: Set_status PDIAG- =R, DASP- =A, BSY=1 Status set, passed diagnostic Device_idle_NS D1HR1:DI2 BSY=0, PDIAG-=A 450 ms < t ≤ 5 s D0HR1:D0HR3 Clear bit 7 Status set, failed diagnostic Device_idle_NS D1HR1:DI2 BSY=0, PDIAG-=N D0HR2: Sample_PDIAGPDIAG- =R, DASP- =R, BSY=1 D0HR3: Set_status PDIAG- =R, DASP- =R, BSY=1 Resample PDIAGD0HR2:D0HR2 PDIAG- asserted D0HR2a:D0HR3 Clear bit 7 Status set D0HR3:DI1 BSY=0 Device_idle_S t > 31 s D0HR2b:D0HR3 Set bit 7 BSY v DRQ 0 REL 0 SERV 0 C/D 0 I/O 0 INTRQ R DMARQ R PDIAGV DASPV Figure 15 − Device power-on or hardware reset state diagram DHR0: RESET State: This state is entered when a valid assertion of the RESET- signal is recognized. The device shall not recognize a RESET- assertion shorter than 20 ns as valid. Devices may recognize a RESET- assertion greater that 20 ns as valid and shall recognize a RESET- assertion equal to or greater than 25 µs as valid. Transition DHR0:DHR1: When a valid RESET- signal is negated, the device shall make a transition to the DHR1: Release_Bus state. Page 312 T13/1410D revision 3b DHR1: Release_bus State: This state is entered when a valid RESET- signal is negated. When in this state, the device shall release bus signals PDIAG-, INTRQ, IORDY, DMARQ, and DD(15:0) and shall set BSY to one within 400 ns after entering this state. The device shall determine if the device is Device 0 or Device 1 by checking the jumper, switch, or CSEL. Transition DHR1:D0HR0: When the device has determined that the device is Device 0, has released the bus signals, and has set BSY to one, then the device shall make a transition to the D0HR0: DASP-_wait state. Transition DHR1:D1HR0: When the device has determined that the device is Device 1, has released the bus signals, and has set BSY to one, then the device shall make a transition to the D1HR0: Set_DASP- state. D0HR0: DASP-_wait State: This state is entered when the device has released the bus signals, set BSY to one, and determined that the device is Device 0. When in this state, the device shall release DASP- and clear the DEV bit in the Device register to zero within 1 ms of the negation of RESET-. Transition D0HR0:D0HR1: When at least 1 ms has elapsed since the negation of RESET-, the device shall make a transition to the D0HR1: Sample_DASP- state. D0HR1: Sample_DASP- State: This state is entered when at least 1 ms has elapsed since the negation of RESET-. When in this state, the device should begin performing the hardware initialization and self-diagnostic testing. This may revert the device to the default condition (the device’s settings may now be different than they were before the host asserted RESET-). All Ultra DMA modes shall be disabled. When in this state, the device shall sample the DASP- signal. Transition D0HR1:D0HR2: When the sample indicates that DASP- is asserted, the device shall make a transition to the D0HR2: Sample_PDIAG- state. Transition D0HR1:D0HR1: When the sample indicates that DASP- is negated and elapsed since the negation of RESET-, then the device shall make a transition to the state. When the sample indicates that DASP- is negated and greater than 450 ms elapsed since the negation of RESET-, then the device may make a transition to the state. less than 450 ms have D0HR1: Sample_DASPbut less than 5 s have D0HR1: Sample_DASP- Transition D0HR1:D0HR3: When the sample indicates that DASP- is negated and 5 s have elapsed since the negation of RESET-, then the device shall clear bit 7 in the Error register and make a transition to the D0HR3: Set_status state. When the sample indicates that DASP- is negated and greater than 450 ms but less than 5 s have elapsed since the negation of RESET-, then the device may clear bit 7 in the Error register and make a transition to the D0HR3: Set_status state. D0HR2: Sample_PDIAG- State: This state is entered when the device has recognized that DASP- is asserted. When in this state, the device shall sample the PDIAG- signal. Transition D0HR2a:D0HR3: When the sample indicates that PDIAG- is asserted, the device shall clear bit 7 in the Error register and make a transition to the D0HR3: Set_status state. Page 313 T13/1410D revision 3b Transition D0HR2b:D0HR3: When the sample indicates that PDIAG- is not asserted and 31 s have elapsed since the negation of RESET-, then the device shall set bit 7 in the Error register and make a transition to the D0HR3: Set_status state. Transition D0HR2:D0HR2: When the sample indicates that PDIAG- is not asserted and less than 31 s have elapsed since the negation of RESET-, then the device shall make a transition to the D0HR2: Sample_PDIAGstate. D0HR3: Set_status State: This state is entered when Bit 7 in the Error register has been set or cleared. When in this state the device shall complete the hardware initialization and self-diagnostic testing begun in the Sample DASP- state if not already completed. The diagnostic code shall be placed in bits (6:0) of the Error register (see Table 26). The device shall set the signature values (see 9.12). The device shall clear the SRST bit to zero in the Device Control register if set set to one. The content of the Features register is undefined. The device shall set word 93 in the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response (see 8.15.49). If the device does not implement the PACKET command feature set, the device shall clear bits 3, 2, and 0 in the Status register to zero. If the device implements the PACKET command feature set, the device shall clear bits 6, 5, 4, 3, 2, and 0 in the Status register to zero. The device shall return the operating modes to their specified initial conditions. MODE SELECT conditions shall be restored to their last saved values if saved values have been established. MODE SELECT conditions for which no values have been saved shall be returned to their default values. Transition D0HR3:DI1: When hardware initialization and self-diagnostic testing is completed and the status has been set, the device shall clear BSY to zero and make a transition to the DI1: Device_idle_S state (see Figure 21). D1HR0: Set_DASP- State: This state is entered when the device has released the bus, set BSY to one, and determined that the device is Device 1. When in this state, the device shall clear the DEV bit in the Device register to zero within 1 ms and shall assert DASP- within 400 ms of the negation of RESET-. When in this state, the device should begin execution of the hardware initialization and self-diagnostic testing. The device may revert to the default condition (the device’s settings may now be in different conditions than they were before RESET- was asserted by the host). All Ultra DMA modes shall be disabled. Transition D1HR0:D1HR1: When DASP- has been asserted, the device shall make a transition to the D1HR1: Set_status state. D1HR1: Set_status State: This state is entered when the device has asserted DASP-. When in this state the device shall complete any hardware initialization and self-diagnostic testing begun in the Set DASP- state if not already completed. The diagnostic code shall be placed in the Error register (see Table 26). If the device passed self-diagnostics, the device shall assert PDIAG-. The device shall set word 93 in the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response (see 8.15.49). All actions required in this state shall be completed in ≤ 30 s. The device shall set the signature values (see 9.12). The content of the Features register is undefined. The device shall clear the SRST bit to zero in the Device Control register if set set to one. Page 314 T13/1410D revision 3b If the device does not implement the PACKET command feature set, the device shall clear bits 3, 2, and 0 in the Status register to zero. If the device implements the PACKET command feature set, the device shall clear bits 6, 5, 4, 3, 2, and 0 in the Status register to zero. The device shall return the operating modes to their specified initial conditions. MODE SELECT conditions shall be restored to their last saved values if saved values have been established. MODE SELECT conditions for which no values have been saved shall be returned to their default values. Transition D1HR1a:DI2: When hardware initialization and self-diagnostic testing is completed, the device passed its diagnostics, and the status has been set, the device shall clear BSY to zero, assert PDIAG-, and make a transition to the DI2: Device_idle_NS state (see Figure 21). Transition D1HR1b:DI2: When hardware initialization and self-diagnostic testing is completed, the device failed its diagnostic, and the status has been set, the device shall clear BSY to zero, negate PGIAG-, and make a transition to the DI2: Device_idle_NS state (see Figure 21). 9.2 Software reset protocol This clause describes the protocol for processing of software reset when the host sets SRST. If the host sets SRST in the Device Control register to one regardless of the power management mode, the device shall execute the software reset protocol. If the host asserts RESET- before a device has completed the software reset protocol, then the device shall execute the hardware reset protocol from the beginning. The host should not set the SRST bit to one in the Device Control while the BSY bit is set to one in either device Status register as a result of executing the software reset protocol. If the host sets the SRST bit in the Device Control register to one before devices have completed execution of the software reset protocol, then the devices shall restart execution of the software reset protocol from the beginning. If the host issues a DEVICE RESET command before devices have completed execution of the software reset protocol, the command shall be ignored. A host should issue an IDENTIFY DEVICE and/or IDENTIFY PACKET DEVICE command after the software reset protocol has completed to determine the current status of features implemented by the device(s). Figure 16 and the text following the figure decribe the software reset protocol for the host. Figure 17 and the text following the figure describes the software reset protocol for Device 0. Figure 18 and the text following the figure describes the software reset protocol for Device 1. HSR0: Set_SRST Software reset required xx:HSR0 SRST asserted ≥ 5 µs (t = 0) HSR0:HSR1 HSR2: Check_status HSR1: Clear_wait t > 2 ms HSR1:HSR2 BSY = 0 HSR2:HI0 Host_idle BSY = 1 HSR2:HSR2 Figure 16 − Host software reset state diagram HSR0: Set_SRST State: This state is entered when the host initiates a software reset. When in this state, the host shall set SRST in the Device Control register to one. The SRST bit shall be written to both devices when the Device Control register is written. The host shall remain in this state with SRST set to Page 315 T13/1410D revision 3b one for at least 5 µs. The host shall not set SRST to one unless the bit has been cleared to zero for at least 5 µs. Transition HSR0:HSR1: When the host has had SRST set to one for at least 5 µs, the host shall make a transition to the HSR1: Clear_wait state. HSR1: Clear_wait State: This state is entered when SRST has been set to one for at least 5 µs. When in this state, the host shall clear SRST in the Device Control register to zero. The host shall remain in this state for at least 2 ms. Transition HSR1:HSR2: When SRST has been cleared to zero for at least 2 ms, the host shall make a transition to the HSR2: Check_status state. HSR2: Check_status State: This state is entered when SRST has been cleared to zero for at least 2 ms. When in this state the host shall read the Status or Alternate Status register. Transition HSR2:HSR2: When BSY is set to one, the host shall make a transition to the HSR2: Check_status state. Transition HSR2:HI0: When BSY is cleared to zero, the host shall check the ending status in the Error register and the signature (see 9.12) and make a transition to the HI0: Host_idle state (see Figure 19). D0SR0: SRST PDIAG- =R, BSY=1 SRST set to one xx:D0SR0 D0SR3: Set_status PDIAG- =R, BSY=1 SRST cleared to zero & no Device 1 (t=0) D0SR0:D0SR3 Clear bit 7 D0SR1: PDIAG-_wait SRST cleared to zero & PDIAG- =R, BSY=1 Device 1 exists (t=0) D0SR0:D0SR1 Status set D0SR3:DI1 BSY=0 Device_ idle_S t>1 ms D0SR1:D0SR2 D0SR2: Sample_PDIAGPDIAG- =R, BSY=1 Resample PDIAG- PDIAG- asserted D0SR2a:D0SR3 Clear bit 7 D0SR2:D0SR2 t > 31 s D0SR2b:D0SR3 Set bit 7 BSY v DRQ 0 REL 0 SERV 0 C/D 0 I/O 0 INTRQ R DMARQ R Figure 17 − Device 0 software reset state diagram Page 316 PDIAGV DASPR T13/1410D revision 3b D0SR0: SRST State: This state is entered by Device 0 when the SRST bit is set to one in the Device Control register. When in this state, the device shall release PDIAG-, INTRQ, IORDY, DMARQ, and DD(15:0) within 400 ns after entering this state. The device shall set BSY to one within 400 ns after entering this state. If the device does not implement the PACKET command feature set, the device should begin performing the hardware initialization and self-diagnostic testing. The device may revert to the default condition (the device’s setting may now be in different conditions than they were before the SRST bit was set to one by the host). However, an Ultra DMA mode setting (either enabled or disabled) shall not be affected by the host setting SRST to one. If the PACKET command feature set is implemented, the device may begin performing the hardware initialization and self-diagnostic testing and the device is not expected to stop any background device activity (e.g., immediate command, see MMC or MMC-2) that was started prior to the time that SRST was set to one. The device shall not revert to the default condition and an Ultra DMA mode setting (either enabled or disabled) shall not be affected by the host setting SRST to one. Transition D0SR0:D0SR1: When SRST is cleared to zero and the assertion of DASP- by Device 1 was detected during the most recent power-on or hardware reset, the device shall make a transition to the D0SR1: PDIAG-_wait state. Transition D0SR0:D0SR3: When SRST is cleared to zero and the assertion of DASP- by Device 1 was not detected during the most recent power-on or hardware reset, the device shall clear bit 7 to zero in the Error register and make a transition to the D0SR3: Set_status state. D0SR1: PDIAG-_wait State: This state is entered when SRST has been cleared to zero and Device 1 is present. The device shall remain in this state for at least 1 ms and shall clear the DEV bit in the Device register to zero within 1 ms. Transition D0SR1:D0SR2: When at least 1 ms has elapsed since SRST was cleared to zero, the device shall make a transition to the D0SR2: Sample_PDIAG- state. D0SR2: Sample_PDIAG- State: This state is entered when SRST has been cleared to zero for at least 1 ms. When in this state, the device shall sample the PDIAG- signal. Transition D0SR2:D0SR2: When the sample indicates that PDIAG- is not asserted and less than 31 s have elapsed since SRST was cleared to zero, then the device shall make a transition to the D0SR2: Sample_PDIAG- state. Transition D0SR2a:D0SR3: When the sample indicates that PDIAG- is asserted, the device device shall clear bit 7 to zero in the Error register and shall make a transition to the D0SR3: Set_status state. Transition D0SR2b:D0SR3: When the sample indicates that PDIAG- is not asserted and 31 s have elapsed since SRST was cleared to zero, the device shall set bit 7 to one in the Error register and shall make a transition to the D0SR3: Set_status state. D0SR3: Set_status State: This state is entered when Bit 7 in the Error register has been set or cleared or Device 1 does not exist. Page 317 T13/1410D revision 3b When in this state, the device shall clear the DEV bit in the Device register to zero within 1 ms. The device shall complete any hardware initialization and self-diagnostic testing begun in the SRST state if not already completed. All actions required in this state shall be completed within 31 s. The diagnostic code shall be placed in bits (6:0) of the Error register (see Table 26). The device shall set the signature values (see 9.12). The content of the Features register is undefined. If the device does not implement the PACKET command feature set, the device shall clear bits 3, 2, and 0 in the Status register to zero. If the device implements the PACKET command feature set, the device shall clear bits 6, 5, 4, 3, 2, and 0 in the Status register to zero. The device shall return the operating modes to their specified initial conditions. MODE SELECT conditions shall be restored to their last saved values if saved values have been established. MODE SELECT conditions for which no values have been saved shall be returned to their default values. Transition D0SR3:DI1: When hardware initialization and self-diagnostic testing is completed and the status has been set, the device shall clear BSY to zero and make a transition to the DI1: Device_idle_S state (see Figure 21). D1SR0: SRST PDIAG-=X, BSY=1 SRST = 1 xx:D1SR0 D1SR1: Release_PDIAGPDIAG- =X, BSY=1 SRST= 0 D1SR2: Set_status PDIAG- =R, BSY=1 PDIAG- released D1SR0:D1SR1 D1SR1:D1SR2 Status set, passed diagnostics Device_ D1SR2a:DI2 idle_NS BSY=0, PDIAG-=A Status set, failed diagnostics Device_ D1SR2b:DI2 idle_NS BSY=0, PDIAG-=N BSY v DRQ 0 REL 0 SERV 0 C/D 0 I/O 0 INTRQ R DMARQ R PDIAGV DASPR Figure 18 − Device 1 software reset state diagram D1SR0: SRST State: This state is entered by Device 1 when the SRST bit is set to one in the Device Control register. When in this state, the device shall release INTRQ, IORDY, DMARQ, and DD(15:0) within 400 ns after entering this state. The device shall set BSY to one within 400 ns after entering this state. If the device does not implement the PACKET command feature set, the device shall begin performing the hardware initialization and self-diagnostic testing. The device may revert to the default condition (the device’s setting may now be in different conditions than they were before the SRST bit was set to one by the host). However, an Ultra DMA mode setting (either enabled or disabled) shall not be affected by the host setting SRST to one. If the PACKET command feature set is implemented, the device may begin performing the hardware initialization and self-diagnostic testing and the device is not expected to stop any background device activity (e.g., immediate command, see MMC and MMC-2) that was started prior to the time that SRST was set to one. The device shall not revert to the default condition and an Ultra DMA mode setting (either enabled or disabled) shall not be affected by the host setting SRST to one. Page 318 T13/1410D revision 3b Transition D1SR0:D1SR1: When SRST is cleared to zero, the device shall make a transition to the D1SR1: Release_PDIAG- state. D1SR1: Release_PDIAG- State: This state is entered when SRST is cleared to zero. When in this state, the device shall release PDIAG- and clear the DEV bit in the Device register to zero within 1 ms of entering this state. Transition D1SR1:D1SR2: When PDIAG- has been released, the device shall make a transition to the D1SR2: Set_status state. D1SR2: Set_status State: This state is entered when the device has negated PDIAG-. When in this state the device shall complete the hardware initialization and self-diagnostic testing begun in the SRST state if not already completed. The diagnostic code shall be placed in the Error register (see Table 26). If the device passed the self-diagnostics, the device shall assert PDIAG-. All actions required in this state shall be completed within 30 s. The device shall set the signature values (see 9.12). The contents of the Features register is undefined. If the device does not implement the PACKET command feature set, the device shall clear bits 3, 2, and 0 in the Status register to zero. If the device implements the PACKET command feature set, the device shall clear bits 6, 5, 4, 3, 2, and 0 in the Status register to zero. The device shall return the operating modes to their specified initial conditions. MODE SELECT conditions shall be restored to their last saved values if saved values have been established. MODE SELECT conditions for which no values have been saved shall be returned to their default values. Transition D1SR2a:DI2: When hardware initialization, self-diagnostic testing is completed, the device passed the diagnostics, and the status has been set, the device shall clear BSY to zero, assert PDIAG-, and make a transition to the DI2: Device_idle_NS state (see Figure 21). Transition D1SR2b:DI2: When hardware initialization, self-diagnostic testing is completed, the device failed the diagnostics, and the status has been set, the device shall clear BSY to zero, negate PDIAG-, and make a transition to the DI2: Device_idle_NS state (see Figure 21). 9.3 Bus idle protocol When the selected device has BSY cleared to zero and DRQ cleared to zero the bus is idle. If command overlap is implemented and enabled, the host may be waiting for a service request for a released command. In this case, the device is preparing for the data transfer for the released command. If command overlap and command queuing are implemented and enabled, the host may be waiting for a service request for a number of released commands. In this case, the device is preparing for the data transfer for one of the released commands. Figure 19 and the text following the figure describe the host state during bus idle for hosts not implementing command overlap and queuing. Figure 20 and the text following the figure describes the additional host state during bus idle required for command overlap and queuing. Figure 21 and the text following the figure describe the device state during bus idle for devices not implementing command overlap and queuing. Figure 22 and the text following the figure describe the additional device state during bus idle required for command overlap and queuing. Page 319 T13/1410D revision 3b HI0: Host_Idle Command completed or power-on, hardware, or software reset xx:HI0 HI1: Check_Status HI2: Device_Select BSY = 0 & DRQ = 0 & wrong device selected Command to initiate HI0:HI1 HI1:HI2 Device selected HI2:HI1 Command to initiate HIO2:HI1 BSY = 1 or DRQ = 1 HI3: Write_parameters BSY = 0 & DRQ = 0 & correct device selected HI1:HI3 Parameters written HI3:HI4 HI1:HI1 HI4: Write_command Command written HI4:xx Command protocol Figure 19 − Host bus idle state diagram HI0: Host_Idle State: This state is entered when a device completes a command or when a power-on, hardware, or software reset has occurred. When in this state, the host waits for a command to be issued to a device. Transition HI0:HI1: When the host has a command to issue to a device, the host shall make a transition to the HI1: Check_Status state. HI1: Check_Status State: This state is entered when the host has a command to issue to a device. When in this state, the host reads the device Status or Alternate Status register. Transition HI1:HI2: When the status read indicates that both BSY and DRQ are cleared to zero but the wrong device is selected, then the host shall make a transition to the HI2: Device_Select state. Transition HI1:HI1: When the status read indicates that either BSY or DRQ is set to one, the host shall make a transition to the HI1: Check_Status state to recheck the status of the selected device. Transition HI1:HI3: When the status read indicates that both BSY and DRQ are cleared to zero and the correct device is selected, then the host shall make a transition to the HI3: Write_Parameters state. HI2: Device_Select State: This state is entered when the wrong device is selected for issuing a new command. When in this state, the host shall write to the Device register to select the correct device. Transition HI2:HI1: When the Device register has been written to select the correct device, then the host shall make a transition to the HI1: Check_Status state. HI3: Write_Parameters State: This state is entered when the host has determined that the correct device is selected and both BSY and DRQ are cleared to zero. When in this state, the host writes all required command parameters to the device Command Block registers (see clause 8). Page 320 T13/1410D revision 3b Transition HI3:HI4: When all required command parameters have been written to the device Command Block registers, the host shall make a transition to the HI4: Write_Command state. HI4: Write_Command State: This state is entered when the host has written all required command parameters to the device Command Block registers. When in this state, the host writes the command to the device Command register. Transition HI4:xx: When the host has written the command to the device Command register, the host shall make a transition to the command protocol for the command written as described in 9.4 through 9.11. Page 321 T13/1410D revision 3b HIO0: INTRQ_wait_A HIO1: Device_select_A Command completed & nIEN = 0 & REL = 0 & SERV = 0 xx:HIO0 Select device HIO0:HIO1 Bus released, REL=1 & nIEN = 0 xx:HIO0 New command to initiate HIO0:HIO2 INTRQ asserted HIO0:HIO3 Device selected HIO1:HIO0 Bus released, REL=1 & nIEN = 1 xx:HIO3 nIEN = 1 HIO2:HI1 Check_ status HIO4: Device_select_B HIO3: Check_status_A Command completed & nIEN = 1 & REL = 0 Select device & SERV = 0 HIO3:HIO4 xx:HIO3 HIO2: Disable_INTRQ Device selected HIO4:HIO3 SERV =0 HIO3:HIO3 New command to initiate HIO3:HIO2 SERV = 1 HIO3:HIO5 HIO5: Write_SERVICE Command completed & SERV = 1 xx:HIO5 HIO6: INTRQ_wait_B Service INTRQ enabled HIO5:HIO6 >1 outstanding command HIO7: Check_status_B >1 outstanding command HIO6:HIO7 1 outstanding command HIO6:HP0 Service HIO6:HPD0 return HIO6:HDMAQ0 Tag checked HIO7:HP0 HIO7:HPD0 HIO7:HDMAQ0 Service return HIO5:HIO7 1 outstanding command & no service INTRQ HIO5:HP0 HIO5:HPD0 HIO5:HDMAQ0 Service return Figure 20 − Additional Host bus Idle state diagram with Overlap or overlap and queuing HIO0: INTRQ_wait_A State: This state is entered when a command has completed with nIEN cleared to zero, REL set to one, and SERV cleared to zero. This state is entered when the device has released the bus with nIEN cleared to zero. This state is entered when the host is waiting for INTRQ to be asserted for bus released commands. When in this state, the host waits for INTRQ to be asserted indicating that a device is ready to resume execution of a bus released command. Transition HIO0:HIO1: When the host has one or more commands outstanding to both devices, the host may make a transition to the HIO1: Device_select_A state to sample INTRQ for the other device. Page 322 T13/1410D revision 3b Transition HIO0:HIO2: When the host has a new command to issue to a device and that device has no command released or supports command queuing, then the host shall make a transition to the HIO2: Disable_INTRQ state. Transition HIO0:HIO3: When the host detects INTRQ asserted, the host shall make a transition to the HIO3: Check_status A state. HIO1: Device_select_A State: This state is entered when the host has outstanding, bus released commands to both devices and nIEN is cleared to zero. When in this state, the host shall disable INTRQ by setting nIEN to one, shall write the Device register to select the other device, and then, shall enable INTRQ by clearing nIEN to zero. Transition HIO1:HIO0: Having selected the other device, the host shall make a transition to the HIO0: INTRQ_wait_A state. HIO2: Disable_INTRQ State: This state is entered when the host has a new command to issue to a device and that device has no outstanding, bus released command or supports command queuing. When in this state, the host shall set nIEN to one. nIEN is set to one to prevent a race condition if the host has to select the other device to issue the command. Transition HIO2:HI1: When nIEN has been set to one, the host shall make a transition to the HI1: Check_status state (see Figure 19). HIO3: Check_status_A State: This state is entered when a command is completed with nIEN set to one, REL set to one, and SERV cleared to zero. This state is entered when the device has released the bus and nIEN is set to one. This state is entered when an interrupt has occured indicating that a device is requesting service. When in this state, the host shall read the Status register of the device requesting service. Transition HIO3:HIO4: If SERV is cleared to zero and the host has released commands outstanding to both devices, then the host may make a transition to the HIO4: Device_select_B state. Transition HIO3:HIO2: If SERV is cleared to zero and the host has a new command to issue to a device, then the host shall make a transition to the HIO2: Disable_INTRQ state. Transition HIO3:HIO3: If SERV is cleared to zero and the host has no new command to issue, then the host shall make a transition to the HIO3: Check_status state. Transition HIO3:HIO5: If SERV is set to one, the host shall make a transition to the HIO5: Write_SERVICE state. HIO4: Device_select_B State: This state is entered when the host has outstanding, bus released commands to both devices and nIEN is set to one. When in this state, the host shall disable INTRQ by setting nIEN to one, shall write the Device register to select the other device, and then, shall enable INTRQ by clearing nIEN to zero. Transition HIO4:HIO3: Having selected the other device, the host shall make a transition to the HIO3: Check_status_A state. Page 323 T13/1410D revision 3b HIO5: Write_SERVICE State: This state is entered when a device has set SERV to one indicating that the device requests service. This state is entered when a command has completed with SERV set to one. When in this state, the host shall write the SERVICE command to the Command register. Transition HIO5:HIO6: When the device is one that implements the PACKET command feature set and the Service interrupt is enabled, then the host shall make a transition to the HIO6: INTRQ_wait_B state. Transition HIO5:HIO7: When the host has more than one released command outstanding to the device and the Service interrupt is disabled, the host shall make a transition to the HIO7: Check_status_B state. Transition HIO5:xx: When the Service interrupt is disabled and the host has only one released command outstanding to the device, the host shall make a transition to the service return for the protocol for the command outstanding (see Figure 31, Figure 33, or Figure 35). HIO6: INTRQ_wait_B State: This state is entered when the SERVICE command has been written to a device implementing the PACKET command feature set and the Service interrupt is enabled. NOTE − READ DMA QUEUED and WRITE DMA QUEUED commands do not implement the Service interrupt. When in this state, the host waits for the assertion of INTRQ. Transition HIO6:HIO7: When the host has more than one released command outstanding to the device and INTRQ is asserted, the host shall make a transition to the HIO7: Check_status_B state. Transition HIO6:xx: When INTRQ has been asserted and the host has only one released command outstanding to the device, then the host shall make a transition to the service return for the protocol for the command outstanding (see Figure 31, Figure 33, or Figure 35). HIO7: Check_status_B State: This state is entered when the SERVICE command has been written and the host has more than one released command outstanding to the device. When in this state the host reads the command tag to determine which outstanding command service is requested for. If a DMA data transfer is required for the command, the host shall set up the DMA engine. Transition HIO7:xx: When the command for which service is requested has been determined, the host shall make a transition to the service return for that command protocol (see Figure 31, Figure 33, or Figure 35). Page 324 T13/1410D revision 3b DI0: Device_Idle_SI INTRQ=A Command completed & nIEN=0 & interrupt pending xx:DI0 Device/Head register written & device selected DI0:DI0 Command written DI0:xx Command protocol Device/Head register written & device deselected DI0:DI2 Device/Head register written & device selected, nIEN=0 & interrupt pending DI2:DI0 Status register read or nIEN set to one DI0:DI1 Power-on, hardware, or software reset if Device 1 xx:DI2 DI1: Device_Idle_S INTRQ=N Power-on, hardware, or software reset if Device 0 xx:DI1 Command completed & (no interrupt pending or nIEN=1) xx:DI1 BSY 0 DRQ 0 REL 0 DI2: Device_Idle_NS INTRQ=R Device/Head register written & device deselected DI1:DI2 Device/Head register written & device selected & (no interrupt pending or nIEN=1) DI2:DI1 Command written DI1:xx Command protocol Device/Head register written & device selected DI1:DI1 SERV 0 C/D 0 I/O 0 INTRQ V DMARQ R PDIAGR DASPR Figure 21 − Device bus Idle state diagram DI0: Device_Idle_SI State (selected/INTRQ asserted): This state is entered when the device has completed the execution of a command protocol with interrupt pending and nIEN=0. When in this state, the device shall have DRQ cleared to zero, INTRQ asserted, and BSY cleared to zero. Reading any register except the Status register shall have no effect. Transition DI0:xx: If the Command register is written, the device shall clear the device internal interrupt pending, shall negate or release INTRQ within 400 ns of the negation of DIOW-, shall release PDIAG- and DSAP- if asserted, and shall make a transition to the command protocol indicated by the content of the Command register. The host should not write to the Command register at this time. Transition DI0:DI1: When the Status register is read, the device shall clear the device internal interrupt pending, negate or release INTRQ within 400 ns of the negation of DIOR-, and make a transition to the DI1: Device_Idle_S state. When nIEN is set to one in the Device Control register, the device shall negate INTRQ and make a transition to the DI1: Device_Idle_S state. Page 325 T13/1410D revision 3b Transition DI0:DI0: When the Device register is written and the DEV bit selects this device or any other register except the Command register is written, the device shall make a transition to the DI0: Device_Idle_SI state. Transition DI0:DI2: When the Device register is written and the DEV bit selects the other device, then the device shall release INTRQ within 400 ns of the negation of DIOW-, and make a transition to the DI2: Device_Idle_NS state. DI1: Device_Idle_S State (selected/INTRQ negated): This state is entered when the device has completed the execution of a command protocol with no interrupt pending or nIEN=1, or when a pending interrupt is cleared. This state is also entered by Device 0 at the completion of a power-on, hardware, or software reset. When in this state, the device shall have BSY and DRQ cleared to zero and INTRQ negated or released. When entering this state from a power-on, hardware, or software reset, if the device does not implement the PACKET command feature set, the device shall set DRDY to one within 30 s of entering this state. When entering this state from a power-on, hardware, or software reset, if the device does implement the PACKET command feature set, the device shall not set DRDY to one. Transition DI1:xx: When the Command register is written, the device shall exit the interrupt pending state, release PDIAG- if asserted and make a transition to the command protocol indicated by the content of the Command register. Transition DI1:DI1: When the Device register is written and the DEV bit selects this device or any register is written except the Command register, the device shall make a transition to the DI1: Device_Idle_S state. Transition DI1:DI2: When the Device register is written and the DEV bit selects the other device, the device shall make a transition to the DI2: Device_Idle_NS state. DI2: Device_Idle_NS State (not selected): This state is entered when the device is deselected. This state is also entered by Device 1 at the completion of a power-on, hardware, or software reset. When in this state, the device shall have BSY and DRQ cleared to zero and INTRQ shall be released. When entering this state from a power-on, hardware, or software reset, if the device does not implement the PACKET command feature set, the device shall set DRDY to one within 30 s of entering this state and shall release DASP- and PDIAG- with 31 s of entering this state. When entering this state from a power-on, hardware, or software reset, if the device does implement the PACKET command feature set, the device shall not set DRDY to one. Transition DI2:DI0: When the Device register is written, the DEV bit selects this device, the device has an interrupt pending, and nIEN is cleared to zero, then the device shall assert INTRQ within 400 ns of the negation of DIOW- and make a transition to the DI0: Device_Idle_SI state. Transition DI2:DI1: When the Device register is written, the DEV bit selects this device, and the device has no interrupt pending or nIEN is set to one, then the device shall make a transition to the DI1: Device_Idle_S state. Page 326 T13/1410D revision 3b DIO0: Device_Idle_SIR INTRQ=A,REL=1, SERV=0 DIO4: Device_Idle_NS INTRQ=R, REL=x, SERV=x Command completed & Command written interrupt pending & nIEN=0 Command protocol DIO0:xx & REL=0 & SERV=0 Device deselected xx:DIO0 DIO0:DIO4 Bus released & interrupt pending & nIEN=0 & REL=1 & SERV=0 Status register read xx:DIO0 Service required DIO0:DIO2 Device selected DIO4:DIO0 DIO1: Device_Idle_SR INTRQ=N,REL=1, SERV=0 DIO0:DIO1 Command completed & (no interrupt pending or nIEN=1) & REL=0 & SERV=0 xx:DIO1 Bus released & (no interrupt pending or nIEN=1) & REL=1 & SERV=0 xx:DIO1 Command written DIO1:xx Cmnd protocol Device deselected DIO1:DIO4 Device selected DIO4:DIO1 Service required & nIEN=0 DIO1:DIO2 Service required & nIEN=1 DIO1:DIO3 DIO3: Device_Idle_SS INTRQ=N, REL=1, SERV=1 Command completed & (no interrupt pending or nIEN=1) & REL=0 & SERV=1 xx:DIO3 DIO2: Device_Idle_SIS INTRQ=A, REL=1, SERV=1 Bus released & (no interrupt pending or nIEN=1) & REL=1 & SERV=1 xx:DIO3 Status register read DIO2:DIO3 Command completed & interrupt pending & nIEN=0 & REL=0 & SERV=1 SERVICE written DIO2:DP0 DIO2:DPD0 DIO2:DDMAQ0 Command written DIO2:xx xx:DIO2 Bus released & interrupt pending & nIEN=0 & REL=1 & SERV=1 DRQ 0 Device selected DIO4:DIO3 SERVICE written DIO3:DP0 DIO3:DPD0 DIO3:DDMAQ0 Service return Command written DIO3:xx Cmnd protocol Service return Command protocol Device deselected DIO2:DIO4 Device selected DIO4:DIO2 xx:DIO2 BSY 0 Device deselected DIO3:DIO4 REL v SERV v C/D x I/O x INTRQ V DMARQ R PDIAGR DASPR Figure 22 − Additional Device bus Idle state diagram with Overlap or overlap and queuing Page 327 T13/1410D revision 3b DIO0: Device_Idle_SIR State (selected/INTRQ asserted/RELset to one): This state is entered when the device has completed the execution of a command protocol with interrupt pending, nIEN=0, REL set to one, and SERV cleared to zero. This state is entered when the device has released an overlapped command with interrupt pending, nIEN=0, REL set to one, and SERV cleared to zero. When in this state, the device is preparing for completion of a released command. The device shall have BSY and DRQ cleared to zero, and INTRQ asserted. Transition DIO0:xx: When the Command register is written, the device shall clear the interrupt pending, shall negate or release INTRQ within 400 ns of the negation of DIOW-, and shall make a transition to the command protocol indicated by the content of the Command register. NOTE − Since a queue exists, only commands in the queued command set may be written to the Command register. If any other command is written to the Command register, the queue is aborted and command aborted is returned for the command (see 6.9). Transition DIO0:DIO1: When the Status register is read, the device shall clear the interrupt pending, negate or release INTRQ within 400 ns of the negation of DIOR-, and make a transition to the DIO1: Device_Idle_SR state. Transition DIO0:DIO2: When the Device register is written and the DEV bit selects the other device, then the device shall release INTRQ within 400 ns of the negation of DIOW- and make a transition to the DIO2: Device_Idle_NS state. Transition DIO0:DIO2: When the device is ready to continue the execution of a released command, the device shall make a transition to the DIO2: Device_idle_SIS state. DIO1: Device_Idle_SR State (selected/INTRQ negated/REL set to one): This state is entered when the device has completed the execution of a command protocol with no interrupt pending or nIEN=1, REL set to one, and SERV cleared to zero. This state is entered when the device has released an overlapped command with no interrupt pending or nIEN=1, REL set to one, and SERV cleared to zero. This state is entered when a pending interrupt is cleared, REL is set to one, and SERV is cleared to zero. When in this state, the device is preparing for completion of a released command. The device shall have BSY and DRQ cleared to zero, and INTRQ negated or released. Transition DIO1:xx: When the Command register is written, the device shall make a transition to the command protocol indicated by the content of the Command register. NOTE − Since a queue exists, only commands in the queued command set may be written to the Command register. If any other command is written to the Command register, the queue is aborted and command aborted is returned for the command (see 6.9). Transition DIO1:DIO4: When the Device register is written and the DEV bit selects the other device, the device shall make a transition to the DIO4: Device_Idle_NS state. Transition DIO1:DIO2: When the device is ready to continue the execution of a released command and nIEN=0, the device shall make a transition to the DIO2: Device_idle_SIS state. Transition DIO1:DIO3: When the device is ready to continue the execution of a released command and nIEN=1, the device shall make a transition to the DIO3: Device_idle_SS state. DIO2: Device_Idle_SIS State (selected/INTRQ asserted/SERV set to one): This state is entered when the device has completed the execution of a command protocol with interrupt pending, nIEN=0, Page 328 T13/1410D revision 3b REL set to one, and SERV set to one. This state is entered when the device has released an overlapped with interrupt pending, nIEN=0, REL set to one, and SERV set to one. Transition DIO2:DIO3: When the Status register is read, the device shall clear the interrupt pending, negate or release INTRQ within 400 ns of the negation of DIOR-, and make a transition to the DIO3: Device_Idle_SS state. Transition DIO2: DIO4: When the Device register is written and the DEV bit selects the other device, the device shall release INTRQ within 400 ns of the negation of DIOW- and make a transition to the DIO4: Device_Idle_NS state. Transition DIO2:DP0/DPD0/DDMAQ0: When the SERVICE command is written into the Command register, the device shall set the Tag for the command to be serviced, negate or release INTRQ within 400 ns of the negation of DIOW-, and make a transition to the Service return of the command ready for service (see Figure 32 Device PACKET non-data and PIO data command protocol, Figure 34 Device PACKET DMA command protocol, or Figure 36 Device DMA QUEUED command protocol). Transition DIO2:xx: When any overlapped command other than SERVICE is written to the Command register, the device shall negate or release INTRQ within 400 ns of the negation of DIOW- and make a transition to the protocol for the new command. DIO3: Device_Idle_SS State (selected/INTRQ negated/SERV set to one): This state is entered when the device has completed the execution of a command protocol with no interrupt pending or nIEN=1, REL set to one, and SERV set to one. This state is entered when the device has released an overlapped with no interrupt pending or nIEN=1, REL set to one, and SERV set to one. Transition DIO3: DIO4: When the Device register is written and the DEV bit selects the other device, the device shall make a transition to the DIO4: Device_Idle_NS state. Transition DIO3:DP0/DPD0/DDMAQ0: When the SERVICE command is written into the Command register, the device shall set the Tag for the command to be serviced and make a transition to the Service return of the command ready for service (see Figure 32, Figure 34, or Figure 36). Transition DIO3:xx: When any overlapped command other than SERVICE is written to the Command register, the device shall make a transition to the protocol for the new command. DIO4: Device_Idle_NS State (not selected): This state is entered when the device is deselected with REL or SERV set to one. When in this state, the device shall have BSY and DRQ cleared to zero and INTRQ shall be released. Transition DIO4:DIO0: When the Device register is written, the DEV bit selects this device, the device has an interrupt pending, nIEN is cleared to zero, REL is set to one, and SERV is cleared to zero, then the device shall assert INTRQ within 400 ns of the negation of DIOW- and make a transition to the DIO0: Device_Idle_SIR state. Transition DIO4:DIO1: When the Device register is written, the DEV bit selects this device, the device has no interrupt pending or nIEN is set to one, REL is set to one, and SERV is cleared to zero, then the device shall make a transition to the DIO1: Device_Idle_SIR state. Transition DIO4:DIO2: When the Device register is written, the DEV bit selects this device, the device has an interrupt pending, nIEN is cleared to zero, REL is set to one, and SERV is set to one, then the device shall assert INTRQ within 400 ns of the negation of DIOW- and make a transition to the DIO2: Device_Idle_SIS state. Page 329 T13/1410D revision 3b Transition DIO4:DIO3: When the Device register is written, the DEV bit selects this device, the device has no interrupt pending or nIEN is set to one, REL is set to one, and SERV is set to one, then the device shall make a transition to the DIO3: Device_Idle_SIR state. 9.4 Non-data command protocol This class includes: − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − CFA ERASE SECTORS CFA REQUEST EXTENDED ERROR CODE CHECK MEDIA CARD TYPE CHECK POWER MODE DEVICE CONFIGURATION FREEZE LOCK DEVICE CONFIGURATION RESTORE FLUSH CACHE FLUSH CACHE EXT GET MEDIA STATUS IDLE IDLE IMMEDIATE MEDIA EJECT MEDIA LOCK MEDIA UNLOCK NOP READ NATIVE MAX ADDRESS READ NATIVE MAX ADDRESS EXT READ VERIFY SECTOR(S) READ VERIFY SECTOR(S) EXT SECURITY ERASE PREPARE SECURITY FREEZE LOCK SEEK SET FEATURES SET MAX ADDRESS SET MAX ADDRESS EXT SET MULTIPLE MODE SLEEP SMART DISABLE OPERATION SMART ENABLE/DISABLE AUTOSAVE SMART ENABLE OPERATIONS SMART EXECUTE OFFLINE IMMEDIATE SMART RETURN STATUS STANDBY STANDBY IMMEDIATE Execution of these commands involves no data transfer. Figure 23 and the text following the figure describes the host state. Figure 24 and the text following the figure decribes the device state. See the NOP command description in 8.22 and the SLEEP command in 8.50 for additional protocol requirements. Page 330 T13/1410D revision 3b HND0: INTRQ_wait HND1: Check_Status INTRQ asserted Command written & nIEN = 0 BSY = 0 HND1:HI0 HND0:HND1 HI4:HND0 Host_Idle BSY =1 HND1:HND1 Command written & nIEN = 1 HI4:HND1 Figure 23 − Host Non-Data state diagram HND0: INTRQ_Wait_State: This state is entered when the host has written a non-data command to the device and the nIEN bit in the device has been cleared to zero. When in this state the host may wait for INTRQ to be asserted by the device. Transition HND0:HND1: When the device asserts INTRQ, the host shall make a transition to the HND1: Check_Status state. HND1: Check_Status State: This state is entered when the host has written a non-data command to the device and the nIEN bit in the device has been set to one, or when INTRQ has been asserted. When in this state, the host shall read the device Status register. When entering this state from another state other than when an interrupt has occurred, the host shall wait 400 ns before reading the Status register. Transition HND1:HI0: When the status read indicates that BSY is cleared to zero, the host shall make a transition to the HI0: Host_Idle state (see Figure 19). If status indicates that an error has occured, the host shall take appropriate error recovery action. Transition HND1:HND1: When the status read indicates that BSY is set to one, the host shall make a transition to the HND1: Check_Status state to recheck device status. DND0: Command_Execution Execution complete & nIEN = 0 Non-data command written DND0:DI0 Device_idle_SI BSY=0, INTRQ=A DI0:DND0 DI1:DND0 Execution complete & nIEN = 1 DND0:DI1 BSY=0 BSY 1 DRQ 0 REL 0 SERV 0 C/D 0 Device_idle_S I/O 0 INTRQ R DMARQ R PDIAGR DASPR Figure 24 − Device Non-Data state diagram DND0: Command_Execution State: This state is entered when a non-data command has been written to the device Command register. Page 331 T13/1410D revision 3b When in this state, the device shall set BSY to one within 400 ns of the writing of the Command register, shall execute the requested command, and shall set the interrupt pending. Transition DND0:DI0: When command execution completes and nIEN is cleared to zero, then the device shall set error bits if appropriate, clear BSY to zero, assert INTRQ, and make a transition to the DI0: Device_Idle_SI state (see Figure 21). Transition DND0:DI1: When command execution completes and nIEN is set to one, the device shall set error bits if appropriate, clear BSY to zero, and make a transition to the DI1: Device_Idle_S state (see Figure 21). 9.5 PIO data-in command protocol This class includes: − − − − − − − − − − − − CFA TRANSLATE SECTOR DEVICE CONFIGURATION IDENTIFY IDENTIFY DEVICE IDENTIFY PACKET DEVICE READ BUFFER READ LOG EXT READ MULTIPLE READ MULTIPLE EXT READ SECTOR(S) READ SECTOR(S) EXT SMART READ DATA SMART READ LOG Execution of this class of command includes the transfer of one or more blocks of data from the device to the host. Figure 25 and the text following the figure describes the host states. Figure 26 and the text following the figure describes the device states. Page 332 T13/1410D revision 3b HPIOI0: INTRQ_wait PIO data in command written & selected device & nIEN = 0 HI4:HPIOI0 HPIOI1: Check_Status INTRQ asserted BSY = 0 & DRQ = 0 HPIOI0:HPIOI1 HPIOI1:HI0 PIO data in command written & selected device & nIEN = 1 Host_idle BSY = 1 HPIOI1:HPIOI1 HI4:HPIOI1 HPIOI2: Transfer_Data Data register read & DRQ data block transferred & all data for command not transferred & nIEN = 0 HPIOI2:HPIOI0 BSY = 0 & DRQ = 1 HPIOI1:HPIOI2 Data register read & DRQ data block transferred & all data for command not transferred & nIEN = 1 HPIOI2:HPIOI1 Data register read & DRQ data block transfer not complete HPIOI2:HPIOI2 Data register read & all data for command transferred HPIOI2:HI0 Host_idle Figure 25 − Host PIO data-In state diagram HPIOI0: INTRQ_Wait State: This state is entered when the host has written a PIO data-in command to the device and nIEN is cleared to zero, or at the completion of a DRQ data block transfer if all the data for the command has not been transferred and nIEN is cleared to zero. When in this state, the host shall wait for INTRQ to be asserted. Transition HPIOI0:HPIOI1: When INTRQ is asserted, the host shall make a transition to the HPIOI1: Check_Status state. HPIOI1: Check_Status State: This state is entered when the host has written a PIO data-in command to the device and nIEN is set to one, or when INTRQ is asserted. When in this state, the host shall read the device Status register. When entering this state from the HI4 state, the host shall wait 400 ns before reading the Status register. When entering this state from the HPIOI2 state, the host shall wait one PIO transfer cycle time before reading the Status register. The wait may be accomplished by reading the Alternate Status register and ignoring the result. Transition HPIOI1:HI0: When BSY is cleared to zero and DRQ is cleared to zero, then the device has completed the command with an error. The host shall perform appropriate error recovery and make a transition to the HI0: Host_Idle state (see Figure 19). Transition HPIOI1:HPIOI1: When BSY is set to one , the host shall make a transition to the HPIOI1: Check_Status state. Page 333 T13/1410D revision 3b Transition HPIOI1:HPIOI2: When BSY is cleared to zero and DRQ is set to one, the host shall make a transition to the HPIOI2: Transfer_Data state. HPIOI2: Transfer_Data State: This state is entered when the BSY is cleared to zero, DRQ is set to one, and the DRQ data block transfer has not completed. When in this state, the host shall read the device Data register to transfer data. Transition HPIOI2:HPIOI0: When the host has read the device Data register and the DRQ data block has been transferred, all blocks for the command have not been transferred, and nIEN is cleared to zero, then the host shall make a transition to the HPIOI0: INTRQ_Wait state. Transition HPIOI2:HPIOI1: When the host has read the device Data register and the DRQ data block has been transferred, all blocks for the command have not been transferred, and nIEN is set to one, then the host shall make a transition to the HPIOI1: Check_Status state. Transition HPIOI2:HPIOI2: When the host has read the device status register and the DRQ data block transfer has not completed, then the host shall make a transition to the HPIOI2: Transfer_Data state. Transition HPIOI2:HI0: When the host has read the device Data register and all blocks for the command have been transferred, then the host shall make a transition to the HI0: Host_Idle state (see Figure 19). The host may read the Status register. Page 334 T13/1410D revision 3b DPIOI0: Prepare_Data BSY=1, DRQ=0, INTRQ=N Command execution aborted with error & nIEN=0 DPIOI0:DI0 BSY=0, INTRQ=A PIO data in command written DI0:DPIOI0 DI1:DPIOI0 Command execution aborted with error & nIEN=1 DPIOI0:DI1 BSY=0 Device_idle_SI Device_idle_S DPIOI2: Data_Rdy_INTRQ BSY=0, DRQ=1, INTRQ=A Data ready to transfer & nIEN=0 DPIOI0:DPIOI2 Data ready to transfer & nIEN=1 DPIOI0:DPIOI1 DPIOI1: Transfer_Data BSY=0, DRQ=1, INTRQ=N Data register read & DRQ data block transferred & all data for command not transferred Status register read DPIOI2:DPIOI1 Data register read & DRQ data block transfer not complete DPIOI1:DPIOI1 DPIOI1:DPIOI0 Data register read & all data for command transferred DPIOI1:DI1 BSY=0 BSY v DRQ v REL 0 SERV 0 C/D 0 I/O 0 INTRQ V DMARQ R Device_idle_S PDIAGR DASPR Figure 26 − Device PIO data-In state diagram DPIOI0: Prepare_Data State: This state is entered when the device has a PIO data-in command written to the Command register. When in this state, device shall set BSY to one within 400 ns of the writing of the Command register and prepare the requested data for transfer to the host. For IDENTIFY DEVICE and IDENTIFY PACKET DEVICE commands, if the device tests CBLID- it shall do so and update bit 13 in word 93. Transition DPIOI0:DI0: When an error is detected that causes the command to abort and nIEN is cleared to zero, then the device shall set the appropriate error bits, clear BSY to zero, assert INTRQ, and make a transition to the DI0: Device_Idle_SI state (see Figure 21). Transition DPIOI0:DI1: When an error is detected that causes the command to abort and nIEN is set to one, then the device shall set the appropriate error bits, clear BSY to zero, and make a transition to the DI1: Device_Idle_S state (see Figure 21). Transition DPIOI0:DPIOI1: When the device has a DRQ data block ready to transfer and nIEN is set to one, then the device shall make a transition to the DPIOI1: Transfer_Data state. Page 335 T13/1410D revision 3b Transition DPIOI0:DPIOI2: When the device has a DRQ data block ready to transfer and nIEN is cleared to zero, then the device shall make a transition to the DPIOI2: Data_Ready_INTRQ state. DPIOI1: Data_Transfer State: This state is entered when the device is ready to transfer a DRQ data block and nIEN is set to one, or when the INTRQ indicating that the device is ready to transfer a DRQ data block has been acknowleged by a read of the Status register. When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is negated, and the device has a data word ready in the Data register for transfer to the host. Transition DPIOI1:DPIOI1: When the Data register is read and transfer of the DRQ data block has not completed, then the device shall make a transition to the DPIOI1: Data_Transfer state. Transition DPIOI1:DPIOI0: When the Data register is read and the transfer of the current DRQ data block has completed, but all blocks for this request have not been transferred, then the device shall make a transition to the DPIOI0: Prepare_Data state. Transition DPIOI1:DI1: When the Data register is read and all blocks for this request have been transferred, then the device shall clear BSY to zero and make a transition to the DI1: Device_Idle_S state (see Figure 21). The interrupt pending is not set on this transition. DPIOI2: Data_Ready_INTRQ State: This state is entered when the device has a DRQ data block ready to transfer and nIEN is cleared to zero. When in this state, BSY is cleared to zero, DRQ is set to one, and INTRQ is asserted. Transition DPIOI2:DPIOI1: When the Status register is read, then the device shall clear the interrupt pending, negate INTRQ, and make a transition to the DPIOI1: Data_Transfer state. 9.6 PIO data-out command protocol This class includes: − − − − − − − − − − − − − − − CFA WRITE MULTIPLE WITHOUT ERASE CFA WRITE SECTORS WITHOUT ERASE DEVICE CONFIGURATION SET DOWNLOAD MICROCODE SECURITY DISABLE PASSWORD SECURITY ERASE UNIT SECURITY SET PASSWORD SECUITY UNLOCK SMART WRITE LOG WRITE BUFFER WRITE LOG EXT WRITE MULTIPLE WRITE MULTIPLE EXT WRITE SECTOR(S) WRITE SECTOR(S) EXT Execution of this class of command includes the transfer of one or more blocks of data from the host to the device. Figure 27 and the text following the figure describes the host states. Figure 28 and the text following the figure describes the device states. Page 336 T13/1410D revision 3b HPIOO0: Check_Status PIO data out command written HI4:HPIOO0 BSY = 0 & DRQ = 0 HPIOO0:HI0 Host_idle BSY = 1 HPIOO0:HPIOO0 HPIOO2: INTRQ_wait INTRQ asserted HPIOO2:HPIOO0 BSY = 0 & DRQ = 1 HPIOO0:HPIOO1 HPIOO1: Transfer_Data Data register written & DRQ data block transferred & nIEN = 1 HPIOO1:HPIOO0 Data register written & DRQ data block transferred & nIEN = 0 HPIOO1:HPIOO2 Data register written & DRQ data block transfer not complete HPIOO1:HPIOO1 Figure 27 − Host PIO data-Out state diagram HPIOO0: Check_Status State: This state is entered when the host has written a PIO data-out command to the device; when a DRQ data block has been written and nIEN is set to one; or when a DRQ data block has been written, nIEN is cleared zero, and INTRQ has been asserted. When in this state, the host shall read the device Status register. When entering this state from the HI4 state, the host shall wait 400 ns before reading the Status register. When entering this state from the HPIOO1 state, the host shall wait one PIO transfer cycle time before reading the Status register. The wait may be accomplished by reading the Alternate Status register and ignoring the result. Transition HPIOO0:HI0: When BSY is cleared to zero and DRQ is cleared to zero, then the device has completed the command and shall make a transition to the HI0: Host_Idle state (see Figure 19). If an error is reported, the host shall perform appropriate error recovery. Transition HPIOO0:HPIOO0: When BSY is set to one and DRQ is cleared to zero, the host shall make a transition to the HPIOO0: Check_Status state. Transition HPIOO0:HPIOO1: When BSY is cleared to zero and DRQ is set to one, the host shall make a transition to the HPIOO1: Transfer_Data state. HPIOO1: Transfer_Data State: This state is entered when the BSY is cleared to zero, DRQ is set to one. When in this state, the host shall write the device Data register to transfer data. Page 337 T13/1410D revision 3b Transition HPIOO1:HPIOO2: When the host has written the device Data register, the DRQ data block has been transferred, and nIEN is cleared to zero, then the host shall make a transition to the HPIOO2: INTRQ_Wait state. Transition HPIOO1:HPIOO0: When the host has written the device Data register, the DRQ data block has been transferred, and nIEN is set to one, then the host shall make a transition to the HPIOO0: Check_Status state. Transition HPIOO1:HPIOO1: When the host has written the device Data register and the DRQ data block transfer has not completed, then the host shall make a transition to the HPIOO1: Transfer_Data state. HPIOO2: INTRQ_Wait State: This state is entered when the host has completed a DRQ data block transfer and nIEN is cleared to zero. When in this state, the host shall wait for INTRQ to be asserted. Transition HPIOO2:HPIOO0: When INTRQ is asserted, the host shall make a transition to the HPIOO0: Check_Status state. Page 338 T13/1410D revision 3b DPIOO0: Prepare BSY=1, DRQ=0, INTRQ=N PIO data out command written DI0:DPIOO0 DI1:DPIOO0 Error or all data for command transferred & nIEN = 0 DPIOO0:DI0 BSY=0, INTRQ=A Device_idle_SI Error or all data for command transferred & nIEN = 1 DPIOO0:DI1 BSY=0 Device_idle_S DPIOO2: Ready_INTRQ BSY=0, DRQ=1, INTRQ=A Ready to receive susequent DRQ data block & nIEN=0 DPIOO0:DPIOO2 Ready to receive susequent DRQ data block & nIEN=1 DPIOO0b:DPIOO1 Ready to receive first DRQ data block DPIOO0a:DPIOO1 DPIOO1: Transfer_Data BSY=0, DRQ=1, INTRQ=N Data register written & DRQ data block transferred DPIOO1:DPIOO0 BSY v DRQ v REL 0 Status register read DPIOO2:DPIOO1 Data register written & DRQ data block transfer not complete DPIOO1:DPIOO1 SERV 0 C/D 0 I/O 0 INTRQ V DMARQ R PDIAGR DASPR Figure 28 − Device PIO data-Out state diagram DPIOO0: Prepare State: This state is entered when the device has a PIO data-out command written to the Command register or when a DRQ data block has been transferred. When in this state, device shall set BSY to one within 400 ns of the writing of the Command register, shall clear DRQ to zero, and negate INTRQ. The device shall check for errors, determine if the data transfer is complete, and if not, prepare to receive the next DRQ data block. Transition DPIOO0a:DPIOO1: When the device is ready to receive the first DRQ data block for a command, the device shall make a transition to the DPIOO1: Transfer_Data state. Transition DPIOO0b:DPIOO1: When the device is ready to receive a subsequent DRQ data block for a command and nIEN is set to one, then the device shall set the interrupt pending and make a transition to the DPIOO1: Transfer_Data state. Page 339 T13/1410D revision 3b Transition DPIOO0:DPIOO2: When the device is ready to receive a subsequent DRQ data block for a command and nIEN is cleared to zero, then the device shall set the interrupt pending and make a transition to the DPIOO2: Ready_INTRQ state. Transition DPIOO0:DI0: When all data for the command has been transferred or an error occurs that causes the command to abort, and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, clear BSY to zero, assert INTRQ, and make a transition to the DI0: Device_Idle_SI state (see Figure 21). Transition DPIOO0:DI1: When all data for the command has been transferred or an error occurs that causes the command to abort, and nIEN is set to one, then the device shall set the interrupt pending, set appropriate error bits, clear BSY to zero, and make a transition to the DI1: Device_Idle_S state (see Figure 21). DPIOO1: Data_Transfer State: This state is entered when the device is ready to receive a DRQ data block. When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is negated, and the device recieves a data word in the Data register. Transition DPIOO1:DPIOO1: When the Data register is written and transfer of the DRQ data block has not completed, then the device shall make a transition to the DPIOO1: Data_Transfer state. Transition DPIOO1:DPIOO0: When the Data register is written and the transfer of the current DRQ data block has completed, then the device shall make a transition to the DPIOO0: Prepare state. DPIOO2: Ready_INTRQ State: This state is entered when the device is ready to receive a DRQ data block and nIEN is cleared to zero. When in this state, BSY is cleared to zero, DRQ is set to one, and INTRQ is asserted. Transition DPIOO2:DPIOO1: When the Status register is read, the device shall clear the interrupt pending, negate INTRQ, and make a transition to the DPIOO1: Data_Transfer state. 9.7 DMA command protocol This class includes: − − − − READ DMA READ DMA EXT WRITE DMA WRITE DMA EXT Execution of this class of command includes the transfer of one or more blocks of data from the host to the device or from the device to the host using DMA transfer. The host shall initialize the DMA channel prior to transferring data. A single interrupt is issued at the completion of the successful transfer of all data required by the command or when the transfer is aborted due to an error. Figure 29 and the text following the figure describes the host states. Figure 30 and the text following the figure describes the device states. Page 340 T13/1410D revision 3b HDMA0: Check_Status DMA command written BSY = 0 & DRQ = 0 HDMA0:HI0 HI4:HDMA0 Host_Idle BSY = 1 & DMARQ negated HDMA0:HDMA0 HDMA2: INTRQ_wait INTRQ asserted HDMA2:HDMA0 ( BSY = 0 & DRQ = 1 & DMARQ asserted) or (BSY = 1 & DRQ = 0 & DMARQ asserted) HDMA0:HDMA1 HDMA1: Transfer_Data (All data for command transferred & nIEN = 1) or (DMA burst terminated & more data to transfer) HDMA1:HDMA0 All data for command transferred & nIEN = 0 HDMA1:HDMA2 Figure 29 − Host DMA state diagram HDMA0: Check_Status State: This state is entered when the host has written a DMA command to the device; when all data for the command has been transferred and nIEN is set to one; or when all data for the command has been transferred, nIEN is cleared zero, and INTRQ has been asserted. When in this state, the host shall read the device Status register. When entering this state from the HI4 state, the host shall wait 400 ns before reading the Status register. When entering this state from the HDMA1 state, the host shall wait one PIO transfer cycle time before reading the Status register. The wait may be accomplished by reading the Alternate Status register and ignoring the result. Transition HDMA0:HI0: When the BSY is cleared to zero and DRQ is cleared to zero, then the device has completed the command and shall make a transition to the HI0: Host_Idle state (see Figure 19). If an error is reported, the host shall perform appropriate error recovery. Transition HDMA0:HDMA0: When BSY is set to one, DRQ is cleared to zero, and DMARQ is negated, then the host shall make a transition to the HDMA0: Check_Status state. Transition HDMA0:HDMA1: When BSY is cleared to zero, DRQ is set to one, and DMARQ is asserted; or if BSY is set to one, DRQ is cleared to zero, and DMARQ is asserted, then the host shall make a transition to the HDMA1: Transfer_Data state. The host shall have set up the host DMA engine prior to making this transition. HDMA1: Transfer_Data State: This state is entered when BSY is cleared to zero, DRQ is set to one, and DMARQ is asserted; or BSY is set to one, DRQ is cleared to zero, and DMARQ is asserted. The host shall have initialized the DMA channel prior to entering this state. When in this state, the host shall perform the data transfer as described in the Multiword DMA timing or the Ultra DMA protocol. Transition HDMA1:HDMA2: When the host has transferred all data for the command and nIEN is cleared to zero, then the host shall make a transition to the HDMA2: INTRQ_Wait state. Page 341 T13/1410D revision 3b Transition HDMA1:HDMA0: The host shall make a transition to the HDMA0: Check_Status state when 1) the host has transferred all data for the command and nIEN is set to one, or 2) the DMA burst has been terminated and al data for the command has not been transferred. HDMA2: INTRQ_Wait State: This state is entered when the host has completed the transfer of all data for the command and nIEN is cleared to zero. When in this state, the host shall wait for INTRQ to be asserted. Transition HDMA2:HDMA0: When INTRQ is asserted, the host shall make a transition to the HDMA0: Check_Status state. DDMA0: Prepare BSY=1, DRQ=0, DMARQ=N Error caused command abort & nIEN=0 DMA command written Device_idle_SI DDMA0:DI0 DI0:DDMA0 DI1:DDMA0 BSY=0, INTRQ=A Ready to transfer data DDMA0:DDMA1 Error caused command abort & nIEN=1 DDMA0:DI1 Device_idle_S BSY=0 DDMA1: Transfer_Data BSY=0, DRQ=1, DMARQ=A, or BSY=1, DRQ=0, DMARQ=A DMA burst terminated and all data for the command not transferred DDMA1:DDMA0 Error or all data transferred & nIEN=0 DDMA1:DI0 Device_idle_SI BSY=0, INTRQ=A Error or all data transferred & nIEN=1 DDMA1:DI1 Device_idle_S BSY=0 BSY v DRQ v REL 0 SERV 0 C/D 0 I/O 0 INTRQ N DMARQ V PDIAGR DASPR Figure 30 − Device DMA state diagram DDMA0: Prepare State: This state is entered when the device has a DMA command written to the Command register. When in this state, device shall set BSY to one, shall clear DRQ to zero, and negate INTRQ. The device shall check for errors, and prepare to transfer data. Transition DDMA0:DI0: When an error is detected that causes the command to abort and nIEN is cleared to zero, the device shall set the appropriate error bits, enter the interrupt pending state, and make a transition to the DI0: Device_Idle_SI state (see Figure 21). Transition DDMA0:DI1: When an error is detected that causes the command to abort and nIEN is set to one, then the device shall set the appropriate error bits, enter the interrupt pending state, and make a transition to the DI1: Device_Idle_S state (see Figure 21). Page 342 T13/1410D revision 3b Transition DDMA0:DDMA1: When the device is ready transfer data for the command, the device shall make a transition to the DDMA1: Transfer_Data state. DDMA1: Data_Transfer State: This state is entered when the device is ready to transfer data. When in this state, BSY is cleared to zero, DRQ is set to one, and INTRQ is negated; or BSY is set to one, DRQ is cleared to zero, and INTRQ is negated. Data is transferred as decribed in Multiword DMA timing or Ultra DMA protocol. Transition DDMA1:DDMA0: When the DMA burst is terminated and all data for the command has not been transferred, the device shall make a transition to the DDMA0: Prepare state. Transition DDMA1:DI0: When the data transfer has completed or the device choses to abort the command due to an error and nIEN is cleared to zero, then the device shall set error bits if appropriate, enter the interrupt pending state, and make a transition to the DI0: Device_Idle_SI state (see Figure 21). Transition DDMA2:DI1: When the data transfer has completed or the device choses to abort the command due to an error and nIEN is set to one, then the device shall set error bits if appropriate, enter the interrupt pending state, and make a transition to the DI1: Device_Idle_S state (see Figure 21). 9.8 PACKET command protocol This class includes: − PACKET The PACKET command has a set of protocols for non-DMA data transfer commands and a set of protocols for DMA data transfer commands. Figure 31 and the text following the figure describes the host protocol for the PACKET command when non-data, PIO data-in, or PIO data-out is requested. Figure 32 and the text following the figure describes the device protocol for the PACKET command when non-data, PIO data-in, or PIO data-out is requested. Figure 33 and the text following the figure describes the host protocol for the PACKET command when DMA data transfer is requested. Figure 34 and the text following the figure describes the device protocol for the PACKET command when DMA data transfer is requested. Page 343 T13/1410D revision 3b HP0: Check_Status_A PACKET command written HI4:HP0 BSY = 1 HP0:HP0 BSY = 0 & DRQ = 1 HP0:HP1 BSY = 0 & DRQ = 0 HP0:HI0 HP2: Check_Status_B Service return HIOx:HP2 BSY = 1 HP2:HP2 HP1: Send_Packet Data register written & command packet transfer not complete HP1:HP1 Host_Idle Command packet transfer complete, nIEN=1 HP1:HP2 Command packet transfer complete, nIEN=0 HP1:HP3 HP3: INTRQ_wait (Ready to transfer data or command compete) & nIEN = 0 HP2:HP3 INTRQ asserted HP3:HP2 BSY = 0 & DRQ = 0 & REL=0 & SERV=0, no queue HP2:HI0 Host_Idle BSY = 0 & DRQ = 0 & REL=0 & SERV=0 & nIEN=0, queue HP2a:HIO0 Command complete BSY = 0 & DRQ = 0 & REL=0 & SERV=0 & nIEN=1, queue HP2a:HIO3 Command complete BSY = 0 & DRQ = 0 & REL=1 & SERV=0 & nIEN=0 HP2b:HIO0 Bus release BSY = 0 & DRQ = 0 & REL=1 & SERV=0 & nIEN=1 HP2b:HIO3 Bus release BSY = 0 & DRQ = 0 & SERV=1 Bus release or command complete HP2:HIO5 BSY = 0 & DRQ = 1 HP2:HP4 HP4: Transfer_Data Data register written or read & DRQ data block transferred HP4:HP2 Data register written or read & DRQ data block transfer not complete HP4:HP4 Figure 31 − Host PACKET non-data and PIO data command state diagram HP0: Check_Status_A State: This state is entered when the host has written a PACKET command to the device. When in this state, the host shall read the device Status register. When entering this state from the HI4 state, the host shall wait 400 ns before reading the Status register. Page 344 T13/1410D revision 3b Transition HP0:HP0: When BSY is set to one, the host shall make a transition to the HP0: Check_Status_A state. Transition HP0:HP1: When BSY is cleared to zero and DRQ is set to one, then the host shall make a transition to the HP1: Send_Packet state. Transition HP0:HI0: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared to zero, and SERV is cleared to zero, then the command is completed and the host shall make a transition to the HI0: Host_Idle state (see Figure 19). If an error is reported, the host shall perform appropriate error recovery. HP1: Send_Packet State: This state is entered when BSY is cleared to zero, DRQ is set to one. When in this state, the host shall write a byte of the command packet to the Data register. Transition HP1:HP1: When the Data register has been written and the writing of the command packet is not completed, the host shall make a transition to the HP1: Send_Packet state. Transition HP1:HP2: When the Data register has been written, the writing of the command packet is completed, and nIEN is set to one, the host shall make a transition to the HP2: Check_Status_B state. Transition HP1:HP3: When the Data register has been written, the writing of the command packet is completed, and nIEN is cleared to zero, the host shall make a transition to the HP3: INTRQ wait state. HP2: Check_Status_B State: This state is entered when the host has written the command packet to the device, when INTRQ has been asserted, when a DRQ data block has been transferred, or from a service return. When in this state, the host shall read the device Status register. When entering this state from the HP1 or HP4 state, the host shall wait one PIO transfer cycle time before reading the Status register. The wait may be accomplished by reading the Alternate Status register and ignoring the result. Transition HP2:HP2: When BSY is set to one, and DRQ is cleared to zero, the host shall make a transition to the HP2: Check_Status_B state. Transition HP2:HP3: When the host is ready to transfer data or the command is complete, and nIEN is cleared to zero, then the host shall make a transition to the HP3: INTRQ_Wait state. Transition HP2:HP4: When BSY is cleared to zero and DRQ is set to one, then the host shall make a transition to the HP4: Transfer_Data state. Transition HP2:HI0: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared to zero, SERV is cleared to zero, and the device queue is empty, then the command is completed and the host shall make a transition to the HI0: Host_Idle state (see Figure 19). If an error is reported, the host shall perform appropriate error recovery. Transition HP2a:HIO0: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared to zero, SERV is cleared to zero, nIEN is cleared to zero, and the device has a queue of released commands, then the command is completed and the host shall make a transition to the HIO0: Command completed state (see Figure 20). If an error is reported, the host shall perform appropriate error recovery. Transition HP2a:HIO3: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared to zero, SERV is cleared to zero, nIEN is set to one, and the device has a queue of released commands, then the command is completed and the host shall make a transition to the HIO3: Command completed state (see Figure 20). If an error is reported, the host shall perform appropriate error recovery. Page 345 T13/1410D revision 3b Transitions HP2b:HIO0: When BSY is cleared to zero, DRQ is cleared to zero, REL is set to one, SERV is cleared to zero, and nIEN is cleared to zero, then the host shall make a transition to the HIO0: INTRQ_wait_A state (see Figure 20). The bus has been released. Transitions HP2b:HIO3: When BSY is cleared to zero, DRQ is cleared to zero, REL is set to one, SERV is cleared to zero, and nIEN is set to one, then the host shall make a transition to the HIO3: Check_status_A state (see Figure 20). The bus has been released. Transitions HP2:HIO5: When BSY is cleared to zero, DRQ is cleared to zero, and SERV is set to one, then the host shall make a transition to the HIO5: Write_SERVICE state (see Figure 20). The command is completed or the bus has been released, and another queued command is ready for service. If an error is reported, the host shall perform appropriate error recovery. HP3: INTRQ_Wait State: This state is entered when the command packet has been transmitted, the host is ready to transfer data or when the command has completed, and nIEN is cleared to zero. When in this state, the host shall wait for INTRQ to be asserted. Transition HP3:HP2: When INTRQ is asserted, the host shall make a transition to the HP2: Check_Status_B state. HP4: Transfer_Data State: This state is entered when BSY is cleared to zero, DRQ is set to one, and C/D is cleared to zero. When in this state, the host shall read the byte count then read or write the device Data register to transfer data. If the bus has been released, the host shall read the Sector Count register to determine the Tag for the queued command to be executed. Transition HP4:HP2: When the host has read or written the device Data register and the DRQ data block has been transferred, then the host shall make a transition to the HP2: Check_Status_B state. Transition HP4:HP4: When the host has read or written the device status register and the DRQ data block transfer has not completed, then the host shall make a transition to the HP4: Transfer_Data state. Page 346 T13/1410D revision 3b DP0: Prepare_A BSY=1, DRQ=0, INTRQ=N, C/D=x, I/O=x PACKET command written xx:DP0 DP1: Receive_packet BSY=0, DRQ=1, INTRQ=N, C/D=1, I/O=0 Ready to receive command packet DP0:DP1 Data register written & command packet transfer complete DP1:DP2 Data register written & command packet transfer not complete DP1:DP1 DP2: Prepare_B BSY=1, DRQ=0, INTRQ=N, C/D=x, I/O=x Service return xx:DP2 Command complete & nIEN=1 & no queue Device_Idle_S DP2:DI1 BSY=0, REL=0, C/D=1, I/O=1 Command complete & nIEN=0 & no queue DP2:DI0 Device_Idle_SI BSY=0, REL=0, C/D=1, I/O=1, INTRQ=A Command complete & nIEN=1 & queue DP2a:DIO1 Device_Idle_SR BSY=0, REL=0, C/D=1, I/O=1 Command complete & nIEN=0 & queue DP2a:DIO0 Device_Idle_SIR BSY=0, REL=0, C/D=1, I/O=1, INTRQ=A Command complete & nIEN = 1 & service required Command complete & nIEN = 0 & service required Device_Idle_SS DP2a:DIO3 Device_Idle_SIS DP2a:DIO2 BSY=0, REL=0, SERV=1, C/D=1, I/O=1 BSY=0, REL=0, SERV=1, C/D=1, I/O=1, INTRQ=A Device_Idle_SIR Bus release & nIEN = 0 DP2b:DIO0 BSY=0, REL=1, C/D=1, I/O=1, INTRQ=A Bus release & nIEN = 1 DP2b:DIO1 BSY=0, REL=1, C/D=1, I/O=1 Device_Idle_SR Bus release & nIEN = 0 & service required Bus release & nIEN = 1 & service required DP2b:DIO3 Device_Idle_SS Device_Idle_SIS DP2b:DIO2 BSY=0, REL=1, SERV=1, C/D=1, I/O=1 BSY=0, REL=1, SERV=1, C/D=1, I/O=1, INTRQ=A DP3: Ready_INTRQ BSY=0, DRQ=1, INTRQ=A, C/D=0, I/O=x DP4: Transfer_Data BSY=0, DRQ=1, INTRQ=N, C/D=0, I/O=x Data register read/written & DRQ data block transfer not complete DP4:DP4 Ready to transfer DRQ SERVICE written & service interrupt enabled data block & nIEN=1 DP2a:DP3 DP2:DP4 Service status read Set byte count & Tag DP3:DP2 Data register read/written & Ready to transfer DRQ DRQ data block complete data block & nIEN=0 DP4:DP2 DP2b:DP3 Set byte count & Tag Status register read DP3:DP4 BSY v DRQ v REL x SERV x C/D v I/O v INTRQ V DMARQ R PDIAGR DASPR Figure 32 − Device PACKET non-data and PIO data command state diagram . DP0: Prepare_A State: This state is entered when the device has a PACKET written to the Command register. Page 347 T13/1410D revision 3b When in this state, device shall set BSY to one, clear DRQ to zero, and negate INTRQ within 400 ns of the receipt of the command and shall prepare to receive a command packet. If the command is a queued command, the device shall verify that the Tag is valid. Transition DP0:DP1: When the device is ready to receive the command packet for a command, the device shall make a transition to the DP1: Receive_Packet state. DP1: Receive_Packet State: This state is entered when the device is ready to receive the command packet. When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is negated, C/D is set to one, I/O is cleared to zero, and REL is cleared to zero. When in this state, the device Data register is written. Transition DP1:DP1: If the Data register is written and the entire command packet has not been received, then the device shall make a transition to the DP1: Receive_Packet state. Transition DP1:DP2: When the Data register is written and the entire command packet has been received, then the device shall make a transition to the DP2: Prepare_B state. DP2: Prepare_B State: This state is entered when the command packet has been received or from a Service return. When in this state, device shall set BSY to one, clear DRQ to zero, and negate INTRQ. Non-data transfer commands shall be executed while in this state. For data transfer commands, the device shall check for errors, determine if the data transfer is complete, and if not, prepare to transfer the next DRQ data block. If the command is overlapped and the release interrupt is enabled, the device shall bus release as soon as the command packet has been received. Transition DP2:DP4: When the device is ready to transfer a DRQ data block for a command and nIEN is set to one, then the device shall set the command Tag and byte count, set the interrupt pending, and make a transition to the DP4: Transfer_Data state. Transition DP2b:DP3: When the device is ready to transfer a DRQ data block for a command and nIEN is cleared to zero, then the device shall set the command Tag and byte count, set the interrupt pending, and make a transition to the DP3: Ready_INTRQ state. Transition DP2a:DP3: When the service interrupt is enabled and the device has SERVICE written to the Command register, then the device shall set the command Tag and byte count and make a transition to the DP3: Ready_INTRQ state. Transition DP2:DI0: When the command has completed or an error occurs that causes the command to abort, the device has no other command released, and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, set C/D and I/O to one, clear BSY to zero, and make a transition to the DI0: Device_Idle_SI state (see Figure 21). Transition DP2:DI1: When the command has completed or an error occurs that causes the command to abort, the device has no other command released, and nIEN is set to one, then the device shall set appropriate error bits, set C/D and I/O to one, clear BSY to zero, and make a transition to the DI1: Device_Idle_S state (see Figure 21). Transition DP2a:DIO0: When the command has completed or an error occurs that causes the command to abort, the device has another command released but not ready for service, and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, set C/D and I/O to one, clear BSY to zero, and make a transition to the DIO0: Device_Idle_SIR state (see Figure 22). Page 348 T13/1410D revision 3b Transition DP2a:DIO1: When the command has completed or an error occurs that causes the command to abort, the device has another command released but not ready for service, and nIEN is set to one, then the device shall set appropriate error bits, set C/D and I/O to one, clear BSY to zero, and make a transition to the DIO1: Device_Idle_SR state (see Figure 22). Transition DP2a:DIO2: When the command has completed or an error occurs that causes the command to abort, the device has another command ready for service, and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, set C/D and I/O to one, set SERV to one, clear BSY to zero, and make a transition to the DIO2: Device_Idle_SIS state (see Figure 22). Transition DP2a:DIO3: When the command has completed or an error occurs that causes the command to abort, the device has another command ready for service, and nIEN is set to one, then the device shall set appropriate error bits, set C/D and I/O to one, set SERV to one, clear BSY to zero, and make a transition to the DIO3: Device_Idle_SS state (see Figure 22). Transition DP2b:DIO0: When the command is released and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, set C/D and I/O to one, set REL to one, clear BSY to zero, and make a transition to the DIO0: Device_Idle_SIR state (see Figure 22). Transition DP2b:DIO1: When the command is released and nIEN is set to one, then the device shall set appropriate error bits, set C/D and I/O to one, set REL to one, clear BSY to zero, and make a transition to the DIO1: Device_Idle_SR state (see Figure 22). Transition DP2b:DIO2: When the command is released, the device has another command ready for service, and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, set C/D and I/O to one, set REL to one, set SERV to one, clear BSY to zero, and make a transition to the DIO2: Device_Idle_SIS state (see Figure 22). Transition DP2b:DIO3: When the command is released, the device has another command ready for service, and nIEN is set to one, then the device shall set appropriate error bits, set C/D and I/O to one, set REL to one, set SERV to one, clear BSY to zero, and make a transition to the DIO3: Device_Idle_SS state (see Figure 22). DP3: Ready_INTRQ State: This state is entered when the device is ready to transfer a DRQ data block and nIEN is cleared to zero. This state is entered to interrupt upon receipt of a SERVICE command when service interrupt is enabled. When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is asserted, C/D is cleared to zero, and I/O is set to one for PIO data-out or cleared to zero for PIO data-in. Transition DP3:DP2: When the Status register is read to respond to a service interrupt, the device shall make a transition to the DP2: Prepare_B state. Transition DP3:DP4: When the Status register is read when the device is ready to transfer data, then the device shall clear the interrupt pending, negate INTRQ, and make a transition to the DP4: Data_Transfer state. DP4: Data_Transfer State: This state is entered when the device is ready to transfer a DRQ data block. When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is negated, C/D is cleared to zero, I/O is set to one for PIO data-out or cleared to zero for PIO data-in, and a data word is read/written in the Data register. Transition DP4:DP4: When the Data register is read/written and transfer of the DRQ data block has not completed, then the device shall make a transition to the DP4: Data_Transfer state. Page 349 T13/1410D revision 3b Transition DP4:DP2: When the Data register is read/written and the transfer of the current DRQ data block has completed, then the device shall make a transition to the DP2: Prepare_B state. HPD1: Send_Packet HPD0: Check_Status_A PACKET command written HI4:HPD0 BSY = 1 HPD0:HPD0 BSY = 0 & DRQ = 1 HPD0:HPD1 BSY = 0 & DRQ = 0 HPD0:HI0 HPD2: Check_Status_B Service return & service interrupt disabled HIOx:HPD2 Data register written & command packet transfer not complete HPD1:HPD1 Host_Idle Command packet transfer complete, nIEN=1 Command packet transfer complete, nIEN=0 HPD1:HPD3 HPD1:HPD2 BSY = 0 & DRQ = 0 & REL=0 & SERV=0, no queue HPD2:HI0 Host_Idle BSY = 0 & DRQ = 0 & REL=0 & SERV=0 & nIEN=0, queue HPD2a:HIO0 Command complete BSY = 0 & DRQ = 0 & REL=0 & SERV=0 & nIEN=1, queue HPD2a:HIO3 Command complete BSY = 0 & DRQ = 0 & REL=1 & SERV=0 & nIEN=0 HPD2b:HIO0 BSY = 1 HPD2:HPD2 Bus release BSY = 0 & DRQ = 0 & REL=1 & SERV=0 & nIEN=1 HPD2b:HIO3 Bus release BSY = 0 & DRQ = 0 & SERV=1 HPD2:HIO5 Bus release or command complete Service return and service interrupt enabled HPD3: INTRQ_wait HIOx:HPD3 INTRQ asserted HPD3:HPD2 BSY = 0 & DRQ = 1& DMARQ asserted HPD2:HPD4 HPD4: Transfer_Data (All data for command transferred & nIEN=1) All data for command transferred & nIEN=0 or (DMA burst HPD4:HPD3 terminated and all data for command not transferred) HPD4:HPD2 Figure 33 − Host PACKET DMA command state diagram HPD0: Check_Status_A State: This state is entered when the host has written a PACKET command to the device. Page 350 T13/1410D revision 3b When in this state, the host shall read the device Status register. When entering this state from the HI4 state, the host shall wait 400 ns before reading the Status register. Transition HPD0:HPD0: When BSY is set to one, the host shall make a transition to the HPD0: Check_Status_A state. Transition HPD0:HPD1: When BSY is cleared to zero and DRQ is set to one, then the host shall make a transition to the HPD1: Send_Packet state. Transition HPD0:HI0: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared to zero, and SERV is cleared to zero, then the command is completed and the host shall make a transition to the HI0: Host_Idle state (see Figure 19). If an error is reported, the host shall perform appropriate error recovery. HPD1: Send_Packet State: This state is entered when BSY is cleared to zero, DRQ is set to one. When in this state, the host shall write a byte of the command packet to the Data register. Transition HPD1:HPD1: When the Data register has been written and the writing of the command packet is not completed, the host shall make a transition to the HPD1: Send_Packet state. Transition HPD1:HPD2: When the Data register has been written, the writing of the command packet is completed, and nIEN is set to one, the host shall make a transition to the HPD2: Check_Status_B state. Transition HPD1:HPD3: When the Data register has been written, the writing of the command packet is completed, and nIEN is cleared to zero, the host shall make a transition to the HPD3: INTRQ wait state. HPD2: Check_Status_B State: This state is entered when the host has written the command packet to the device, when INTRQ has been asserted, when a DRQ data block has been transferred, or from a service return when the service interrupt is disabled. When in this state, the host shall read the device Status register. When entering this state from the HPD1 or HPD4 state, the host shall wait one PIO transfer cycle time before reading the Status register. The wait may be accomplished by reading the Alternate Status register and ignoring the result. Transition HPD2:HPD2: When BSY is set to one, and DRQ is cleared to zero, the host shall make a transition to the HPD2: Check_Status_B state. Transition HPD2:HPD4: When BSY is cleared to zero, DRQ is set to one, and DMARQ is asserted, then the host shall make a transition to the HPD4: Transfer_Data state. The host shall have set up the DMA engine before this transition. Transition HPD2:HI0: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared to zero, SERV is cleared to zero, and the device queue is empty, then the command is completed and the host shall make a transition to the HI0: Host_Idle state (see Figure 19). If an error is reported, the host shall perform appropriate error recovery. Transition HPD2a:HIO0: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared to zero, SERV is cleared to zero, nIEN is cleared to zero, and the device has a queue of released commands, then the command is completed and the host shall make a transition to the HIO0: Command completed state (see Figure 20). If an error is reported, the host shall perform appropriate error recovery. Transition HPD2a:HIO3: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared to zero, SERV is cleared to zero, nIEN is set to one, and the device has a queue of released commands, then the command is completed and the host shall make a transition to the HIO3: Command completed state (see Figure 20). If an error is reported, the host shall perform appropriate error recovery. Page 351 T13/1410D revision 3b Transition HPD2b:HIO0: When BSY is cleared to zero, DRQ is cleared to zero, REL is set to one, SERV is cleared to zero, and nIEN is cleared to zero, then the host shall make a transition to the HIO0: INTRQ_wait_A state (see Figure 20). The bus has been released. Transition HPD2b:HIO3: When BSY is cleared to zero, DRQ is cleared to zero, REL is set to one, SERV is cleared to zero, and nIEN is set to one, then the host shall make a transition to the HIO3: Check_status_A state (see Figure 20). The bus has been released. Transition HPD2:HIO5: When BSY is cleared to zero, DRQ is cleared to zero, and SERV is set to one, then the host shall make a transition to the HIO5: Write_SERVICE state (see Figure 20). The command is completed or the bus has been released, and another queued command is ready for service. If an error is reported, the host shall perform appropriate error recovery. HPD3: INTRQ_Wait State: This state is entered when the command packet has been transmitted, when a service return is issued and the service interrupt is enabled, or when the command has completed and nIEN is cleared to zero. When in this state, the host shall wait for INTRQ to be asserted. Transition HPD3:HPD2: When INTRQ is asserted, the host shall make a transition to the HPD2: Check_Status_B state. HPD4: Transfer_Data State: This state is entered when BSY is cleared to zero, DRQ is set to one, and DMARQ is asserted. When in this state, the host shall read or write the device Data port to transfer data. If the bus has been released, the host shall read the Sector Count register to determine the Tag for the queued command to be executed. Transition HPD4:HPD2: The host shall make a transition to the HPD2: Check_Status_B state when 1) all data for the request has been transferred and nIEN is set to one, or 2) the DMA burst has been terminated and all data for the command has not been transferred. Transition HPD4:HPD3: When all data for the request has been transferred and nIEN is cleared to zero, then the host shall make a transition to the HPD3: INTRQ_wait state. Page 352 T13/1410D revision 3b DPD0: Prepare_A BSY=1, DRQ=0, INTRQ=N, C/D=x, I/O=x, DMARQ=N PACKET command written xx:DPD0 DPD1: Receive_packet BSY=0, DRQ=1, INTRQ=N, C/D=1, I/O=0, DMARQ=N Data register written & command packet transfer not complete Ready to receive command packet DPD0:DPD1 Data register written & command packet transfer complete DPD1:DPD2 DPD1:DPD1 DPD2: Prepare_B BSY=1, DRQ=0, INTRQ=N, C/D=x, I/O=x, DMARQ=N Service return xx:DPD2 Command complete & nIEN=1 & no queue DPD2:DI1 BSY=0, REL=0,C/D=1, I/O=1 Command complete & nIEN=0 & no queue DPD2:DI0 Device_Idle_SI BSY=0, REL=0, C/D=1, I/O=1, INTRQ=A Command complete & nIEN=1 & queue Command complete & nIEN=0 & queue DPD2a:DIO0 Device_Idle_SIR BSY=0, REL=0, C/D=1, I/O=1, INTRQ=A Device_Idle_S Device_Idle_SR DPD2a:DIO1 BSY=0, REL=0, C/D=1, I/O=1 Command complete & nIEN = 1 & service required Command complete & nIEN = 0 & service required Device_Idle_SS DPD2a:DIO3 DPD2a:DIO2 Device_Idle_SIS BSY=0, REL=0, SERV=1, C/D=1, I/O=1 BSY=0, REL=0, SERV=1, C/D=1, I/O=1, INTRQ=A Bus release & nIEN = 0 DPD2b:DIO0 Device_Idle_SIR BSY=0, REL=1, C/D=1, I/O=1, INTRQ=A Bus release & nIEN = 1 DPD2b:DIO1 BSY=0, REL=1, C/D=1, I/O=1 Device_Idle_SR Bus release & nIEN = 0 & service required Bus release & nIEN = 1 & service required Device_Idle_SIS DPD2b:DIO2 DPD2b:DIO3 Device_Idle_SS BSY=0, REL=1, SERV=1, C/D=1, I/O=1, INTRQ=A BSY=0, REL=1, SERV=1, C/D=1, I/O=1 DPD3: Ready_INTRQ BSY=0, DRQ=1, INTRQ=A, C/D=0, I/O=x, DMARQ=N DPD4: Transfer_Data BSY=0, DRQ=1, INTRQ=N, C/D=0, I/O=x, DMARQ=A Ready to transfer DMA SERVICE written & service data interrupt enabled DPD2:DPD3 DPD2:DPD4 Set byte count & Tag Service status read DPD3:DPD2 DMA burst terminated DPD4:DPD2 BSY v DRQ v REL x SERV x C/D v I/O v INTRQ V DMARQ V PDIAGR DASPR Figure 34 − Device PACKET DMA command state diagram DPD0: Prepare_A State: This state is entered when the device has a PACKET written to the Command register. When in this state, device shall set BSY to one, clear DRQ to zero, and negate INTRQ within 400 ns of the receipt of the command and shall prepare to receive a command packet. If the command is a queued command, the device shall verify that the Tag is valid. Page 353 T13/1410D revision 3b Transition DPD0:DPD1: When the device is ready to receive the command packet for a command, the device shall make a transition to the DPD1: Receive_Packet state. DPD1: Receive_Packet State: This state is entered when the device is ready to receive the command packet. When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is negated, C/D is set to one, I/O is cleared to zero, and REL is cleared to zero. When in this state, the device Data register is written. Transition DPD1:DPD1: If the Data register is written and the entire command packet has not been received, then the device shall make a transition to the DPD1: Receive_Packet state. Transition DPD1:DPD2: When the Data register is written and the entire command packet has been received, then the device shall make a transition to the DPD2: Prepare_B state. DPD2: Prepare_B State: This state is entered when the command packet has been received or from a Service return. When in this state, device shall set BSY to one, clear DRQ to zero, and negate INTRQ. The device shall check for errors, determine if the data transfer is complete, and if not, prepare to transfer the DMA data. If the command is overlapped and the release interrupt is enabled, the device shall bus release as soon as the command packet has been received. Transition DPD2:DPD4: When the device is ready to transfer DMA data for a command and nIEN is set to one, then the device shall set the command Tag and byte count, set the interrupt pending, and make a transition to the DPD4: Transfer_Data state. Transition DPD2:DPD3: When the service interrupt is enabled and the device has SERVICE written to the Command register, then the device shall set the command Tag and byte count and make a transition to the DPD3: Ready_INTRQ state. Transition DPD2:DI0: When the command has completed or an error occurs that causes the command to abort, the device has no other command released, and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, set C/D and I/O to one, clear BSY to zero, and make a transition to the DI0: Device_Idle_SI state (see Figure 21). Transition DPD2:DI1: When the command has completed or an error occurs that causes the command to abort, the device has no other command released, and nIEN is set to one, then the device shall set appropriate error bits, set C/D and I/O to one, clear BSY to zero, and make a transition to the DI1: Device_Idle_S state (see Figure 21). Transition DPD2a:DIO0: When the command has completed or an error occurs that causes the command to abort, the device has another command released but not ready for service, and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, set C/D and I/O to one, clear BSY to zero, and make a transition to the DIO0: Device_Idle_SIR state (see Figure 22). Transition DPD2a:DIO1: When the command has completed or an error occurs that causes the command to abort, the device has another command released but not ready for service, and nIEN is set to one, then the device shall, set appropriate error bits, set C/D and I/O to one, clear BSY to zero, and make a transition to the DIO1: Device_Idle_SR state (see Figure 22). Transition DPD2a:DIO2: When the command has completed or an error occurs that causes the command to abort, the device has another command ready for service, and nIEN is cleared to zero, then the device shall set Page 354 T13/1410D revision 3b the interrupt pending, set appropriate error bits, set C/D and I/O to one, set SERV to one, clear BSY to zero, and make a transition to the DIO2: Device_Idle_SIS state (see Figure 22). Transition DPD2a:DIO3: When the command has completed or an error occurs that causes the command to abort, the device has another command ready for service, and nIEN is set to one, then the device shall set appropriate error bits, set C/D and I/O to one, set SERV to one, clear BSY to zero, and make a transition to the DIO3: Device_Idle_SS state (see Figure 22). Transition DPD2b:DIO0: When the command is released and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, set C/D and I/O to one, set REL to one, clear BSY to zero, and make a transition to the DIO0: Device_Idle_SIR state (see Figure 22). Transition DPD2b:DIO1: When the command is released and nIEN is set to one, then the device shall, set appropriate error bits, set C/D and I/O to one, set REL to one, clear BSY to zero, and make a transition to the DIO1: Device_Idle_SR state (see Figure 22). Transition DPD2b:DIO2: When the is released, the device has another command ready for service, and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, set C/D and I/O to one, set REL to one, set SERV to one, clear BSY to zero, and make a transition to the DIO2: Device_Idle_SIS state (see Figure 22). Transition DPD2b:DIO3: When the command is released, the device has another command ready for service, and nIEN is set to one, then the device shall set appropriate error bits, set C/D and I/O to one, set REL to one, set SERV to one, clear BSY to zero, and make a transition to the DIO3: Device_Idle_SS state (see Figure 22). DPD3: Ready_INTRQ State: This state is entered upon receipt of a SERVICE command when service interrupt is enabled. When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is asserted, C/D is cleared to zero, and I/O is set to one for PIO data-out or cleared to zero for PIO data-in. Transition DPD3:DPD2: When the Status register is read to respond to a service interrupt, the device shall make a transition to the DPD2: Prepare_B state. DPD4: Data_Transfer State: This state is entered when the device is ready to transfer DMA data. When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is negated, C/D is cleared to zero, I/O is set to one for data-out or cleared to zero for data-in, DMARQ is asserted, and data is transferred as described in Multiword DMA timing or Ultra DMA protocol. Transition DPD4:DPD2: When the DMA burst is terminated, then the device shall make a transition to the DPD2: Prepare_B state. All of the data for the command may not yet be transferred. 9.9 READ/WRITE DMA QUEUED command protocol This class includes: − − − − READ DMA QUEUED READ DMA QUEUED EXT WRITE DMA QUEUED WRITE DMA QUEUED EXT Execution of this class of command includes the transfer of one or more blocks of data from the host to the device or from the device to the host using DMA transfer. All data for the command may be transferred without a bus release between the command receipt and the data transfer. This command may bus release before Page 355 T13/1410D revision 3b transferring data. The host shall initialize the DMA channel prior to transferring data. When data transfer is begun, all data for the request shall be transferred without a bus release. Figure 35 and the text following the figure describes the host states. Figure 36 and the text following the figure describes the device states. HDMAQ0: Check_Status DMA QUEUED command written HI4:HDMAQ0 BSY = 0 & DRQ = 0 & REL=0 & SERV=0, no queue HDMAQ0:HI0 Host_Idle DMA QUEUED service return HIO5:HDMAQ0 HIO7:HDMAQ0 BSY = 0 & DRQ = 0 & REL=0 & SERV=0 & nIEN=0, queue HDMAQ0a:HIO0 Command complete BSY = 0 & DRQ = 0 & REL=0 & SERV=0 & nIEN=1, queue HDMAQ0a:HIO3 Command complete BSY = 0 & DRQ = 0 & REL=1 & SERV=0 & nIEN=0 HDMAQ0b:HIO0 Bus release BSY = 0 & DRQ = 0 & REL=1 & SERV=0 & nIEN=1 HDMAQ0b:HIO3 Bus release BSY = 0 & DRQ = 0 & SERV=1 HDMAQ0:HIO5 Bus release or command complete BSY = 1, DMARQ=N HDMAQ0:HDMAQ0 HDMAQ2: INTRQ_wait INTRQ asserted HDMAQ2:HDMAQ0 BSY = 0 & DRQ = 1& DMARQ asserted HDMAQ0:HDMAQ1 HDMAQ1: Transfer_Data (All data for command transferred & nIEN=1) or (the DMA burst is terminated and all data for command has not been transferred) HDMAQ1:HDMAQ0 All data for command transferred & nIEN=0 HDMAQ1:HDMAQ2 Figure 35 − Host DMA QUEUED state diagram HDMAQ0: Check_Status State: This state is entered when the host has written a READ/WRITE DMA QUEUED command to the device, when all data for the command has been transferred and nIEN is set to one, or when all data for the command has been transferred, nIEN is cleared to zero, and INTRQ has been asserted. It is also entered when the SERVICE command has been written to continue execution of a bus released command. When in this state, the host shall read the device Status register. When entering this state from the HI4, HIO5, or HIO7 state, the host shall wait 400 ns before reading the Status register. When entering this state from the HDMAQ1 state, the host shall wait one PIO transfer cycle time before reading the Status register. The wait may be accomplished by reading the Alternate Status register and ignoring the result. When entering this state from the DMA QUEUED service return, the host shall check the Tag for the command to be serviced before making a transition to transfer data. Page 356 T13/1410D revision 3b Transition HDMAQ0:HDMAQ0: When BSY is set to one and DMARQ is negated, the host shall make a transition to the HDMAQ0: Check_Status state. Transition HDMAQ0:HDMAQ1: When BSY is cleared to zero, DRQ is set to one, and DMARQ is asserted, then the host shall set up the DMA engine and then make a transition to the HDMAQ1: Transfer_Data state. Transition HDMAQ0:HI0: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared to zero, SERV is cleared to zero, and the device queue is empty, then the command is completed and the host shall make a transition to the HI0: Host_Idle state (see Figure 19). If an error is reported, the host shall perform appropriate error recovery. Transition HDMAQ0a:HIO0: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared to zero, SERV is cleared to zero, nIEN is cleared to zero, and the device has a queue of released commands, then the command is completed and the host shall make a transition to the HIO0: Command completed state (see Figure 20). If an error is reported, the host shall perform appropriate error recovery. Transition HDMAQ0a:HIO3: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared to zero, SERV is cleared to zero, nIEN is set to one, and the device has a queue of released commands, then the command is completed and the host shall make a transition to the HIO3: Command completed state (see Figure 20). If an error is reported, the host shall perform appropriate error recovery. Transition HDMAQ0b:HIO0: When BSY is cleared to zero, DRQ is cleared to zero, REL is set to one, SERV is cleared to zero, and nIEN is cleared to zero, then the host shall make a transition to the HIO0: INTRQ_wait_A state (see Figure 20). The bus has been released. Transition HDMAQ0b:HIO3: When BSY is cleared to zero, DRQ is cleared to zero, REL is set to one, SERV is cleared to zero, and nIEN is set to one, then the host shall make a transition to the HIO3: Check_status_A state (see Figure 20). The bus has been released. Transition HDMAQ0:HIO5: When BSY is cleared to zero, DRQ is cleared to zero, and SERV is set to one, then the host shall make a transition to the HIO5: Write_SERVICE state (see Figure 20). The command is completed or the bus has been released, and another queued command is ready for service. If an error is reported, the host shall perform appropriate error recovery. HDMAQ1: Transfer_Data State: This state is entered when BSY is cleared to zero, DRQ is set to one, and DMARQ is asserted. When in this state, the host shall read or write the device Data port to transfer data. If the bus has been released, the host shall read the Tag in the Sector Count register to determine the queued command to be executed and initialize the DMA channel. Transition HDMAQ1:HDMAQ0: The host shall make a transition to the HDMAQ0: Check_Status state when 1) all data for the request has been transferred and nIEN is set to one, or 2) the DMA burst is terminated and all data for the request has not been transferred. Transition HDMAQ1:HDMAQ2: When all data for the request has been transferred and nIEN is cleared to zero, then the host shall make a transition to the HDMAQ2: INTRQ_wait state. HDMAQ2: INTRQ_Wait State: This state is entered when the command has completed, and nIEN is cleared to zero. When in this state, the host shall wait for INTRQ to be asserted. Transition HDMAQ2:HDMAQ0: When INTRQ is asserted, the host shall make a transition to the HDMAQ0: Check_Status state. Page 357 T13/1410D revision 3b DDMAQ0: Prepare BSY=1, DRQ=0, INTRQ=N, DMARQ=N Service return DMA QUEUED command written xx:DDMAQ0 xx:DDMAQ0 Command complete & nIEN=1 & no queue Device_Idle_S DDMAQ0:DI1 BSY=0, REL=0 Command complete & nIEN=1 & queue Device_Idle_SR DDMAQ0a:DIO1 BSY=0, REL=0 Command complete & nIEN = 1 & service required Device_Idle_SS DDMAQ0a:DIO3 Device_Idle_SIR Command complete & nIEN=0 & no queue DDMAQ0:DI0 Device_Idle_SI BSY=0, REL=0, INTRQ=A Command complete & nIEN=0 & queue DDMAQ0a:DIO0 Device_Idle_SIR BSY=0, REL=0, INTRQ=A BSY=0, REL=0, SERV=1 Command complete & nIEN = 0 & service required DDMAQ0a:DIO2 Device_Idle_SIS BSY=0, REL=0, SERV=1, INTRQ=A Bus release & nIEN = 0 DDMAQ0b:DIO0 BSY=0, REL=1, INTRQ=A Bus release & nIEN = 1 DDMAQ0b:DIO1 BSY=0, REL=1 Bus release & nIEN = 0 & service required Device_Idle_SIS DDMAQ0b:DIO2 BSY=0, REL=1, SERV=1, INTRQ=A Device_Idle_SR Bus release & nIEN = 1 & service required DDMAQ0b:DIO3 BSY=0, REL=1, SERV=1 Device_Idle_SS Ready to transfer DMA data DDMAQ0:DDMAQ1 DDMAQ1: Transfer_Data BSY=0, DRQ=1, INTRQ=N, DMARQ=A DMA burst terminated DDMAQ1:DDMAQ0 BSY v DRQ v REL x SERV x C/D x I/O x INTRQ V DMARQ V PDIAGR DASPR Figure 36 − Device DMA QUEUED command state diagram DDMAQ0: Prepare State: This state is entered when the device has a READ/WRITE DMA QUEUED or SERVICE command written to the Command register, when the data has been transferred, or when the command has completed. When in this state, device shall set BSY to one, clear DRQ to zero, and negate INTRQ. If the command is a queued command, the device shall verify that the Tag is valid. If commands are queued, the Tag for the command to be serviced shall be placed into the Sector Count register. Transition DDMAQ0:DDMAQ1: When the device is ready to transfer the data for a command, then the device shall make a transition to the DDMAQ1: Transfer_Data state. Transition DDMAQ0:DI0: When the command has completed or an error occurs that causes the command to abort, the device has no other command released, and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, clear BSY to zero, assert INTRQ, and make a transition to the DI0: Device_Idle_SI state (see Figure 21). Page 358 T13/1410D revision 3b Transition DDMAQ0:DI1: When the command has completed or an error occurs that causes the command to abort, the device has no other command released, and nIEN is set to one, then the device shall set appropriate error bits, clear BSY to zero, assert INTRQ, and make a transition to the DI1: Device_Idle_S state (see Figure 21). Transition DDMAQ0a:DIO0: When the command has completed or an error occurs that causes the command to abort, the device has another command released but not ready for service, and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, clear BSY to zero, assert INTRQ, and make a transition to the DIO0: Device_Idle_SIR state (see Figure 22). Transition DDMAQ0a:DIO1: When the command has completed or an error occurs that causes the command to abort, the device has another command released but not ready for service, and nIEN is set to one, then the device shall, set appropriate error bits, clear BSY to zero, and make a transition to the DIO1: Device_Idle_SR state (see Figure 22). Transition DDMAQ0a:DIO2: When the command has completed or an error occurs that causes the command to abort, the device has another command ready for service, and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, set SERV to one, clear BSY to zero, assert INTRQ, and make a transition to the DIO2: Device_Idle_SIS state (see Figure 22). Transition DDMAQ0a:DIO3: When the command has completed or an error occurs that causes the command to abort, the device has another command ready for service, and nIEN is set to one, then the device shall set appropriate error bits, set SERV to one, clear BSY to zero, and make a transition to the DIO3: Device_Idle_SS state (see Figure 22). Transition DDMAQ0b:DIO0: When the bus is released and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, set REL to one, clear BSY to zero, assert INTRQ, and make a transition to the DIO0: Device_Idle_SIR state (see Figure 22). Transition DDMAQ0b:DIO1: When the bus is released and nIEN is set to one, then the device shall, set appropriate error bits, set REL to one, clear BSY to zero, and make a transition to the DIO1: Device_Idle_SR state (see Figure 22). Transition DDMAQ0b:DIO2: When the bus is released, the device has another command ready for service, and nIEN is cleared to zero, then the device shall set the interrupt pending, set appropriate error bits, set REL to one, set SERV to one, clear BSY to zero, assert INTRQ, and make a transition to the DIO2: Device_Idle_SIS state (see Figure 22). Transition DDMAQ0b:DIO3: When the bus is released, the device has another command ready for service, and nIEN is set to one, then the device shall set appropriate error bits, set REL to one, set SERV to one, clear BSY to zero, and make a transition to the DIO3: Device_Idle_SS state (see Figure 22). DDMAQ1: Data_Transfer State: This state is entered when the device is ready to transfer DMA data. When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is negated, DMARQ is asserted, and data is transferred as described in Multiword DMA timing or Ultra DMA protocol. Transition DDMAQ1:DDMAQ0: When the DMA burst is terminated, then the device shall make a transition to the DDMAQ0: Prepare state. All of the data for the command may not be transferred. 9.10 EXECUTE DEVICE DIAGNOSTIC command protocol This class includes: Page 359 T13/1410D revision 3b − EXECUTE DEVICE DIAGNOSTIC If the host asserts RESET- before devices have completed executing their EXECUTE DEVICE DIAGNOSTIC protocol, then the devices shall start executing the power-on or hardware reset protocol from the beginning. If the host sets SRST to one in the Device Control register before the devices have completed execution of their EXECUTE DEVICE DIAGNOSTIC protocol, then the devices shall start executing their software reset protocol from the beginning. Figure 37 and the text following the figure describe the EXECUTE DEVICE DIAGNOSTIC protocol for the host. Figure 38 and the text following the figure describe the EXECUTE DEVICE DIAGNOSTIC protocol for Device 0. Figure 39 and the text following the figure describe the EXECUTE DEVICE DIAGNOSTIC protocol for Device 1. HED0: Wait EXECUTE DEVICE DIAGNOSTIC command written & nIEN=1 HI4:HED0 HED2: Check_status 2 ms timeout complete HED0:HED2 BSY = 0 HED2:HI0 Host_idle BSY = 1 HED2:HED2 HED1: INTRQ_Wait EXECUTE DEVICE DIAGNOSTIC command written & nIEN=0 HI4:HED1 INTRQ asserted HED1:HED2 Figure 37 − Host EXECUTE DEVICE DIAGNOSTIC state diagram HED0: Wait State: This state is entered when the host has written the EXECUTE DEVICE DIAGNOSTIC command to the devices and nIEN is set to one. The host shall remain in this state for at least 2 ms. Transition HED0:HED1: When at least 2 ms has elapsed since the command was written, the host shall make a transition to the HED1: Check_status state. HED1: INTRQ_wait: This state is entered when the host has written the EXECUTE DEVICE DIAGNOSTIC command to the devices and nIEN is cleared to zero. When in this state the host shall wait for INTRQ to be asserted. Transition HED1:HED2: When INTRQ is asserted, the host shall make a transition to the HED2: Check_status state. HED2: Check_status State: This state is entered when at least 2 ms since the command was written or INTRQ has been asserted. When in this state, the host shall read the Status or Alternate Status register. Transition HED2:HED2: When BSY is set to one, the host shall make a transition to the HED1: Check_status state. Transition HED2:HI0: When BSY is cleared to zero, the host shall check the results of the command (see 9.16) and make a transition to the HI0: Host_idle state (see Figure 19). Page 360 T13/1410D revision 3b D0ED0: Release_bus EXECUTE DEVICE DIAGNOSTIC command written DI0:D0ED0 DI1:D0ED0 Bus released & no Device 1 D0ED0:D0ED3 Clear bit 7 Bus released & Device 1 exists D0ED0:D0ED1 D0ED1: PDIAG-_wait 1 ms wait complete D0ED1:D0ED2 D0ED2: Sample_PDIAG- Resample PDIAGD0ED2:D0ED2 D0ED3: Set_status PDIAG- asserted D0ED2a:D0ED3 Clear bit 7 6 s timeout D0ED2b:D0ED3 Set bit 7 BSY 1 DRQ 0 REL 0 SERV 0 C/D 0 Status set & nIEN=1 D0ED3:DI1 BSY=0, INTRQ=A Device_idle_S Status set & nIEN=0 D0ED3:DI0 BSY=0 Device_idle_SI I/O 0 INTRQ N DMARQ R PDIAGR DASPR Figure 38 − Device 0 EXECUTE DEVICE DIAGNOSTIC state diagram D0ED0: Release_bus State: This state is entered when the EXECUTE DEVICE DIAGNOSTIC command has been written. When in this state, the device shall release PDIAG-, INTRQ, IORDY, DMARQ, and DD(15:0) and shall set BSY to one within 400 ns after entering this state. The device should begin performing the self-diagnostic testing. Transition D0ED0:D0ED1: When the bus has been released, BSY set to one, and the assertion of DASP- by Device 1 was detected during the most recent power-on or hardware reset, then the device shall make a transition to the D0ED1: PDIAG-_wait state. Transition D0ED0:D0ED3: When the bus has been released, BSY set to one, and the assertion of DASP- by Device 1 was not detected during the most recent power-on or hardware reset, then the device shall clear bit 7 in the Error register and make a transition to the D0ED3: Set_status state. D0ED1: PDIAG-_wait State: This state is entered when the bus has been released, BSY set to one, and Device 1 exists. The device shall remain in this state until least 1 ms has elapsed since the command was written and shall clear the DEV bit in the Device register to zero within 1 ms. Transition D0ED1:D0ED2: When at least 1 ms has elapsed since the command was written, the device shall make a transition to the D0ED2: Sample_PDIAG- state. Page 361 T13/1410D revision 3b D0ED2: Sample_PDIAG- State: This state is entered when at least 1 ms has elapsed since the command was written. When in this state, the device shall sample the PDIAG- signal. Transition D0ED2:D0ED3: When the sample indicates that PDIAG- is asserted, the device shall clear bit 7 in the Error register and make a transition to the D0ED3: Set_status state. Transition D0ED2:D0ED2: When the sample indicates that PDIAG- is not asserted and less than 6 s have elapsed since the command was written, then the device shall make a transition to the D0ED2: Sample_PDIAG- state. Transition D0ED2:D0ED3: When the sample indicates that DASP- is not asserted and 6 s have elapsed since the command was written, then the device shall set bit 7 in the Error register and make a transition to the D0ED3: Set_status state. D0ED3: Set_status State: This state is entered when Bit 7 in the Error register has been set or cleared. When in this state, the device shall clear the DEV bit in the Device register to zero within 1 ms. The device shall complete the self-diagnostic testing begun in the Release bus state if not already completed. Results of the self-diagnostic testing shall be placed in bits (6:0) of the Error register (see Table 26). The device shall set the signature values (see 9.12). The contents of the Features register is undefined. If the device does not implement the PACKET command feature set, the device shall clear bits 3, 2, and 0 in the Status register to zero. If the device implements the PACKET command feature set, the device shall clear bits 6, 5, 4, 3, 2, and 0 in the Status register to zero. The device shall return the operating modes to their specified initial conditions. MODE SELECT conditions shall be restored to their last saved values if saved values have been established. MODE SELECT conditions for which no values have been saved shall be returned to their default values. Transition D0ED3:DI1: When hardware initialization and self-diagnostic testing is completed, the status has been set, and nIEN is set to one, then the device shall clear BSY to zero, and make a transition to the DI1: Device_idle_S state (see Figure 21). Transition D0ED3:DI0: When hardware initialization and self-diagnostic testing is completed, the status has been set, and nIEN is cleared to zero, then the device shall clear BSY to zero, assert INTRQ, and make a transition to the DI0: Device_idle_SI state (see Figure 21). Page 362 T13/1410D revision 3b D1ED0: Release_bus PDIAG=x EXECUTE DEVICE DIAGNOSTIC command written DI0:D1ED0 DI1:D1ED0 D1ED1: Negate_PDIAGPDIAG- =R Bus released D1ED0:D1ED1 D1ED2: Set_status PDIAG- =N PDIAG- negated D1ED1:D1ED2 Status set D1ED2:DI2 BSY=0, PDIAG-=A BSY 1 DRQ 0 REL 0 SERV 0 C/D 0 I/O 0 Device_idle_NS INTRQ N DMARQ R PDIAGV DASPR Figure 39 − Device 1 EXECUTE DEVICE DIAGNOSTIC command state diagram D1ED0: Release_bus State: This state is entered when the EXECUTE DEVICE DIAGNOSTIC command is written. When in this state, the device shall release INTRQ, IORDY, DMARQ, and DD(15:0) within 400 ns after entering this state. The device shall set BSY to one within 400 ns after entering this state. The device should begin performing the self-diagnostic testing. Transition D1ED0:D1ED1: When the bus has been released and BSY set to one, then the device shall make a transition to the D1ED1: Negate_PDIAG- state. D1ED1: Negate_PDIAG- State: This state is entered when the bus has been released and BSY set to one. When in this state, the device shall negate PDIAG- and clear the DEV bit in the Device register within less than 1 ms of the receipt of the EXECUTE DEVICE DIAGNOSTIC command. Transition D1ED1:D1ED2: When PDIAG- has been negated, the device shall make a transition to the D1ED2: Set_status state. D1ED2: Set_status State: This state is entered when the device has negated PDIAG-. When in this state the device shall complete the hardware initialization and self-diagnostic testing begun in the Release bus state if not already completed. Results of the self-diagnostic testing shall be placed in the Error register (see Table 26). If the device passed the self-diagnostics, the device shall assert PDIAG-. The device shall set the signature values (see 9.12). The effect on the Features register is undefined. If the device does not implement the PACKET command feature set, the device shall clear bits 3, 2, and 0 in the Status register to zero. If the device implements the PACKET command feature set, the device shall clear bits 6, 5, 4, 3, 2, and 0 in the Status register to zero. The device shall return the operating modes to their specified initial conditions. MODE SELECT conditions shall be restored to their last saved values if saved values have been established. MODE SELECT conditions for which no values have been saved shall be returned to their default values. Page 363 T13/1410D revision 3b A requirements for this state shall be completed within 5 s or less from the writing of the command. Transition D1ED2:DI2: When hardware initialization and self-diagnostic testing is completed and the status has been set, then the device shall clear BSY to zero, assert PDIAG- if diagnostics were passed, and make a transition to the DI2: Device_idle_NS state (see Figure 21). 9.11 DEVICE RESET command protocol This class includes: − DEVICE RESET If the host asserts RESET- before the device has completed executing a DEVICE RESET command, then the device shall start executing the hardware reset protocol from the begining. If the host sets the SRST bit to one in the Device Control register before the device has completed executing a DEVICE RESET command, the device shall start executing the software reset protocol from the beginning. The host should not issue a DEVICE RESET command while a DEVICE RESET command is in progress. If the host issues a DEVICE RESET command while a DEVICE RESET command is in progress, the results are indeterminate. Figure 40 and the text following the figure describe the DEVICE RESET command protocol for the host. Figure 41 and the text following the figure describe the DEVICE RESET command protocol for the device. HDR0: Wait DEVICE RESET command written HDR1: Check_status 400 ns timeout complete HDR0:HDR1 HI4:HDR0 BSY = 0 HDR1:HI0 Host_idle BSY = 1 HDR1:HDR1 Figure 40 − Host DEVICE RESET command state diagram HDR0: Wait State: This state is entered when the host has written the DEVICE RESET command to the device. The host shall remain in this state for at least 400 ns. Transition HDR0:HDR1: When at least 400 ns has elapsed since the command was written, the host shall make a transition to the HDR1: Check_status state. HDR1: Check_status State: This state is entered when at least 400 ns has elapsed since the command was written. When in this state the host shall read the Status register. Transition HDR1:HDR1: When BSY is set to one, the host shall make a transition to the HDR1: Check_status state. Page 364 T13/1410D revision 3b Transition HDR1:HI0: When BSY is cleared to zero, the host shall make a transition to the HI0: Host_idle state (see Figure 19). If status indicates that an error has occurred, the host shall take appropriate action. DDR0: Release_bus DEVICE RESET command written DDR1: Set_status Status set DDR1:DI1 BSY=0 Bus released DDR0:DDR1 DI0:DDR0 DI1:DDR0 BSY 1 DRQ 0 REL 0 SERV 0 C/D 0 I/O 0 INTRQ N DMARQ R Device_idle_S PDIAGR DASPR Figure 41 − Device DEVICE RESET command state diagram DDR0: Release_bus State: This state is entered when the DEVICE RESET command is written. When in this state, the device shall release INTRQ, IORDY, DMARQ, and DD(15:0) within 400 ns after entering this state. The device shall set BSY to one within 400 ns after entering this state. Transition DDR0:DDR1: When the bus has been released and BSY set to one, the device shall make a transition to the DDR1: Set_status state. DDR1: Set_status State: This state is entered when the device has released the bus and set BSY to one. When in this state the device should stop execution of any uncompleted command. The device should end background activity (e.g., immediate commands, see MMC and MMC-2). The device should not revert to the default condition. If the device reverts to the default condition, the device shall report an exception condition by setting CHK to one in the Status register. MODE SELECT conditions shall not be altered. The device shall set the signature values (see 9.12). The content of the Features register is undefined. The device shall clear bit 7 in the ERROR register to zero. The device shall clear bits 6, 5, 4, 3, 2, and 0 in the Status register to zero. Transition DDR1:DI1: When the status has been set, the device shall clear BSY to zero and make a transition to the DI1: Device_idle_S state (see Figure 21). 9.12 Signature and persistence A device not implementing the PACKET command feature set shall place the signature in the Command Block registers listed below for power-on reset, hardware reset, software reset, and the EXECUTE DEVICE DIAGNOSTIC command. If the device does not implement the PACKET command feature set, the signature shall be: Sector Count 01h LBA Low 01h LBA Mid 00h LBA High 00h Device 00h Page 365 T13/1410D revision 3b A device implementing the PACKET command feature set shall place the signature in the Command Block registers listed below for power-on reset, hardware reset, software reset, the EXECUTE DEVICE DIAGNOSTIC command, and the DEVICE RESET command. The DEVICE RESET command shall not change the value of the DEV bit when writing the signature into the Device register for a device implementing the PACKET command feature set. If the device implements the PACKET command feature set, the signature is also written in the registers for the IDENTIFY DEVICE and READ SECTOR(S) commands. If the device implements the PACKET command feature set, the signature shall be: Sector Count 01h LBA Low 01h LBA Mid 14h LBA High EBh Device 000x0000b where x equals 0 except when responding to a DEVICE RESET, IDENTIFY DEVICE, or READ SECTOR(S) command. For a DEVICE RESET, IDENTIFY DEVICE, or READ SECTOR(S) command the value of x is not changed from that existing when the command is written to the Command register. If the PACKET command feature set is implemented by a device, then the signature values written by the device in the Command Block registers following power-on reset, hardware reset, software reset, or the DEVICE RESET command shall not be changed by the device until the device receives a command that sets DRDY to one. Writes by the host to the Command Block registers that contain the signature values shall overwrite the signature values and invalidate the signature. 9.13 Ultra DMA data-in commands 9.13.1 Initiating an Ultra DMA data-in burst The following steps shall occur in the order they are listed unless otherwise specified. Timing requirements are shown in 10.2.4 and10.2.4.1. a) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated. b) The device shall assert DMARQ to initiate an Ultra DMA burst when DMACK- is negated. After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE. c) Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP. d) The host shall negate HDMARDY-. e) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst. f) Steps (c), (d), and (e) shall have occurred at least tACK before the host asserts DMACK-. The host shall keep DMACK- asserted until the end of an Ultra DMA burst. g) The host shall release DD(15:0) within tAZ after asserting DMACK-. h) The device may assert DSTROBE tZIORDY after the host has asserted DMACK-. Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at the end of an Ultra DMA burst. i) The host shall negate STOP and assert HDMARDY- within tENV after asserting DMACK-. After negating STOP and asserting HDMARDY-, the host shall not change the state of either signal until after receiving the first negation of DSTROBE from the device (i.e., after the first data word has been received). j) The device shall drive DD(15:0) no sooner than tZAD after the host has asserted DMACK-, negated STOP, and asserted HDMARDY-. k) The device shall drive the first word of the data transfer onto DD(15:0). This step may occur when the device first drives DD(15:0) in step (j). l) To transfer the first word of data the device shall negate DSTROBE within tFS after the host has negated STOP and asserted HDMARDY-. The device shall negate DSTROBE no sooner than tDVS after driving the first word of data onto DD(15:0). Page 366 T13/1410D revision 3b 9.13.2 The data-in transfer The following steps shall occur in the order they are listed unless otherwise specified. Timing requirements are shown in 10.2.4 and 10.2.4.2. a) The device shall drive a data word onto DD(15:0). b) The device shall generate a DSTROBE edge to latch the new word no sooner than tDVS after changing the state of DD(15:0). The device shall generate a DSTROBE edge no more frequently than tCYC for the selected Ultra DMA mode. The device shall not generate two rising or two falling DSTROBE edges more frequently than t2cyc for the selected Ultra DMA mode. c) The device shall not change the state of DD(15:0) until at least tDVH after generating a DSTROBE edge to latch the data. d) The device shall repeat steps (a), (b), and (c) until the Ultra DMA burst is paused or terminated by the device or host. 9.13.3 Pausing an Ultra DMA data-in burst The following steps shall occur in the order they are listed unless otherwise specified. Timing requirements are shown in 10.2.4 and 10.2.4.3. 9.13.3.1 Device pausing an Ultra DMA data-in burst a) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred. b) The device shall pause an Ultra DMA burst by not generating additional DSTROBE edges. If the host is ready to terminate the Ultra DMA burst (see 9.13.4.2). c) The device shall resume an Ultra DMA burst by generating a DSTROBE edge. 9.13.3.2 Host pausing an Ultra DMA data-in burst a) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred. b) The host shall pause an Ultra DMA burst by negating HDMARDY-. c) The device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY-. d) When operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one, or two additional data words after negating HDMARDY-. While operating in Ultra DMA modes 5, 4, or 3 the host shall be prepared to receive zero, one, two, or three additional data words after negating HDMARDY-. The additional data words are a result of cable round trip delay and tRFS timing for the device. e) The host shall resume an Ultra DMA burst by asserting HDMARDY-. 9.13.4 Terminating an Ultra DMA data-in burst 9.13.4.1 Device terminating an Ultra DMA data-in burst Burst termination is completed when the termination protocol has been executed and DMACK- negated. The device shall terminate an Ultra DMA burst before command completion. The following steps shall occur in the order they are listed unless otherwise specified. Timing requirements are shown in 10.2.4 and 10.2.4.4. a) The device shall initiate termination of an Ultra DMA burst by not generating additional DSTROBE edges. b) The device shall negate DMARQ no sooner than tSS after generating the last DSTROBE edge. The device shall not assert DMARQ again until after DMACK- has been negated. c) The device shall release DD(15:0) no later than tAZ after negating DMARQ. Page 367 T13/1410D revision 3b d) The host shall assert STOP within tLI after the device has negated DMARQ. The host shall not negate STOP again until after the Ultra DMA burst is terminated. e) The host shall negate HDMARDY- within tLI after the device has negated DMARQ. The host shall continue to negate HDMARDY- until the Ultra DMA burst is terminated. Steps (d) and (e) may occur at the same time. f) The host shall drive DD(15:0) no sooner than tZAH after the device has negated DMARQ. For this step, the host may first drive DD(15:0) with the result of the host CRC calculation (see 9.15); g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra DMA burst is terminated. h) If the host has not placed the result of the host CRC calculation on DD(15:0) since first driving DD(15:0) during (f), the host shall place the result of the host CRC calculation on DD(15:0) (see 9.15). i) The host shall negate DMACK- no sooner than tMLI after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than tDVS after the host places the result of the host CRC calculation on DD(15:0). j) The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-. k) The device shall compare the CRC data received from the host with the results of the device CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command the device shall report the first error that occurred (see 9.15). l) The device shall release DSTROBE within tIORDYZ after the host negates DMACK-. m) The host shall not negate STOP nor assert HDMARDY- until at least tACK after negating DMACK-. n) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating DMACK. 9.13.4.2 Host terminating an Ultra DMA data-in burst The following steps shall occur in the order they are listed unless otherwise specified. Timing requirements are shown in 10.2.4 and 10.2.4.5. a) The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred. b) The host shall initiate Ultra DMA burst termination by negating HDMARDY-. The host shall continue to negate HDMARDY- until the Ultra DMA burst is terminated. c) The device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY-. d) When operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two additional data words after negating HDMARDY-. While operating in Ultra DMA modes 5, 4, or 3 the host shall be prepared to receive zero, one, two, or three additional data words after negating HDMARDY-. The additional data words are a result of cable round trip delay and tRFS timing for the device. e) The host shall assert STOP no sooner than tRP after negating HDMARDY-. The host shall not negate STOP again until after the Ultra DMA burst is terminated. f) The device shall negate DMARQ within tLI after the host has asserted STOP. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated. g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra DMA burst is terminated. h) The device shall release DD(15:0) no later than tAZ after negating DMARQ. i) The host shall drive DD(15:0) no sooner than tZAH after the device has negated DMARQ. For this step, the host may first drive DD(15:0) with the result of the host CRC calculation (see 9.15). j) If the host has not placed the result of the host CRC calculation on DD(15:0) since first driving DD(15:0) during (9), the host shall place the result of the host CRC calculation on DD(15:0) (see 9.15). k) The host shall negate DMACK- no sooner than tMLI after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than tDVS after the host places the result of the host CRC calculation on DD(15:0). l) The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-. m) The device shall compare the CRC data received from the host with the results of the device CRC calculation. If a miscompare error occurs during one or more Ultra DMA burst for any one command, at the end of the command, the device shall report the first error that occurred (see 9.15) . Page 368 T13/1410D revision 3b n) The device shall release DSTROBE within tIORDYZ after the host negates DMACK-. o) The host shall neither negate STOP nor assert HDMARDY- until at least tACK after the host has negated DMACK-. p) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating DMACK. 9.14 Ultra DMA data-out commands 9.14.1 Initiating an Ultra DMA data-out burst The following steps shall occur in the order they are listed unless otherwise specified. Timing requirements are shown in 10.2.4 and 10.2.4.6. a) b) c) d) e) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated. The device shall assert DMARQ to initiate an Ultra DMA burst when DMACK- is negated. Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP. The host shall assert HSTROBE. The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst. f) Steps (c), (d), and (e) shall have occurred at least tACK before the host asserts DMACK-. The host shall keep DMACK- asserted until the end of an Ultra DMA burst. g) The device may negate DDMARDY- tZIORDY after the host has asserted DMACK-. Once the device has negated DDMARDY-, the device shall not release DDMARDY- until after the host has negated DMACK- at the end of an Ultra DMA burst. h) The host shall negate STOP within tENV after asserting DMACK-. The host shall not assert STOP until after the first negation of HSTROBE. i) The device shall assert DDMARDY- within tLI after the host has negated STOP. After asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host. j) The host shall drive the first word of the data transfer onto DD(15:0). This step may occur any time during Ultra DMA burst initiation. k) To transfer the first word of data: the host shall negate HSTROBE no sooner than tUI after the device has asserted DDMARDY-. The host shall negate HSTROBE no sooner than tDVS after the driving the first word of data onto DD(15:0). 9.14.2 The data-out transfer The following steps shall occur in the order they are listed unless otherwise specified. Timing requirements are shown in 10.2.4 and 10.2.4.7. a) The host shall drive a data word onto DD(15:0). b) The host shall generate an HSTROBE edge to latch the new word no sooner than tDVS after changing the state of DD(15:0). The host shall generate an HSTROBE edge no more frequently than tCYC for the selected Ultra DMA mode. The host shall not generate two rising or falling HSTROBE edges more frequently than t2cyc for the selected Ultra DMA mode. c) The host shall not change the state of DD(15:0) until at least tDVH after generating an HSTROBE edge to latch the data. d) The host shall repeat steps (a), (b), and (c) until the Ultra DMA burst is paused or terminated by the device or host. 9.14.3 Pausing an Ultra DMA data-out burst The following steps shall occur in the order they are listed unless otherwise specified. Timing requirements are shown in 10.2.4 and 10.2.4.8. Page 369 T13/1410D revision 3b 9.14.3.1 Host pausing an Ultra DMA data-out burst a) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred. b) The host shall pause an Ultra DMA burst by not generating an HSTROBE edge. If the host is ready to terminate the Ultra DMA burst (see 9.14.4.1). c) The host shall resume an Ultra DMA burst by generating an HSTROBE edge. 9.14.3.2 Device pausing an Ultra DMA data-out burst a) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred. b) The device shall pause an Ultra DMA burst by negating DDMARDY-. c) The host shall stop generating HSTROBE edges within tRFS of the device negating DDMARDY-. d) When operating in Ultra DMA modes 2, 1, or 0 the device shall be prepared to receive zero, one or two additional data words after negating DDMARDY-. While operating in Ultra DMA modes 5, 4 or 3 the device shall be prepared to receive zero, one, two or three additional data words after negating DDMARDY-. The additional data words are a result of cable round trip delay and tRFS timing for the host. e) The device shall resume an Ultra DMA burst by asserting DDMARDY-. 9.14.4 Terminating an Ultra DMA data-out burst 9.14.4.1 Host terminating an Ultra DMA data-out burst The following steps shall occur in the order they are listed unless otherwise specified. Timing requirements are shown in 10.2.4 and 10.2.4.9. a) The host shall initiate termination of an Ultra DMA burst by not generating additional HSTROBE edges. b) The host shall assert STOP no sooner than tSS after the last generated an HSTROBE edge. The host shall not negate STOP again until after the Ultra DMA burst is terminated. c) The device shall negate DMARQ within tLI after the host asserts STOP. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated. d) The device shall negate DDMARDY- within tLI after the host has negated STOP. The device shall not assert DDMARDY- again until after the Ultra DMA burst termination is complete. e) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on HSTROBE. HSTROBE shall remain asserted until the Ultra DMA burst is terminated. f) The host shall place the result of the host CRC calculation on DD(15:0) (see 9.15). g) The host shall negate DMACK- no sooner than tMLI after the host has asserted HSTROBE and STOP and the device has negated DMARQ and DDMARDY-, and no sooner than tDVS after placing the result of the host CRC calculation on DD(15:0). h) The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-. i) The device shall compare the CRC data received from the host with the results of the device CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 9.15). j) The device shall release DDMARDY- within tIORDYZ after the host has negated DMACK-. k) The host shall neither negate STOP nor negate HSTROBE until at least tACK after negating DMACK-. l) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating DMACK. 9.14.4.2 Device terminating an Ultra DMA data-out burst Burst termination is completed when the termination protocol has been executed and DMACK- negated. The device shall terminate an Ultra DMA burst before command completion. Page 370 T13/1410D revision 3b The following steps shall occur in the order they are listed unless otherwise specified. Timing requirements are shown in 10.2.4 and 10.2.4.10. a) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred. b) The device shall initiate Ultra DMA burst termination by negating DDMARDY-. c) The host shall stop generating an HSTROBE edges within tRFS of the device negating DDMARDY-. d) When operating in Ultra DMA modes 2, 1, or 0 the device shall be prepared to receive zero, one or two additional data words after negating DDMARDY-. While operating in Ultra DMA modes 5, 4 or 3 the device shall be prepared to receive zero, one, two or three additional data words after negating DDMARDY-. The additional data words are a result of cable round trip delay and tRFS timing for the host. e) The device shall negate DMARQ no sooner than tRP after negating DDMARDY-. The device shall not assert DMARQ again until after DMACK- is negated. f) The host shall assert STOP within tLI after the device has negated DMARQ. The host shall not negate STOP again until after the Ultra DMA burst is terminated. g) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of HSTROBE. HSTROBE shall remain asserted until the Ultra DMA burst is terminated. h) The host shall place the result of the host CRC calculation on DD(15:0) (see 9.15). i) The host shall negate DMACK- no sooner than tMLI after the host has asserted HSTROBE and STOP and the device has negated DMARQ and DDMARDY-, and no sooner than tDVS after placing the result of the host CRC calculation on DD(15:0). j) The device shall latch the host’s CRC data from DD(15:0) on the negating edge of DMACK-. k) The device shall compare the CRC data received from the host with the results of the device CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 9.15). l) The device shall release DDMARDY- within tIORDYZ after the host has negated DMACK-. m) The host shall neither negate STOP nor HSTROBE until at least tACK after negating DMACK-. n) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating DMACK. 9.15 Ultra DMA CRC rules The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command. 1) Both the host and the device shall have a 16-bit CRC calculation function. 2) Both the host and the device shall calculate a CRC value for each Ultra DMA burst. 3) The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred. 4) For each STROBE transition used for data transfer, both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual CRC functions and the word being transferred. CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged. 5) At the end of any Ultra DMA burst the host shall send the results of the host CRC calculation function to the device on DD(15:0) with the negation of DMACK-. 6) The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function. If the two values do not match, the device shall save the error. A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an error saved from a previous Ultra DMA burst in the same command. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, the device shall report the first error that occurred. If the device detects that a CRC error has occurred before data transfer for the command is complete, the device may complete the transfer and report the error or abort the command and report the error. 7) For READ DMA, WRITE DMA, READ DMA QUEUED, or WRITE DMA QUEUED commands: When a CRC error is detected, the error shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error register) to one. ICRC is defined as the Interface CRC Error bit. The host shall respond to this error by re-issuing the command. Page 371 T13/1410D revision 3b 8) For a REQUEST SENSE packet command (see SPC NCITS 301:1997 for definition of the REQUEST SENSE command): When a CRC error is detected during transmission of sense data the device shall complete the command and set CHK to one. The device shall report a Sense key of 0Bh (ABORTED COMMAND). The device shall preserve the original sense data that was being returned when the CRC error occurred. The device shall not report any additional sense data specific to the CRC error. The host device driver may retry the REQUEST SENSE command or may consider this an unrecoverable error and retry the command that caused the Check Condition. 9) For any packet command except a REQUEST SENSE command: If a CRC error is detected, the device shall complete the command with CHK set to one. The device shall report a Sense key of 04h (HARDWARE ERROR). The sense data supplied via a subsequent REQUEST SENSE command shall report an ASC/ASCQ value of 08h/03h (LOGICAL UNIT COMMUNICATION CRC ERROR). Host drivers should retry the command that resulted in a HARDWARE ERROR. 10) A host may send extra data words on the last Ultra DMA burst of a data-out command. If a device determines that all data has been transferred for a command, the device shall terminate the burst. A device may have already received more data words than were required for the command. These extra words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA data-out burst, the extra words shall be discarded by the device. 11) The CRC generator polynomial is: G(X) = X16 + X12 + X5 + 1. Table 65 describes the equations for 16-bit parallel generation of the resulting polynomial (based on a word boundary). NOTE − Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic is then equivalent to shifting sixteen bits serially through the generator polynomial where DD0 is shifted in first and DD15 is shifted in last. NOTE − If excessive CRC errors are encountered while operating in an Ultra mode, the host should select a slower Ultra mode. Caution: CRC errors are detected and reported only while operating in an Ultra mode. DD(15:0) CRCOUT (15:0) CRCIN (15:0:) Combinational Logic Edge Triggered Register Device f1-f16 Word Clock Figure 42 − Example Parallel CRC generator Page 372 T13/1410D revision 3b Table 65 − Equations for parallel generation of a CRC polynomial CRCIN0 = f16 CRCIN8 = f8 XOR f13 CRCIN1 = f15 CRCIN9 = f7 XOR f12 CRCIN2 = f14 CRCIN10 = f6 XOR f11 CRCIN3 = f13 CRCIN11 = f5 XOR f10 CRCIN4 = f12 CRCIN12 = f4 XOR f9 XOR f16 CRCIN5 = f11 XOR f16 CRCIN13 = f3 XOR f8 XOR f15 CRCIN6 = f10 XOR f15 CRCIN14 = f2 XOR f7 XOR f14 CRCIN7 = f9 XOR f14 CRCIN15 = f1 XOR f6 XOR f13 f1 = DD0 XOR CRCOUT15 f9 = DD8 XOR CRCOUT7 XOR f5 f2 = DD1 XOR CRCOUT14 f10 = DD9 XOR CRCOUT6 XOR f6 f3 = DD2 XOR CRCOUT13 f11 = DD10 XOR CRCOUT5 XOR f7 f4 = DD3 XOR CRCOUT12 f12 = DD11 XOR CRCOUT4 XOR f1 XOR f8 f5 = DD4 XOR CRCOUT11 XOR f1 f13 = DD12 XOR CRCOUT3 XOR f2 XOR f9 f6 = DD5 XOR CRCOUT10 XOR f2 f14 = DD13 XOR CRCOUT2 XOR f3 XOR f10 f7 = DD6 XOR CRCOUT9 XOR f3 f15 = DD14 XOR CRCOUT1 XOR f4 XOR f11 f8 = DD7 XOR CRCOUT8 XOR f4 f16 = DD15 XOR CRCOUT0 XOR f5 XOR f12 NOTES − 1 f = feedback 2 DD = Data to or from the bus 3 CRCOUT = 16-bit edge triggered result (current CRC) 4 CRCOUT(15:0) are sent on matching order bits of DD(15:0) 5 CRCIN = Output of combinatorial logic (next CRC) 9.16 Single device configurations 9.16.1 Device 0 only configurations In a single device configuration where Device 0 is the only device and the host selects Device 1, Device 0 shall respond as follows: 1) A write to the Device Control register shall complete as if Device 0 was the selected device; 2) A write to a Command Block register, other than the Command register, shall complete as if Device 0 was selected; 3) A write to the Command register shall be ignored, except for EXECUTE DEVICE DIAGNOSTIC; 4) If the device does not implement the PACKET Command feature set, a read of the Control Block or Command Block registers, other than the Status or Alternate Status registers, shall complete as if Device 0 was selected. A read of the Status or Alternate status register shall return the value 00h.; 5) If the device implements the PACKET Command feature set, a read of the Control Block or Command Block registers shall return the value 00h. NOTE − Even though Device 1 is not present, the register content may appear valid for Device 1. Further means may be necessary to determine the existence of Device 1 (e.g., issuing a command). 9.16.2 Device 1 only configurations Host support of Device 1 only configurations is host specific. In a single device configuration where Device 1 is the only device and the host selects Device 0, Device 1 shall respond to accesses of the Command Block and Control Block registers in the same way it would if Device 0 was present. This is because Device 1 cannot determine if Device 0 is, or is not, present. Page 373 T13/1410D revision 3b Host implementation of read and write operations to the Command and Control Block registers of non-existent Device 0 are host specific. NOTE − The remainder of this subclause is a recommendation for hosts. The host implementor should be aware of the following when supporting Device 1 only configurations: 1) Following a hardware reset or software reset, the following steps may be used to reselect Device 1: a) Write to the Device register with DEV bit set to one; b) Using one or more of the Command Block registers that may be both written and read, such as the Sector Count or LBA Low, write a data pattern other than 00h or FFh to the register(s); c) Read the register(s) written in step (b). If the data read is the same as the data written, proceed to step (e); d) Repeat steps (a) to (c) until the data matches in step (c) or until 31 s has past. After 31 s the host may assume that Device 1 is not functioning properly; e) Read the Status register and Error registers. Check the Status and Error register contents for any error conditions that Device 1 may have posted. 2) Following the execution of an EXECUTE DEVICE DIAGNOSTIC command, no interrupt pending should be set to signal command completion. After writing the EXECUTE DEVICE DIAGNOSTIC command to the Command register, execute steps (a) to (e) as described in (1) above; 3) At all other times, do not write zero into the DEV bit of the Device register. All other commands execute normally. 10 Timing 10.1 Deskewing For PIO and Multiword DMA modes all timing values shall be measured at the connector of the selected device. The host shall account for cable skew. For Ultra DMA modes unless otherwise specified, timing parameters shall be measured at the connector of the host or device to which the parameter applies. 10.2 Transfer timing The minimum cycle time supported by the device in PIO mode 3, 4 and Multiword DMA mode 1, 2 respectively shall always be greater than or equal to the minimum cycle time defined by the associated mode e.g., a device supporting PIO mode 4 timing shall not report a value less than 120 ns, the minimum cycle time defined for PIO mode 4 timings. See 3.2.8 for timing diagram conventions. 10.2.1 Register transfers Figure 43 defines the relationships between the interface signals for register transfers. Peripherals reporting support for PIO mode 3 or 4 shall power-up in a PIO mode 0, 1, or 2. For PIO modes 3 and above, the minimum value of t0 is specified by word 68 in the IDENTIFY DEVICE parameter list. Table 66 defines the minimum value that shall be placed in word 68. Both hosts and devices shall support IORDY when PIO mode 3 or 4 are the currently selected mode of operation. Page 374 T13/1410D revision 3b t0 ADDR valid (See note 1) t2 t1 t9 t2i DIOR-/DIOWWRITE DD(7:0) (See note 2) t3 t4 READ DD(7:0) (See note 2) t5 t6 t6z IORDY (See note 3,3-1) IORDY (See note 3,3-2) IORDY (See note 3,3-3) tA tC tRD tB tC NOTES − 1 Device address consists of signals CS0-, CS1-, and DA(2:0) 2 Data consists of DD(7:0). 3 The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made by the host after tA from the assertion of DIOR- or DIOW-. The assertion and negation of IORDY are described in the following three cases: 3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated. 3-2 Device negates IORDY before tA, but causes IORDY to be asserted before t A. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: no wait generated. 3-3 Device negates IORDY before tA. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIOR- is asserted, the device shall place read data on DD(7:0) for tRD before asserting IORDY. 4 DMACK- shall remain negated during a register transfer. Figure 43 − Register transfer to/from device Page 375 T13/1410D revision 3b Table 66 − Register transfer to/from device Register transfer timing parameters Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Note ns ns ns ns ns t0 Cycle time (min) 600 383 330 180 120 1,4,5 t1 Address valid to DIOR-/DIOW- (min) 70 50 30 30 25 setup t2 DIOR-/DIOW- pulse width 8-bit (min) 290 290 290 80 70 1 t2i DIOR-/DIOW- recovery time (min) 70 25 1 t3 DIOW- data setup (min) 60 45 30 30 20 t4 DIOW- data hold (min) 30 20 15 10 10 t5 DIOR- data setup (min) 50 35 20 20 20 t6 DIOR- data hold (min) 5 5 5 5 5 t6Z DIOR- data release (max) 30 30 30 30 30 2 t9 DIOR-/DIOW- to address valid hold (min) 20 15 10 10 10 tRD Read Data Valid to IORDY active (min) 0 0 0 0 0 (if IORDY initially low after tA) tA IORDY Setup time 35 35 35 35 35 3 tB IORDY Pulse Width (max) 1250 1250 1250 1250 1250 tC IORDY assertion to release (max) 5 5 5 5 5 NOTES − 1 t0 is the minimum total cycle time, t2 is the minimum DIOR-/DIOW- assertion time, and t2i is the minimum DIOR-/DIOW- negation time. A host implementation shall lengthen t2 and/or t2i to ensure that t0 is equal to or greater than the value reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation. 2 This parameter specifies the time from the negation edge of DIOR- to the time that the data bus is released by the device. 3 The delay from the activation of DIOR- or DIOW- until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at the tA after the activation of DIOR- or DIOW-, then t5 shall be met and tRD is not applicable. If the device is driving IORDY negated at the time tA after the activation of DIOR- or DIOW-, then tRD shall be met and t5 is not applicable. 4 ATA/ATAPI standards prior to ATA/ATAPI-5 inadvertently specified an incorrect value for mode 2 time t0 by utilizing the 16-bit PIO value 5 Mode shall be selected no higher than the highest mode supported by the slowest device. 10.2.2 PIO data transfers Figure 44 defines the relationships between the interface signals for PIO data transfers. Peripherals reporting support for PIO mode 3 or 4 shall power-up in a PIO mode 0, 1, or 2. For PIO modes 3 and above, the minimum value of t0 is specified by word 68 in the IDENTIFY DEVICE parameter list. Table 67 defines the minimum value that shall be placed in word 68. IORDY shall be supported when PIO mode 3 or 4 are the current mode of operation. NOTE − Some devices implementing the PACKET Command feature set prior to ATA/ATAPI-4 power-up in PIO mode 3 and enable IORDY as the default. Page 376 T13/1410D revision 3b t0 ADDR valid (See note 1) t2 t1 t9 t2i DIOR-/DIOWWRITE DD(15:0) DD(7:0) (See note 2) t3 READ DD(15:0) DD(7:0) (See note 2) t4 t5 t6 t6z IORDY (See note 3,3-1) IORDY (See note 3,3-2) IORDY (See note 3,3-3) tA tC tRD tB tC NOTES − 1 Device address consists of signals CS0-, CS1-, and DA(2:0) 2 Data consists of DD(15:0) for all devices except devices implementing the CFA feature set when 8-bit transfers is enabled. In that case, data consists of DD(7:0). 3 The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the cycle is to be extended is made by the host after t A from the assertion of DIOR- or DIOW-. The assertion and negation of IORDY are described in the following three cases: 3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated. 3-2 Device negates IORDY before tA, but causes IORDY to be asserted before t A. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: no wait generated. 3-3 Device negates IORDY before tA. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIOR- is asserted, the device shall place read data on DD(7:0) for tRD before asserting IORDY. 4 DMACK- shall be negated during a PIO data transfer. Figure 44 − PIO data transfer to/from device Page 377 T13/1410D revision 3b Table 67 − PIO data transfer to/from device PIO timing parameters Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Note ns ns ns ns ns t0 Cycle time (min) 600 383 240 180 120 1,4 t1 Address valid to DIOR-/DIOW- (min) 70 50 30 30 25 setup t2 DIOR-/DIOW(min) 165 125 100 80 70 1 t2i DIOR-/DIOW- recovery time (min) 70 25 1 t3 DIOW- data setup (min) 60 45 30 30 20 t4 DIOW- data hold (min) 30 20 15 10 10 t5 DIOR- data setup (min) 50 35 20 20 20 t6 DIOR- data hold (min) 5 5 5 5 5 t6Z DIOR- data release (max) 30 30 30 30 30 2 t9 DIOR-/DIOW- to address valid hold (min) 20 15 10 10 10 tRD Read Data Valid to IORDY active (min) 0 0 0 0 0 (if IORDY initially low after tA) tA IORDY Setup time 35 35 35 35 35 3 tB IORDY Pulse Width (max) 1250 1250 1250 1250 1250 tC IORDY assertion to release (max) 5 5 5 5 5 NOTES − 1 t0 is the minimum total cycle time, t2 is the minimum DIOR-/DIOW- assertion time, and t2i is the minimum DIOR-/DIOW- negation time. A host implementation shall lengthen t2 and/or t2i to ensure that t0 is equal to or greater than the value reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation. 2 This parameter specifies the time from the negation edge of DIOR- to the time that the data bus is released by the device. 3 The delay from the activation of DIOR- or DIOW- until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle is completed. If the device is not driving IORDY negated at the tA after the activation of DIOR- or DIOW-, then t5 shall be met and tRD is not applicable. If the device is driving IORDY negated at the time tA after the activation of DIOR- or DIOW-, then tRD shall be met and t5 is not applicable. 4 Mode may be selected at the highest mode for the device if CS(1:0) and DA(2:0) do not change between read or write cycles or selected at the highest mode supported by the slowest device if CS(1:0) or DA(2:0) do change between read or write cycles. Page 378 T13/1410D revision 3b 10.2.3 Multiword DMA data transfer Figure 45 through Figure 48 define the timing associated with Multiword DMA transfers. For Multiword DMA modes 1 and above, the minimum value of t0 is specified by word 65 in the IDENTIFY DEVICE parameter list. Table 68 defines the minimum value that shall be placed in word 65. Devices shall power-up with mode 0 as the default Multiword DMA mode. Table 68 − Multiword DMA data transfer Multiword DMA timing parameters Mode 0 Mode 1 Mode 2 Note ns ns ns t0 Cycle time (min) 480 150 120 see note tD DIOR-/DIOW- asserted pulse width (min) 215 80 70 see note tE DIOR- data access (max) 150 60 50 tF DIOR- data hold (min) 5 5 5 tG DIOR-/DIOW- data setup (min) 100 30 20 tH DIOW- data hold (min) 20 15 10 tI DMACK to DIOR-/DIOW- setup (min) 0 0 0 tJ DIOR-/DIOW- to DMACK hold (min) 20 5 5 tKR DIOR- negated pulse width (min) 50 50 25 see note tKW DIOW- negated pulse width (min) 215 50 25 see note tLR DIOR- to DMARQ delay (max) 120 40 35 tLW DIOW- to DMARQ delay (max) 40 40 35 tM CS(1:0) valid to DIOR-/DIOW(min) 50 30 25 tN CS(1:0) hold (min) 15 10 10 tZ DMACK- to read data released (max) 20 25 25 NOTE − t0 is the minimum total cycle time, tD is the minimum DIOR-/DIOW- assertion time, and tK (t KR or tKW, as appropriate) is the minimum DIOR-/DIOW- negation time. A host shall lengthen tD and/or tK to ensure that t0 is equal to the value reported in the devices IDENTIFY DEVICE data. 10.2.3.1 Initiating a Multiword DMA data burst The values for the timings for each of the Multiword DMA modes are contained in Table 68. Page 379 T13/1410D revision 3b CS0-/CS1tM See note DMARQ See note DMACKtD tI DIOR-/DIOWtE Read DD(15:0) tG Write DD(15:0) tG tF tH NOTE − The host shall not assert DMACK- or negate both CS0 and CS1 until the assertion of DMARQ is detected. The maximum time from the assertion of DMARQ to the assertion of DMACK- or the negation of both CS0 and CS1 is not defined. Figure 45 − Initiating a Multiword DMA data burst Page 380 T13/1410D revision 3b 10.2.3.2 Sustaining a Multiword DMA data burst The values for the timings for each of the Multiword DMA modes are contained in Table 68. CS0-/CS1t0 DMARQ DMACKtK tD DIOR-/DIOWRead DD(15:0) Write DD(15:0) tE tE tG tG tF tH tG tG tF tH F igure 46 − Sustaining a Multiword DMA data burst Page 381 T13/1410D revision 3b 10.2.3.3 Device terminating a Multiword DMA data burst The values for the timings for each of the Multiword DMA modes are contained in Table 68. CS0-/CS1tN t0 DMARQ (See note) tL DMACKtK tD tJ DIOR-/DIOWtZ tE Read DD(15:0) tG tF Write DD(15:0) tG tH NOTE − To terminate the data burst, the Device shall negate DMARQ within tL of the assertion of the current DIOR- or DIOW- pulse. The last data word for the burst shall then be transferred by the negation of the current DIOR- or DIOW- pulse. If all data for the command has not been transferred, the device shall reassert DMARQ again at any later time to resume the DMA operation as shown in figure 44. Figure 47 − Device terminating a Multiword DMA data burst Page 382 T13/1410D revision 3b 10.2.3.4 Host terminating a Multiword DMA data burst The values for the timings for each of the Multiword DMA modes are contained in Table 68. CS0-/CS1tN t0 DMARQ (See note 2) DMACK(See note 1) tK tD tJ DIOR-/DIOWtE Read DD(15:0) Write DD(15:0) tZ tG tG tF tH NOTE − 1 To terminate the transmission of a data burst, the host shall negate DMACK- within tJ after a DIOR- or DIOW- pulse. No further DIOR- or DIOW- pulses shall be asserted for this burst. 2 If the device is able to continue the transfer of data, the device may leave DMARQ asserted and wait for the host to reassert DMACK- or may negate DMARQ at any time after detecting that DMACKhas been negated. Figure 48 − Host terminating a Multiword DMA data burst Page 383 T13/1410D revision 3b 10.2.4 Ultra DMA data transfer Figure 49 through Figure 58 define the timings associated with all phases of Ultra DMA bursts. Table 69 contains the values for the timings for each of the Ultra DMA modes. Table 70 contains descriptions and comments for each of the timing values in Table 69. Table 71 contains timings specified for the IC alone. All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V. Name Mode 0 (in ns) Min Max 240 112 230 15.0 5.0 70.0 6.2 15.0 5.0 70.0 6.2 0 70.0 230 0 150 20 0 10 20 0 20 70 75 160 20 0 20 50 Table 69 − Ultra DMA Mode 1 Mode 2 (in ns) (in ns) Min Max Min Max 160 120 73 54 153 115 10.0 7.0 5.0 5.0 48.0 31.0 6.2 6.2 10.0 7.0 5.0 5.0 48.0 31.0 6.2 6.2 0 0 48.0 31.0 200 170 0 150 0 150 20 20 0 0 10 10 20 20 0 0 20 70 20 70 70 60 125 100 20 20 0 0 20 20 50 50 data burst timing requirements Mode 3 Mode 4 Mode 5 (in ns) (in ns) (in ns) Min Max Min Max Min Max 90 60 40 39 25 16.8 86 57 38 7.0 5.0 4.0 5.0 5.0 4.6 20.0 6.7 4.8 6.2 6.2 4.8 7.0 5.0 5.0 5.0 5.0 5.0 20.0 6.7 10.0 6.2 6.2 10.0 0 0 35 20.0 6.7 25 130 120 90 0 100 0 100 0 75 20 20 20 0 0 0 10 10 10 20 20 20 0 0 0 20 55 20 55 20 50 60 60 50 100 100 85 20 20 20 0 0 0 20 20 20 50 50 50 Measurement location. t2CYCTYP Sender tCYC Recipient t2CYC Sender tDS Recipient tDH Recipient tDVS Sender tDVH Sender tCS Device tCH Device tCVS Host tCVH Host tZFS Device tDZFS Sender tFS Device tLI Note 2 tMLI Host tUI Host tAZ Note 3 tZAH Host tZAD Device tENV Host tRFS Sender tRP Recipient tIORDYZ Device tZIORDY Device tACK Host tSS Sender NOTES − 1 All signal transitions for a timing parameter shall be measured at the connector specified in the measurement location column. For example, in the case of tRFS, both STROBE and DMARDY- transitions are measured at the sender connector. 2 The parameter tLI shall be measured at the connector of the sender or recipient that is responding to an incoming transition from the recipient or sender respectively. Both the incoming signal and the outgoing response shall be measured at the same connector. 3 The parameter tAZ shall be measured at the connector of the sender or recipient that is releasing the bus. Page 384 T13/1410D revision 3b Table 70 − Ultra DMA data burst timing descriptions Name Comment t2CYCTY Typical sustained average two cycle time P tCYC t2CYC Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge) Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of STROBE) tDS Data setup time at recipient (from data valid until STROBE edge) (see note 2,5) tDH Data hold time at recipient (from STROBE edge until data may become invalid) (see note 2,5) tDVS Data valid setup time at sender (from data valid until STROBE edge) (see Note 3) tDVH Data valid hold time at sender (from STROBE edge until data may become invalid) (see Note 3) tCS CRC word setup time at device (see note 2) tCH CRC word hold time device (see note 2) tCVS CRC word valid setup time at host (from CRC valid until DMACK- negation) (see Note 3) tCVH CRC word valid hold time at sender (from DMACK- negation until CRC may become invalid) (see Note 3) tZFS Time from STROBE output released-to-driving until the first transition of critical timing. tDZFS Time from data output released-to-driving until the first transition of critical timing. tFS First STROBE time (for device to first negate DSTROBE from STOP during a data in burst) tLI Limited interlock time (see Note 1) tMLI Interlock time with minimum (see Note 1) tUI Unlimited interlock time (see Note 1) tAZ Maximum time allowed for output drivers to release (from asserted or negated) tZAH Minimum delay time required for output tZAD drivers to assert or negate (from released) tENV Envelope time (from DMACK- to STOP and HDMARDY- during data in burst initiation and from DMACK to STOP during data out burst initiation) tRFS Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of DMARDY-) tRP Ready-to-pause time (that recipient shall wait to pause after negating DMARDY-) tIORDYZ Maximum time before releasing IORDY tZIORDY Minimum time before driving IORDY (see note 4) tACK Setup and hold times for DMACK- (before assertion or negation) tSS Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst) NOTES − 1 The parameters tUI, tMLI (in Figure 52 and Figure 53), and tLI indicate sender-to-recipient or recipient-tosender interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding. tUI is an unlimited interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum. tLI is a limited time-out that has a defined maximum. 2 80-conductor cabling (see Annex A) shall be required in order to meet setup (t DS, tCS) and hold (t DH, tCH) times in modes greater than 2. 3 Timing for tDVS, tDVH , tCVS and tCVH shall be met for lumped capacitive loads of 15 and 40 pf at the connector where the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these timing measurements are not valid in a normally functioning system. 4 For all modes the parameter tZIORDY may be greater than tENV due to the fact that the host has a pull-up on IORDY- giving it a known state when released. 5 The parameters tDS, and tDH for mode 5 are defined for a recipient at the end of the cable only in a configuration with one device at the end of the cable. Page 385 T13/1410D revision 3b Name tDSIC tDHIC tDVSIC tDVHIC Table 71 − Ultra DMA sender and recipient IC timing requirements Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) Min Max Min Max Min Max Min Max Min Max Min Max 14.7 9.7 6.8 6.8 4.8 2.3 4.8 4.8 4.8 4.8 4.8 2.8 72.9 50.9 33.9 22.6 9.5 6.0 9.0 9.0 9.0 9.0 9.0 6.0 Comment Recipient IC data setup time (from data valid until STROBE edge) (see note 1) Recipient IC data hold time (from STROBE edge until data may become invalid) (see note 1) Sender IC data valid setup time (from data valid until STROBE edge) (see note 2) Sender IC data valid hold time (from STROBE edge until data may become invalid) (see note 2) tDSIC tDHIC tDVSIC tDVHIC NOTES − 1 The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at tDSIC and tDHIC timing (as measured through 1.5 V). 2 The parameters tDVSIC and tDVHIC shall be met for lumped capacitive loads of 15 and 40 pf at the IC where all signals have the same capacitive load value. Noise that may couple onto the output signals from external sources in a normally functioning system has not been included in these values. Page 386 T13/1410D revision 3b 10.2.4.1 Initiating an Ultra DMA data-in burst The values for the timings for each of the Ultra DMA modes are contained in 10.2.4. DMARQ (device) tUI DMACK(host) tACK tZAD STOP (host) HDMARDY(host) tFS tENV tACK tFS tENV tZAD tZIORDY DSTROBE (device) tZFS tDZFS tAZ tDVS tDVH DD(15:0) tACK DA0, DA1, DA2, CS0-, CS1NOTES − 1 See 9.13.1 Initiating an Ultra DMA data-in burst. 2 The definitions for the DIOW-:STOP, DIOR-:HDMARDY-:HSTROBE, and IORDY:DDMARDY-:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 49 − Initiating an Ultra DMA data-in burst Page 387 T13/1410D revision 3b 10.2.4.2 Sustained Ultra DMA data-in burst The values for the timings for each of the Ultra DMA modes are contained in 10.2.4. t2CYC tCYC tCYC t2CYC DSTROBE at device tDVH tDVHIC tDVS tDVH tDVHIC tDVSIC tDVS tDVH tDVHIC tDVSIC DD(15:0) at device DSTROBE at host DD(15:0) at host tDH tDHIC tDS tDSIC tDH tDHIC tDS tDSIC tDH tDHIC NOTES − 1 See 9.13.2 The data in transfer. 2 DD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device. Figure 50 − Sustained Ultra DMA data-in burst Page 388 T13/1410D revision 3b 10.2.4.3 Host pausing an Ultra DMA data-in burst The values for the timings for each of the Ultra DMA modes are contained in 10.2.4. DMARQ (device) DMACK(host) tRP STOP (host) HDMARDY(host) tRFS DSTROBE (device) DD(15:0) (device) NOTES − 1 See 9.13.3.2 Host pausing an Ultra DMA data in burst. 2 The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY- is negated. 3 After negating HDMARDY-, the host may receive zero, one, two, or three more data words from the device. Figure 51 − Host pausing an Ultra DMA data-in burst Page 389 T13/1410D revision 3b 10.2.4.4 Device terminating an Ultra DMA data-in burst The values for the timings for each of the Ultra DMA modes are contained in 10.2.4. DMARQ (device) tMLI DMACK(host) tLI tACK tLI STOP (host) tACK tLI HDMARDY(host) tSS tIORDYZ DSTROBE (device) tZAH tAZ DD(15:0) tCVS tCVH CRC tACK DA0, DA1, DA2, CS0-, CS1NOTES − 1 See 9.13.4.1 Device terminating an Ultra DMA data in burst. 2 The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 52 − Device terminating an Ultra DMA data-in burst Page 390 T13/1410D revision 3b 10.2.4.5 Host terminating an Ultra DMA data-in burst The values for the timings for each of the Ultra DMA modes are contained in 10.2.4. DMARQ (device) tLI tMLI DMACK(host) tZAH tAZ tRP tACK STOP (host) tACK HDMARDY(host) tRFS tLI tMLI tIORDYZ DSTROBE (device) tCVS DD(15:0) tCVH CRC tACK DA0, DA1, DA2, CS0-, CS1NOTES − 1 See 9.13.4.2 Host pausing an Ultra DMA data in burst. 2 The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 53 − Host terminating an Ultra DMA data-in burst Page 391 T13/1410D revision 3b 10.2.4.6 Initiating an Ultra DMA data-out burst The values for the timings for each of the Ultra DMA modes are contained in 10.2.4. DMARQ (device) tUI DMACK(host) tACK tENV STOP (host) tZIORDY tLI tUI DDMARDY(device) tACK HSTROBE (host) tDZFS tDVS tDVH DD(15:0) (host) tACK DA0, DA1, DA2, CS0-, CS1NOTES − 1 See 9.14.1 Initiating an Ultra DMA data out burst. 2 The definitions for the STOP, DDMARDY, and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 54 − Initiating an Ultra DMA data-out burst Page 392 T13/1410D revision 3b 10.2.4.7 Sustained Ultra DMA data-out burst The values for the timings for each of the Ultra DMA modes are contained in 10.2.4. t2CYC tCYC tCYC t2CYC HSTROBE at host tDVH tDVHIC tDVS tDVH tDVHIC tDVSIC tDVS tDVH tDVHIC tDVSIC DD(15:0) at host HSTROBE at device tDH tDHIC tDS tDSIC tDH tDHIC tDS tDSIC tDH tDHIC DD(15:0) at device NOTES − 1 See 9.14.2 The data out transfer. 2 DD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host. Figure 55 − Sustained Ultra DMA data-out burst Page 393 T13/1410D revision 3b 10.2.4.8 Device pausing an Ultra DMA data-out burst The values for the timings for each of the Ultra DMA modes are contained in 10.2.4. tRP DMARQ (device) DMACK(host) STOP (host) DDMARDY(device) tRFS HSTROBE (host) DD(15:0) (host) NOTES − 1 See 9.14.3.2 Device pausing an Ultra DMA data out burst. 2 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t RP after DDMARDY- is negated. 3 After negating DDMARDY-, the device may receive zero, one, two, or three more data words from the host. Figure 56 − Device pausing an Ultra DMA data-out burst Page 394 T13/1410D revision 3b 10.2.4.9 Host terminating an Ultra DMA data-out burst The values for the timings for each of the Ultra DMA modes are contained in 10.2.4. tLI DMARQ (device) tMLI DMACK(host) tLI tSS tACK STOP (host) tLI tIORDYZ DDMARDY(device) tACK HSTROBE (host) tCVS DD(15:0) (host) tCVH CRC tACK DA0, DA1, DA2, CS0-, CS1NOTES − 1 See 9.14.4.1 Host terminating an Ultra DMA data out burst. 2 The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 57 − Host terminating an Ultra DMA data-out burst Page 395 T13/1410D revision 3b 10.2.4.10 Device terminating an Ultra DMA data-out burst The values for the timings for each of the Ultra DMA modes are contained in 10.2.4. DMARQ (device) DMACK(host) tLI tMLI tACK STOP (host) tRP tIORDYZ DDMARDY(device) tRFS tLI tMLI tACK HSTROBE (host) tCVS DD(15:0) (host) tCVH CRC tACK DA0, DA1, DA2, CS0-, CS1NOTES − 1 See 9.14.4.2 Device pausing an Ultra DMA data out burst. 2 The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 58 − Device terminating an Ultra DMA data-out burst Page 396 T13/1410D revision 3b Annex A (normative) Connectors and cable assemblies The device shall implement one of the connector options described in this annex. A.1 40-pin Connector The I/O connector is a 40-pin connector. The header mounted to a host or device is shown in figure A.1 and the dimensions are shown in table A.1. The connector mounted to the end of the cable is shown in figure A.2 and the dimensions are shown in table A.2. Signal assignments on these connectors are shown in table A.3. The pin locations are governed by the cable plug, not the receptacle. The way in which the receptacle is mounted on the printed circuit board affects the pin positions, and pin 1 shall remain in the same relative position. This means the pin numbers of the receptacle may not reflect the conductor number of the plug. The header receptacle may or may not be polarized, and all the signals are relative to pin 20, which is keyed. By using the plug positions as primary, a straight cable can connect devices. As shown in figure A.3, conductor 1 on pin 1 of the plug shall be in the same relative position no matter what the receptacle numbering looks like. If receptacle numbering was followed, the cable would have to twist 180 degrees between a device with top-mounted receptacles, and a device with bottom-mounted receptacles. Page 397 T13/1410D revision 3b A1 ± T1 Pos. 2 A13 max Pos. 40 A3 min A2 ± T2 A14 ± T6 A5 max A6 min A10 ± T5 Pos. 1 Pin 1 Indicator Pos. 20 Pin removed Pos. 39 A8 ± T4 Square or round pin F Detail A Detail A A9 min A12 min A7 max A11 +T5/-T3 A4 ± T3 A10 ± T5 F Section F-F Figure A.1 − Host or device 40-pin I/O header Table A.1 − Host or device 40-pin I/O header Dimension Millimeters Inches A1 58.17 2.290 A2 48.26 1.900 A3 56.01 2.205 A4 5.84 0.230 A5 9.55 0.376 A6 6.22 0.245 A7 10.16 0.400 A8 0.64 0.025 A9 4.06 0.160 A 10 2.54 0.100 A 11 6.35 0.250 A 12 6.48 0.255 A 13 0.33 0.013 A 14 0.58 0.023 T1 0.51 0.020 T2 0.13 0.005 T3 0.25 0.010 T4 0.03 0.001 T5 0.08 0.003 T6 0.18 0.007 Page 398 T13/1410D revision 3b A5 min A8 min A7 max Pos. 1 Indicator See NOTE Mating pins 0.025 sq. or round A1 ± T3 Pos. 39 A2 ± T1 Pos. 1 A4 ± T2 A8 ± T3 Pos. 2 Pos. 20 Blocked A3 ± T1 A4 ± T2 Pos. 40 NOTE − The optional polarizing feature is recommended. Some host receptacles do not provide a polarizing slot. Figure A.2 − 40-pin I/O cable connector Table A.2 − 40-pin I/O cable connector Dimension Millimeters Inches A1 55.37 2.180 A2 48.26 1.900 A3 6.10 0.240 A4 2.54 0.100 A5 6.48 0.255 A6 4.57 0.180 A7 3.81 0.150 A8 1.27 0.050 T1 0.13 0.005 T2 0.08 0.003 T3 0.25 0.010 Page 399 T13/1410D revision 3b Signal name Table A.3 − 40-pin I/O connector interface signals Connector Conductor Connector Signal name contact contact 1 1 2 2 Ground 3 3 4 4 DD8 5 5 6 6 DD9 7 7 8 8 DD10 9 9 10 10 DD11 11 11 12 12 DD12 13 13 14 14 DD13 15 15 16 16 DD14 17 17 18 18 DD15 19 19 20 20 (keypin) 21 21 22 22 Ground 23 23 24 24 Ground 25 25 26 26 Ground RESETDD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 Ground DMARQ DIOW-:STOP DIOR-:HDMARDY:HSTROBE IORDY:DDMARDY27 27 28 28 :DSTROBE DMACK29 29 30 30 INTRQ 31 31 32 32 DA1 33 33 34 34 DA0 35 35 36 36 CS037 37 38 38 DASP39 39 40 40 NOTE − Pin 32 was defined as IOCS16 in ATA-2, ANSI X3.279-1996. 40 20 Circuit board CSEL Ground Obsolete (see note) PDIAG-:CBLIDDA2 CS1Ground 1 2 Circuit board 40 20 1 2 Figure A.3 − 40-pin I/O header mounting A.1.1 40-conductor cable The 40-conductor cable assemby is shown in figure A.4 with dimensions in table A.4. Cable capacitance shall not exceed 35 pf. Page 400 T13/1410D revision 3b A1 A2 Host Connector Polarity stripe on #1 conductor A3 Device 0 Connector Device 1 Connector Figure A.4 − 40-conductor cable configuration Table A.4 − 40-conductor cable configuration Dimension Millimeters Inches A1 254.00 min 10.00 min 457.20 max 18.00 max A2 127.00 min 5.00 min 304.80 max 12.00 max A3 127.00 min 5.00 min 152.40 max 6.00 max A.1.2 80-conductor cable assembly using the 40-pin connector To provide better signal integrity, the optional 80-conductor cable assembly is specified for use with 40-pin connectors. Use of this assembly is mandatory for systems operating at Ultra DMA modes greater than 2. The mating half of the connector is as described in A.1. Every other conductor in the 80-conductor cable is connected to the ground pins in each connector. The electrical requirements of the 80-conductor ribbon cable are shown in table A.5 and the physical requirements are described in figure A.5 and table A.6. Figure A.6 and table A.7 describe the physical dimensions of the cable assembly. The connector in the center of the cable assembly labeled Device 1 Connector is optional. The System Board connector shall have a blue base and a black or blue retainer. The Device 0 Connector shall have a black base and a black retainer. The Device 1 Connector shall have a gray base and a black or gray retainer. The cable assembly may be printed with connector identifiers. There are alternative cable conductor to connector pin assignments depending on whether the connector attaches all even or odd conductors to ground. Table A.8 shows the signal assignments for connectors that ground the even numbered conductors. Table A.9 shows the signal assignments for connectors that ground the odd numbered conductors. Only one connector type, even or odd, shall be used in a given cable assembly. Connectors shall be labeled as grounding the even or odd conductors as shown in figure A.7. Cable assemblies conforming to table A.8 are interchangable with cable assemblies conforming to table A.9. All connectors shall have position 20 blocked to provide keying. Pin 28 in Device 1 Connector shall not be attached to any cable conductor, the connector contact may be removed to meet this requirement (see 5.2.13.2). Pin 34 in the Host Connector shall not be attached to any cable conductor and shall be attached to Ground within the connector (see 6.7). Page 401 T13/1410D revision 3b Table A.5 − 80-conductor cable electrical Conductor Ground-signal-ground Single ended impedance (Ω) Capacitance (pF/ft) (pF/m) Inductance (µH) Propagation delay (nsec/ft) (nsec/m) requirements 30 AWG 70-90 13-22 42-72 0.08-0.16 1.35-1.65 4.43-5.41 A1 ± T1 Polarity stripe on #1 conductor A2 ± T1 A3 ± T2 A4 ± T3 A5 ± T4 Figure A.5 − 80-conductor ribbon cable Table A.6 − 80-conductor ribbon cable Dimension Millimeters Inches A1 50.800 2.000 A2 50.165 1.975 A3 0.635 0.025 A4 0.6858 0.027 A5 0.3175 0.0125 T1 0.127 0.005 T2 0.0406 0.0016 T3 0.0508 0.002 T4 0.102 0.004 Page 402 t T13/1410D revision 3b A2 A3 Polarity stripe on #1 conductor Device 0 Device 1 Connector Device 0 Connector Figure A.6 − 80-conductor cable configuration Table A.7 − 80-conductor cable configuration Dimension Millimeters Inches A1 457.20 max 18.00 max A2 127.00 min 5.00 min A3 152.40 max 6.00 max A2 min shall be greater than or equal to A3. 1 Host Connector e c i v eD H o s A1 Page 403 T13/1410D revision 3b Table A.8 − Signal assignments for connectors grounding even conductors Signal name Connector Conductor Signal name contact RESET1 1 2 Ground Ground 2 3 4 Ground DD7 3 5 6 Ground DD8 4 7 8 Ground DD6 5 9 10 Ground DD9 6 11 12 Ground DD5 7 13 14 Ground DD10 8 15 16 Ground DD4 9 17 18 Ground DD11 10 19 20 Ground DD3 11 21 22 Ground DD12 12 23 24 Ground DD2 13 25 26 Ground DD13 14 27 28 Ground DD1 15 29 30 Ground DD14 16 31 32 Ground DD0 17 33 34 Ground DD15 18 35 36 Ground Ground 19 37 38 Ground (keypin) 20 39 40 Ground DMARQ 21 41 42 Ground Ground 22 43 44 Ground DIOW23 45 46 Ground Ground 24 47 48 Ground DIOR25 49 50 Ground Ground 26 51 52 Ground IORDY 27 53 54 Ground CSEL 28 55 56 Ground DMACK29 57 58 Ground Ground 30 59 60 Ground INTRQ 31 61 62 Ground Reserved 32 63 64 Ground DA1 33 65 66 Ground PDIAG34(see note) 67 68 Ground DA0 35 69 70 Ground DA2 36 71 72 Ground CS037 73 74 Ground CS138 75 76 Ground DASP39 77 78 Ground Ground 40 79 80 Ground NOTE − Pin 34 in the Host Connector shall not be attached to any cable conductor and shall be attached to Ground within the connector (see 6.7). Page 404 T13/1410D revision 3b Table A.9 − Signal assignments for connectors grounding odd conductors Signal name Conductor Connector Signal name contact Ground 1 2 1 RESETGround 3 4 2 Ground Ground 5 6 3 DD7 Ground 7 8 4 DD8 Ground 9 10 5 DD6 Ground 11 12 6 DD9 Ground 13 14 7 DD5 Ground 15 16 8 DD10 Ground 17 18 9 DD4 Ground 19 20 10 DD11 Ground 21 22 11 DD3 Ground 23 24 12 DD12 Ground 25 26 13 DD2 Ground 27 28 14 DD13 Ground 29 30 15 DD1 Ground 31 32 16 DD14 Ground 33 34 17 DD0 Ground 35 36 18 DD15 Ground 37 38 19 Ground Ground 39 40 20 (keypin) Ground 41 42 21 DMARQ Ground 43 44 22 Ground Ground 45 46 23 DIOWGround 47 48 24 Ground Ground 49 50 25 DIORGround 51 52 26 Ground Ground 53 54 27 IORDY Ground 55 56 28 CSEL Ground 57 58 29 DMACKGround 59 60 30 Ground Ground 61 62 31 INTRQ Ground 63 64 32 Reserved Ground 65 66 33 DA1 Ground 67 68 34 (see note) PDIAGGround 69 70 35 DA0 Ground 71 72 36 DA2 Ground 73 74 37 CS0Ground 75 76 38 CS1Ground 77 78 39 DASPGround 79 80 40 Ground NOTE − Pin 34 in the Host Connector shall not be attached to any cable conductor and shall be attached to Ground within the connector (see 6.7). Page 405 T13/1410D revision 3b Pin 1 Termination block Characters located approximately where shown XXX = EVN or ODD Figure A.7 − Connector labeling for even or odd conductor grounding Page 406 T13/1410D revision 3b A.2 4-pin power connector The power connector is a 4-pin connector. The header mounted to a device is shown in figure A.8 and the dimensions are shown in table A.10. The connector mounted to the end of the cable is shown in figure A.9 and the dimensions are shown in table A.11. Pin assignments for these connectors are shown in table A.12. A7 ± T2 X 45 ° (2X) A6 +T3/-T2 -C-A- A16 min* A8 min A12 A10 R A14 Ref A13 (4X) Spherical R ∅ A2 A5 ± T2 A9 ± T2 ∅ A1 ± T1 (4X) ⊕ ∅ A2 A B C A3 -BA4 A11 A15 Pin 1 Unless otherwise specified, all tolerances are ± T3 * The tolerance build up of A6 and A7 shall not exceed A16 Figure A.8 − Device 4-pin power header Table A.10 − Device 4-pin power header Dimension Millimeters Inches A1 2.10 0.083 A2 3.50 0.138 A3 5.08 0.200 A4 15.24 0.600 A5 6.60 0.260 A6 21.32 0.839 A7 1.65 0.065 A8 7.50 0.295 A9 6.00 0.236 A 10 4.95 0.195 A 11 1.00 0.039 A 12 11.18 0.440 A 13 3.80 0.150 A 14 3.00 0.118 A 15 5.10 0.201 A 16 17.80 0.701 T1 0.04 0.0016 T2 0.15 0.006 T3 0.25 0.010 Page 407 T13/1410D revision 3b A11 A10 (4X) 20 ° Ref A12 A9 min A7 ± T2 -A- A13 min A5 +T2/-T3 -C- A8 Pin 1 A6 ± T1 X 45° Ref (2x) A4 ± T1 ∅ A14 (4X) A2 -B- A3 ∅ A1 Ref ⊕ ∅ T4 A B C Unless otherwise specified, all tolerances are ± T3. Figure A.9 − 4-pin power cable connector Table A.11 − 4-pin power cable connector Dimension Millimeters Inches A1 2.03 0.080 A2 5.08 0.200 A3 15.24 0.600 A4 6.35 0.250 A5 21.00 0.827 A6 1.78 0.070 A7 7.87 0.310 A8 5.51 0.217 A9 1.19 0.047 A 10 5.08 0.200 A 11 11.18 0.440 A 12 1.19 0.047 A 13 2.00 0.079 A 14 4.06 0.160 T1 0.10 0.004 T2 0.15 0.006 T3 0.25 0.010 T4 0.60 0.024 Table A.12 − 4-pin power connector pin assignments Power line Pin +12 volts 1 +12 volt return 2 +5 volt return 3 +5 volts 4 Page 408 T13/1410D revision 3b A.2.1 Mating performance Mating force should be 3.85 lbs (1.75 kg) maximum per contact. Unmating force should be 0.25 lbs (113.5 g) minimum per contact. A.3 Unitized connectors The 40-pin I/O signal header and the 4-pin power connector may be implemented in one of two unitized connectors that provide additional pins for configuration jumpers. The dimensioning of the 40-pin I/O signal area shall be as defined in figure A.1 and the dimensioning of the 4-pin power connector area shall be as defined in figure A.8 for both unitized connectors. The first of the unitized connectors is shown in figure A.10 with dimensions as shown in table A.13. The jumper pins, A through I, have been assigned as follows: − − − − − − E-F - CSEL G-H - Master G-H and E-F - Master with slave present No jumper - Slave A through D - Vendor specific I - Reserved The second of the unitized connectors is shown in figure A.11 with dimensions as shown in table A.14. The jumper pins, A through J, have been assigned as follows: − − − − A-B - CSEL C-D - Slave E-F - Master G through J - Vendor specific Dimensioning of the 4-pin power connector area per figure A.7 Dimensioning of the 40- pin signal connector area per figure A.1 A6 Pin H A7 Pin 40 A3 Pin B Pin A A1 ± T1 Pin 1 A4 A2 A5 A8 A9 Tolerances ±0.010 inches unless otherwise specified Figure A.10 − Unitized connector Page 409 T13/1410D revision 3b Table A.13 − Unitized connector Dimension Millimeters Inches A1 2.54 0.100 A2 4.06 0.160 A3 8.40 0.331 A4 5.26 0.207 A5 63.50 2.500 A6 13.54 0.533 A7 2.54 0.100 A8 70.825 2.788 A9 95.50 3.760 T1 0.15 0.006 Dimensioning of the 4-pin power connector area per figure A.7 Dimensioning of the 40-pin signal connector area per figure A.1 Pin B A5 Pin J A6 Pin 40 A1 Pin 1 A7 Pin A A2 A3 A4 A8 A9 Tolerances ±0.010 inches unless otherwise specified Figure A.11 − Unitized connector Table A.14 − Unitized connector Dimension Millimeters Inches A1 8.51 0.335 A2 5.51 0.217 A3 57.15 2.250 A4 10.16 0.400 A5 17.88 0.704 A6 8.94 0.352 A7 2.54 0.100 A8 75.29 2.964 A9 100.33 3.950 A.4 50-pin connector An alternative connector is often used for 2 1/2 inch or smaller devices. This connector is shown in figure A.12 with dimensions shown in table A.15. Signal assignments are shown in table A.16. Although there are 50 pins in the plug, a 44-pin mating receptacle may be used. Pins E, F, and 20 are keys and are removed. Some devices may use pins A, B, C, and D for option selection via physical jumpers. If a device uses pins A, B, C, and D for device selection, when no jumper is present the device should be designated as Device 0. Page 410 T13/1410D revision 3b When a jumper is present between pins B and D, the device should respond to the CSEL signal to determine the device number. A Pos. 43 A2 ± T1 Pos. 1 A1 Pos. C Pos. A Pos. B Pos. D A Pos. 44 Pos. 20 Pin removed Pos. 2 Pos. E and F Pins removed A2 ± T1 A3 ± T2 A1 Section A-A Figure A.12 − 50-pin connector Dimension A1 A2 A3 T1 T2 Table A.15 − 50-pin connector Millimeters Inches 2.00 0.079 0.50 0.020 3.86 0.152 0.05 0.002 0.20 0.008 Page 411 T13/1410D revision 3b Table A.16 − Signal assignments for 50-pin connector Signal name Connector Conductor Connector Signal name contact contact Option selection pins A B Option selection pins Option selection pins C D Option selection pins (keypin) E F (keypin) RESET1 1 2 2 Ground DD7 3 3 4 4 DD8 DD6 5 5 6 6 DD9 DD5 7 7 8 8 DD10 DD4 9 9 10 10 DD11 DD3 11 11 12 12 DD12 DD2 13 13 14 14 DD13 DD1 15 15 16 16 DD14 DD0 17 17 18 18 DD15 Ground 19 19 20 20 (keypin) DMARQ 21 21 22 22 Ground DIOW-:STOP 23 23 24 24 Ground DIOR-:HDMARDY25 25 26 26 Ground :HSTROBE IORDY:DDMARDY27 27 28 28 CSEL :DSTROBE DMACK29 29 30 30 Ground INTRQ 31 31 32 32 Obsolete (see note) DA1 33 33 34 34 PDIAGDA0 35 35 36 36 DA2 CS037 37 38 38 CS1DASP39 39 40 40 Ground +5 V (logic) 41 41 42 42 +5 V (motor) Ground(return) 43 43 44 44 Reserved - no connection NOTE − Pin 32 was defined as IOCS16 in ATA-2, ANSI X3.279-1996. A.5 68-pin PCMCIA connector This clause defines the pinouts used for the 68-pin alternative connector for the AT Attachment Interface. This connector is defined in the PCMCIA PC Card Standard. This clause defines a pinout alternative that allows a device to function as an AT Attachment Interface compliant device, while also allowing the device to be compliant with PC Card ATA mode defined by PCMCIA. The signal protocol allows the device to identify the host interface as being 68-pin as defined in this standard or PC Card ATA. To simplify the implementation of dual-interface devices, the 68-pin AT Attachment Interface maintains commonality with as many PC Card ATA signals as possible, while supporting full command and signal compliance with this standard. The 68-pin pinout shall not cause damage or loss of data if a PCMCIA card is accidentally plugged into a host slot supporting this interface. The inversion of the RESET signal between this standard and PCMCIA interfaces prevents loss of data if the device is unable to reconfigure itself to the appropriate host interface. A.5.1 Signals This specification relies upon the electrical and mechanical characteristics of PCMCIA and unless otherwise noted, all signals and registers with the same names as PCMCIA signals and registers have the same meaning as defined in PCMCIA. Page 412 T13/1410D revision 3b The PC Card ATA specification is used as a reference to identify the signal protocol used to identify the host interface protocol. A.5.2 Signal descriptions Any signals not defined below shall be as described in this standard, PCMCIA, or the PC Card ATA documents. Table A.15 shows the signals and relationships such as direction, as well as providing the signal name of the PCMCIA equivalent. Page 413 T13/1410D revision 3b Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Signal Ground DD3 DD4 DD5 DD6 DD7 CS0- Hst x x x x x x x SELATA- x CS1- x INTRQ x Vcc x Table A.15 − Signal assignments for 68-pin connector Dir Dev PCMCIA Pin Signal Hst Dir → x Ground 35 Ground x → ↔ x D3 36 CD1x ← ↔ x D4 37 DD11 x ↔ ↔ x D5 38 DD12 x ↔ ↔ x D6 39 DD13 x ↔ ↔ x D7 40 DD14 x ↔ → x CE141 DD15 x ↔ → i A10 42 CS1x → → x OE43 ← 44 DIORx → → x(1) A9 45 DIOWx → → i A8 46 47 48 → i WE49 ← x READY/ 50 IREQ→ x Vcc 51 Vcc x → 52 53 54 55 M/Sx → → i A7 56 CSEL x → → i A6 57 ← → i A5 58 RESETx → → i A4 59 IORDY o ← → i A3 60 DMARQ o ← → x A2 61 DMACKo → → x A1 62 DASPx ↔ Dev x x x x x x x x(1) i x x PCMCIA Ground CD1D11 D12 D13 D14 D15 CE2VS1IORDIOWR- x Vcc 17 18 19 20 21 22 23 24 25 26 27 28 DA2 DA1 x x 29 DA0 x → x A0 63 PDIAG- x ↔ x 30 31 32 33 DD0 DD1 DD2 x x x x ↔ ↔ ↔ ← x x x x D0 D1 D2 WP/ IOIS16 Ground 64 65 66 67 DD8 DD9 DD10 CD2- x x x x ↔ ↔ ↔ ← x x x x VS2RESET WAITINPACKREGBVD2/ SPKRBVD1/ STSCHG D8 D9 D10 CD2- 34 Ground x → x 68 Ground x → Key: Dir = the direction of the signal between host and device. x in the Hst column = this signal shall be supported by the Host. x in the Dev column = this signal shall be supported by the device. i in the Dev column = this signal shall be ignored by the device while in 68-pin mode. o = this signal is Optional. Nothing in Dev column = no connection should be made to that pin. x Ground NOTES − 1 The device shall support only one CS1- signal pin. 2 The device shall support either M/S- or CSEL but not both. 3 The device shall hold this signal negated if it does not support the function. Page 414 x(2) x(2) i x x(3) x(3) o x T13/1410D revision 3b A.5.2.1 CD1- (Card Detect 1) This signal shall be grounded by the device. CD1- and CD2- are used by the host to detect the presence of the device. A.5.2.2 CD2- (Card Detect 2) This signal shall be grounded by the device. CD1- and CD2- are used by the host to detect the presence of the device. A.5.2.3 CS1- (Device chip select 1) Hosts shall provide CS1- on both the pins identified in table A.15. Devices shall recognize only one of the two pins as CS1-. A.5.2.4 DMACK- (DMA acknowledge) This signal is optional for hosts and devices. If this signal is supported by the host or the device, the function of DMARQ shall also be supported. A.5.2.5 DMARQ (DMA request) This signal is optional for hosts. If this signal is supported by the host or the device, the function of DMACK- shall also be supported. A.5.2.6 IORDY (I/O channel ready) This signal is optional for hosts. A.5.2.7 M/S- (Master/slave) This signal is the inverted form of CSEL. Hosts shall support both M/S- and CSEL though devices need only support one or the other. Hosts shall assert CSEL and M/S- prior to applying VCC to the connector. A.5.2.8 SELATA- (Select 68-pin ATA) This pin is used by the host to select which mode to use, PC Card ATA mode or the 68-pin mode defined in this standard. To select 68-pin ATA mode, the host shall assert SELATA- prior to applying power to the connector, and shall hold SELATA- asserted. The device shall not re-sample SELATA- as a result of either a hardware or software reset. The device shall ignore all interface signals for 19 ms after the host supplies Vcc within the device's voltage tolerance. If SELATA- is negated following this time, the device shall either configure itself for PC Card ATA mode or not respond to further inputs from the host. A.5.3 Removability considerations This specification supports the removability of devices that use the protocol. As removability is a new consideration for devices, several issues need to be considered with regard to the insertion or removal of devices. Page 415 T13/1410D revision 3b A.5.3.1 Device recommendations The following are recommendations to device implementors: − − − CS0-, CS1-, RESET-, and SELATA- signals be negated on the device to prevent false selection during hot insertion. Ignore all interface signals except SELATA- until 19 ms after the host supplies VCC within the device's voltage tolerance. This time is necessary to de-bounce the device's power-on reset sequence. Once in the 68-pin mode as defined in this standard, if SELATA- is ever negated following the 19 ms de-bounce delay time, the device disables itself until VCC is removed. Provide a method to prevent unexpected removal of the device or media. A.5.3.2 Host recommendations The following are recommendations to host implementors: − − − − − Connector pin sequencing to protect the device by making contact to ground before any other signal in the system. SELATA- to be asserted at all times. All devices reset and reconfigured to the same base address each time a device at that address is inserted or removed. The removal or insertion of a device at the same address to be detected so as to prevent the corruption of a command. Provide a method to prevent unexpected removal of the device or media. A.6 CompactFlash connector Device compliant with the CompactFlash Association Specification use the connector defined in that specification. Page 416 T13/1410D revision 3b Annex B (normative) Device determination of cable type B.1 Overview This standard requires that, for systems using a cable assembly, an 80-conductor cable assembly shall be installed before a system may operate with Ultra DMA modes greater than 2. However, some hosts have not implemented circuitry to determine the installed cable type by detecting whether PDIAG-:CBLID- is connected to ground as mandated by this standard. The following describes an alternate method for using IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data from the device to determine the cable type. It is not recommended that a host use the method described in this annex. If a host uses IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data from the device to determine the cable type, then a 0.047 µf capacitor shall be installed from CBLID- to ground at the host connector. The tolerance on this capacitor is +/- 20% or less. After receiving an IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command the device detects the presence or absence of the capacitor by asserting PDIAG-:CBLID- to discharge the capacitor, releasing PDIAG-, and sampling PDIAG-:CBLID- before the installed capacitor could recharge through the 10 kΩ pull-up resistor(s) on PDIAG-:CBLID- at the device(s). If the host system has a capacitor on PDIAG-:CBLID- and a 40-conductor cable is installed, the rise time of the signal will be slow enough that the device will sample PDIAG-:CBLID- while the signal is still below VIL. Otherwise, if PDIAG-:CBLID- is not connected from the host connector to the devices in an 80-conductor cable assembly, the device will detect that the signal is pulled above VIH through the resistor(s) on the device(s). The capacitor test results will then be reported to the host in the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data. The host will use the data to determine the maximum transfer rate of which the system is capable and use this information when setting the transfer rate using the SET FEATURES command. B.2 Sequence for device detection of installed capacitor The following is the sequence for a host using IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data from the device to determine the cable type: a) the host issues an IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command (according to device type) first to Device 1 and then to Device 0 after every power-on or hardware reset sequence (the command is issued to Device 1 first to ensure that Device 1 releases PDIAG-:CBLID- before Device 0 is selected. Device 0 will be unable to distinguish a discharged capacitor if Device 1 is driving the line to its electrically low state. Issuing the command to Device 1 forces it to release PDIAG-:CBLID-); b) the selected device asserts PDIAG-:CBLID- for at least 30 µs after receipt of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command but before transferring data for the command; c) the device releases PDIAG-:CBLID- and samples it between two and thirteen µs after release; d) if the device detects that PDIAG-:CBLID- is below VIL, then the device returns a value of zero in bit 13 of word 93 in its IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data (if the host system has a capacitor on that signal and a 40-conductor cable is installed, the rise time of the signal will be slow enough that it will be sampled by the device while it is still below VIL); e) if the device detects that the signal is above VIH, then the device returns a value of one in bit 13 of word 93 in its IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data. This signal is not connected between the host and the devices in an 80-conductor cable assembly, thus, the sampling device will see this signal pulled above VIH through the 10 kΩ resistor(s) installed on the device(s); f) the host then uses its knowledge of its own capabilities and the content of word 88 and word 93 to determine the Ultra DMA modes of which the system is capable; g) the host then uses the SET FEATURES command to set the transfer mode. Page 417 T13/1410D revision 3b Host PCB Host connector Device 0 connector Device 1 connector PDIAG-:CBLIDconductor Device 0 PCB Device 1 PCB Figure B.1 – Example configuration of a system where the device detects a 40-conductor cable Table B.1 – Device detection of installed capacitor Cable assembly Device 1 Value reported in Device-determined Determination type releases PDIAG- ID data by device cable type correct? 40-conductor Yes 0 40-conductor Yes 80-conductor Yes 1 80-conductor Yes 40-conductor No 0 40-conductor Yes 80-conductor No 0 40-conductor No (see note) NOTE − Ultra DMA modes greater than 2 will not be set even though the system supports them. Table B.2 – Results of device based cable detection if the host does not have the capacitor installed Cable assembly Device 1 Value reported in Device-determined Determination type releases PDIAG- ID data by device cable type correct? 40-conductor Yes 1 80-conductor No (see note 1) 80-conductor Yes 1 80-conductor Yes 40-conductor No 0 40-conductor Yes 80-conductor No 0 40-conductor No (see note 2) NOTES – 1 Ultra DMA modes greater than 2 may be set incorrectly resulting in ICRC errors. 2 Ultra DMA modes greater than 2 will not be set even though the system supports them. B.3 Using the combination of methods for detecting cable type Determining the cable assembly type may be done either by the host sensing the condition of the PDIAG:CBLID- signal, by relying on information from the device, or a combination of both methods. Table B.3 describes the results of using both host and device cable detection methods. Page 418 T13/1410D revision 3b Table B.3 – Results of using both host and device cable detection methods Cable assembly Device 1 Electrical state of Value reported in Determined Determination type Releases PDIAG- CBLID- at host ID data by device cable type correct? 40-conductor Yes 1 0 40 Yes 80-conductor Yes 0 1 80 Yes 40-conductor No 0 0 40 Yes (see note) 80-conductor No 0 0 40 No (see note) NOTE – The 0,0 result is independent of cable type and indicates that Device 1 is incorrectly asserting PDIAG-. When the host determines this result, it shall not operate with Ultra DMA modes greater than 2 and it may respond in several ways: 1 report that Device 1 is incompatible with Ultra DMA modes higher than 2 and should be used on a different port in order to use those modes on the port being detected; 2 report that Device 1 is not allowing the cable type to be properly detected; 3 do not notify the user of any problem but detect the cable as a 40-conductor. The Table B.4 below illustrates intermediate results for all combinations of cable, device, and host, for hosts that support Ultra DMA modes greater than 2. Table B.4 – Results for all combinations of device and host cable detection methods Design options Intermediate actions and results Results 80-conDevice Host Host uses Host Device Capa- ID word Host Host ductor supports senses ID data, capacitor tests for citor 93 Bit checks may set cable UDMA PDIAG-: capacitor connected capa- detec13 ID word UDMA installed modes >2 CBLIDinstalled to device citor ted value 93 bit 13 mode >2 No No Yes No No No No 0 No No No Yes Yes No No Yes No 1 No No Yes No Yes No No No No 0 No No Yes Yes Yes No No Yes No 1 No Yes No No No Yes Yes No No 0 Yes No No Yes No Yes Yes Yes Yes 0 Yes No Yes No No Yes No No No 0 Yes No Yes Yes No Yes No Yes No 1 Yes Yes Page 419 T13/1410D revision 3b Annex C (informative) Signal integrity and UDMA implementation guide C.1 Introduction This annex is intended as an aid to the implementation of Ultra DMA in host systems, ATA controllers, and peripherals. Clarification of some aspects of the protocol and details not specifically stated in the normative sections of the standard have been included for the benefit of component, PCB, and device driver engineers. This annex is not intended to be comprehensive but rather informative on subjects that have caused design questions. Included are warnings about proper interpretation of protocol where interpretation errors seem possible. The information provided is relevant to implementation of all Ultra ATA modes 0 through 5, as well as earlier protocols. This annex uses the term data-out to indicate a transfer from the host to a device and data-in to indicate a transfer from the device to the host. The ATA bus is a storage interface originally designed for the ISA Bus of the IBM PC/AT . With the advent of faster host systems and devices, the definition of the bus has been expanded to include new operating modes. Each of the PIO modes, numbered zero through four, is faster than the one before (higher numbers translate to faster transfer rates). PIO modes 0, 1, and 2 correspond to transfer rates for the interface as was originally defined with maximum transfer rates of 3.3, 5.2, and 8.3 megabytes per second (MB/s), respectively. PIO mode 3 defines a maximum transfer rate of 11.1 MB/s, and PIO mode 4 defines a maximum rate of 16.7 MB/s. Additionally, Multiword DMA and Ultra DMA modes have been defined. Multiword DMA mode 0, 1, and 2 have maximum transfer rates of 4.2, 13.3, and 16.7 MB/s, respectively. Ultra DMA modes 0, 1, 2, 3, 4, and 5 have maximum transfer rates of 16.7, 25, 33.3, 44.4, 66.7, and 100 MB/s, respectively. Ultra DMA features such as increased frequencies, double-edge clocking, and non-interlocked signaling require improved signal integrity on the bus relative to that required by PIO and Multiword DMA modes. For Ultra DMA modes 0, 1, and 2 this is achieved by the use of partial series termination and controlled slew rates. For modes 3 and above an 80-conductor cable assembly is required in addition to partial series termination and controlled slew rates. This cable assembly has ground lines between all signal lines on the bus in order to control impedance and reduce crosstalk, eliminating many of the signal integrity problems inherent to the 40conductor cable assembly. However, many of the design considerations and measurement techniques required for the 80-conductor cable assembly are different from those used for the 40-conductor assembly. Hosts and devices capable of Ultra DMA modes greater than 2 should be designed to meet all requirements for operation with both cable types. Unless otherwise stated, 40- and 80-conductor cables are assumed to be 18 inches long, the maximum allowed by this standard. Timing and signal integrity issues as discussed apply to this length cable. C.2 The issues The following describe the issues and design challenges while providing suggestions for implementation with respect to timing, crosstalk, ground bounce, and ringing. C.2.1 Timing Two of the features Ultra DMA introduced to the bus are double-edge clocking and non-interlocked (also known as source-synchronous) signaling. Double-edge clocking allows a word of data to be transferred on each edge of STROBE (this is HSTROBE for an Ultra DMA data-out transfer and DSTROBE for a data-in transfer), resulting in doubling the data rate without increasing the fundamental frequency of signaling on the bus. Noninterlocked signaling means that DATA and STROBE are both generated by the sender during a data transfer. Page 420 T13/1410D revision 3b In addition to signal integrity issues such as clocking the same data twice due to ringing on the STROBE signal and delay-limited interlock timings on the bus, non-interlocked signaling makes settling time and skew between different signals on the bus critical for proper Ultra DMA operation. C.2.1.1 Cabling The 80-conductor cable assembly adds 40 ground lines to the cable between the 40 signal lines defined for the 40-conductor cable assembly. These added ground lines are connected inside each connector on the cable assembly to the seven ground pins defined for the 40-conductor cable assembly. These additional ground lines allow the return current for each signal line to follow a closer path to the outgoing current than was allowed by the grounding scheme in the 40-conductor cable assembly. This results in a lower impedance and greatly reduced crosstalk for signals on the data bus. The controlled impedance and reduced crosstalk of the 80conductor cable assembly results in much improved behavior of electrical signals on the bus and reduces the data settling time to effectively zero regardless of switching conditions. Thus, the signal at the recipient is monotonic, such that the first crossing of the input threshold is considered final. Reducing the time allowed for data settling time (DST) from greater than 25 ns in Ultra DMA mode 2, to 0 ns with the 80-conductor cable assembly allows nominal cycle time to be reduced from 60 ns for mode 2, to 20 ns for mode 5. C.2.1.2 Skew Skew is the difference in total propagation delay between two signals as they transit the bus. Propagation delay is the amount of time required for a single input signal at one part of the system to cause a disturbance to be observed at another part of the system in a system containing continuously distributed capacitance and inductance. Propagation delay is determined by the velocity of light within the dielectric materials containing the electric fields in the system. For systems with uniform properties along their length, propagation delay is often specified as seconds per foot or seconds per meter. Skew will be positive or negative depending on which signal is chosen as the reference. All skews in the Ultra DMA timing derivations are defined as STROBE delay minus data delay. A positive skew is a STROBE that is delayed more than the data. Skew corresponds to the reduction in setup and hold times that occurs between the sender and the recipient. If the bus contributes skew that exceeds the difference between the setup time produced by the sender and that required by the recipient, data will be stored incorrectly. The same is true for hold time. Skew between signals is caused by differences in the electrical characteristics of the paths followed by each signal. Ultra DMA mode 5 requires less skew within the physical cable system than the previous modes. In order to reduce the amount of skew created as signals transit the system, mode 5 places a number of new requirements on the analog electrical aspects of system design. The primary requirement is that all Ultra DMA mode 5 devices and hosts use 3.3 volt signaling. This eliminates the contribution to skew from the asymmetry of the input thresholds with the previous 5 volt VoH. A second requirement is that hosts use a 4.7 kΩ pull-up resistor on IORDY/DSTROBE instead of the 1 kΩ resistor used for previous modes. The pull-up shall be to the host’s 3.3 V internal supply. Third, the total output impedance consisting of driver resistance plus series termination resistor shall match the typical cable impedance of 75 to 85 Ω. C.2.1.3 Source-terminated bus The bus operates as a source-terminated bus, meaning that the only low-impedance connection to ground is via the source impedance of the drivers in the sender. Page 421 T13/1410D revision 3b R_source 100 Ω Cable Z0=100 Ω TD=4 ns R_rec 1 MΩ + − V_source Figure C.1 − A transmission line with perfect source termination On a source-terminated transmission line, the initial voltage level produced at the source propagates through the system until it reaches the receiving end that, by definition, is an open circuit or at least has high impedance relative to the characteristic impedance of the transmission line. This open circuit produces a reflection of the original step with the same polarity and amplitude as the original step but travelling in the opposite direction. The reflected step adds to the first step to raise the voltage throughout the system to two times the original step voltage. In a perfectly terminated system (see figure C.1), R_source matches the cable impedance resulting in an initial step voltage on the transmission line equal to fifty percent of V_source, and the entire system has reached a steady state at V_source once the reflection returns to the source. The waveforms that are measured on the bus as a result of this behavior depend on the ratio of the signal rise time to the propagation delay of the system. If the rise time is shorter than the one-way propagation delay, the initial voltage step will be visible at the sender. At the recipient the incoming voltage step is instantaneously doubled as it reflects back to the sender and no step is observed (see figure C.2). 8v 4v transmitter receiver 0v -4 v 0 ns 20 ns 40 ns 60 ns 80 ns time Figure C.2 – Waveforms on a source-terminated bus with rise time less than Tprop If the rise time is longer than the propagation delay, the sender waveform changes, but the same behavior still occurs: the reflected step adds to the initial step at the sender while a delayed doubling of the initial step is observed at the recipient. Because the rising edges of the two steps overlap when measured at the sender, Page 422 T13/1410D revision 3b there is a temporary increase in slew rate instead of a step seen at the sender while the rising edge of the reflection adds to the edge still being generated by the sender (see figure C.3). 6v 4v transmitter receiver 0v -1 v 0 ns 20 ns 40 ns time 60 ns 80 ns Figure C.3 – Waveforms on a source-terminated bus with rise time greater than Tprop In figure C.2 and C.3, the source impedance is perfectly matched to the cable impedance with the result that, after the first reflection returns to the source, there are no further reflections, and the system is at a steady state. In a system that is not perfectly terminated, there are two possibilities. The first possibility is when the source impedance is less than the characteristic impedance of the transmission line, the initial step is greater than fifty percent of VoH, and the system is at a voltage higher than VoH when the first reflection returns to the recipient (see figure C.4). In this case another reflection occurs at the source to reduce the system to a voltage below VoH but closer to VoH than the initial peak. Reflections continue but are further reduced in amplitude each time they reflect from the termination at the source. Page 423 T13/1410D revision 3b 8v 4v transmitter receiver 0v -4 v 0 ns 20 ns 40 ns 60 ns 80 ns time Figure C.4 – Waveforms on a source-terminated bus with R_source less than cable Z0 The second possibility is when the source impedance is higher than the characteristic impedance, the initial step is less than fifty percent of VoH, and multiple reflections back and forth on the bus will be required to bring the whole system up to a steady state at VoH (see figure C.5). 5v transmitter receiver 0v 0 ns 20 ns 40 ns 60 ns 80 ns time Figure C.5 – Waveforms on a source-terminated bus with R_source greater than cable Z0 Note that falling edges exhibit the same transmission line behavior as rising edges. The only difference between the edges is that VoH and VoL are reversed. In actual systems output impedance and slew rate of the drivers are often different between rising and falling edges, resulting in different step voltages and waveform shapes. Page 424 T13/1410D revision 3b For typical implementations using 33 Ω series termination, the effective driving impedance of a sender’s component I/O viewed from the cable connector ranges from 50 to 90 Ω. The component I/O is the combined input and/or output circuitry, bond wire, and pin on an IC that is responsible for receiving and/or sending data on a particular conductor within the bus. The initial voltage step produced when an edge is driven onto the cable will be equal to the driver’s open-circuit VoH divided by the effective output impedance and the input impedance of the cable (typically 82 Ω), or a 50 to 60 Ω printed circuit board trace in the case of hosts. This step voltage will fall in the range from 50 to 70 percent of VoH. For example, for a theoretical source with zero output impedance using 33 Ω termination driving an 82 Ω cable the resulting step voltage is not greater than 100 ∗ ( 82 ÷ (33 + 82 ) ) = 71.3 percent of VoH. Because the thresholds of an input are not centered with respect to the high and low voltages, the initial voltage step produced by a driver will often cross the recipient’s input threshold on a rising edge but not on a falling edge. However, since the signal received at the end of the bus is a doubled version of the initial output from the sender, it will cross the switching thresholds for any reasonably low output impedance. Because of this the main voltage step only affects skew and delay for signals received at devices that are not at the end of the cable. The greater the distance a device is from the device end of the cable (i.e., closer to the host), the longer the duration of the step observed (see figures C.6 and C.7). transmitter receiver -20 ns #Avg 16 30 ns 10.00 ns/div 80 ns repetitive Figure C.6 – Typical step voltage seen in ATA systems using an 80-conductor cable (measured at drive and host connectors during read) Page 425 T13/1410D revision 3b transmitter receiver -20 ns # Avg 16 30 ns 10.0 ns/div 80 ns repetitive Figure C.7 – Typical step voltage seen in ATA systems using an 80-conductor cable (measured at host and drive connectors during write) In addition to the step produced by the initial voltage driven onto the bus and the subsequent reflection, smaller steps are produced each time the propagating signal encounters a change in the bus impedance. The major impedance changes that occur in a system are: 1) at the connections between the cable and the printed circuit boards (PCBs) of the hosts and devices, 2) along the traces of the PCBs as the result of changing layers, and 3) at the connection between a motherboard and a backplane. The transmission line behavior of the 80-conductor cable assembly adds skew to the received signal in two ways. First, impedance differences along one line versus another will result in different amounts of delay and attenuation on each line due to reflections on the bus. This produces a time difference between the two signals’ threshold crossings at the recipient. Secondly, signals received at the device that is not at the end of the cable may cross the threshold during the initial voltage step or after the reflection from the end of the cable is received, depending on the supply voltage, series termination, output impedance, VoH, and PCB trace characteristics of the host. Factors other than cable characteristics also contribute to skew. Differences in the capacitive loading between the STROBE and DATA lines on devices attached to the bus will delay propagating signals by differing amounts. Differences in slew rate or output impedance between drivers when driving the 82 Ω load will result in skew being generated as the signal is sent at the sender. Differences between the input RC delays on STROBE and DATA lines will add skew at the recipient. The fundamental requirement for minimizing skew in the entire system is to make the STROBE and DATA lines as uniform as possible throughout the system. C.2.1.4 Timing measurements for the 80-conductor cable assembly The reflections that are present in a system make it difficult to measure skew and delays accurately. For the received signal at a device, the propagation delay from the device connector to the device integrated circuit (IC) connector pin is about 300 ps for typical device PCBs and trace lengths. The IC is the entire component (die and package) that contains the ATA bus interface circuitry. This delay introduces an error of plus or minus 300 ps in timing measurements made at the device connector since rising edges and falling edges will be measured before and after the step respectively. When comparing two signals, this results in an error in measured skew of plus or minus 600 ps due to the measurement Page 426 T13/1410D revision 3b position. This error is small enough relative to the total timing margin of an Ultra DMA system that it may be ignored in most cases. Since the trace length on host PCBs are often much longer than those on devices, the propagation time for a signal from the host connector to the host IC may be as high as 2 ns. This results in a plus or minus 2 ns accuracy in the measurement of a single signal and a plus or minus 4 ns accuracy for skew between two signals. These errors are not removed by adding or subtracting an allowance for PCB propagation delay depending on rising or falling edges because characteristics of the PCB and termination will affect the step levels and skew that occur at the component I/Os. As a result of this, accurate measurements of skew in signals received at the host are made either at pins of the host IC, or at points on the PCB traces as close to the IC pins as possible. Test pads, headers, or unconnected vias in PCB layouts may be designed allowing connection to DATA, STROBE, and ground for this purpose. It is important to note that the timing specifications for Ultra DMA in the standard are based on measuring signals at the interface connector. C.2.1.5 Simulations for the 80-conductor cable assembly The difficult nature of measuring skew in actual systems makes simulations a more important tool in determining the effect on skew of design decisions regarding component I/Os, PCB layout, cable lengths, and other aspects of system design. Because of the well-controlled impedance of the 80-conductor cable assembly, single line transmission line models provide accurate predictions of the delay through the bus based on a given design choice for a given set of conditions on the bus. To be certain of the system-wide consequences of particular design choices, a large number of simulations encompassing many different combinations of parameters were used to determine the timing specifications for Ultra DMA mode 5. Results of these simulations are also the basis of the guidelines that follow. Output skew is measured at the connector of the sender into capacitive loads to ground of 15 pf and 40 pf. An alternate loading arrangement is to measure the signal produced at the end of an 18-inch 80-conductor cable assembly into typical device and host loads of 20 pf or 25 pf that are held uniform across STROBE and DATA lines. Skew is measured at the crossing of the 1.5 volt threshold. All combinations of rising and falling edges on the signals involved are used when skew is measured. Minimizing output skew is the best assurance of reliable signaling across the full range of cable loading and recipient termination conditions that will occur in systems. C.2.2 Crosstalk Although the ground-signal-ground configuration of the 80-conductor cable assembly greatly reduces coupling between wires on the cable, the host and device connectors generate a large amount of crosstalk because they still use the original ground configuration with no ground lines separating the 16 signals of the data bus. In addition, crosstalk between traces on the PCB may reach high levels in systems with long traces or with tight spacing between traces. Cumulative crosstalk plus ground bounce measured at the connector of the recipient in typical systems using the 80-conductor cable ranges from 400 mV to 1 V peak, in short pulses with a frequency content equivalent to the frequency content of the edge rates of the drivers being used. Although this level of total crosstalk may seem like a hazard to reliable signaling, crosstalk exceeding 800 mV detected at the recipient does not affect the setup or hold times when it occurs during the interval when other signals are switching (see figure C.8). This figure was generated using the first falling STROBE edge for a trigger and showing a middle data signal staying low while all other lines switch high to low. With infinite persistence, the pattern was then changed to all lines switching low to high for the same STROBE edge. The crosstalk that occurs on the line staying low while all others switch high to low is in excess of 800 mV but has more hold and setup time margin than data lines that are switching and therefore it does not reduce setup or hold time margin. Page 427 T13/1410D revision 3b X1 Y1 Y2 X2 108 ns 118 ns 2.0 ns/div Y2 Y1 delta Y 800 mV 1.5 V -700 mV 128 ns realtime X2 X1 delta X 1/delta X 119 ns 117 ns 1.8 ns 555.556 MHz Figure C.8 – Positive crosstalk pulse during a falling edge (does not affect data setup or hold time) A larger signal integrity hazard exists when crosstalk extends into the middle of the cycle when data could be clocked. This may result from a high level of reverse crosstalk detected at the recipient as the reflected signal propagates from the recipient input back to the sender output in the switching lines. X1 Y2 Y1 X2 -21 ns 29 ns 10 ns/div Y2 Y1 delta Y 552.125 mV 504.8 mV 47.3250 mV X2 X1 delta X 1/delta X 79 ns realtime 42.2 ns 21.2 ns 21.0 ns 47.6190 MHz Figure C.9 – Reverse crosstalk waveform from reflected edge (seen at the receiver in the middle of a cycle – marker X1) Reducing a system’s creation of and susceptibility to forward and reverse crosstalk requires an understanding of how crosstalk is generated and propagates through the system. Crosstalk results from coupling between signals in the form of either a capacitance from one signal conductor to another or inductors in the path of each Page 428 T13/1410D revision 3b signal with overlapping magnetic fields. The capacitive and inductive coupling are easiest to understand if treated as separate effects. C.2.2.1 Capacitive coupling Capacitive coupling in its simplest form consists of a capacitor connecting together two transmission lines somewhere along their length. When a change in voltage occurs on one line (called the aggressor line), a pulse on the non-switching signal (called the victim line) is produced with a peak amplitude proportional to the rate of change of voltage (dV/dt) on the aggressor line. The pulse on the victim line propagates both forward and backward from the point of coupling and has the same sign in both directions. Forward and backward are defined relative to the direction that the aggressor signal was propagating. Forward means that the propagation is in the same direction as the aggressor signal. Backward means that propagation is in the opposite the direction of the aggressor signal. Figure C.10 is a schematic of a model for capacitive coupling. Figure C.11 shows waveforms resulting from capacitive coupling at the sender and recipient component I/Os of the aggressor and victim lines. Aggressor_src 100 Ω T1 Z0=100 Ω TD=5 ns T2 Z0=100 Ω TD=5 ns Aggressor_rec 100 Ω + − C1 6 pf V_source Victim_src 100 Ω T3 Z0=100 Ω TD=5 ns T4 Z0=100 Ω TD=5 ns Victim_rec 100 Ω Figure C.10 – Model of capacitive coupling Page 429 T13/1410D revision 3b 1.5 V -0.5 V Aggressor at receiver 200 mV -200 mV Victim at source 200 mV -200 mV 0 ns 10 ns Victim at receiver 20 ns 30 ns 40 ns 50 ns 60 ns Time Figure C.11 – Waveforms resulting from capacitive coupling (at transmitter and receiver of aggressor and victim lines) C.2.2.2 Inductive coupling In the following, inductive coupling is modeled as an inductor in series with each signal, with some coupling factor K representing the extent to which the inductors’ magnetic fields overlap. In effect these two inductors constitute a transformer, creating a stepped-down version of the aggressor signal on the victim line. The amplitude of the signal produced on the victim line is proportional to the rate of change in current (di/dt) on the aggressor line. Since the impedance of a transmission line is resistive, for points in the middle of a transmission line di/dt will be proportional to dV/dt. Because the crosstalk signal produced across the inductance in the victim line is in series with the transmission line, it has a different sign at each end of the inductor. Because the current in an inductor always opposes the magnetic field that produced it, the polarity of the crosstalk signal is reversed from the polarity of the di/dt on the aggressor line that produced it. As a result of these two facts, inductive crosstalk creates a pulse of forward crosstalk with polarity opposite to the edge on the aggressor, and a pulse of reverse crosstalk with the same polarity as the aggressor edge. Figure C.12 is a schematic of a model for inductive coupling. Figure C.13 shows waveforms resulting from inductive coupling at the sender and recipient component I/Os of the aggressor and victim lines. Page 430 T13/1410D revision 3b Aggressor_src 100 Ω T2 Z0=100 Ω TD=5 ns T1 Z0=100 Ω TD=5 ns Aggressor_rec 100 Ω L1 50 nH + − MUTUAL COUPLING=1 V_source Victim_src 100 Ω T4 Z0=100 Ω TD=5 ns T3 Z0=100 Ω TD=5 ns Victim_rec 100 Ω L2 50 nH Figure C.12 – Model of inductive coupling Note that the box in figure C.12, figure C.14, and figure C.18 between L1, L2 and K2 is a PSPICE element representing the inductive coupling between L1 and L2 having the coupling value listed in the figure. 1.5 V -0.5 V 100 mV Aggressor at receiver -100 mV 100 mV Victim at receiver -100 mV 10 ns 20 ns Victim at source 30 ns 40 ns 50 ns 60 ns 70 ns Time Figure C.13 – Waveforms resulting from inductive coupling (at transmitter and receiver of aggressor and victim lines) Page 431 T13/1410D revision 3b C.2.2.3 Mixed capacitive and inductive coupling Most occurrences of electromagnetic coupling involve both capacitive and inductive coupling. In this case the forward and reverse crosstalk contributions of the capacitance and inductance add together. Because the forward inductive crosstalk and the forward capacitive crosstalk have opposite signs, they tend to cancel, while the reverse crosstalk from both effects have the same sign and add together. Depending on the ratio of inductive to capacitive coupling, the forward crosstalk may sum to zero when both effects are added together. Figure C.14 is a schematic of a model for mixed capacitive and inductive coupling. Figure C.15 shows waveforms resulting from mixed capacitive and inductive coupling at the sender and recipient component I/Os of the aggressor and victim lines. T2 Z0=100 Ω TD=5 ns T1 Z0=100 Ω TD=5 ns Aggressor_src 100 Ω Aggressor_rec 100 Ω L1 50 nH + − MUTUAL COUPLING=1 V_source C12 6 pf Victim_src 100 Ω T4 Z0=100 Ω TD=5 ns T3 Z0=100 Ω TD=5 ns L2 50 nH Figure C.14 – Model of capacitive and inductive coupling Page 432 Victim_rec 100 Ω T13/1410D revision 3b 1.5 V -0.5 V Aggressor at receiver 200 mV -200 mV 200 mV Victim at receiver -200 mV 10 ns 20 ns 30 ns Victim at source 40 ns 50 ns 60 ns 70 ns Time Figure C.15 – Waveforms resulting from mixed capacitive and inductive coupling (at transmitter and receiver of aggressor and victim lines) C.2.2.4 Crosstalk from distributed coupling When transmission lines are placed parallel with and in close proximity to each other, as is the case for PCB traces, wires in a ribbon cable, etc., the coupling that occurs is continuous along the length of the transmission lines. To find the crosstalk waveforms at the source and recipient, divide the transmission lines into segments and treat each segment as an instance of capacitive and inductive coupling. Each segment produces forward and reverse crosstalk as the aggressor edge goes by. Sum the contributions from each of these segments, delaying their arrival at the ends according to the segment’s position along the transmission line. This procedure shows that the forward crosstalk contributions all add together and arrive simultaneously with the aggressor edge, while the reverse crosstalk is spread out along the length of the transmission line and produces a long flat pulse travelling back toward the source. Figure C.16 shows a schematic model for a transmission line with three coupled conductors, connected as two signal wires and a ground return. The waveform at the source end of the victim line in figure C.17 shows that the reverse crosstalk pulse begins when the edge is driven onto the aggressor line and continues to be observed at the source until one system delay after the end of the edge is terminated at the recipient on the aggressor line. The waveform at the victim recipient’s component I/O shows that the forward crosstalk arrives simultaneously with the edge on the aggressor line, or even slightly before, because the energy in the crosstalk pulse has been subtracted from the edge on the aggressor, reducing its rise time at the recipient. Page 433 T13/1410D revision 3b Aggressor_rec 100 Ω Aggressor_src 100 Ω + − V12 Victim_src 100 Ω in 1 out 1 in 2 out 2 In 3 out 3 Victim_rec 100 Ω T3 coupled L=500 nH C=50 pf LM= 100 nH CM=1- pf Figure C.16 – Model of distributed coupling 1.5 V -0.5 V Aggressor at receiver 100 mV -100 mV Victim at receiver 100 mV -100 mV 0 ns 10 ns Victim at source 20 ns 30 ns 40 ns 50 ns 60 ns Time Figure C.17 – Waveforms resulting from distributed coupling (at transmitter and receiver of aggressor and victim lines) The above simulation results shown in figures C.11, C.13, C.15, and C.17 are simplified by the assumption that all transmission lines are perfectly terminated at both ends. In actual systems only the sender end of the bus has a low-impedance termination to ground, and this termination is seldom perfect. The consequences of this help to explain some characteristics of crosstalk in a system: Page 434 T13/1410D revision 3b 1) Crosstalk is produced by both the initial and reflected edges on the aggressor lines. Forward crosstalk produced by the initial edge as it propagates from the sender to the recipient arrives at the same time as the edge that produced it. The edge on the aggressor signals reflects from the high impedance at the recipient input (or at the end of the cable) and returns back to the sender. Reverse crosstalk produced as this reflected edge propagates back to the sender is observed on the victim line at the recipient. 2) If reverse crosstalk from the initial edge is not perfectly terminated at the sender’s component I/O it will be reflected (with reduced amplitude) back towards the recipient. The quality of the sender’s component I/O termination depends on the instantaneous output impedance of drivers as they are switching, as well as the on resistance of the drivers in the high or low state once they have completed switching. Since the source impedance is made up of the driver output impedance in series with the termination resistors, the most accurate source termination is achieved by using drivers with low output impedance combined with high value series resistors, creating a total output impedance near 75 Ω. 3) Crosstalk is observed with doubled amplitude at the high-impedance endpoint of the system (at the host input during read operations and at the device end of the cable during write operations) due to the reflection. Since crosstalk occurs as a pulse rather than a step, the initial and reflected portions of the pulse only sum at the endpoint while the pulse is reflecting, and not at other points along the bus. 4) Series termination resistors at the receiving end of the bus serve to attenuate the amplitude of crosstalk observed at the receiving component I/Os. Because the component I/O impedance is predominantly capacitive, its impedance decreases at high frequencies. At the frequency where the impedance of the component I/O equals the impedance of the series termination resistor, the crosstalk pulse amplitude observed at the IC input will be about half of the amplitude measured at the connector. The formula for determining this frequency is F = 1 / (2 ∗ π ∗ R ∗ C) where F is the frequency, R is the value of the series termination resistor, and C is the input capacitance of the recipient’s component I/O. So when crosstalk levels are high enough to be a serious concern, the best place to make measurements of the crosstalk is at the component I/O or on the IC side of the termination resistor. In design of systems, this filtering effect is used to reduce a system’s susceptibility to crosstalk by increasing the value of series termination resistors and placing them close to the connector to maximize the amount of capacitance on the IC side of the resistor. In systems using the 80-conductor cable the largest contributors to crosstalk are the connector at the sender, and the PCB traces in systems with long traces or a large amount of coupling between traces. The connector at the receiving end of the system generates less crosstalk than the one at the sending end because the net current flow through the aggressor lines is less at the receiving end. This is because the load on the IC side of the recipient’s connector is the PCB trace and a small capacitance inside the component I/O; only enough current flows through the connector to charge this total capacitance. At the sending end of the system, the instantaneous value of current through the connector is determined by the input impedance of the cable, and this amount of current flows for a length of time sufficient to charge the entire system including the cable and all attached devices up to the sender’s VoH . Crosstalk in the connectors is almost entirely inductive. It is produced in both directions from the connector but not necessarily in equal amplitudes. The highest amplitude crosstalk is generated by many switching lines coupling into a small number of victim lines. This lowers the effective source impedance of the crosstalk, making it approximate a voltage source. This voltage source is in series with the transmission line impedance on each side of the connector on the victim line. As a result, the crosstalk voltage is divided between the two directions proportional to the impedance seen in each direction. Figure C.18 shows the schematic of a model that demonstrates this. The PCB and cable on the victim line have been replaced with resistors to simplify the resulting waveforms. Figure C.19 shows the current through the inductor on the aggressor line and the crosstalk voltage produced on the victim line into the resistors representing the PCB and cable impedance. The waveforms indicate that the crosstalk voltage divides in the expected ratio. In this example the PCB receives (50 / (82 + 50)) ∗ 100% = 37.9% of the total voltage across the inductor, while the cable receives the remaining 62.1%. In an actual system, the crosstalk at the source is terminated by the driver impedance. The crosstalk measured at the recipient’s component I/O on the victim line is double the value of the crosstalk pulse initially produced into the cable impedance. Page 435 T13/1410D revision 3b Aggressor_src 100 Ω T2 Z0=100 Ω TD=5 ns T1 Z0=100 Ω TD=5 ns Aggressor_rec 100 Ω L1 50 nH + − V_source MUTUAL COUPLING=1 Cable 82 Ω PCB_trace 50 Ω L2 50 nH Figure C.18 – Model of voltage divider for connector crosstalk formed by PCB and cable 15 ma -5 ma at L1 200 mV -200 mV At PCB trace 200 mV -200 mV 10 ns 0 ns at cable 20 ns 30 ns 40 ns 50 ns 60 ns Time Figure C.19 – Waveforms showing connector crosstalk dividing between PCB and cable For each edge on the bus four crosstalk pulses are created on non-switching victim lines due to the combined crosstalk in the PCB, connector, and cable: Page 436 T13/1410D revision 3b 1) Forward crosstalk from the initial edge has the same sign as the edge and is seen at the recipient as a pulse that arrives with the edge. The amplitude of the pulse is doubled at the recipient’s component I/O, however because it occurs during the interval when the data is changing it may decrease the signal’s setup or hold time but it presents a minor risk to data integrity overall. 2) Reverse crosstalk from the initial edge travels back towards the driver as a flat pulse with a width equal to the transition time of the driver. Based on the degree of mismatch between the driver’s output impedance and the cable impedance, this pulse may be reflected back towards the recipient with reduced amplitude. Because it continues to arrive at the recipient well after the driver has completed switching, it creates a risk of incorrect data at the recipient in the middle of the cycle. However, this edge will seldom create a high enough amplitude at the recipient to cause a problem. 3) Forward crosstalk from the reflected edge arrives back at the driver simultaneously with the reflected edge on the aggressor lines. Depending on the impedance mismatch at the source, the edge will be reflected back towards the recipient with reduced amplitude and arrives in the middle of the cycle, however this edge will seldom create a high enough amplitude at the recipient to cause problems. 4) Reverse crosstalk from the reflected edge on the aggressor lines will be created travelling back toward the recipient and arrives there in the middle of the cycle. In host systems where the termination resistors are not placed next to the connector a larger portion of the crosstalk created in the connector will be reverse crosstalk on the cable side because of the divider formed by the 50 to 60 Ω PCB and the 82 Ω cable impedance. The pulse will be seen with doubled amplitude by the device at the end of the cable and presents a serious hazard to data integrity if its amplitude at the recipient’s component I/O exceeds 800 mV. C.2.2.5 Measuring crosstalk in a system To measure the total crosstalk in a system set up a data pattern in which one line in the middle of the data bus is held low while all other lines are asserted simultaneously. Measure the low line at the recipient connector or component I/O. This measurement includes ground bounce at the sender IC discussed in C.2.3 as well as the contributions to crosstalk of the PCBs, connectors, and cables. Determining the exact sources of the different features of the crosstalk measured by this technique is difficult. An effective method to isolate the crosstalk produced into a victim line in a given portion of the system is to sever the line before and after the feature being tested. Terminate the isolated segment to ground at the breaks with resistors equivalent to the transmission line impedance that is normally seen at those points. Measuring the crosstalk voltage across the termination resistors will indicate the raw quantity of crosstalk into the victim line produced by that portion of the system, independent of reflections due to impedance mismatches and attenuation due to capacitance along the bus. Adjusting for impedance mismatches and delays will allow the crosstalk from that portion to be identified in the total crosstalk of the system, and adjusting the impedance changes through the system may allow the impact of that crosstalk to be minimized. C.2.2.6 System design considerations to minimize crosstalk Because all crosstalk throughout the system is proportional to edge rate, a major factor in controlling crosstalk is controlling the output slew rate of the drivers. Another major factor is the impedance match of sources to the cable including the value and placement of termination resistors. Source impedance matching is important to prevent reverse crosstalk from reflecting off the source and out to the recipient. Drivers, PCB layout, and termination resistors are selected to provide a good source termination for crosstalk and the reflected signal edge. Ideal termination at each connector is when the impedance seen looking back toward the source matches the cable impedance in the forward direction. For devices, this means that the sum of driver output impedance and termination resistance match the cable impedance (typically 80 to 85 Ω), minus five to ten percent to allow for attenuation due to the capacitive loading of other devices on the cable. Because the PCB traces on a device are short, they have little effect on the device’s output impedance. Due to other design constraints, many hosts PCB traces are so long that, for high-frequency crosstalk, the impedance at the host connector is determined by the PCB trace impedance and termination resistors (if they are located at the connector), rather than by the driver’s output impedance. Because of this, there are two options for hosts with longer traces to ensure an ideal source termination: Page 437 T13/1410D revision 3b 1) Place the termination resistors near the sender’s component I/O and use a PCB trace impedance that matches the source impedance of the sender’s component I/O plus termination resistor. This ideal impedance is slightly less than the cable impedance. In this case, trace impedance of 70 to 75 Ω with a large enough trace spacing to keep crosstalk (especially reverse crosstalk) between PCB traces to a minimum is ideal. 2) Place the termination resistors near the connector and select PCB trace impedance and termination resistance to sum to the cable impedance or slightly less. In this case, matching the sender’s component I/O source impedance to the PCB trace impedance rather than the cable impedance is ideal, since that is the load that is driven. Option 2 is desirable for backward compatibility with older systems using the 40-conductor cable because placing the resistor near the connector helps to damp the ringing that occurs with that cable. In addition, 50 to 60 Ω traces are easier to implement and produce less crosstalk than higher impedance traces making the second option a better choice in most cases. In either case, matching the total output impedance to the cable impedance under all conditions of steady-state or switching is the best solution. C.2.3 Ground/Power Bounce Supply bounce is a form of crosstalk that results from changes in current through power and ground pins of IC packages. For single-ended drivers, the return current for all signals flows through the power and ground leads, with the result that any voltage drop across these pins is imposed on all signals equally. Voltage drops across these pins occur due to both resistance and inductance whenever there is a net current flow into or out of the signal pins of the IC, though inductance has the greatest effect. In terms of the voltage seen at the recipient’s component I/O, crosstalk due to supply bounce is indistinguishable from inductive crosstalk, with a sign opposite the polarity of the edge on the aggressor signal(s). See figure C.20 for a model of ground bounce in an IC package. See figure C.21 for waveforms resulting from ground bounce at the sender’s and recipient’s component I/O of the aggressor and victim signals. In order to measure supply bounce in a functioning system, it is necessary to remove all other sources of crosstalk (especially reverse crosstalk from points later in the system). To remove the other sources of crosstalk, disconnect the component I/O pin on which the measurement is being taken from the PCB and measure the voltage at the component I/O while all other lines are switching. The initial and the reflected edges on the switching lines will produce supply bounce. Measurements with the victim line in a high state show power bounce and with the victim line in a low state show ground bounce. The ground inside the IC will bounce and produce crosstalk on a low victim line when many lines are switching from high to low and sinking current through the ground pins. The power inside the IC will bounce and produce crosstalk on a high victim line when many lines are switching from low to high, and drawing current through the power pins. Page 438 T13/1410D revision 3b T1 Z0=100 Ω TD=5 ns Aggressor_src 100 Ω Aggressor_rec 100 Ω + − V12 L1 50 nH Victim_rec 100 Ω Victim_src 100 Ω T2 Z0=100 Ω TD=5 ns Figure C.20 – Model of ground bounce in IC package 1.5 V Aggressor at source Aggressor at receiver -0.5 V 400 mV -400 mV Victim at receiver 400 mV -400 mV 0 ns 10 ns Victim at source 20 ns 30 ns 40 ns 50 ns 60 ns Time Figure C.21 – Waveforms resulting from ground bounce (at transmitter and receiver of aggressor and victim lines) Page 439 T13/1410D revision 3b In order to reduce the susceptibility of Ultra DMA mode 5 to crosstalk, a tighter specification of input thresholds is defined. This Ultra DMA mode 5 requirement prevents strobing an incorrect data value due to crosstalk with a peak amplitude less than 1.5 V positive from ground or negative from the minimum Vdd of 3.3 V. C.2.4 Ringing and data settling time (DST) for the 40-conductor cable assembly High amplitude ringing may occur for some data patterns in systems using the 40-conductor cable assembly. The sixteen data lines (DD(15:0)) in a 40-conductor cable assembly are adjacent to each other and have only one ground on each side of the data lines. There are only seven ground lines present in the entire cable assembly. This lack of ground return paths has three negative effects on data signal integrity: 1) Crosstalk between data lines is very high due to inductive coupling. 2) Conductors in the center of the set of data lines (e.g., DD 11) exhibit very high inductance because the distance from these signal lines to the current return path is large and the ground return path is shared with many other signal lines. 3) Conductors in the center of the set of data lines are shielded from ground by the other data lines around them. When these lines are switching in the same direction there is no potential difference and therefore no effective capacitance between lines. This combination of factors results in the impedance of the conductors in the center of the set of data lines rising from 110 to 150 Ω (measured when a single line is asserted or negated) to an almost purely inductive 300 to 600 Ω when all lines are asserted or negated simultaneously in the same direction. Measured impedance varies with data pattern, edge rate, cable length, loading, and distance from chassis ground. Unlike the 40-conductor cable, the 80-conductor cable has the additional 40 ground lines making all signals ground-signal-ground. This makes the 80-conductor cable impedance relatively constant with respect to pattern. Matching impedance and controlling PCB trace geometry as discussed in C.3.4 will result in well damped ringing and crosstalk in victim lines that remains below 800 mV. In the following simplified model of the 40-conductor cable assembly with all data lines switching, a conductor in the center of the set of data lines is described as a pure inductor, forming a series RLC resonant circuit with the capacitance of the component I/O and PCB traces, and the combined resistance of the driver source impedance and source series termination resistor (see figure C.22). The voltage across C will ring sinusoidally in response to an input pulse at V_source, exponentially decaying over time towards a steady state value. The formula for determining the frequency of this ringing is F = 1 / (2π ∗ SQRT(LC)) where F is the frequency, R is the value of the series termination resistor, and C is the input capacitance of the recipient’s component I/O. The rate of decay is proportional to R/L. Figure C.23 shows the output of a simple RLC model with the waveforms as seen at the connectors of the sender and recipient. R 40 Ω + − V_source L 0.8 µH C 25 pf Figure C.22 – Simple RLC model of 40-conductor cable with all data lines switching Page 440 T13/1410D revision 3b 10 v source end 5v receiving end 0v -5 v 0 ns 50 ns 100 ns 150 ns Time Figure C.23 – Output of Simple RLC model: waveforms at source and receiving connectors DST is defined as the portion of cycle time required for ringing to decrease in amplitude until a signal reaches the threshold of 2.0 volts (V iH) or 800 mV (V iL ). The worst-case situation for most systems occurs when all data lines are switching except for one line near the middle of the bus that is being held low (see figure C.24). In this situation crosstalk creates a pulse on the signal line being held low that rings with a frequency and damping determined by the effective RLC parameters of the system. The DST value is the duration of time between the nominal beginning of the cycle (i.e., when the switching lines cross the 1.5 volt threshold) and the time when the ringing on the line drops below ViL for the last time as measured at the recipient’s component I/O. Page 441 T13/1410D revision 3b X1 driven line Y1 Y2 victim line X2 -22 ns 28 ns 10 ns/div Y2 Y1 delta Y 800 mV 1.5 V -700 mV 78 ns repetitive X2 X1 delta X 1/delta X 17.6 ns -1.0 ns 18.6 ns 53.7634 MHz Figure C.24 – DST measurement for a line held low while all others are switching high (ch1 on DD3 at rec., ch2 on DD11 at rec.) The same situation also occurs with reversed signal polarity (e.g., one line staying high while others are switching). Another case arises when all lines are switching simultaneously and the voltage on conductors in the center of the set of data lines rings back across the switching threshold (see figure C.25). This is normally only a problem in the high state as low side ringing is greatly reduced by the substrate diode clamp to ground that is inherent in CMOS logic. Page 442 T13/1410D revision 3b X1 receiving end source end Y1 Y2 X2 -22 ns #Avg 28 ns 10.0 ns/div Y2 Y1 delta Y 2.0 V 1.5 V 500 mV 78 ns repetitive X2 X1 delta X 1/delta X 31.8 ns 5.0 ns 26.8 ns 37.3134 MHz Figure C.25 – DST measurement for all lines switching (ch1 at source, ch2 at rec.) As seen in figure C.25, the use of 3.3 volt signaling removes the high side voltage margin provided by the asymmetric threshold of the recipient input. Consequently it is important to use slew rate controlled drivers to control ringing. C.2.4.1 Controlling ringing on a 40-conductor cable assembly An improved RLC model allows comparison between different termination schemes (see figures C.26 and C.27). These models include separate capacitors to represent trace and component I/O capacitance at the recipient’s component I/O, as well as a clamping diode, representing the substrate diode in CMOS logic. Because this single-line simplified model does not include crosstalk between lines in the data bus, it is not used to predict DST for a particular design and combination of parameters. However, it does indicate the direction of changes in ringing frequency and damping in response to changes in system parameters. R_source 7Ω Cable 1 µH C_trace 15 pf + − R_series_src 33 Ω R_series_rec 33 Ω C_ICpin 10 pf D1 D1N914 V_source Figure C.26 – Improved model of 40-conductor cable ringing with termination at IC Page 443 T13/1410D revision 3b R_source 7Ω R_series_src 33 Ω Cable 1 µH R_series_rec 33 Ω C_trace 15 pf + − C_ICpin 10 pf D1 D1N914 V_source Figure C.27 – Improved model of 40-conductor cable ringing with termination at connector Comparing the results (figure C.28) given by these models for recipient termination resistors located at the IC versus the connector shows that greater damping is provided when termination is near the connector. 10 v waveform at receiver IC waveform at receiver connector 5v 0v waveform at source connector -5 v 0 ns 100 ns 50 ns 150 ns time Figure C.28 – Results of improved 40-conductor model with termination at IC vs. connector These simple models are used in a similar way to determine the effects of changing slew rate, termination resistor value, output impedance, PCB trace length, or the length of the cable. Page 444 T13/1410D revision 3b 10 v 1 ns risetime 5 ns risetime 10 ns risetime 5v 0v -5 v 0 ns 100 ns 50 ns 150 ns time Figure C.29 – Results of improved 40-conductor model with source rise time of 1,5,and 10ns As the results in figure C.29 show, increasing the rise time to above 5 ns results in a large decrease in the amplitude of the ringing. Drivers with control over the shape of rising and falling edges are used to reduce ringing even more. Figures C.28 and C.29 show that, although the diode clamps the voltage at the recipient at one diode drop below ground, a ringback pulse appears at around 100 ns. This pulse occurs because the combined series resistance of the termination resistor and diode is much lower than the impedance of the LC circuit that is ringing. In addition the diode only clamps the voltage across part of the capacitance involved in the ringing. A higher-resistance clamping diode would be more effective at dissipating energy from the resonant circuit but would be less effective at clamping the input voltage. C.2.4.2 STROBE lines on the 40-conductor cable Although the data bus on the 40-conductor cable has such a high level of crosstalk that transmission line effects are barely perceptible, the STROBE lines on the 40-conductor cable have a more controlled impedance of about 115 Ω because they are in a ground-signal-ground configuration. Although the STROBE lines are well shielded against crosstalk from each other and from the data bus, some devices using drivers with fast edge rates and no source termination resistors have experienced problems with overshoot and ringback on the STROBE lines. Ringing will occur when a large impedance mismatch exists between the driver output impedance and the 115 Ω transmission line. If the ringback on a falling edge exceeds 800 mV, STROBE may cross the threshold multiple times and cause extra words to be clocked at the recipient. After these problems were experienced almost all device and host manufacturers began using series termination resistors on the STROBE lines at both the sender and the recipient. With current component I/O technology and the requirement for series termination resistors, ringing on the STROBE lines is seldom a problem for current systems. However, it is important to keep in mind that these are high speed edge triggered signals, and the possibility of double crossing of input thresholds due to noise, ringing, or transmission line reflections still exists. Because of this it is important that all hosts and devices implement some amount of hysteresis on STROBE inputs in addition to glitch filtering by digital logic after the inputs. Page 445 T13/1410D revision 3b C.3 System Guidelines for Ultra DMA This is a summary of recommendations for device, system, and chipset designers. These guidelines are not strict mandates, but are intended as tools for developing compatible, reliable, high-performance systems. C.3.1 System capacitance All hosts and devices are required in the body of the standard to meet maximum values of capacitance as measured at the connector. These values are specified to be 25 pf at the host and 20 pf at the device. With typical interface IC and PCB manufacturing technology, this limits host trace length to four to six inches. It is recommended that capacitance be measured at 20 MHz as this is representative of typical ringing frequencies on an 18-inch 40-conductor cable assembly. PCB traces up to 12 inches long may be used if the following conditions are met: 1) The host chipset uses 3.3 volt signaling, 2) The host chipset allows timing margin for the additional propagation delay in all delay-limited interlocks, 3) Termination resistors are chosen to minimize input and output skew and are placed near the connector, 4) Total capacitance of traces, additional components, and host component I/Os is held to the minimum possible, and 5) An 80-conductor cable is installed for operation at Ultra DMA modes 2 and higher. In this case capacitance at the connector will exceed the maximum value specified. As a result of this, systems may not operate reliably with a 40-conductor cable assembly in any Ultra DMA mode above mode 1 (22.2 megabytes per second). Under these conditions it is advisable that a host not set mode 2 or above without insuring that an 80-conductor cable assembly is installed in the system. C.3.2 Pull-up and pull-down resistors For hosts supporting Ultra DMA mode 5, the pull-up on IORDY is a 4.7 kΩ resistor to 3.3 V rather than a 1 kΩ resistor to 5 V. Other pull-up resistors on devices and hosts may be to 3.3 V or to 5 V. Pull-up and pull-down resistors should never have nominal values lower than the value specified by the standard. Placement of pull-up and pull-down resistors on the source side of the series termination minimizes loss of DC margin due to pull-up/pull-down current through the series termination resistors. C.3.3 Cables and connectors Exceeding a spacing of six inches between device connectors on an 80-conductor cable will cause increased skew when signaling to or from the device not at the end of the cable. As spacing between the devices decreases, the capacitance of the two devices (or the host and the device not at the end of the cable) act in parallel, resulting in decreased ringing frequency and increased DST. In systems using a 40-conductor cable assembly, provide a continuous electrical connection from ground on the device chassis through the system chassis to the ground plane on the host PCB. Routing the cable in close contact with the chassis will reduce data settling time, as long as it is done without significantly increasing the cable length. C.3.4 PCB and IC design As has been stated, matching the total output impedance of hosts and devices to the cable impedance is ideal to minimize reflections and reverse crosstalk due to the impedance mismatch between the PCB and cable. The impedance of the 80-conductor cable is specified to fall within the range of 70 to 90 Ω and is between 80 and 85 Ω for typical cables with solid wire and PVC insulation. Page 446 T13/1410D revision 3b Keeping the ratio of PCB trace spacing to height above ground plane high helps to control crosstalk between traces. Controlling PCB trace characteristics to minimize differences in propagation delay between STROBE and all DATA lines limits the skew. Factors that affect the delay are: 1) Trace length; 2) Additional capacitance due to stubs, routing on inner layers, pads, and external components such as pull-up resistors and clamping diodes; and 3) Additional inductance due to vias, series components such as termination resistors, and routing across a break in the ground plane, over areas with no ground plane, or at a larger height above the ground plane. In systems using an 80-conductor cable to support Ultra DMA modes 3 and higher, series termination values should be selected to meet the required output impedance into the cable based on the on-resistance of the driver when it is asserting (signal at VoH) and negating (signal at VoL). Place series termination resistors as close as possible to the cable header or connector. Choose series termination values to equalize input RC delays for the STROBE and DD(15:0) lines. For typical host IC implementations the same type of component I/O is used on all signals and therefore all termination resistors at both STROBE and DD(15:0) may have the same value. Use sufficient ground and power pins on interface ICs to control supply bounce when many lines are switching at the same time. C.3.5 Sender and recipient component I/Os The 80-conductor cable assembly impedance is less than half that of the typical 40-conductor cable assembly impedance when multiple lines are switching at the same time. For some types of drivers this will result in more than double the current draw during switching and as a consequence the amplitude of ground bounce will also double. As is required in this standard, design drivers to have a slew rate between 0.4 and 1.25 V/ns across the full range of loading conditions, process, and temperature. Design component I/Os to produce output setup and hold times at the connector as specified in this standard across the full range of loading conditions, process, and temperature. Provide margin to allow for skew introduced between the IC and the connector. Design device PCB traces and component I/Os to present similar loading between STROBE and DD(15:0) at the connector to minimize additional skew added to signaling between other devices on the bus. Use hysteresis on both DD(15:0) and STROBE inputs. Initial voltage steps on the bus are at undefined levels and may be near the thresholds, causing slow slew rates through the threshold that result in high sensitivity to noise if hysteresis is not used. Test drivers as well as host and device output characteristics at the connector with the following loading conditions: 1) 2) 3) 4) 5) 6) 7) 0 pf to ground (open circuit, minimize test fixture capacitance) 15 pf to ground 40 pf to ground 470 Ω to ground, switching low to high (simulates the 40-conductor cable with all lines switching) 470 Ω to Vcc, switching high to low (simulates the 40-conductor cable with all lines switching) 82 Ω to ground, switching low to high (simulates the initial edge into an 80-conductor cable) 82 Ω to ground, switching high to low (simulates the initial edge into an 80-conductor cable) Page 447 T13/1410D revision 3b All tests (except open circuit) are conducted with the intended series termination resistance in place. Output skew and slew rates are measured between the series termination and the load. C.4 Ultra DMA electrical characteristics Along with the electrical characteristics defined for Ultra DMA modes 0 through 4, additional electrical characteristics have been added for Ultra DMA mode 5. C.4.1 DC characteristics The ATA interface was originally designed to use 5 V signaling. All pull-up resistor values are defined based on 5 V Vcc, and many hosts and devices still use 5 V VoH signaling levels. The advantage to using 5 V I/O cell technology is that the I/O cells will be 5 V tolerant. There are, however, many disadvantages to using a 5 V VoH. One disadvantage is timing. The standard defines typical timings using a 1.5 V threshold. 5 V VoH is 2 V further from this threshold than 0 V VoL. With identical rising and falling slew rates, the time for a signal to transition from 5 V to 1.5 V on a falling edge will be longer than the time for a signal to transition from 0 V to 1.5 V on a rising edge. For example, with an average slew rate of 500 mV/ns, a falling edge could take 4 ns longer to get from 5 V to 1.5 V than a rising edge to get from 0 V to 1.5 V. In fact, typical TTL thresholds are centered even lower than 1.5 V, at 1.3 V or 1.4 V, making the situation worse for timing to actual thresholds. Setup and hold time margins must account for both rising and falling edge skew. The skew with a 5 V VoH signaling level may be minimized by using asymmetric slew rates, but this poses its own difficulties and results in higher overall skew over process and voltage variations as does skew using 3.3 V signaling. Another disadvantage to 5 V signaling is higher crosstalk. Given a 5 V transition and a 3.3 V transition having the same rise time, the 5 V transition will generate more crosstalk than the 3.3 V transition because the 5 V transition will result in higher di/dt and dv/dt to achieve the same rise time as the 3.3 V transition. Given a 3.3 V transition and 5 V transition of the same slew rate (dv/dt), the 5 V transition will still have higher crosstalk than the 3.3 V transition because the 5 V transition will be transitioning for a longer period of time. A third disadvantage to 5 V VoH levels is overshoot. Given the high edge rates and low output impedance commonly observed on the ATA interface, a 5 V edge will nearly double at the receiver because the interface is series-terminated and the receiver is high impedance. In cases where edges are generated on DD(15:0) closer than they should be for any Ultra DMA mode (less than 15 ns apart), the ringing may be pumped even higher, in one observed case to nearly 11 V. Many 5 V tolerant parts are not designed to handle this level of overshoot. C.4.1.1 ViH maximum Since Ultra DMA mode 5 outputs are required to have 3.3 V VoH levels, it is still important for a designer to remember that many hosts and devices use 5 V VoH levels. Since a 5 V device may be connected to a 3.3 V host, that host and any other device attached to the same bus must be 5 V tolerant. Since a 3.3 V device may be connected to an existing 5 V host, all devices must be 5 V tolerant. To emphasize the requirement for 5 V tolerance, a ViH maximum of 5.5 V has been added to the standard. Also added was a note stating that ringing may generate AC voltages higher than the DC maximum ViH. C.4.1.2 VDD3 (mode 5 only) Data setup and hold timings for Ultra DMA mode 5 are more stringent than for lesser modes, and the starting VoH voltage is critical for low skew. Since VDD3 of the sender and recipients typically do not track, the input threshold will not track with the VoH level. Without a defined supply voltage variation, it is difficult for an IC designer to determine if output and input I/Os will meet the required output and input skews required to meet system timing. For this reason the limits were defined for the 3.3 V supply. It should be noted that these limits are as measured at the interface IC. More careful control of the voltage may be required from the supply in order to meet these limits at the IC. Page 448 T13/1410D revision 3b C.4.1.3 VoH2 minimum and maximum (mode 5 only) The specification for the minimum and maximum VoH2 levels requires that 3.3 V I/O cells be used. The minimum VoH2 ensures that the I/O cell has a low enough on resistance to 3.3 V for proper termination with an 80-conductor cable. The maximum VoH2 ensures that when the I/O cell is enabled and the bus is above 3.3 V, the I/O will pull the bus down to 3.3 V. This prohibits the use of a 5 V I/O cell and the use of I/O cell structures that have high impedance when enabled in the high state with an output voltage of more than 1 diode drop above the output supply voltage. It is important that the output both pull up and pull down to 3.3 V so that starting voltage is always at or near 3.3 V no matter what the initial condition on the bus. Starting at a voltage at or near 3.3 V for all transitions will help insure low skew for all signal transitions. C.4.1.4 V+ and V- thresholds (mode 5 only) CRC errors may occur in some systems operating at Ultra DMA mode 5 if the thresholds are too low and crosstalk occurs that exceeds the threshold. This may cause a zero to be strobed as a one. CRC errors due to excessive skew and setup or hold violations may also occur when the thresholds are low and negative going transitions beginning at beginning 5 V do not cross the threshold on the incident edge or its first reflection. Other transfer errors have been observed that resulted from thresholds that were set too high. A V+ minimum of 1.5 V was specified to ensure that with normal levels of crosstalk, bounce, and ringing at ViL, the low-to-high threshold is not crossed. A V- maximum of 1.5 V was specified to ensure that with normal levels of crosstalk, bounce, and ringing at ViH, the high-to-low threshold is not crossed. The minimum V- was set above the maximum ViL level of 0.8 V to be consistent with thresholds centered on 1.5 V and a maximum V+ of 2.0 V. The average between the V+ and V- thresholds has also been specified with VTHRAVG. This value is used to ensure that the thresholds remain centered at 1.5 V. Shifting in the thresholds from center results in larger skew on rising verses falling inputs. Some shift is allowed to account for threshold shifts due to voltage, process, and temperature variation but less than would be allowed by the V+ and V- minimum and maximum specifications themselves. The specified VTHRAVG value ensures that, with linear and symmetric rising and falling edges that cross 1.5 V at the same time once the first threshold is crossed, the other edge will be no more than 400 mV from its actual switching threshold. C.4.1.5 Hysteresis (V HYS) (mode 5 only) Hysteresis on STROBE and DD(15:0) inputs is required so that small amounts of noise on the signal do not cause input data capturing logic or the CRC value generation logic to double clock. Cases where the wrong CRC value is generated but the correct data is captured have been observed that resulted from double clocking of the CRC generator. Cases where the correct CRC value was generated but the wrong data was captured due to lack of hysteresis on the STROBE input have also been observed. Hysteresis on DD(15:0) decreases crosstalk and improves noise immunity. C.4.2 AC characteristics High levels of ringing and crosstalk on the interface are due to the AC characteristics of the sender. While additional DC characteristics have been defined so that recipients are more tolerant of high crosstalk and ringing, requirements have been added to reduce generation of these by the sender for Ultra DMA mode 5. This provides more margin, higher reliability, and better compatibility with older components that do not meet the Ultra DMA mode 5 electrical specifications. C.4.2.1 SRISE2 and SFALL2 (mode 5 only) Maximum slew rate is defined for Ultra DMA mode 4 with SRISE and SFALL. However, it was determined that these maximums were not sufficient to reduce crosstalk to levels where victim signals maintain guaranteed low or high states. Simulations and data from many Ultra DMA mode 4 systems was used to determine the maximum slew rate for mode 5, which is lower than for modes 0 through 4. The values for SRISE2 and SFALL2 were chosen to prevent the crosstalk from exceeding 800 mV at VoL. Page 449 T13/1410D revision 3b C.4.2.2 VDSSO and VHSSO (mode 5 only) Restricting the slew rate only is not sufficient to reduce the crosstalk maximum. Following good layout practices, like the guidelines in this document, and using I/O cells with sufficient power and ground pins for the maximum current and change in current that occurs during a transition is also important. VDSSO and VHSSO measure crosstalk from the sender’s IC through the sender’s connector during a simultaneously switching output (SSO) condition. This accounts for the majority of crosstalk in a system. Since the host typically requires longer trace lengths than devices, the VHSSO value is larger. A sender that meets this SSO maximum and the maximum slew rate should not produce excessive crosstalk at the recipient for a recipient that also meets its SSO maximum as a sender. C.4.2.3 Cratio (mode 5 only) This is the ratio between the STROBE input capacitance and input capacitance of data signals. Sometimes different I/O cells are used for STROBE than for the bi-directional data lines, or additional loading is placed on some of the data lines. Under these conditions, the RC time constant of data input lines through the series termination could be very different than the time constant of the STROBE input. This could generate a large skew between data and STROBE. The Cratio value was defined to reduce the chance of high skew due to large loading variation and to encourage the use of the same I/O cell for STROBE and DATA inputs. C.5 Ultra DMA timing and protocol C.5.1 Ultra DMA timing assumptions C.5.1.1 System delays and skews Many of the system delays and skews used to determine timing specifications for Ultra DMA modes 0 through 4 were also used to determine mode 5 timing specifications. However, more stringent specifications on IC electrical characteristics are required to operate at the mode 5 transfer rate. This resulted in improvements in the specifications. These improvements apply to any Ultra DMA mode at which an Ultra DMA mode 5 capable host or device is operating, but are noted separately in the following for operation at mode 5. Timing values are also included for some cases where a single device at the end of the cable provides additional improvement. C.5.1.1.1 Source termination resistor delays Min rising source transition delay = 0.34 ns (1.9 ns for mode 5) Min falling source transition delay = 0.23 ns (1.9 ns for mode 5) Max falling source transition delay = 2.61 ns (2.7 ns for mode 5) C.5.1.1.2 Recipient termination resistor delays Max rising recipient transition delay = 0.12 ns Max falling recipient transition delay = 0.12 ns C.5.1.1.3 Transmission skews and delays All skew values are the STROBE delay minus the data delay. The value for maximum negative skew is the minimum STROBE delay minus the maximum data delay for a worst-case system configuration. The value for maximum positive skew is the maximum STROBE delay minus the minimum data delay for a worst-case system configuration. The worst case system configurations were determined through simulation and include all possible system configurations that meet the requirements of the standard. Included in these values are skew due to variation in PCB trace length, PCB trace impedance, recipient component I/O capacitance, sender and recipient series termination, pattern, and common mode capacitance. Unless otherwise noted, timings are measured at 1.5 V. Page 450 T13/1410D revision 3b Sender’s component I/O to recipient’s component I/O actual thresholds max negative skew = −5.99 ns (-4.34 ns for mode 5) Sender’s component I/O to recipient’s connector max negative skew = −3.98 ns (-2.69 ns for mode 5, -1.72 ns for mode 5 with single device only at the end of the cable) Sender’s component I/O to recipient’s component I/O actual thresholds max positive skew = 5.38 ns (3.83 ns for mode 5) Sender’s component I/O to recipient’s connector max positive skew = 3.42 ns (1.83 ns for mode 5, 1.11 ns for mode 5 with single device only located at the end of the cable) Sender’s component I/O to recipient’s component I/O maximum delay = 6.2 ns For Ultra DMA modes 0, 1, and 2 using a 40-conductor cable, an additional -70, -36, and -22 ns are included in the two maximum negative skew values listed above to account for long data settle time due to crosstalk and ringing. The maximum positive skew values are not affected since the crosstalk and ringing on STROBE is not sufficient to increase its settle time. C.5.1.2 IC and PCB timings, delays, and skews It is recommended that the timing values shown in this clause be met but they are only an example of timing values that result in a system that meets all requirements for Ultra DMA specified in the standard. A system that does not meet one or more of the timing values below may be able to meet all timing requirements by producing other timing values more stringent than those shown below. C.5.1.2.1 Possible clocks for bus timing and their characteristics All frequencies are assumed to have 60 / 40 % asymmetry (worst case) 25 MHz (supports modes 0 and 1) Typical Period = 40 ns Clock variation = 1 % 30 MHz (supports modes 0, 1, and 2) Typical Period = 33.3 ns Clock variation = 1 % 33 MHz (supports modes 0, 1, and 2) Typical Period = 30 ns Clock variation = 1 % 50 MHz (supports modes 0, 1, 2, and 3) Typical Period = 20 ns Clock variation = 3.5 % 66 MHz (supports modes 0, 1, 2, 3, and 4) Typical Period = 15 ns Clock variation = 3.5 % 100 MHz (supports mode 0, 1, 2, 3, 4, and 5) Typical Period = 10 ns Clock variation = 4.0 % C.5.1.2.2 PCB traces The PCB trace skew value is based on 2.5 ns/ft propagation delay, 10 inch maximum host trace length, 2.5 inch maximum device trace length, and data trace lengths being +/- 0.5 inch STROBE trace lengths. Page 451 T13/1410D revision 3b Max PCB trace skew = 0.1 ns Max PCB trace delay = 2.1 ns C.5.1.2.3 IC inputs The input delay value includes values for bond wire, buffer, routing, and logic component delay between the input to the IC and the flip-flop that first latches the data. Input delay is measured from 1.5 V and includes the delay between 1.5 V and the input's threshold. The value for input skew is either positive or negative depending on the direction of the STROBE and data transitions. This value is the difference in STROBE signal delay from the input switching threshold to the internal flip-flop that first latches data and data delay from the input switching threshold to the same flip-flop. The routing component of skew that accounts for about 30 % of the value listed here is systematic (i.e., always the same polarity in a system implementation) and could be either positive or negative. Min input slew rate for testing = 0.4 V/ns Max input delay = 5.5 ns (4.0 ns for mode 5) Max input skew = 2.45 ns (1.35 ns for mode 5) Max input skew from 1.5 V to actual thresholds with linear 0.4 V/ns input = 1.75 ns (1.0 ns for mode 5) C.5.1.2.4 IC outputs Output delay is from the internal active clock edge that generates an output transition until the time that the transition crosses 1.5 V at the associated component I/O of the IC. Max output disable delay is from the internal enable negation of an I/O output until the time that the signal is released at the component I/O. Single component I/O output skew is the difference in delay of rising and falling edges on a single output. This single component I/O skew does include skew due to noise that may be present on the signal in a functional system. It may be positive or negative depending on the direction of the STROBE and data transitions. Output skew is the difference in the output delay of the active STROBE and the output delay of any data transition that occurs within cycle time before or after the STROBE transition. This timing is met under all expected loading conditions and starting voltages. This timing is the combination of: – – – – – single component I/O output skew, skew due to output routing differences between all data and STROBE signals, skew due to process, temperature, and voltage variation between all data and STROBE signals at the moments when transitions are generated, skew due to clock routing to all data and STROBE logic that generates output transitions, and skew due to supply bounce differences that may occur between the transitions being compared. As with the single component I/O output skew, this skew may be positive or negative depending on the direction of the STROBE and data transitions. Some of the components of this skew (i.e. differences in routing) may be systematic but could be either positive or negative so are included in derivations using either. Max Max Max Max output delay = 14 ns output disable delay = 10 ns single component I/O output skew = 2.5 ns (2.33 ns for mode 5) output skew = 5.4 ns (3.85 ns for mode 5) Max output skew to support modes 0 and 1 with a 25 MHz clock = 5.0 ns Max output skew to support modes 0, 1, and 2 with a 50 MHz clock = 5.2 ns Max output skew to support mode 4 with a 30 or 33 MHz clock = 2.8 ns Page 452 T13/1410D revision 3b Noise skew = 0.45 ns (0.33 ns for Ultra DMA mode 5). Noise skew is part of the output skews above. It is also listed here so that the noise skew contribution can be removed from timings defined at the sender IC. However, this is intended to be used only for simulations that will not include high frequency noise coupled into the traces and cable. Noise skews for Ultra DMA mode 4 and mode 5 are based on peak-to-peak noise of 0.18 V and 0.13 V respectively and a minimum slew rate of 0.4 V/ns. Up to 3 ns of additional output delay may be needed for data compared to STROBE in cases that use 30 and 33 MHz clocks to support Ultra DMA modes 0, 1, and 2. With these clocks, the data is held by a half cycle, and a minimum half cycle is not sufficient to meet the output hold time given the output skews listed above. An additional delay on data would insure that the required hold time is met even with a short half clock cycle. Alternatively, improvements in output skew beyond those listed above could also allow the output hold time to be met with a short half clock cycle. C.5.1.2.5 IC flip-flops The setup and hold times listed here are intended to represent only the flip-flops inside an IC that latch data. Timing is assumed from the inputs of the flip-flop. Min flip-flop setup time = 0.5 ns (0.2 ns for mode 5) Min flip-flop hold time = 0.5 ns (0.2 ns for mode 5) C.5.2 Ultra DMA timing parameters System timings for all Ultra DMA modes are measured at the connector of the sender or receiver to which the parameter applies. Internally the IC accounts for input and output delays and skews associated with all signals getting from the connector to the internal flip-flop of the IC and from the flip-flop of the IC to the connector. Timings as listed in the body of the specification were derived using the formulas listed below and the timing assumptions give above. All applicable clocks were evaluated for each timing parameter and the worst-case value was used in the body of the standard. It is recommended that the system designer re-derive all timings based on the specific characteristics of the internal clock, IC, and PCB that are to be used to confirm that timing requirements are met by that implementation. C.5.2.1 Typical average two-cycle time (t2CYCTYP) This is the typical sustained average time of STROBE for the given transfer rate from rising edge to rising edge or falling edge to falling edge measured at the recipient’s connector. C.5.2.2 Cycle time (tCYC ) This is the time allowed for STROBE from rising edge to falling edge or falling edge to rising edge measured at the recipient’s connector. This timing accounts for STROBE and internal clock variation. The formula for the minimum value is: + (Number of clock cycles to meet minimum typical cycle time with a minimum cycle time due to clock variation) ∗ (clock cycle time) – Max single component I/O output skew tCYC should be measured at the recipient connector at the end of the cable. Measurement of this parameter at the sender connector is obscured by reflections on the bus. Page 453 T13/1410D revision 3b C.5.2.3 Two-cycle time (t2CYC ) This is the time for STROBE for the given transfer rate from rising edge to rising edge or falling edge to falling edge measured at the recipient’s connector. Since this timing is measured from falling edge to falling edge or rising edge to rising edge of STROBE, asymmetry in rise and fall time has no affect on the timing. Clock variation is the only significant contributor to t2CYC variation. The formula for the minimum values is: + (2 ∗ (Number of clock cycles to meet minimum typical cycle time with a minimum cycle time due to clock variation percent) ∗ (clock cycle time)) C.5.2.4 Data setup time (tDS) This is the data setup time at the recipient. Since timings are measured at the connector and not at the component I/O, consider the effect of the termination resistors and traces when generating this number. Depending on the direction of the data signal and STROBE transitions, the skew between the two changes in both the positive and negative directions. A longer data signal delay will reduce the setup time, and a longer STROBE delay will increase the setup time. In order to meet the input skews given above, minimize the number of buffers or amount of logic between the incoming signals and the input latch or flip-flop. This may require the data input buffers to be routed directly to the input latch with no delay elements and the STROBE signal to be routed directly from its input buffer to the input latch clock with no delay elements. The internal latch or flip-flop has a non-zero setup and hold time. tDS is sufficient to insure that the setup time of the flip-flop is met. The minimum setup required at the threshold of the component I/O is: + Max input skew + Min flip-flop setup time The formula for the value at the recipient’s component I/O based on the timings given in C.4 is: + (Number of clock cycles to meet typical cycle time with a minimum cycle time due to clock variation) ∗ (clock cycle time) − (Number of clock cycles used to hold data with a minimum cycle time due to clock variation or with a minimum cycle symmetry if a half cycle is used) ∗ (clock cycle time) − Max output skew + Sender’s component I/O to recipient’s component I/O actual thresholds max negative skew In order to meet both setup and hold times over process, temperature, and voltage, clock edges rather than gate delays are used to generate the hold time. The assumption is made that one 50 or 66.7 MHz clock cycle or half of a 33 MHz or slower clock cycle has been used to hold data within the sender IC. After it is shown that the sender is producing a setup time that meets the requirement of the recipient, the specification for setup time at the recipient connector produced by the sender is determined as follows. The tDS values in the specification were based on the results of the following formula using all possible clocks for the modes they support. The tDS value for mode 5 was defined for a single device only located at the end of the cable in order for best determination of system margin during validation. A value for two devices attached to the cable is determined with the timings given above. + (Number of clock cycles to meet typical cycle time with a minimum cycle time due to clock variation) ∗ (clock cycle time) − (Number of clock cycles used to hold data with a minimum cycle time due to clock variation or with a minimum cycle symmetry if a half cycle is used) ∗ (clock cycle time) − Max output skew + Sender’s component I/O to recipient connector max negative skew Page 454 T13/1410D revision 3b C.5.2.5 Data hold time (tDH) This is the data hold time at the recipient. This time is sufficient to insure that the hold time of the internal flipflop is met. The longest STROBE delay and shortest data delay is the worst case for hold time. The analysis is similar to the one for tDS above. The minimum hold required at the component I/O at its threshold is: + Maximum input skew + Minimum flip-flop hold time The formula for the value at the recipient’s component I/O based on the timings given above is: + (Number of clock cycles used to hold data with a minimum cycle time due to clock variation or with a minimum cycle symmetry if a half cycle is used) ∗ (clock cycle time) − Max output skew − Sender’s component I/O to recipient’s component I/O actual thresholds max positive skew After it is shown that the sender is producing hold time that meets the requirement of the recipient, the specification for hold time at the recipient connector produced by the sender is determined as follows. The tDH values in the specification were based on the results of the following formula using all possible clocks for the modes they support. The tDH value for mode 5 was defined for a single device only located at the end of the cable in order for best determination of system margin during validation. A value for two devices attached to the cable is determined with the timings given above. − (Number of clock cycles used to hold data with a minimum cycle time due to clock variation or with a minimum cycle symmetry if a half cycle is used) ∗ (clock cycle time) − Max output skew − Sender’s component I/O to recipient connector max positive skew C.5.2.6 Data valid setup time (tDVS) This is the data valid setup time measured at the sender’s connector. This timing is measured using a test load with no cable or recipient. This is the timing that, if met by the sender, will insure that the data setup time is met at the recipient. It is important that this timing be met using capacitive loads from 15 to 40 pf to ensure reliable operation for any system configuration that meets specification. In the case of Ultra DMA modes 0, 1, and 2, long data settle times occur due to crosstalk in the cable and on the PCB, and the ringing frequency of the system. For modes above 2, there is little or no margin for ringing on the cable. For these modes, the 80-conductor cable assembly that reduces the crosstalk between signals is required so that crosstalk and ringing are reduced to a level that does not cross the input switching thresholds during data setup or hold times. Modes 3 and 4 timing requirements were derived to be met with the same input and output timing characteristics as a system supporting Ultra DMA mode 2. Since the formulas presented for tDS show that sufficient setup time is produced with the given system timings, using those same timings in the formula below will produce tDVS values that also represent sufficient timing for the system. An achievable value for tDVS is calculated as follows: + (Number of clock cycles to meet minimum typical cycle time at the minimum cycle time due to clock variation) ∗ (clock cycle time) − (Number of clock cycles used to hold data at the minimum cycle time due to clock variation or at the minimum cycle symmetry if a half cycle is used) ∗ (clock cycle time) − Max output skew − Max PCB trace skew − Max falling source transition delay + Min rising source transition delay Page 455 T13/1410D revision 3b C.5.2.7 Data hold time (tDVH ) This is the data valid hold time measured at the sender’s connector. This timing is measured using a test load with no cable or recipient. This is the timing that, if met by the sender, will insure that data hold time at the recipient is met. It is important that this timing be met using capacitive loads from 15 to 40 pf to insure reliable operation for any system configuration that meets specification. Since the formulas presented for tDH show that sufficient hold time is produced with the given system timings, using those same timings in the formula below will produce tDVS values that also represent sufficient timing for the system. An achievable value for tDVH is calculated as follows: + (Number of clock cycles used to hold data at the minimum cycle time due to clock variation or at the minimum cycle symmetry if a half cycle is used) ∗ (clock cycle time) − Max output skew − Max PCB trace skew − Max falling source transition delay + Min rising source transition delay C.5.2.8 CRC word setup time (tCS) (mode 5 only) For Ultra DMA modes 0 through 4 the value for tCS is the same as the value for tDS. The formula and details used to determine tCS are identical to the ones used to determine tDS. In order to determine the value for tCS for mode 5, Ultra DMA mode 4 output, system, and input skew values are used rather than the mode 5 values. This is because DMACK- is used to strobe the CRC word rather than HSTROBE. Host system designers sometimes pay very close attention to the skew between HSTROBE and DD(15:0). The secondary function of DMACK- is as a clock for the CRC word. On the device, flip-flops to capture data will be carefully placed to minimize skew between incoming data and HSTROBE. Rather than require the device to add the additional flipflops needed to capture the CRC word with respect to the DMACK- signal, the value for tDS for Ultra DMA mode 4 is specified. C.5.2.9 CRC word hold time (tCH) (mode 5 only) For Ultra DMA modes 0 through 4 the value for tCH is the same as the value for tDH. The formula and details used to determine tCH are identical to the ones used to determine tDH. In order to determine the value for tCH for mode 5, Ultra DMA mode 4 output, system, and input skew values are used rather than the mode 5 values. This is because DMACK- is used to strobe the CRC word rather than HSTROBE. Host system designers sometimes pay very close attention to the skew between HSTROBE and DD(15:0). The secondary function of DMACK- is as a clock for the CRC word. On the device, flip-flops to capture data will be carefully placed to minimize skew between incoming data and HSTROBE. Rather than require the device to add the additional flipflops needed to capture the CRC word with respect to the DMACK- signal, the value for tDH for Ultra DMA mode 4 is specified. C.5.2.10 CRC word valid setup time (tCVS) (mode 5 only) For Ultra DMA modes 0 through 4 the value for tCVS is the same as the value for tDVS. The formula and details used to determine tCVS are identical to the ones used to determine tDVS. In order to determine the value for tCVS for mode 5, Ultra DMA mode 4 output, system, and input skew values are used rather than the mode 5 values for reasons given in the description for tCS. If specified to be the same value for mode 5 as that specified for mode 4, tCVS for mode 5 would be less than the time of one 100 MHz clock cycle. Though a single system clock cycle was sufficient for tCVS for mode 4, consideration of all output skews demonstrates that the mode 4 setup time is not met with a single 100 MHz clock cycle. Therefore, the value for mode 5 tCVS was set to 10 ns. Page 456 T13/1410D revision 3b C.5.2.11 CRC word valid hold time (tCVH ) (mode 5 only) For Ultra DMA modes 0 through 4 the value for tCVH is the same as the value for tDVH . The formula and details used to determine tCVH are identical to the ones used to determine tDVH . In order to determine the value for tCVH for mode 5, Ultra DMA mode 4 output, system, and input skew values are used rather than the mode 5 values for reasons given in C.5.2.9. If specified to be the same value for mode 5 as that specified for mode 4, tCVH for mode 5 would be less than the time of one 100 MHz clock cycle. Though a single system clock cycle was sufficient for tCVH for mode 4, consideration of all output skews demonstrates that the mode 4 setup time is not met with a single 100 MHz clock cycle. Therefore, the value for mode 5 tCVH was set to 10 ns. C.5.2.12 First DSTROBE time (tZFS) (mode 5 only) The protocol for every Ultra DMA mode relies on the fact that IORDY has a pull-up resistor at the host. It is true, however, that if the device chooses to generate the first high-to-low transition by switching the driver from released to negated (as is allowed by the protocol for Ultra DMA modes less than 5) that transition could have a longer delay than other high-to-low transitions. This is especially true in the case where there is an I/O buffer with a 3.3 V VoH level and a bus that is pulled up to 5 V. On subsequent high-to-low transitions, the transition would start at or near 3.3 V instead of at or near 5 V, which would result in a shorter fall time and better delay matching with the rising transition through the input thresholds. In all modes less than mode 5, there is sufficient timing margin to use 5 V I/O cells. Many device and host implementations for Ultra DMA mode 4 use 5 V VoH outputs. In the case of an output with a 5 V VoH, the released-to-negated transition may have about the same delay as an asserted-to-negated transition. With a 5 V output I/O cell having reasonable skew and a typical hold time of 15 ns, the first high-to-low STROBE transition could be generated by going from released to negated while still meeting the hold time minimum. The mode 5 setup and hold timings require much lower skews between rising and falling edges than previous modes. It is therefore required that the mode 5 STROBE first falling edge start at or near 3.3 V and is generated with an output that is settled. The mode 5 timing tZFS minimum requires the device to assert DSTROBE a specified time before the first negation. When enabled high, I/O cells used for mode 5 are required to pull the bus down to a value at or near 3.3 V if the bus is higher than 3.3 V when enabled. Starting a negation from being asserted at or near 3.3 V will provide better symmetry between negating and asserting transitions than when starting at or near 5 V. I/O cells may also have some internal transistors and reference settle times after being enabled. If the first negation is generated by switching from released to negated, the transition will not be as well controlled as one generated after the output has been asserted long enough to settle. For mode 5, DSTROBE must be asserted for the specified time before the first high-to-low transition in order for that transition to start at or near 3.3 V and for that transition to have the same edge rate control and delay as any other high-to-low transition. It should be noted that when DSTROBE is first asserted, it must not produce any glitch that would pull the bus down below the host’s V- threshold. In that case, the host would incorrectly detect a DSTROBE transition. In order to force the device to enable DSTROBE asserted before generating the first DSTROBE negation, the tZFS timing parameter was added. C.5.2.13 Data enabled to the first DSTROBE edge time (tDZFS) (mode 5 only) As described above, DSTROBE must be asserted for a sufficient time before first negation to provide good timing and slew rate for that negation. DD(15:0) must also be driven for a sufficient time before the first STROBE transition is generated for DD(15:0) to be settled long enough to meet the setup time and to generate good edges after the required hold time. If DD(15:0) are enabled for the typical setup time before the first STROBE transition, the setup time will not be met. As with DSTROBE, this is because a transition generated from released to negated or asserted will have a longer delay than a transition generated from negated to asserted or asserted to negated. The tDZFS timing for mode 5 assumes a typical 10 ns hold time for DD(15:0) and, since this time is referenced to the STROBE transition, it assumes the same delay for DD(15:0) from enabled to first transition as tZFS is for DSTROBE. For most cases, it is sufficient for DD(15:0) to settle in time Page 457 T13/1410D revision 3b to meet the required setup time. However, if the released to asserted or released to negated time is longer than about 10 ns, a longer enabled to first STROBE time is required in order to meet tDVS. C.5.2.14 First DSTROBE time (tFS) This is the time for the device to first negate DSTROBE to clock the first word of data for a data-in burst after the device has detected that the host has negated STOP and asserted HDMARDY-. This parameter is measured from the when both STOP is negated and HDMARDY- is asserted at the device connector until the first negation of DSTROBE at the device connector. Synchronization may be achieved with two flip-flops. After synchronization is achieved, data is driven on to DD(15:0) and internal clock cycles counted to meet the minimum setup time before generating the first DSTROBE transition. In order for an IC based on a 25, 30, or 33 MHz clock to meet tFS, DD(15:0) must be driven no later than 2.5 clock cycles after the control signal transitions. This could be achieved by synchronizing with both edges of the system clock or by using only one edge to synchronize and then driving data onto DD(15:0) on the next inactive edge of the clock after the signals are detected at the output of the second synchronization flip-flop. With a 50 MHz clock, the first word of data must be driven out no later than three cycles after the control transitions and with a 66 MHz clock, it may be four cycles. The formula for the maximum tFS timing is as follows: + + + + + Max falling recipient transition delay Max PCB trace delay Max input delay Min flip-flop setup time The time for two, three, or four clock cycles at the maximum period due to frequency variation to synchronize the control signals and start the data transfer cycle. For 25, 30, and 33 MHz systems, the data would be driven out one half cycle after the incoming signal is synchronized since data is held one half cycle when using these clock frequencies and therefore sent on a half cycle. + The time for as many cycles as required to meet the tDVS minimum timing for the first word of data at the maximum period due to frequency variation. + Max output buffer delay + Max PCB trace delay + Max falling source transition delay C.5.2.15 Limited interlock time (tLI) The time is for limited interlock from sender to recipient or recipient to sender. This is the interlock time in the Ultra DMA protocol that has a specified maximum. The value of tLI must be large enough to give a recipient of the signal enough time to respond to an input signal from the sender of the signal. The derivation of tLI is similar to that of tFS since both involve the recipient of the signal responding to the control signal of the sender of the signal. As with tFS, the number of internal clock cycles that an IC may require before responding is dependent on the frequency of the clock being used. For a 25 or 30 MHz clock, the maximum time to respond is three cycles, for 33 MHz clock it is four, for a 50 MHz clock it is five, and for a 66 MHz clock it is seven cycles maximum for modes 0 through 2. Modes 3, 4, and 5 require a faster response time. For a 30 or 33MHz clock it is two cycles, for a 50 MHz clock it is three cycles and for a 66 MHz clock it is four clock cycles maximum. The formula for the values of tLI is as follows: + + + + + Max falling recipient transition delay or max rising recipient transition delay Max PCB trace delay Max input delay Min flip-flop setup time The time for two, three, four, five, or seven clock periods (depending on clock used and modes supported) at the maximum period due to frequency variation to synchronize the signals to the internal clock and respond appropriately. + Max output buffer delay Page 458 T13/1410D revision 3b + Max PCB trace delay + Max falling source transition delay C.5.2.16 Limited interlock time with minimum (tMLI) This time is for the minimum limited interlock from sender to recipient. This timing insures that the respective control signals are in their proper state before DMACK- is negated. It is important that STROBE and the control signals are in their proper states because all signals revert to their non-Ultra DMA definitions at the negation of DMACK-. If the signals are not in their proper state, the selected device or another device may incorrectly interpret a STROBE signal. For all control signals to be in their proper state and detectable at the device before DMACK- is negated, tMLI must exceed the sum of the following: + Sender’s component I/O to recipient’s component I/O maximum delay + Max input delay + Min flip-flop setup time The value calculated by the formula above for tMLI for all modes is under 14 ns. The specified value for this timing allows for additional margin. C.5.2.17 Unlimited interlock time (tUI) This interlock timing is measured from an action by a device to a reaction by the host. In order to allow the host to indefinitely delay the start of a read or write transfer, this value has no maximum. The reason for this parameter is to ensure that one event occurs before another, for this reason the minimum is set to zero. In practice the host will take some non-zero positive time to respond to the incoming signal from the device. C.5.2.18 Maximum driver release time (tAZ) This is the maximum time that an output driver has to make the transition from being asserted or negated to being released. During data bus direction turn around, the driver of DD(15:0) is required to release these signal lines. For the beginning of a read burst, the host releases DD(15:0) before or on the same internal clock cycle that it asserts DMACK-. For the end of a read burst, the device releases DD(15:0) before or on the same clock cycle that it negates DMARQ. If the same clock is used, the maximum delay is calculated using the following formula: + Max output skew − Min falling source transition delay The value calculated by the formula above for tAZ for all modes is under 6 ns. The specified value for this timing allows for additional margin. C.5.2.19 Minimum delay time (tZAH ) This is the minimum time that the host waits after the negation of DMARQ at the termination of a data-in transfer to begin driving data onto DD(15:0) for the purpose of transferring the CRC word to the device. In this case the device is allowed to continue driving DD(15:0) for a maximum of tAZ after the DMARQ negation. The host is required to wait tZAH after the DMARQ negation to drive the data. Skew on the cable is the major factor to consider here and a longer data delay than DMARQ delay (i.e., max negative skew) is the worst case. For modes using a 40-conductor cable, the component of maximum negative skew associated with data settle time as described above should not be included since DD(15:0) is being released for this timing. To avoid bus contention, this value is calculated using the following formula: + Max specified tAZ – Sender’s component I/O to recipient’s component I/O actual thresholds max negative skew Page 459 T13/1410D revision 3b The value calculated by the formula above for tZAH is under 17 ns in all cases. The specified value for this timing allows for additional margin. C.5.2.20 Minimum driver assert/negate time (tZAD ) This is the minimum time after STOP is negated or HDMARDY- is asserted (whichever comes later) that a device drives DD(15:0) at the initiation of a data-in burst. This is when DD(15:0) are changed from host driving or released to device driving. The STOP negation and HDMARDY- assertion are required by the standard to meet tENV timing that is a minimum of 20 ns from the point where the host releases DD(15:0). No additional delay is necessary based on the tZAH evaluation that is applicable to the conditions of this timing. The device waits for STOP to be negated and HDMARDY- to be asserted and then may start driving DD(15:0). The use of STOP negated and HDMARDY− asserted guarantees that a system failure will not occur leaving the host in a Multiword DMA mode and the device in an Ultra DMA mode. STOP is the same signal line as DIOW-, and HDMARDY- is the same signal line as DIOR-. The Multiword DMA protocol never allows assertion of both DIOW- and DIOR- at the same time. The negation of STOP and assertion of HDMARDY- is equivalent to both DIOW- and DIOR- being asserted. Since the device requires both signals to be in this state before driving DD(15:0), it insures that the host is in an Ultra DMA mode and not a Multiword DMA mode and has released DD(15:0). Even though tZAD has a 0 ns minimum for all modes, in practice, most devices will take two flip-flop delays to synchronize the incoming STOP and HDMARDY- transitions making the tZAD time dependant on the clock frequency used by the device. Since DD(15:0) are driven long enough before the first STROBE to meet the setup time requirement, this synchronization time has been taken into account in the tFS derivation above. C.5.2.21 Envelope time (tENV) This time is from when the host asserts DMACK- until it negates STOP and asserts HDMARDY- at the beginning of a data-in burst, and the time from when the host asserts DMACK- until it negates STOP at the beginning of a data-out burst. Since tENV only applies to outputs from the host, the timings are synchronous with the host clock. Based on an argument similar to the one for tMLI in C.5.2.16, the minimum for tENV is 20 ns. This insures that all control signals at all the devices are in their proper (non-Ultra DMA mode) states before DMACK- is asserted and are sensed as changing only after DMACK- has been asserted. The 20 ns accounts for cable and gate skew between DMACK- and the control signals on device inputs. Since tENV involves synchronous events only and an increase in tENV reduces the performance of the specification, a maximum is specified. Enough internal clock cycles are used between the assertion of DMACK- and the other control signals to insure tENV minimum is met. For a 25, 30, or 33 MHz clock this is a single cycle, for 50 or 66 MHz clocks this is two cycles. The following formula is used to verify that the minimum tENV value of 20 ns is met by any particular system implementation: + (One or two host clock cycles (depending on frequency used) at the minimum period due to frequency variation to delay control signals inside the IC) ∗ (clock cycle time) – Max output skew – PCB trace skew – Max falling source transition delay + Min falling source transition delay The minimum is achieved by using the number of clock cycles specified above for each possible frequency. Based on the number of clock cycles needed to meet the minimum, reasonable maximums for tENV are determined. Rather than limiting the possible cycles to generate tENV, the following assumption was made: for a 25 or 30 MHz clock a single cycle is used; for a 33 or 50 MHz clock a maximum of two cycles is used; and, Page 460 T13/1410D revision 3b for a 66 MHz clock a maximum of three clock cycles is used. Using these numbers of cycles, the formula to determine the maximum tENV is as follows: + (One, two, or three cycles (depending on frequency used) at the maximum period due to frequency variation to delay control signals inside the IC) ∗ (clock cycle time) + Max output skew + PCB trace skew + Max falling source transition delay − Min falling source transition delay It may be possible that fewer or more clock cycles are used with some frequencies given reduced output skew. If the AC timing characteristics described above are just met, the following number of clock cycles for the internal IC delay to meet tENV minimum and maximum values are used. 1) 2) 3) 4) 5) 6) with 25 MHz, delay is one cycle with 30 MHz, delay is one cycle with 33 MHz, delay is one or two cycles with 50 MHz, delay is two cycles with 66 MHz, delay is two or three cycles (only two for modes above 2) with 100 MHz, delay is three cycles C.5.2.22 STROBE to DMARDY- time (tSR ) If DMARDY- is negated before this maximum time after a STROBE edge, then the recipient will not receive more than one additional STROBE (i.e., one more word of valid data). This timing is applicable only to modes 0, 1, and 2 because the transfer rate of modes 3, 4, and 5 is too high to insure that only one additional STROBE will be sent after DMARDY- is negated. Though there is no known implementation of the following method, this timing could be met by the recipient through the synchronization of the outgoing DMARDY- negation and the incoming STROBE signal from the sender. Design complexity would be added with little advantage. For this reason tSR was removed from the timing table for Ultra DMA mode 4. The asynchronous negation of DMARDY- with respect to the incoming STROBE is the preferred implementation. In this implementation, the negation of DMARDY- for pauses would be controlled by the state of the FIFO. Once a near-full condition occurs, DMARDY- could be negated. There is no advantage toward FIFO size in trying to meet tSR since synchronizing the outgoing DMARDY- signal with the incoming STROBE requires an additional STROBE to occur after a FIFO near-full condition is detected before the DMARDY- can be negated. If the asynchronous method is selected as recommended, then the recipient will always be ready for the maximum number of words allowed after it negates DMARDY-. C.5.2.23 DMARDY- to final STROBE time (tRFS) This is the maximum time after DMARDY- is negated after which the sender will not transmit any more STROBE edges (i.e., no additional valid data words). This timing gives the sender time to detect the negation of DMARDY- and respond by not sending any more STROBES. The tRFS time may affect the number of words transferred. Since tRFS involves a response to a request for a pause, the sender needs to stop sending data as soon as practical. An example of an input synchronization method is to use two flip-flops where the first is clocked on the active edge of the internal clock and the second on the unused (inactive) edge of the clock. The action to stop the STROBE signal would be taken on the next active clock edge (i.e., if there had been a STROBE scheduled for that edge it would not be sent). In this example a half cycle of the clock gives adequate time to avoid metastability while synchronizing the signal. The following timing diagram shows one possible case: Page 461 T13/1410D revision 3b tRFS range Next STROBE would have been here Clock STROBE DMARDYFF1 FF2 Figure C.30 – DMARDY- to final STROBE tRFS synchronization Figure C.30 shows the range of possible STROBE to DMARDY- transition relationships and the possible synchronization flip-flop responses. When a 66 MHz or higher clock frequency is used, two clock periods may be used to synchronize the data as long as no STROBE edge is sent on the subsequent clock edges until the transfer is resumed. The tRFS time may be the longest when the DMARDY- transition occurs before an internal clock cycle, but, due to skews and missed setup time, the transition is not clocked into the first flip-flop until the next clock (the dotted line transition on FF1 and later on FF2). When this happens one clock cycle before a STROBE transition is generated (as shown by the left tRFS range marker near the middle of the DMARDY- transition range in the diagram above), the next STROBE transition will occur (as shown in dotted lines). For all other cases, the tRFS time will be shorter. The maximum tRFS is calculated using the following formula: + + + + + Max rising recipient transition delay Max PCB trace delay Max input delay Min flip-flop setup time (One or two clock cycles at the maximum system clock period due to frequency variation for synchronization) ∗ (clock cycle time) + Max output delay + Max PCB trace delay + Max falling source transition delay C.5.2.24 DMARDY- to pause time (tRP) This is the minimum time after DMARDY- is negated after which the recipient may assert STOP or negate DMARQ-. After this time the recipient will not receive any more STROBE edges (i.e., no additional valid data words). STROBE edges may arrive at the recipient until this time. Since this time parameter applies to the recipient only as the recipient waits for STROBEs, the parameter is measured at the recipient connector. Because of this, the output delay of DMARDY- from inside the IC to the connector and the input delay of a STROBE edge from the connector to the associated internal IC flip-flop are considered. There are two ways to determine the tRP minimum. One method is to consider how long it will take from the negation of DMARDY- at the recipient for the sender to see the negation and become paused. This would involve synchronizing DMARDY- as it is done for tRFS, and then taking one more system clock cycle to change the state of the state machine to a paused state. Using this method, the minimum time is calculated using the following formula: + Sender’s component I/O to recipient’s component I/O maximum delay + Max input delay + Min flip-flop setup time Page 462 T13/1410D revision 3b + (Two or three clock cycles (depending on clock used) at the maximum period due to clock frequency variation) ∗ (clock cycle time) A second method to calculate this value is to consider how long it might take for the last STROBE to be detected after negating DMARDY-, and make sure tRP is long enough so that the internal assertion of STOP occurs after the last STROBE has latched the last word of data. This method is applied in the following formula: + + + + + Sender’s component I/O to recipient’s component I/O maximum delay Maximum tRFS for mode Sender’s component I/O to recipient’s component I/O maximum delay Max input delay Min flip-flop setup time Using both of the above, it may be shown that tRP is met given the tRFS requirement and is sufficient to receive the last STROBE for all modes with all clock frequencies. All of the values are measured at the connector, and the time to wait internal to the IC will be longer than the value of tRP. For higher frequency clocks, the internal delay may need to be more than one clock cycle longer than the value of tRP in order to account for total output and input delays. C.5.2.25 Maximum IORDY release time (tIORDYZ) This is the maximum time allowed for the device to release IORDY:DDMARDY-:DSTROBE at the end of a burst. The tIORDYZ time allows IORDY to be asserted immediately after DMACK- is asserted. DMACK- being asserted may be used to enable the IORDY output. As soon as the DMACK- is negated, the component I/O cell will be released. For this implementation, the following formula determines the maximum tIORDYZ: + + + + + Max falling recipient transition delay Max PCB trace delay Max in delay (in this case to enable IORDY) Max output disable delay Max trace delay C.5.2.26 Minimum IORDY assert time (tZIORDY) This is the minimum time allowed for the device to assert IORDY:DDMARDY-:DSTROBE when the host asserts DMACK- at the beginning of a burst. When STOP is negated and HDMARDY- is asserted, it is important that the IORDY:DDMARDY-:DSTROBE signal be electrically high (DSTROBE asserted or DDMARDY- negated). This could be achieved by the device driving the IORDY:DDMARDY-:DSTROBE signal, but it also occurs when this signal is released by the device because of the pull-up at the host required by the standard. Since the correct state of IORDY:DDMARDY:DSTROBE occurs when it is released, no maximum tZIORDY is required. As with some other timings having no maximum defined, the state of this signal will eventually be changed as governed by other timing parameters. For Ultra DMA, DDMARDY-:DSTROBE is only driven during a data burst. At the initiation of a data-in burst, the device may wait until the time to generate the first DSTROBE and enable DSTROBE in a negated state. The device may wait tZIORDY then assert DSTROBE and, for the first data transfer, the device would negate DSTROBE. In both cases the host sees a negation for the first DSTROBE. The first STROBE of a burst is never a low-to-high transition. At the initiation of a data-out burst, the device waits until ready before asserting DDMARDY-. If the device does not use this implementation, it waits tZIORDY then negates DDMARDY- (i.e., drives it electrically high). Then, to signal that the device is ready to receive data, the device may negate DDMARDY-. Both implementations are equivalent since the negated state of this signal will appear the same to the host as the released state. Page 463 T13/1410D revision 3b Since this timing was defined for the sole purpose of requiring DMARDY- to be asserted before IORDY is driven, the minimum value for this timing in all modes is 0 ns. C.5.2.27 Setup and hold before DMACK- time (tACK) The tACK value is defined for the setup and hold times before assertion and after negation of DMACK-. It is applied to all control signals generated by the host related to an Ultra DMA burst. These signals are STOP, HDMARDY-, HSTROBE, CS1-, CS0-, and DA(2:0). The burst begins with the assertion of DMACK- and ends with the negation of DMACK-. For this burst period, all control signals start, remain, and end in specific states as defined by the protocol. Since there may be some skew between signals from the host to the device due to transmission and component I/O circuitry effects, the host is required to set up all the control signals before asserting DMACK-. This insures that by the time all the signals reach the device, they will all be in the proper state when DMACK- is asserted. Using tACK as the hold time for the signals after the negation of DMACKinsures that at the termination of the burst, the control signals as seen by the device are in the proper states. This avoids any device state machine confusion. Based on the same analysis used for tMLI, the minimum for tACK is 20 ns. C.5.2.28 STROBE to DMARQ/STOP time (tSS) This is the minimum time after a STROBE edge before a device as a sender negates DMARQ or a host as a sender asserts STOP to terminate a transfer. This time is to allow at least one recipient clock cycle between the last STROBE and the termination signal to avoid the possibility of a race condition between the two events and ensure the last word is seen as valid by the recipient. The formula used to determine tSS minimum is: + Sender’s component I/O to recipient’s component I/O actual thresholds max positive skew + Max input skew + (One recipient clock cycle at the maximum period due to frequency variation) ∗ (clock cycle time) For modes 0 and 1, a 25 MHz recipient clock is assumed and for all other modes a 30 MHz recipient clock is assumed. While the value specified could have been lower for modes using 30 MHz or higher clock frequencies, tSS is specified to be the same value for all modes for extra margin. C.5.2.29 Data setup time at IC component (tDSIC) (mode 5 only) This parameter defines the minimum setup time at the input to the recipient’s IC given linear 0.4 V/ns transitions on DD(15:0) and STROBE through 1.5 V. It is included so that IC designers will have an explicit recipient setup time to be simulated during the design phase that will result in a functional system. The formula and details used to determine tDSIC are identical to the ones used to determine tD S above except for the following. First, the IC-to-IC skew is used rather than IC-to-connector skew as in tDS. Second, since the IC-toI/C skew is defined from 1.5 V at the sender to the actual thresholds of the recipient’s I/C, the value of the maximum input skew from 1.5 V to actual thresholds with linear 0.4 V/ns input defined in IC input skew above is added to the modified tDS value. The resulting value is the setup time with 0.4 V/ns transitions through 1.5 V that shall be met to be equivalent to the setup time generated in a functioning system. C.5.2.30 Data hold time at IC component (tDHIC) (mode 5 only) This parameter defines the minimum hold time at the input to the recipient’s IC given linear 0.4 V/ns transitions on DD(15:0) and STROBE through 1.5 V. It is included so that IC designers will have an explicit recipient hold time to be simulated during the design phase that will result in a functional system. The formula and details used to determine tDHIC are identical to the ones used to determine tDH except for the following. First, the IC-toIC skew is used rather than IC-to-connector skew as in tDS. Second, since the IC-to-IC skew is defined from 1.5 V at the sender to the actual thresholds of the recipient’s IC, the value of the maximum input skew from 1.5 V to actual thresholds with linear 0.4 V/ns input defined in IC input skew above is added to the modified tDS value. The resulting value is the hold time with 0.4 V/ns transitions through 1.5 V that shall be met to be equivalent to the hold generated in a functioning system. Page 464 T13/1410D revision 3b C.5.2.31 Data valid setup time at IC component (tDVSIC) (mode 5 only) This parameter defines the minimum setup time that the sender must generate at the I/O pin into a defined load in order to meet all setup times in a system. It is included so that IC designers will have an explicit sender setup time to be simulated during the design phase that will result in a functional system. The formula and details used to determine tDVSIC are identical to the ones used to determine tDVS except for the following. First, the maximum PCB trace skew, the maximum falling source transition delay, and minimum rising source transition delay are removed from the equation because they account for the skews that occur after the IC. Second, since the maximum output skew includes noise on the signal seen in a functional system that is usually not included in a simulation of an I/O into a lumped load, the noise skew defined above is added to the modified tDVS value. The resulting value is the setup time at the sender IC that shall be met to be equivalent to the setup requirements for a system. C.5.2.32 Data valid hold time at component IC (tDVHIC) (mode 5 only) This parameter defines the minimum hold time that the sender component must generate at the I/O pin into a defined load in order to meet all hold times in a system. It is included so that IC designers will have an explicit sender hold time that could be simulated during the design phase that will result in a functional system. The formula and details used to determine tDVHIC are identical to the ones used to determine tDVH except for the following. First, the maximum PCB trace skew, the maximum falling source transition delay, and the minimum rising source transition delay are removed from the equation because they account for the skews that occur after the component I/O. Second, since the maximum output skew includes noise on the signal seen in a system that would not be part of a simulation of and I/O into a lumped load, the noise skew defined above is added to the modified tDVH value. The resulting value is the hold time at the sender component I/O that shall be met to be equivalent to the hold requirements for a system. C.5.3 Ultra DMA Protocol Considerations C.5.3.1 Recipient pauses The Ultra DMA protocol allows a recipient to pause a burst at any point in the transfer. The clauses below discuss some of the issues and design considerations associated with the Ultra DMA recipient pausing protocol. C.5.3.1.1 DMARDY- minimum negation time An Ultra DMA recipient pause is initiated through the recipient's negation of DMARDY-. Once DMARDY- is negated, the protocol allows for additional words to be transferred. Pausing is typically done for two reasons. One is that the recipient’s input FIFO or buffer is almost full and would overflow if the burst continued. The second is that the recipient is preparing to terminate the burst. Normally the case of pausing to free space in the FIFO or buffer would result in DMARDY- being negated for at least a few transfer cycles. However, there is no minimum time for the negation of DMARDY-. The recipient does not have to wait for possible additional words or for any minimum time from when the recipient negates DMARDY- until it re-asserts DMARDY-. If, after negating DMARDY-, the recipient becomes ready, it may immediately reassert DMARDY-. Based on the implementation of the sender, a negation and immediate re-assertion of DMARDY- may cause a subsequent STROBE to be delayed. It is recommended that some hysteresis be used in the FIFO trigger points for assertion and negation of DMARDY- to avoid DMARDY- being negated after every word or two. C.5.3.1.2 Number of additional words from sender An Ultra DMA burst may be paused with zero, one, or two additional data transfers as seen at the recipient connector for modes 0, 1, and 2, and up to three additional transfers for modes 3, 4, and 5. This does not imply that the sender is allowed to send up to two or three more STROBES after it detects the negation of DMARDY-. In most cases it would be a violation of tRFS to do so. Rather than counting words after detecting the negation of DMARDY-, under all conditions the sender stops generating STROBE edges within tRFS of the recipient negating DMARDY-. Even in cases where tRFS is met and less than the maximum number of words Page 465 T13/1410D revision 3b are sent, it is still possible for the recipient to see the maximum number of STROBE edges after it negates DMARDY-. This is due to the delay of the signals through the cable. An example of this is explained below and shown in figure C.31. In mode 2 when the STROBE time is 60 ns and signal delays add up to 6 ns, both STROBE from sender to recipient and DMARDY- from recipient to sender experience a cable delay of 6 ns. While the recipient negates DMARDY- after the sender toggles STROBE, it does not receive the STROBE transition until after the DMARDY- negation. This would account for the first word received. By the time the sender detects the DMARDY- negation, there are only 49 ns until the next STROBE. This STROBE is within tRFS so the sender may send STROBE without violating the protocol. To the recipient, this would be the second transfer after it has negated DMARDY-, but to the sender it would be the first and only allowable STROBE transition after detecting the DMARDY- negation. 60 ns STROBE @ sender 49 ns DMARDY- @ sender 6 ns STROBE @ recipient 6 ns DMARDY- @ recipient 5 ns Figure C.31 – STROBE and DMARDY- at sender and recipient C.5.3.1.3 Sender output data handling during a pause In most cases of a recipient pause, a sender stops toggling STROBE in less than one transfer cycle time after DMARDY- negates at its input in order to meet tRFS. Since the incoming DMARDY- negation is asynchronous with the sender's internal clock, the incoming DMARDY- signal should be synchronized with the internal clock. In this condition data may be gated or latched to DD(15:0) but never strobed. If an output register is used when data is transferred from memory for presentation on DD(15:0), no assumptions are made that that data has been or will be transferred. If a pointer in memory is incremented or the data is cleared from memory when it is sent to the output register, data may be lost unless some recovery mechanism is present to decrement the pointer or restore the data if it is never strobed due to a burst termination after a pause. During a pause, other bus activity like a Status register read might occur. A design using an output register would have data in that register overwritten during this other activity. Other designs may involve similar considerations. It is most important to remember that data on DD(15:0) is not sent and is not to be treated as sent until there is a valid STROBE edge. C.5.3.1.4 Additional words at recipient After DMARDY- is negated, the recipient may receive additional data words. There will be some output delay of DMARDY- from the logic that first generates it inside the IC to the connector, and there will be input delay of STROBE from the connector to inside the IC. In addition to this, data may be pipelined before the FIFO and there may be logic delays between triggering a near full condition in the FIFO and generating the DMARDYnegation. The depth of the recipient's input FIFO where it triggers a condition to negate DMARDY- to avoid an overflow is therefore dependent on the particular design approach. When determining the FIFO trigger point, all Page 466 T13/1410D revision 3b FIFO near-full trigger threshold-to-DMARDY- negation delays, the cable delay, tRFS time, input delays, input data pipelining, and the minimum cycle time for the mode supported should be considered. The recipient may receive STROBE edges until tRP after it negates DMARDY-. The receipt of two or three words by the recipient after a pause has been initiated is not an indication that the sender has paused. The recipient waits until tRP after the pause was initiated before taking any other action (e.g., terminating the burst). Waiting tRP allows for cable delays between the recipient and sender and allows the sender time to complete its process of transitioning to a paused state. The process of switching to a paused state may take additional system clocks after the sender has sent it’s last STROBE transition. Since the recipient’s and sender’s clocks are asynchronous with respect to each other, there is not a single fixed number of words that the recipient will receive after negating DMARDY-. Every time a recipient begins a pause, a sender may send from zero to the maximum number of words specified for the mode. The Ultra DMA protocol does not give the recipient any means of pausing or stopping on an exact, predetermined boundary. C.5.3.2 CRC calculation and comparison For each STROBE transition used for data transfer, both the host and device calculate a CRC value. Only words successfully transferred in the transfer phase of the burst are used to calculate this value. This includes words transferred after a pause has been requested. Words put on DD(15:0) but never strobed are not to be used for CRC calculation. In addition, if STROBE is negated at the end of a pause and then the burst is terminated, the protocol requires STROBE to be re-asserted after DMARQ is negated or STOP is asserted. No data is transferred on this STROBE edge and any data on DD(15:0) that was not strobed during the transfer phase of the burst is not used in the CRC calculation on this re-assertion of STROBE. It is not advisable to use STROBE to clock the CRC generator. Noise on the STROBE signal could cause the recipient's CRC generator to double-clock the generator on a single edge. At the same time, the noise glitch seen by the CRC generator may not affect the data input portion of the logic. This type of implementation has led to CRC errors on systems where data is properly received but the wrong CRC value is calculated. Using different versions of STROBE to clock the CRC generator and to clock data into the FIFO or buffer also leads to a fatal error that has been seen on an implementation of the Ultra DMA protocol. Noise, lack of setup or hold time, race conditions in the logic, or other problems could result in the wrong data being clocked into the FIFO or buffer. At the same time the correct data may be clocked into the CRC generator since it is using a different instance of STROBE. In this case, the resultant CRC value is correct when the data in the recipient is not. Designs may internally generate a delayed version of STROBE that is synchronous with the recipient clock. This synchronized version of the STROBE is then used to place data into the FIFO or buffer. It is advisable for the recipient to use the same clock that places data into its FIFO or buffer to clock data into its CRC generator. Following this design approach will maximize the probability of clocking the same data into both the CRC generator and FIFO or buffer and clocking both the same number of times. The standard includes the equations that define the XOR manipulations to make on each bit and the structure required to perform the calculation using a clock generated from STROBE. Through the given equations, the correct CRC is calculated by using a small number of XOR gates, a single 16-bit latch, and a word clock (one clock per STROBE edge). The equations define the value and order of each bit, and the order of each bit is mapped to the same order lines of DD(15:0). The CRC register is pre-set to 4ABAh. This requires pre-setting the latch (CRCOUT) to 4ABAh before the first word clock occurs. After that, CRCIN15 to the latch is tied through to CRCOUT15. When the burst is terminated CRCOUT15 is the final CRC bit 15 that is sent or received on DD15. This direct matching of bit order is true for all CRC bits. The proper use of the data sent on DD(15:0) during the burst transfer is defined in the equations. The value on the DD15 signal line has the same value as bit DD15 in the equations to calculate CRC. This direct mapping is true for all bits strobed on DD(15:0) during a burst. Once the burst is terminated and the host sends the CRC data to the device (the host always sends the CRC independent of whether the burst was a data-in or data-out transfer), the device compares this to the CRC it has calculated. While other CRC validation implementations may be possible, a CRC input register may be used Page 467 T13/1410D revision 3b on the device in combination with a digital comparator to verify that the CRC value in the input register matches the value in its own CRC calculation register. C.5.3.3 The IDENTIFY DEVICE and IDENTIFY PACKET DEVICE commands A device communicates its Ultra DMA capabilities and current settings to the host in the data returned by the device as a result of an IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command. For the PIO and Multiword DMA protocols, only the host generates data STROBES so the minimum cycle times reported for those protocols in the IDENTIFY DEVICE and IDENTIFY PACKET DEVICE data are used by the host for both data-in and data-out transfers to insure that the device’s capabilities are not exceeded. For the Ultra DMA protocol, both the host and device strobe data depending on the direction of the transfer. The host determines a mode setting based on both the device’s capabilities and its own. The sender may send data (toggle STROBE) at a minimum period of tCYC . A recipient receives data at the minimum tCYC for the currently active mode. If the device indicates that it is capable of an Ultra DMA mode, it receives at the minimum time for that mode, no additional cycle time information is required. C.5.3.4 STROBE minimums and maximums The Ultra DMA protocol does not define a maximum STROBE time. The sender may strobe as slowly as it chooses independent of the mode that has been set, though it has to meet the specified setup and hold times for the mode that has been set by the host. The sender is also not required to maintain a consistent cycle time throughout the burst. It would not be a violation of protocol for the cycle time to change on every cycle so long as all cycles are longer than or equal to the minimum cycle time for the mode that is set. An upper timing bound or PLL is not used by the recipient to qualify the STROBE signal. Regardless of the frequency of the STROBE, the recipient has to meet the setup and hold times of the received signal specified for the mode that has been set. The limit on the maximum STROBE time is determined by the system time-out. This time-out is typically on the order of a few seconds. If a device begins to strobe once every ten seconds during a data-in burst, this would not be in violation of the protocol. However, this could cause a software driver to determine that the device is not responding and perform a recovery mechanism. The recovery will often be a hardware reset to the device. Unlike a recipient pause where the recipient has to wait tR P after negating DMARDY- before the pause is complete. The sender may consider the burst paused as soon as it meets the data hold time tDVH . The implication of this is that data to the recipient may stop on any word. After each word, the recipient waits (with exception of pauses or stops) but never requires an additional word before allowing the burst to be terminated. C.5.3.5 Typical STROBE cycle timing Neither minimum nor typical cycle times are required to be used by the sender. Other cycle times may be used by systems that do not have internal clocks that provide a frequency to generate signals at those cycle times. The typical mode 1 cycle time of 80 ns will not be met using a common system clock rate of 66.7 MHz. Instead a STROBE cycle time of 90 ns for mode 1 is used and is not a violation of the specification. A typical cycle time of 90 ns reflects 22.2 megabytes per second. C.5.3.6 Holding data to meet setup and hold times Following are three examples of holding data in an attempt to meet the setup and hold times. The first method is to use the same clock edge to change data and the STROBE, but delay the data through some gates. The second method is to use one edge of the clock to change the STROBE and then use the next opposite edge to change data (half cycle). The third method is to use one active edge of the clock to change STROBE and the next to change data. Using gate delays to hold data may lead to large variations in hold time over process, temperature, and supply voltage. Meeting Ultra DMA mode 4 or 5 timings with gate delays to hold data is not advisable and could lead to timing violations under some conditions. Mode 4 hold time may be met by a single 66.6MHz clock cycle Page 468 T13/1410D revision 3b with all timings being met. With a slower 25, 30, or 33 MHz clock, a half cycle rather than full cycle hold would be required in order to still meet the setup time requirements for the higher modes. If the data transitions are not at the middle of a mode 4 or 5 cycle, either the setup or hold time margin will be reduced. C.5.3.7 Opportunities for the host to delay the start of a burst After a device has asserted DMARQ, the host has one opportunity to delay the start of the burst indefinitely for a data-in burst and two opportunities for a data-out burst. For both a data-in and a data-out burst, the first opportunity that the host has to delay the burst is by delaying the assertion of DMACK-. This delay has no specified maximum limit. This is necessary for cases of overlap in system bus access that may cause a delay in the time it takes for the host to become ready to receive data from a device after sending a data-in command. For a data-out burst, the host may delay the first STROBE signal. The difference in overhead between delaying and not delaying may seem small but may still be used to optimize for a faster overall system data transfer rate. The device does not delay its STROBE indefinitely since the device controls the signal that starts the transfer process (DMARQ). Note that it is a violation of the protocol to terminate the burst unless at least one word has been transferred. After asserting DMACK- the host sends or receives at least one word of data before terminating a burst. C.5.3.8 Maximums on all control signals from the device The timings for all signals from the device used to perform burst initiation, pause, and burst termination have maximum values. This is to bound the time it takes to perform burst initiation, pause, and termination so the host always knows in advance how long tasks performed by the device may take. Rather than waiting a few seconds for a command or burst to time-out, the host determines that a problem exists if activity is not detected within the specified maximums and sets time-outs for functions performed by the device. For instance, the longest the initiation of a data-in burst may take from the host assertion of DMACK- to the first STROBE is tENV max plus tRS max. Also, the host may require a burst to terminate in a timely manner in order to service some other device on the bus or the system depending on the chip set design. C.6 Cable detection The ATA interface was originally designed to use a 40-conductor cable assembly. To achieve transfer rates for Ultra DMA modes greater than 2 an 80-conductor cable assembly was developed. This assembly improves signal quality allowing for the faster transfer rates. The improvement in signal quality provided by the 80conductor cable assembly is the result of placing ground lines between each of the 40 signal lines to decrease crosstalk and reduce settling times. In order to use Ultra DMA modes greater than 2, hosts are required to determine that an 80-conductor cable assembly is installed in the system. The methods for performing this detection are described in the standard. The following clauses provide additional information about determination of cable assembly type. Page 469 T13/1410D revision 3b C.6.1 80-conductor cable assembly electrical feature In order to allow detection of the presence of an 80-conductor cable assembly by a host, a unique electrical configuration for the 80-conductor cable assembly was developed. For the 40-conductor cable assembly, PDIAG- is connected to the associated pin on all three connectors. For the 80-conductor cable assembly, PDIAG- was opened between the device connectors and the host connector and grounded in the host connector. Since PDIAG- is pulled up through resistors on devices, this signal will be electrically high at the host connector pin in a system with a 40-conductor cable assembly, and will be at ground at the host connector pin in a system with an 80-conductor cable assembly. Therefore, the host can determine the cable assembly type by sensing the electrical state of this pin. PDIAG- was renamed to be PDIAG-:CBLID- to reflect this additional function. PDIAG- remains connected between the two devices in the 80-conductor cable assembly for proper power-on and hardware reset handshaking. C.6.2 Host determination of cable assembly type In a system with an 80-conductor cable assembly, devices cannot affect the state of CBLID- at the host connector since that signal is open to the host and is grounded inside the host connector. In a system with a 40-conductor cable assembly, the state of PDIAG- at the host will be the same at all three connectors. Since the devices are required to have pull-up resistors on PDIAG-, the state of that signal will be high when all devices have released it. The standard specifies that devices shall release PDIAG- after the first command has been sent to Device 1 after a power-on or hardware reset. If, after that, the host senses the signal as electrically high, a 40-conductor cable assembly is installed in the system. If the host senses the signal as electrically low, then there are two possibilities: either an 80-conductor cable assembly is installed in the system, or a 40-conductor cable assembly is installed in the system and Device 1 is continuing to assert PDIAG- after is should have released that signal. Any device claiming compliance to ATA-3 or later as indicated in IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data should properly release PDIAG- after a power-on or hardware reset upon receiving the first command or after 31 seconds have elapsed since the reset, whichever comes first. This is why the standard specifies that one of those two commands is to be sent to Device 1 before a host samples the state of CBLID-. From the returned data the host can determine that device 1 indicates compliance with the standard, and, if it does, that the device has released PDIAG-. An advantage of this detection method is that the cable assembly type may be determined by the host regardless of the devices attached to the cable. Two disadvantages are: this method does require an IC pin on the host for each port to connect to CBLID-, and, as described above, it is possible for a host to make an incorrect determination of cable type if a device is present that does not correctly release PDIAG-. Page 470 T13/1410D revision 3b C.6.3 Device determination of cable assembly type A second method for determination of cable assembly type was developed because some hosts capable of operating at Ultra DMA modes greater than 2 were unable to connect to CBLID-, even though this is required by the standard. For this method the host is required to place a capacitor on CBLID- to ground. After receiving an IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command a device negates PDIAG-:CBLID- allowing the capacitor (if present) to discharge, releases PDIAG-:CBLID-, samples PDIAG-:CBLID- within a window where the signal would still be low before the capacitor charges, and then returns data for the command. If the device senses the signal as electrically low, then there are two possibilities: either a 40-conductor cable assembly is installed in the system, or an 80-conductor cable assembly is installed in the system and Device 1 is continuing to assert PDIAG- after is should have released that signal. If the device senses the signal as electrically high, then an 80-conductor cable assembly is installed in the system. The device places the results from its determination of cable assembly type into the data returned for the IDENTIFY DEVICE command. As with the host determination method, the host uses the data from the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command from both devices to verify that Device 1 indicates compliance with ATA-3. The host then checks to see what cable assembly type the device indicates having determined. For this algorithm the host issues the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command to Device 1 first to insure that it has properly released PDIAG-. Two advantages to device determination of cable assembly type are, first, the host is not required to use an IC pin for PDIAG- on each port that supports Ultra DMA modes greater than 2. The device assisted cable detection method provides the only solution for this configuration. Second, while both the host and device cable assembly type determination methods may result in incorrect determination of cable assembly type when Device 1 does not correctly release PDIAG-, Device 0 will indicate that it has determined that a 40-conductor cable assembly is installed when an 80-conductor cable assembly is installed. Though the host will not set Device 0 to operate at Ultra DMA modes greater than 2, this will not result in the potential for poor system operation that could result if a host set a device to operate at Ultra DMA modes greater than 2 when a 40conductor cable assembly is installed in a system. C.6.3.1 Capacitor on CBLIDAll devices must be able to assert PDIAG-. This is required for the device to function as Device 1 during execution of the power-on hardware and software reset protocols. The standard recommends an open collector output on that pin. Some designers may chose to use drivers capable of a high-impedance state for this signal but never negate it. The signal is negated to a high state through a required 10 kΩ pull-up resistor on each device. All devices must also be able to detect the state of PDIAG-. This is required for the device to function as Device 0 during execution of the power-on hardware and software reset protocols. The timing for asserting or detecting PDIAG- power-on hardware and software reset protocols is on the order of milliseconds or more so the assertion and detection need not be controlled by hardware only but rather be controlled through firmware or some combination of hardware and firmware. In order for the device detection algorithm to work properly, the device firmware needs to have I/O control of PDIAG-. C.6.3.1.1 Capacitor size determination The device pull-up on PDIAG- must always be to 5 V rather than 3.3 V as is required for all other signals for Ultra DMA mode 5. On some hosts a 10 kΩ pull-down resistor was placed on PDIAG-:CBLID- so that the signal could be connected to a non-5 V tolerant input. In this case, the pull-down resistor acts in conjunction with the device pull-up(s) to divide the PDIAG-:CBLID- voltage. If a 3.3 V pull-up is used, the value of CBLIDdetected by the host input could be only 1.5 V, which is not a valid high level. The determination of capacitor size is based on a pull-up to 5 V. With the capacitor installed, the power-on and reset handshaking must still function. At the beginning of this handshaking, Device 1 releases PDIAG- within 400 ns after reset, and the signal must be electrically high within 1 ms after reset. While a single Device 1 configuration is defined in the standard, this is an atypical Page 471 T13/1410D revision 3b configuration. However, the timing for handshaking during the power-on and reset protocols for all configuration must be taken into account when selecting a capacitor value. The pull-up resistors on the devices are specified to be 10 kΩ plus or minus 5%. In addition, a device may have up to 20 pF of load on any signal, the host may have up to 25 pF of load on any signal, and the cable may add an additional 40 pF to any signal. V = threshold voltage VPU = pull-up voltage C = Capacitive load on signal R = pull-up resistor value t = time to reach threshold V = VPU ( 1 − e ( -t / RC ) ) assuming that the starting voltage is 0 V Solving for C: C = −t / (R ( ln ( 1 − ( V / VPU ) ) ) ) Solving for t: t = ( −R ∗ C ) ∗ ( ln (1 − ( V / VPU ) ) ) As described above, there are host systems that place a 10 kΩ pull-down resistor on PDIAG-:CBLID- at the host. The worst-case condition for slow pull-up on PDIAG- would be with a +5% resistor on the device, a −5% resistor at the host, and a −10% supply voltage. The Thevenin equivalent of this voltage divider circuit given these values is the following: ViH = 2.0 V VPU = 2.14 V R = 4990 Ω t = 1.0 ms Using the equation for C and the values immediately above, the maximum value that may be used for C is 0.073 µF. With a higher value, the timing for handshaking may no longer be met. A lower value shortens the time to charge the capacitor by the device pull-up resistors making the detection window narrower. A standard value capacitor is 0.047 µF. With a 20% tolerance, the maximum value would be 0.0564 µF, which is within the maximum limit. The additional loading of 20, 25, and 40 pF for the device, host, and cable as mentioned above is insignificant given this order magnitude capacitor. C.6.3.1.2 Timing window determination Given the selection of a 0.047 µF capacitor, the limits of the window where PDIAG- would be high for an 80conductor cable and low for a 40-conductor cable may be determined. The minimum time of the window is determined by the maximum time it will take for PDIAG- to go to an electrically high state with an 80-conductor cable assembly installed in a system. With an 80-conductor cable assembly installed, the capacitor would not be loading the PDIAG- signal because the signal is not connected from the host to the devices. The only load would be that of the device itself (20 pF maximum) and the cable (40 pF maximum). Since the load of the cable is independent of the number of devices attached, the maximum rise time will be for the case with a single device installed on the cable. As described above, the pull-up resistor is connected to 5 V in order to be compatible with some hosts. The pull-up resistor could be 10 kΩ +5%. R = 10500 ohm Vpu = 4.5 V ViH = 2.0 V C = 60 pF With the above values and the time equation given in C.6.3.1.1, the longest time that PDIAG- may take to reach the electrically high state in a system with an 80-conductor cable assembly installed is 0.3 µs. The maximum time of the window is determined by the minimum time that it will take for PDIAG- to an electrically high state with a 40-conductor cable assembly installed in a system. With a 40-conductor cable Page 472 T13/1410D revision 3b assembly installed, the capacitor at the host is connected to the devices through the cable. Since each device has a pull-up resistor, the shortest time for the signal to go to an electrically high state will occur when two devices are installed on a cable. Each device will have a pull-up resistor as low as 9.5 kΩ (10 kΩ minus 5%). Additionally, some devices have pull-up current through their IC. The highest additional IC pull-up current may be equivalent to a 27500 Ω resistor. The two external and two internal pull-up resistors in parallel are equivalent to a single 3530 Ω resistor. An ATA output driver must be able to drive VoL of 0.5 V at IoL. To reach 0.5 V with an IoL of 4 mA, the driver must have a resistance to ground of less than 125 Ω. At 125 Ω, a driver would pulldown a 3530 Ω load to 188 mV (i.e. 5.5 ∗ 125 ∗ ( 3530 + 125 ) ). Assume though that the voltage is only pulled to 0.3 V before it is released. R = 3530 Ω VPU = 5.5 V C = 0.0376 µF (lowest value for 20% tolerance capacitor) With V = 0.8 V: t = 20.4 µs With V = 0.3 V: t = 7.4 µs With the above values, the shortest time that PDIAG- may take to reach an electrically high state with a 40conductor cable (from 0.3 to 0.8 V) is 13 µs. It is also important to know how long it will take to discharge the capacitor when a device asserts PDIAG-. The maximum time to discharge the capacitor (down to 0.3 V) would depend on the maximum resistance to ground. As stated above, the driver itself may have 125 Ω maximum. In combination with the 3530 Ω pull-up, the lowest level that the signal could reach is 188 mV. Assuming this were 200 mV, the exponential curve will be to a minimum of 200 mV. This would be equivalent to a curve from 5.3 to 0 V. V = VPU (e ( -t / RC ) ) Solving for t: t = ( −R ∗ C ) ∗ ( ln ( V / VPU ) ) V = 0.1 V VPU = 5.3 V R = 125 Ω C = 0.0564 µF (maximum for 20% tolerance capacitor) These numbers result in a maximum 28 µs to discharge the capacitor. Page 473 T13/1410D revision 3b Annex D (informative) Bibliography AT Attachment - 3 (ATA-3), ANSI X3.298-1997 AT Attachment with Packet Interface Extension (ATA/ATAPI-4), ANSI NCITS.317-1998 AT Attachment with Packet Interface (ATA/ATAPI-5), ANSI NCITS.340-2000 BIOS Enhanced Disk Drive Specification (EDD), NCITS TR-21:1998 BIOS Enhanced Disk Drive Services, ANSI NCITS.347-2001 Protected Area Run Time Interface Extension, ANSI NCITS.346-2001 Address Offset Reserved Area Boot, NCITS TR-27:2001 Suite of 2.5” Form Factor Specifications, EIA-7201 Suite of 3.5” Form Factor Specifications, EIA-740, SFF-83012 1) EIA documents may be obtained from: Global Engineering 15 Inverness Way East Englewood, CO 80112-5704 Tel: 303-792-2181 or 800-854-7179 Fax: 303-792-2192 2) SFF documents are published by: SFF 14426 Black Walnut Court, Saratoga, California 95070 FaxAccess: 408 741-1600 SFF documents may be obtained from: Global Engineering 15 Inverness Way East Englewood, CO 80112-5704 Tel: 303-792-2181 or 800-854-7179 Fax: 303-792-2192 Page 474 T13/1410D revision 3b Annex E (informative) Command set summary The following four tables are provided to facilitate the understanding of the command set. Table E.1 provides information on which command codes are currently defined. Table E.2 provides a list of all of the commands in order of command code. Table E.3 provides a summary of all commands with the protocol, required use, command code, and registers used for each. Table E.4 shows the status and error bits used by each command. Table E.1 − Command matrix 0x 1x 2x 3x 4x 5x 6x 7x 8x 9x Ax Bx Cx Dx Ex Fx x0 C O C C C O R C V C C C F R C V x1 R E O O O R R E V O* C C* V C* C C x2 R E O O C* R R E V C C R V M* C C x3 C E O O R R R E V R R R V M* C C x4 R E C* C* R R R E V E R R C M* C C x5 R E C* C* R R R E V E R R C R C C x6 R E C* C* R R R E V E R R C R C C Key: C = a defined command. R = Reserved, undefined in current specifications. V = Vendor specific commands. O = Obsolete. E=a retired command. F=If the device does not implement the CFA feature set, this command code is Vendor specific. x7 R E C* C* R R R E F E R R C R C V x8 C E R C R R R E V E R A C R C C x9 R E C* C* R R R E V E R A O R E C xA R E R R R R R E V V R A C C C* V xB R E R R R R R E V R R A O E R V xC R E R O R R R E V R R A C E C V xD R E R R R R R E V R R A C E C V xE R E R R R R R E V R R A R C O V xF R E C* C* R R R E V R R A R C C V A=Reserved for assignment by the CompactFlash Association M=Reserved for the Media Card Pass Through Command feature set. * indicates that the entry in this table has changed from ATA/ATAPI-5, NCITS 340-2000. Page 475 T13/1410D revision 3b protocol ND ND DR PI PI DM DMO ND PI PI PO PO DM DMO ND PO PO PO ND ND ND PI DD PO P PI P ND ND ND ND PI PI ND PO ND PI ND PO Page 476 Table E.2 − Command codes Command Devices not implementing the PACKET Command feature set NOP O CFA REQUEST EXTENDED ERROR O DEVICE RESET O READ SECTOR(S) M READ SECTOR(S) EXT O READ DMA EXT O READ DMA QUEUED EXT O READ NATIVE MAX ADDRESS EXT O READ MULTIPLE EXT O READ LOG EXT O WRITE SECTOR(S) M WRITE SECTOR(S) EXT O WRITE DMA EXT O WRITE DMA QUEUED EXT O SET MAX ADDRESS EXT O CFA WRITE SECTORS W/OUT ERASE O WRITE MULTIPLE EXT O WRITE LOG EXT O READ VERIFY SECTOR(S) M READ VERIFY SECTOR(S) EXT O SEEK M CFA TRANSLATE SECTOR O EXECUTE DEVICE DIAGNOSTIC M DOWNLOAD MICROCODE O PACKET N IDENTIFY PACKET DEVICE N SERVICE O SMART DISABLE OPERATIONS O SMART ENABLE/DISABLE AUTOSAVE O SMART ENABLE OPERATIONS O SMART EXECUTE OFF_LINE O SMART READ DATA O SMART READ LOG SECTOR O SMART RETURN STATUS O SMART WRITE LOG SECTOR O DEVICE CONFIGURATION FREEZE LOCK O DEVICE CONFIGURATION IDENTIFY O DEVICE CONFIGURATION RESTORE O DEVICE CONFIGURATION SET O Devices implementing the PACKET Command feature set M N M N N N N N N O N N N N N N N O N N N N M N M M O N N N N N N N N O O O O Command code 00h 03h 08h 20h 24h 25h 26h 27h 29h 2Fh 30h 34h 35h 36h 37h 38h 39h 3Fh 40h 42h 70h 87h 90h 92h A0h A1h A2h B0h B0h B0h B0h B0h B0h B0h B0h B1h B1h B1h B1h (continued) T13/1410D revision 3b protocol ND PI PO ND DMO DM DM DMO PO ND ND ND ND ND ND ND ND PI ND ND ND PO ND PI ND ND PO PO ND PO ND PO ND ND Table E.2 − Command codes (continued) Command Devices not implementing the PACKET Command feature set CFA ERASE SECTORS O READ MULTIPLE M WRITE MULTIPLE M SET MULTIPLE MODE M READ DMA QUEUED O READ DMA M WRITE DMA M WRITE DMA QUEUED O CFA WRITE MULTIPLE W/OUT ERASE O CHECK MEDIA CARD TYPE O GET MEDIA STATUS O MEDIA LOCK O MEDIA UNLOCK O STANDBY IMMEDIATE M IDLE IMMEDIATE M STANDBY M IDLE M READ BUFFER O CHECK POWER MODE M SLEEP M FLUSH CACHE M WRITE BUFFER O FLUSH CACHE EXT O IDENTIFY DEVICE M MEDIA EJECT O SET FEATURES M SECURITY SET PASSWORD O SECURITY UNLOCK O SECURITY ERASE PREPARE O SECURITY ERASE UNIT O SECURITY FREEZE LOCK O SECURITY DISABLE PASSWORD O READ NATIVE MAX ADDRESS O SET MAX ADDRESS O Devices implementing the PACKET Command feature set N N N N N N N N N N O N N M M O O N M M O N N N N M O O O O O O O O Command code C0h C4h C5h C6h C7h C8h CAh CCh CDh D1h DAh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h EAh ECh EDh EFh F1h F2h F3h F4h F5h F6h F8h F9h (continued) Page 477 T13/1410D revision 3b protocol VS Table E.2 − Command codes (continued) Command Devices not implementing the PACKET Command feature set Vendor specific V Devices implementing the PACKET Command feature set V - Retired E E - Obsolete B B - Reserved: all remaining codes R R Command code 9Ah,C0hC3h,8xh, F0h,F7h, FAh-FFh 11h-1Fh, 71h-7Fh, 94h-99h, DBh-DDh, E9h 10h, 21h-23h, 31h-33h, 3Ch, 41h, 50h, C9h, CBh, EEh Key: ND = Non-data command PI = PIO data-in command PO = PIO data-out command DM = DMA command DMO = DMA QUEUED command DR = DEVICE RESET command DD = EXECUTE DEVICE DIAGNOSTIC command P = PACKET command VS = Vendor specfic M = Mandatory O = Optional N = Use prohibited V = Vendor specific implementation E = Retired B = Obsolete R = Reserved (concluded) Page 478 T13/1410D revision 3b protocol ND ND PI PO PO ND ND ND PI ND PO DR PO DD ND ND ND PI PI ND ND ND ND ND ND P PI DM DM DMO DMO PI PI PI ND ND PI PI ND ND PO ND Table E.3 − Command codes Command Devices not implementing the PACKET Command feature set CFA ERASE SECTORS O CFA REQUEST EXTENDED ERROR O CFA TRANSLATE SECTOR O CFA WRITE MULTIPLE W/OUT ERASE O CFA WRITE SECTORS W/OUT ERASE O CHECK MEDIA CARD TYPE O CHECK POWER MODE M DEVICE CONFIGURATION FREEZE LOCK O DEVICE CONFIGURATION IDENTIFY O DEVICE CONFIGURATION RESTORE O DEVICE CONFIGURATION SET O DEVICE RESET O DOWNLOAD MICROCODE O EXECUTE DEVICE DIAGNOSTIC M FLUSH CACHE M FLUSH CACHE EXT O GET MEDIA STATUS O IDENTIFY DEVICE M IDENTIFY PACKET DEVICE N IDLE M IDLE IMMEDIATE M MEDIA EJECT O MEDIA LOCK O MEDIA UNLOCK O NOP O PACKET N READ BUFFER O READ DMA M READ DMA EXT O READ DMA QUEUED O READ DMA QUEUED EXT O READ LOG EXT O READ MULTIPLE M READ MULTIPLE EXT O READ NATIVE MAX ADDRESS O READ NATIVE MAX ADDRESS EXT O READ SECTOR(S) M READ SECTOR(S) EXT O READ VERIFY SECTOR(S) M READ VERIFY SECTOR(S) EXT O SECURITY DISABLE PASSWORD O SECURITY ERASE PREPARE O Devices implementing the PACKET Command feature set N N N N N N M O O O O M N M O N O N M O M N N N M M N N N N N O N N O N N N N N O O Command code C0h 03h 87h CDh 38h D1h E5h B1h B1h B1h B1h 08h 92h 90h E7h EAh DAh ECh A1h E3h E1h EDh DEh DFh 00h A0h E4h C8h 25h C7h 26h 2Fh C4h 29h F8h 27h 20h 24h 40h 42h F6h F3h (continued) Page 479 T13/1410D revision 3b protocol PO ND PO PO ND P ND ND ND ND ND ND ND ND ND PI PI ND PO ND ND PO DM DM DMO DMO PO PO PO