DATASHEET

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8
1-88
Dual High Frequency Differential Amplifier
For Low Power Applications Up to
500MHz
The CA3102 consists of two independent differential
amplifiers with associated constant current transistors on a
common monolithic substrate. The six transistors which
comprise the amplifiers are general purpose devices which
exhibit low 1/f noise and a value of fT in excess of 1GHz.
These features make the CA3102 useful from DC to
500MHz. Bias and load resistors have been omitted to
provide maximum application flexibility.
The monolithic construction of the CA3102 provides close
electrical and thermal matching of the amplifiers. This
feature makes this device particularly useful in dual channel
applications where matched performance of the two
channels is required.
The CA3102 has a separate substrate connection for greater
design flexibility.
TEMP.
RANGE (oC)
October 12, 2005
611.7
Features
• Power Gain 23dB (Typ) . . . . . . . . . . . . . . . . . . . . 200MHz
• Noise Figure 4.6dB (Typ) . . . . . . . . . . . . . . . . . . . 200MHz
• Two Differential Amplifiers on a Common Substrate
• Independently Accessible Inputs and Outputs
• Full Military Temperature Range . . . . . . . -55oC to 125oC
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• VHF Amplifiers
• VHF Mixers
• Multifunction Combinations - RF/Mixer/Oscillator;
Converter/IF
• IF Amplifiers (Differential and/or Cascode)
• Product Detectors
• Doubly Balanced Modulators and Demodulators
Ordering Information
PART NUMBER
(BRAND)
CA3102
PACKAGE
PKG.
DWG. #
CA3102E
(CA3102E)
-55 to 125
14 Ld PDIP
E14.3
CA3102M
(3102)
-55 to 125
14 Ld SOIC
M14.15
CA3102MZ
(CA3102MZ)
(Note)
-55 to 125
• Balanced Quadrature Detectors
• Cascade Limiters
• Synchronous Detectors
• Balanced Mixers
• Synthesizers
14 Ld SOIC
(Pb-free)
M14.15
• Sense Amplifiers
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
• Balanced (Push-Pull) Cascode Amplifiers
Pinout
CA3102
(PDIP, SOIC)
TOP VIEW
1
14
2
13
3
12 SUBSTRATE
4
11
SUBSTRATE 5
10
6
9
7
8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2002, 2005, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
CA3102
Absolute Maximum Ratings
Thermal Information
Collector-to-Emitter Voltage, VCEO . . . . . . . . . . . . . . . . . . . . . . 15V
Collector-to-Base Voltage, VCBO . . . . . . . . . . . . . . . . . . . . . . . . 20V
Collector-to-Substrate Voltage, VCIO (Note 1). . . . . . . . . . . . . . 20V
Emitter-to-Base Voltage, VEBO . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Collector Current, IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
205
Maximum Power Dissipation (Any One Transistor) . . . . . . . 300mW
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3102 is isolated from the substrate by an integral diode. The substrate (Terminal 9) must be connected
to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
TA = 25oC
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
0.25
5.0
mV
-
0.3
3.0
μA
-
13.5
33
μA
-
1.1
-
μV/oC
DC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER
Input Offset Voltage (Figures 1, 4)
VIO
Input Offset Current (Figure 1)
IIO
Input Bias Current (Figures 1, 5)
IB
I3 = I9 = 2mA
ΔV IO
---------------ΔT
DC CHARACTERISTICS FOR EACH TRANSISTOR
Temperature Coefficient
Magnitude of Input Offset Voltage
DC Forward Base-to-Emitter Voltage
(Figure 6)
VBE
VCE = 6V, IC = 1mA
674
774
874
mV
Temperature Coefficient of
Base-to-Emitter Voltage
(Figure 6)
ΔV BE
-------------ΔT
VCE = 6V, IC = 1mA
-
-0.9
-
mV/oC
Collector Cutoff Current (Figure 7)
ICBO
VCB = 10V, IE = 0
-
0.0013
100
nA
15
24
-
V
Collector-to-Emitter Breakdown Voltage
V(BR)CEO
IC = 1mA, IB = 0
Collector-to-Base Breakdown Voltage
V(BR)CBO
IC = 10μA, IE = 0
20
60
-
V
Collector-to-Substrate Breakdown Voltage
V(BR)CIO
IC = 10μA, IB = IE = 0
20
60
-
V
Emitter-to-Base Breakdown Voltage
V(BR)EBO
IE = 10μA, IC = 0
5
7
-
V
DYNAMIC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER
1/f Noise Figure (For Single Transistor)
(Figure 12)
NF
f = 100kHz, RS = 500Ω,
IC = 1mA
-
1.5
-
dB
Gain Bandwidth Product (For Single
Transistor) (Figure 11)
fT
VCE = 6V, IC = 5mA
-
1.35
-
GHz
Note 3
-
0.28
-
pF
Note 4
-
0.15
-
pF
IC = 0, VCI = 5V
-
1.65
-
pF
I3 = I9 = 2mA
-
100
-
dB
-
75
-
dB
18
22
-
dB
Collector-Base Capacitance (Figure 8)
Collector-Substrate
Capacitance (Figure 8)
CCB
CCI
Common Mode Rejection Ratio
CMRR
AGC Range, One Stage (Figure 2)
AGC
Voltage Gain, Single-Ended Output
(Figures 2, 9, 10)
A
2
IC = 0,
VCB = 5V
Bias Voltage = -6V
Bias Voltage = -4.2V,
f = 10MHz
611.7
October 12, 2005
CA3102
TA = 25oC (Continued)
Electrical Specifications
PARAMETER
SYMBOL
Insertion Power Gain (Figure 3)
GP
Noise Figure (Figure 3)
NF
Input Admittance
Y11
Reverse Transfer Admittance
TEST CONDITIONS
VCC = 12V, for
Cascode
Configuration
I3 = I9 = 2mA. For
Diff. Amp.
Configuration
I3 = I9 = 4mA (Each
Collector IC ≅ 2mA)
f = 200MHz
Y12
Forward Transfer
Admittance
Y21
Output Admittance
Y22
MIN
TYP
MAX
UNITS
Cascode
-
23
-
dB
Cascode
-
4.6
-
dB
Cascode (Figures
14, 16, 18)
-
1.5 + j2.45
-
mS
Diff. Amp. (Figures
15, 17, 19)
-
0.878 + j1.3
-
mS
Cascode
-
0.0 - j0.008
-
mS
Diff. Amp.
-
0.0 - j0.013
-
mS
Cascode (Figures
26, 28, 30)
-
17.9 - j30.7
-
mS
Diff. Amp. (Figures
27, 29, 31)
-
-10.5 + j13
-
mS
Cascode (Figures
20, 22, 24)
-
-0.503 - j15
-
mS
Diff. Amp. (Figures
21, 23, 25)
-
0.071 + j0.62
-
mS
NOTES:
3. Terminals 1 and 14 or 7 and 8.
4. Terminals 13 and 4 or 6 and 11.
Schematic Diagram
CA3102E, CA3102M
1
14
13
Q2
4
12
8
Q1
2
6
Q6
5
11
Q5
10
Q3
3
7
Q4
9
SUBSTRATE
3
611.7
October 12, 2005
CA3102
Test Circuits
+6V
1kΩ
V+ (+6V)
VOUT
+1V
(7) 14
1kΩ
S2
1kΩ
VO
M
1kΩ
10μF
S2
VIN
M
(8)
13 (6)
Q2
(Q6)
1
Q1
(Q5)
100Ω
S1
4
(11)
100Ω
S1
(10)
-1V
BIAS
VOLTAGE
5
VX
M
Q3 (Q4)
2
3 (9)
500Ω
12
I3 or I9
V- (-6V)
-6V
FIGURE 1. DC CHARACTERISTICS TEST CIRCUIT FOR CA3102
FIGURE 2. AGC RANGE AND VOLTAGE GAIN TEST CIRCUIT
FOR CA3102
1/2 CA3102
14(7)
Q2
(Q6)
1(8)
0.005μF
5(12)
Q1
(Q5)
SUBSTRATE
Q3 (Q4)
2 (10)
3 (9)
4 (11)
13 (6)
2.7pF
5.6pF
INPUT
RG = 50Ω
L1
C1
5μF
100Ω
6V
2+
0.001
μF
OUTPUT
RL = 50Ω
5pF C2
L2
0.001μF
0.001μF
0.001μF
MA
2kΩ
100pF
13kΩ
1kΩ
0.001μF
100pF
FERRITE
BEADS
100pF
5kΩ
NOTES:
5. Numbers in parentheses refer to the other
half of the CA3102.
6. L1, L2 - Approximately 1/2 Turn #18 Tinned
Copper Wire, 5/8” Diameter.
470pF
7. C1, C2 - 15pF Variable Capacitors
(Hammarlund, MAC-15; or Equivalent).
10kΩ
+12V
0.001μF
FIGURE 3. 200MHz CASCODE POWER GAIN AND NOISE FIGURE TEST CIRCUIT
4
611.7
October 12, 2005
CA3102
Typical Performance Curves
100
0.5
INPUT BIAS CURRENT (μA)
INPUT OFFSET VOLTAGE (mV)
TA = 25oC
0.4
0.3
0.2
0.1
1
EMITTER CURRENT (mA)
10
TA = -40oC
TA = 25oC
TA = 85oC
1.0
0.1
0.1
10
FIGURE 4. INPUT OFFSET VOLTAGE vs EMITTER CURRENT
1.0
EMITTER CURRENT (mA)
10
FIGURE 5. INPUT BIAS CURRENT vs EMITTER CURRENT
1.0
COLLECTOR CUTOFF CURRENT (pA)
BASE-TO-EMITTER VOLTAGE (V)
1000
TA = 85oC
TA = 25oC
TA = -40oC
0.9
0.8
0.7
0.6
0.5
0.1
1.0
COLLECTOR CURRENT (mA)
3
VCB = 10V
100
VCB = 5V
10
1.0
0.1
0.01
-100
10
FIGURE 6. BASE-TO-EMITTER VOLTAGE vs COLLECTOR
CURRENT
VCB = 15V
-50
-25
0
25
TEMPERATURE (οC)
50
75
100
FIGURE 7. COLLECTOR CUTOFF CURRENT vs TEMPERATURE
70
TA = 25oC
TA = 25oC
V+ = 6V, V- = -6V
f = 1kHz
60
VOLTAGE GAIN (dB)
50
CAPACITANCE (pF)
-75
2
CCI
1
TERMINALS 14 AND 1; 7 AND 8
TERMINALS 13 AND 4; 6 AND 11
40
30
20
10
0
-10
-20
-30
-40
CCB
-50
0
0
1
2
3
4
5
6 7
8 9
BIAS VOLTAGE (V)
10 11
12 13
FIGURE 8. CAPACITANCE vs DC BIAS VOLTAGE
5
14
0
-1
-2
-3
-4
-5
-6
-7
BIAS VOLTAGE ON TERMINALS 2 AND 10 (V)
FIGURE 9. VOLTAGE GAIN vs DC BIAS VOLTAGE
611.7
October 12, 2005
CA3102
Typical Performance Curves
(Continued)
2.0
40
30
25
20
15
10
5
0
0.01
1.0
FREQUENCY (MHz)
10
NOISE FIGURE (dB)
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
100
FIGURE 10. VOLTAGE GAIN vs FREQUENCY
30
TA = 25oC
1.9
0.8
0.1
TA = 25oC
RSOURCE = 500Ω
0
2
3
4 5
6
7 8
9 10 11 12 13
COLLECTOR CURRENT (mA)
TA = 25oC
f = 10Hz
14
f = 100Hz
20
f = 1kHz
f = 10kHz
f = 100kHz
f = 10Hz
f = 100Hz
RSOURCE = 1kΩ
30
10
1
FIGURE 11. GAIN BANDWIDTH PRODUCT vs COLLECTOR
CURRENT
NOISE FIGURE (dB)
VOLTAGE GAIN (dB)
35
GAIN BANDWIDTH PRODUCT (GHz)
TA = 25oC
20
f = 1kHz
f = 10kHz
10
f = 100kHz
0
0.01
0
0.01
0.1
1.0
COLLECTOR CURRENT (mA)
FIGURE 12. 1/f NOISE FIGURE vs COLLECTOR CURRENT
6
20
TA = 25oC
15
1.5
1.0
10
g11
5
0.5
b11
0
10
102
FREQUENCY (MHz)
0
103
FIGURE 14. INPUT ADMITTANCE (Y11) vs FREQUENCY
6
INPUT CONDUCTANCE (g11)
2.0
OR SUSCEPTANCE (b11) (mS)
CASCODE AMPLIFIER
VCC = 12V
I3 = I9 = 2mA
INPUT SUSCEPTANCE (b11) (mS)
INPUT CONDUCTANCE (g11) (mS)
FIGURE 13. 1/f NOISE FIGURE vs COLLECTOR CURRENT
25
2.5
0.1
1.0
COLLECTOR CURRENT (mA)
DIFFERENTIAL AMPLIFIER
VCC = 12V
I3 = I9 = 4mA
TA = 25oC
5
4
b11
3
2
g11
1
0
10
102
FREQUENCY (MHz)
103
FIGURE 15. INPUT ADMITTANCE (Y11) vs FREQUENCY
611.7
October 12, 2005
CA3102
CASCODE AMPLIFIER
I3 = I9 = 2mA
f = 200MHz
TA = 25oC
3
INPUT CONDUCTANCE OR
SUSCEPTANCE (mS)
(Continued)
b11
2
g11
1
DIFFERENTIAL AMPLIFIER
I3 = I9 = 4mA
f = 200MHz
TA = 25oC
3
INPUT CONDUCTANCE OR
SUSCEPTANCE (mS)
Typical Performance Curves
0
2
b11
1
g11
0
0
10
20
30
0
40
10
FIGURE 16. INPUT ADMITTANCE (Y11) vs COLLECTOR
SUPPLY VOLTAGE
CASCODE AMPLIFIER
VCC = 12V
f = 200MHz
TA = 25oC
4
3
b11
2
g11
1
0
g11
2
b11
1
0
0
2
4
6
8
0
5
10
15
20
EMITTER CURRENT (I3 OR I9) (mA)
EMITTER CURRENT (I3 OR I9) (mA)
FIGURE 18. INPUT ADMITTANCE (Y11) vs EMITTER CURRENT
FIGURE 19. INPUT ADMITTANCE (Y11) vs EMITTER CURRENT
3
4
1
OUTPUT CONDUCTANCE OR
SUSCEPTANCE (mS)
CASCODE AMPLIFIER
VCC = 12V
I3 = I9 = 2mA
TA = 25oC
2
OUTPUT CONDUCTANCE OR
SUSCEPTANCE (mS)
40
DIFFERENTIAL AMPLIFIER
VCC = 12V
f = 200MHz
TA = 25oC
3
INPUT CONDUCTANCE OR
SUSCEPTANCE (mS)
INPUT CONDUCTANCE OR
SUSCEPTANCE (mS)
5
30
FIGURE 17. INPUT ADMITTANCE (Y11) vs COLLECTOR
SUPPLY VOLTAGE
7
6
20
COLLECTOR SUPPLY VOLTAGE (V)
COLLECTOR SUPPLY VOLTAGE (V)
0
g22
-1
b22
-2
-3
-4
DIFFERENTIAL AMPLIFIER
VCC = 12V
I3 = I9 = 4mA
3
TA = 25oC
2
b22
1
0
-1
g22
-5
-6
10
102
FREQUENCY (MHz)
103
FIGURE 20. OUTPUT ADMITTANCE (Y22) vs FREQUENCY
7
-2
10
102
103
FREQUENCY (MHz)
FIGURE 21. OUTPUT ADMITTANCE (Y22) vs FREQUENCY
611.7
October 12, 2005
CA3102
Typical Performance Curves
g22
CASCODE AMPLIFIER
I3 = I9 = 2mA
f = 200MHz
TA = 25oC
-1
b22
-2
b22
0.4
0.2
g22
0
-3
0
10
20
30
0
40
10
FIGURE 22. OUTPUT ADMITTANCE (Y22) vs COLLECTOR
SUPPLY VOLTAGE
30
40
FIGURE 23. OUTPUT ADMITTANCE (Y22) vs COLLECTOR
SUPPLY VOLTAGE
OUTPUT CONDUCTANCE OR
SUSCEPTANCE (mS)
CASCODE AMPLIFIER
VCC = 12V
f = 200MHz
TA = 25oC
OUTPUT CONDUCTANCE OR
SUSCEPTANCE (mS)
20
COLLECTOR SUPPLY VOLTAGE (V)
COLLECTOR SUPPLY VOLTAGE (V)
g22
0
-1
-2
b22
DIFFERENTIAL AMPLIFIER
VCC = 12V
f = 200MHz
TA = 25oC
1
b22
g22
0
-3
-1
0
2
4
6
0
8
5
EMITTER CURRENT (I3 OR I9) (mA)
50
TA = 25oC
g21
40
30
20
10
0
0
-10
-20
b21
-20
10
102
FREQUENCY (MHz)
-40
103
FIGURE 26. FORWARD TRANSFER ADMITTANCE (Y21) vs
FREQUENCY
8
15
20
FIGURE 25. OUTPUT ADMITTANCE (Y22) vs EMITTER CURRENT
50
FORWARD TRANSFER CONDUCTANCE
OR SUSCEPTANCE (mS)
CASCODE AMPLIFIER
VCC = 12V
I3 = I9 = 2mA
FORWARD TRANSFER SUSCEPTANCE (mS)
70
60
10
EMITTER CURRENT (I3 OR I9) (mA)
FIGURE 24. OUTPUT ADMITTANCE (Y22) vs EMITTER CURRENT
FORWARD TRANSFER CONDUCTANCE (mS)
DIFFERENTIAL AMPLIFIER
I3 = I9 = 4mA
f = 200MHz
TA = 25oC
0.6
OUTPUT CONDUCTANCE OR
SUSCEPTANCE (mS)
OUTPUT CONDUCTANCE OR
SUSCEPTANCE (mS)
0
(Continued)
DIFFERENTIAL AMPLIFIER
VCC = 12V
I3 = I9 = 4mA
40
30
TA = 25oC
20
b21
10
0
g21
-10
-20
-30
-40
10
102
FREQUENCY (MHz)
103
FIGURE 27. FORWARD TRANSFER ADMITTANCE (Y21) vs
FREQUENCY
611.7
October 12, 2005
CA3102
Typical Performance Curves
(Continued)
FORWARD TRANSFER CONDUCTANCE
OR SUSCEPTANCE (mS)
FORWARD TRANSFER CONDUCTANCE
OR SUSCEPTANCE (mS)
20
20
g21
10
CASCODE AMPLIFIER
I3 = I9 = 2mA
f = 200MHz
TA = 25oC
0
-10
-20
-30
b21
15
b21
10
5
DIFFERENTIAL AMPLIFIER
I3 = I9 = 4mA
f = 200MHz
TA = 25oC
0
-5
-10
g21
-15
0
5
10
15
20
25
30
COLLECTOR SUPPLY VOLTAGE (V)
35
0
20
30
40
COLLECTOR SUPPLY VOLTAGE (V)
FIGURE 28. FORWARD TRANSFER ADMITTANCE (Y21) vs
COLLECTOR SUPPLY VOLTAGE
FIGURE 29. FORWARD TRANSFER ADMITTANCE (Y21) vs
COLLECTOR SUPPLY VOLTAGE
40
50
30
FORWARD TRANSFER CONDUCTANCE
OR SUSCEPTANCE (mS)
FORWARD TRANSFER CONDUCTANCE
OR SUSCEPTANCE (mS)
10
g21
20
10
0
CASCODE AMPLIFIER
VCC = 12V
f = 200MHz
TA = 25oC
-10
-20
-30
-40
-50
-60
b21
-70
DIFFERENTIAL AMPLIFIER
VCC = 12V
f = 200MHz
TA = 25oC
40
30
b21
20
10
0
-10
g21
-20
-80
0
2
4
6
8
10
EMITTER CURRENT (I3 OR I9) (mA)
12
FIGURE 30. FORWARD TRANSFER ADMITTANCE (Y21) vs
EMITTER CURRENT
9
14
0
4
8
12
16
EMITTER CURRENT (I3 OR I9) (mA)
FIGURE 31. FORWARD TRANSFER ADMITTANCE (Y21) vs
EMITTER CURRENT
611.7
October 12, 2005
CA3102
Dual-In-Line Plastic Packages (PDIP)
N
E14.3 (JEDEC MS-001-AA ISSUE D)
E1
INDEX
AREA
1 2 3
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N/2
INCHES
-B-
SYMBOL
-AD
E
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
eA
A1
eC
B
0.010 (0.25) M
C
L
C A B S
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
MILLIMETERS
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.15
1.77
8
C
0.008
0.014
0.204
0.355
-
D
0.735
0.775
18.66
D1
0.005
-
0.13
-
5
19.68
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
6
eB
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
14
14
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
10
611.7
October 12, 2005
CA3102
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
µα
e
A1
B
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3367
0.3444
8.55
8.75
3
E
0.1497
0.1574
3.80
4.00
4
e
C
0.10(0.004)
B S
0.050 BSC
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
NOTES:
MILLIMETERS
α
14
0o
14
8o
0o
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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11
611.7
October 12, 2005
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