an9743

The HMP8154EVAL1 Encoder
Evaluation Platform
TM
Application Note
July 1997
AN9743
Author: Steven Martin
Features
• HMP8154 Video Encoder
board includes an encoder, voltage references and decoupling, analog output filters, and I/O connectors.
• Digital Parallel ITU-R BT.656 Input
The board’s primary input is via a 50 pin receptacle. It may be
used for wiring the board into an existing system. The connector provides access to all of the encoder’s digital I/O signals.
• 50 Pin, Dual Row Receptacle
• Analog Output Formats
The board outputs analog video via four coax connectors.
The board can output one composite video signal and
either S-Video and a second composite signal, or component RGB video.
- Y/C + Two Composite
- RGB + Composite (SCART)
• NTSC and PAL Operation
• ITU-R BT.601 and Square Pixel Operation
The board also accepts a digital parallel BT.656 data stream.
Translators convert the ECL input to TTL levels and drive the
encoder. The encoder converts the data and its embedded
timing information into analog video.
Description
The HMP8154EVAL1 encoder evaluation platform is a small
(index card size) printed circuit board designed to demonstrate the capabilities and performance of the HMP8156 and
HMP8154 and HMP8170-73 NTSC/PAL encoders. The
For non-default operation, the encoder must be programmed via the I2C bus. Application software to drive the
I2C bus via the parallel port of a PC is provided with the
evaluation kit.
Board Block Diagram
HMP8154
ENCODER
DATA
24
ECL TO TTL
BT.656
CONNECTOR
ANALOG
OUTPUTS
BUS SWITCH 9
9
MAIN I/O
RECEPTACLE
4
SYNCS AND
HOST I/O
ANALOG
COMP/REF
35
I2C I/O,
PARALLEL PORT
RECONSTRUCTION
FILTERS
4
COMPENSATION
AND
REFERENCE
VOLTAGE
5
CLOCKS
2
POWER AND GROUND CONNECTIONS NOT SHOWN
1
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Application Note 9743
Operating Modes
The HMP8154EVAL1 board has two main operating modes.
It may be installed on a mother board as a daughter card or it
may be connected with other system components as a
stand-alone board.
5.0V, 300mA
5.2V, 150mA
Stand-Alone BT.656 Operation
In stand-alone mode, the HMP8154EVAL1 is connected to
external power supplies, a BT.656 signal generator, a PC
parallel port, and a monitor or measurement equipment. The
interconnections are shown in Figure 1.
+5V, J7
-5V, J10
GND, J8
GND, J9
FIGURE 2. POWER SUPPLY CONNECTIONS
+5V AND -5.2V
DUAL POWER
SUPPLY
Daughter Card Operation
BT.656
VIDEO TEST
PATTERN
GENERATOR
HMP8154
EVAL1
BOARD
MONITOR
AND/OR
VM700
PC
(PARALLEL
PORT)
FIGURE 1. STAND-ALONE INTERCONNECTIONS
The test pattern generator may be any that generates digital
parallel YCbCr video per the ITU-R BT.656 (formerly
CCIR-656) standard. The BT.656 interface uses differential
signals with ECL logic levels. It includes 8 or 10 bits of data
and a 27.0MHz clock.
For best results, use a linear power supply with isolated dual
outputs. The power required is 5.0V ±5% at 300mA and
-5.2V ±10% at 150mA. The board grounds are tied together
so the power supplies’ should not be. The power supply connections are shown in Figure 2. The connections should be
made with 20-24 AWG twisted pair wires.
In stand-alone BT.656 mode, the encoder must be
programmed for non-default operation. The board includes
a header which provides access to the encoder’s host
interface bus. The header is designed to interface with a
standard PC parallel port. The PC is then used to program
the encoder via its I2C interface. Application software
included with the evaluation kit is used to program the
encoder. It is described in the Application Software section
below.
Any high quality monitor may be used to observe the
encoder’s performance. The encoder supports NTSC and
PAL displays that have composite, S-Video, or component
RGB inputs. An oscilloscope and video measurement equipment are also useful. In all cases, the board’s outputs should
be terminated with a 75Ω load.
2
The HMP8154EVAL1 board has a 50 pin, two row receptacle
which allows connection into an existing system. The main
connector provides access to all of the encoder’s digital
inputs and outputs. The daughter card uses its own output
connectors as in stand-alone mode.
When installed on a mother board, the daughter card’s
BT.656 interface must be disabled. The bus switch may be
opened by installing a jumper shunt on the board at location
JP6. The switch may also be opened by asserting its disable
signal on the main connector - P1, pin 14.
The HMP8156EVAL2 is the Intersil designed mother board
for the HMP8154EVAL1. The mother board is a standard
size PC add in card with an ISA bus interface and application software. The HMP8156EVAL2 kit is a complete system
which allows demonstrating all of the encoder’s operating
modes. It has analog video inputs for composite, S-video,
and component RGB signals. The analog signals are converted/decoded to the digital domain and input to the daughter card. The board also provides a 3 megabyte video RAM
for image capture and display and a BT.656 connector and
interface.
Application Software
In stand-alone BT.656 mode, the encoder must be programmed for non-default operation. The board includes a
header which provides access to the encoder’s host interface bus. The header is designed to interface with a standard PC parallel port. Application software is provided to
control the I2C bus via the parallel port.
The board must be connected to the PC printer port and a
clock source in order for the application software to operate
correctly. The pixel clock may be driven from the main connector (P1), the BT.656 connector (J1), or the clock connector, (J2). Without an active clock, the encoder will not
respond to I2C commands.
The evaluation kit includes two software applications to program the encoder and observe its internal registers. One is a
DOS program with a simple command line interface which
will run on any PC. The other is a windows program which
will only run on PCs using Win95™.
Microsoft Windows™ is a trademark of Microsoft Corporation
Application Note 9743
TABLE 1. EXAMPLE DCIIC COMMANDS
FUNCTION
Reset
DCIIC USAGE
EXAMPLE DOS COMMAND AND OUTPUT
dciic -r
c:\hmp8154> dciic -r
c:\hmp8154>
Load Configuration
dciic filename
c:\hmp8154> dciic bt656.cfg
dciic: bt656.cfg loaded.
c:\hmp8154>
Read I2C Register
dciic -i sub-address
c:\hmp8154> dciic -i 0
dciic: read: 0x40,0X00 = 0x54
c:\hmp8154>
Write I2C Register
dciic -i sub-address value
c:\hmp8154> dciic -i 2 0x1c
dciic: wrote: 0x40,0X02 = 0x1c
c:\hmp8154>
dciic -?
c:\hmp8154> dciic -?
usage: dciic [options] [file.cfg ...]
reads or writes i2c registers.
options:
[-r] do chip reset
[-p <port_adrs>] set printer port base address
[-s <slv_adrs>] set device slave address
[-i <regAdrs> [<data>]]
c:\hmp8154>
Help
DCIIC DOS Application Program
DCIIC (Daughter card I2C) is a simple DOS program written
in C. The program allows the user to:
1. Assert the encoder’s RESET signal to initialize the part to
its default operating state,
2. Load the encoder’s programmable registers from a
configuration file, and
3. Read and/or write any of the encoder’s programmable
registers individually.
By default, the program writes to the parallel port located at
PC I/O space address 0x378. If the board is connected to a
port which is not located at the default address, then the -p
option must be included with the other command line arguments. Other common locations for the parallel port are
addresses 0x3bc and 0x278.
When dciic starts, it searches for an encoder by reading the
product ID register at register sub-address 0 for slave
addresses 0x40 and 0x42. If the encoder does not respond,
the program prints an error message and exits. The slave
address may be set from the command line using the -s
option. If set from the command line, the program does not
read the product ID register.
The dciic configuration files are ASCII files which may be
edited with any text editor. They have the same format as
3
those used by the HMP8156EVAL2 MMVideoEval software
application. However, dciic only supports a subset of the
commands -- namely the SetReg command. Any other commands are silently ignored.
The dciic SetReg command consists of the case-sensitive
keywords “SetReg CHMP8154” followed by the register subaddress and its value. The numeric values follow the usual C
conventions for decimal, octal, or hexadecimal bases. An
example command is below:
SetReg CHMP8154 4 0x28
If a different encoder is used on the board, then its part number should be substituted in the second keyword, i.e.
“CHMP8156” instead of “CHMP8154”
Although written in standard ANSI C, the dciic program was
written for compilation using Microsoft Visual C++, version
1.52. The source code is included with the evaluation kit.
MMEncEval Win95 Application Program
The MMEncEval application program for Win95 is not complete at this time. When complete, its interface will be very
similar to the MMVideoEval application program used with
the HMP8156EVAL2 frame grabber evaluation platform.
Application Note 9743
Physical Interfaces
STAND-ALONE
POWER SUPPLY
CONNECTIONS
ENCODER
SLAVE ADDRESS
SELECT JUMPER
I2C INTERFACE
HEADER
ANALOG OUTPUTS
BNC JACKS
BT.656 INPUT
FEMALE D-SUB
BT.656
ECL TO TTL
TRANSLATORS
RSET POT
BT.656 INPUT
BUS SWITCH
REFERENCE VOLTAGE
AND SELECT JUMPER
Interface Connectors
The HMP8154EVAL1 board’s interface connectors are
listed in Table 2. In the table, the column titled “Board Part
Number” lists a manufacturer and part number of the
connector component installed on the board. On some
boards, equivalent components may be substituted. The
“Mating Part Number” column lists a typical connector
which will interconnect correctly with the component
installed on the board.
The P1 and P2 connectors do not have standard pin numbers. The pin numbers and locations are shown in Figure 3.
The signals for each pin are listed in Tables 3 and 4.
4
MAIN I/O CONNECTOR
RECEPTACLE (ON BOTTOM)
CLOCK
SMA JACK
RECONSTRUCTION
FILTERS
Application Note 9743
TABLE 2. INTERFACE CONNECTOR DEFINITION
INTERFACE
NAME
CONNECTOR
STYLE
BOARD PART
NUMBER
MATING PART
NUMBER
COMMENTS
Main,
P1
50 pin,
Dual Row
Receptacle
AMP 2-635585-1
Header
AMP 2-102973-5
Industry standard receptacle and header using 0.025 inch
square posts with 100 mil pin spacing.
I2C,
P2
5 pin,
Single Row
Header,
Molex 22-23-2051
Receptacle housing,
Molex 22-01-3057;
and Contacts,
Molex 08-55-0102
Header and receptacle are keyed and include the locking
ramp. Some Molex documentation defines pin 1s on
opposite ends of the header and housing.
BT656,
J1
25 pin,
D-Subminiature
Sockets,
AMP 745967-7
Pins,
AMP 747912-2
Connectors and pinout defined by ITU-R BT.656 standard.
CLK,
J2
SMA
Coaxial
Jack,
Johnson Components
142-0701-211
Plug,
Johnson Components
142-0403-011
The clock interface is bidirectional. The connector must not
be driven when the BT656 interface is active or when the
Main connector clock pin is driven.
Analog
Outputs,
J3-J6
BNC
Coaxial
Jack,
Amphenol 31-5329
Plug,
Amphenol 68175
Terminate each analog output with a 75Ω load from the
center conductor to the cable shield for best results.
Plated thru-holes
in PCB
Stranded Wire,
20 - 24 AWG
When not powered via the main P1 connector, the board
may be wired to external power supplies.
Power,
J7-J10
TOP, COMPONENT SIDE
BOTTOM, SOLDER SIDE
TOP VIEW,
LOOKING THROUGH BOARD
1
3
2
I2C CONNECTOR, P2
5 POSITION HEADER
MAIN CONNECTOR, P1
50 POSITION RECEPTACLE,
0.100 INCH SPACING,
AMP 2-535585-1
49
0.100 INCH SPACING,
1
5
NOT TO SCALE
50
FIGURE 3. MAIN AND I2C CONNECTOR PIN LOCATIONS.
5
MOLEX 22-23-2051
Application Note 9743
TABLE 3. MAIN CONNECTOR P1 PINOUT
SIGNAL
PIN
SIGNAL
PIN
SIGNAL
PIN
VCC
1
PIX<12>
18
PIX<1>
35
GND
2
PIX<11>
19
PIX<0>
36
N/C
3
PIX<10>
20
VCC
37
VEE
4
PIX<9>
21
GND
38
PIX<23>
5
PIX<8>
22
N/C
39
PIX<22>
6
-VSYNC_ENC
23
-BLANK_ENC
40
PIX<21>
7
GND
24
FIELD_ENC
41
PIX<20>
8
VCC
25
N/C
42
PIX<19>
9
VCC
26
SCLK
43
PIX<18>
10
GND
27
SDATA
44
PIX<17>
11
-HSYNC_ENC
28
N/C
45
PIX<16>
12
PIX<7>
29
-RESET_A
46
GND
13
PIX<6>
30
PIXCLK
47
-BT656_ENA (VCC)
14
PIX<5>
31
VIDCLK
48
PIX<15>
15
PIX<4>
32
GND
49
PIX<14>
16
PIX<3>
33
VCC
50
PIX<13>
17
PIX<2>
34
TABLE 4. I2C CONNECTOR P2 PINOUT
(NOTE 1)
BOARD
HEADER
PIN NUMBER
(NOTE 1)
RECEPTACLE
HOUSING
PIN NUMBER
(NOTE 2)
PC PARALLEL
PORT
PIN NUMBER
Reset
1
5
4
The reset signal is active low. It should be asserted for at least
four CLK cycles following board powerup.
Output Enable
2
4
3
The serial data signal (and the encoder’s SDATA I/O pin) is
driven low when the output enable signal is asserted.
Otherwise, it is pulled high by an on board resistor.
Ground
3
3
18
Signal return path.
Serial Data
4
2
12
For the encoder, serial data is bidirectional; for the PC, it is only
an input.
Serial Clock
5
1
2
The encoder SCLK signal. The encoder pixel clock signal must
also toggle for the I2C interface to operate.
NAME
COMMENTS
NOTES:
1. Different versions of the Molex documentation for the board header shows pin 1 on either end of the connector. The documentation for the
receptacle housing shows pin 1 on the end opposite of the one chosen for the header. Therefore, the pins are reversed so that when connected,
pin 1 of the header aligns with pin 5 of the housing.
2. The standard PC parallel port uses a 25 pin D-subminiature connector with sockets. A cable end connector which will interconnect with the PC
is part 747912-2 from AMP.
6
Application Note 9743
Moveable Jumpers
Schematics and Layout
The board uses several movable jumpers to control its operation and connectivity. The jumpers and the functions they
control are described in Table 5.
The board schematics are shown in Figures 4-10. Notes in
the schematics indicate assembly options. The parts list follows in the HMP8154EVAL1 Evaluation Board Parts List.
TABLE 5. JUMPER FUNCTIONS
The board consists of four layers laid out to optimize the performance of the encoder. The top and bottom layers are signal trace layers. The inner layers are used for power and
ground planes. The art work for the board is shown in Figures 11-15.
FUNCTION
NAME
OPEN
SHUNTED
NOTES
JP1
Clock
-
J2 is connected to
CLK2
3
JP2
I2C Slave
Address
Encoder responds
to slave address
0x40.
Encoder responds to
slave address 0x42.
4
JP3, JP4
Ground
-
Digital and analog
grounds connected.
3
JP5
External
Reference
Encoder uses its
internal reference
voltage.
Encoder reference
voltage is driven by
the board’s reference
circuit.
4, 5
JP6
BT.656
BT.656 clock and
BT.656 clock and
data drivers may be data drivers are
enabled.
disabled.
6, 7
NOTES:
3. Jumper is hardwired and should not be changed.
4. Default position is shunted.
5. The relation between the reference voltage and output current is
described in the encoder’s data sheet.
6. Default position is open.
7. The BT.656 driver enable signal is also connected to the main P1
connector pin 14 and to a resistor to ground.
Adjustable Components
The board uses a single potentiometer, R5, to set the RSET
value and thus the encoder’s full scale output current. The
resistor should be adjusted so that the output voltage measured at the load is 1.0VPP from the sync tip to the white
level. The resistor is set at the factory for correct video levels
when driving the board reconstruction filter and an external
75Ω terminator.
The adjustable resistor is not needed when the filter and
load are fixed. The adjustment is provided on the board only
to allow flexibility to support different, changeable, loads. As
shown in the encoder’s data sheet, the variability of the output levels is small. They remain within video tolerances
when using a fixed 1% tolerance resistor.
7
The power plane is split into three sections for VEE, VCC,
and VAA. VCC and VEE are powered by the main connector
or by external supplies. VAA is connected to VCC via a single
ferrite bead. Each section of power plane includes its own
bulk area capacitors to ground for decoupling.
The ground plane is split into two sections for digital and
analog grounds. Although isolated in their own planes, the
two ground areas are not electrically distinct. The ground
planes are connected via a solid wire at one point.
Intersil customers may use any part of the schematics or layout. Electronic versions are also available.
FIGURE 4. ENCODER
8
1
2
1
2
TTX
49
50
51
52
53
54
55
58
7
6
5
4
3
2
1
0
5A6>
SCLK
5A6> SDATA
SADRS
5A6> −RESET
5A6>
37
38
43
44
45
46
47
48
15
14
13
12
11
10
9
8
3C1>
AGND3
39
41
18
19
20
21
25
22
23
27
28
29
30
31
32
23
22
21
20
19
18
17
16
5A6> VIDCLK
5D2> 5B2> 5A6> PIXCLK
SLAVE ADDRESS
SELECT JUMPER
3C1> AGND3
JP2
R3
6.8K
10%, 0.1W
CR1206
3D1> VAA3
5D6> 5D2> PIX<23..0>
2
C23
0.1µ
10%, 25V
CR1206
C22
0.1µ
10%, 25V
CR1206
CLK (REF)
CLK2 (PIX)
SCLK
SDATA
SADRS
RESERVED
RESET
PIX7
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
PIX15
PIX14
PIX13
PIX12
PIX11
PIX10
PIX9
PIX8
PIX23
PIX22
PIX21
PIX20/M1
PIX19/M0
PIX18/OL2
PIX17/OL1
PIX16/OL0
2
1
63
1
64
C1
GND
HMP8154
U10
MQFP
VAA
BLANK
HSYNC
VSYNC
FIELD
NP2
NP1
C
Y
VREF
FSA
57
40
24
13
9
5
2
1
60
59
56
42
26
17
16
14
12
10
8
6
4
3D1> VAA3
C2
COMPENSATION CAPS
33
35
36
34
15
11
7
3
61
62
CR1206
R4
51
10%, 0.1W
1
2
−BLANK_ENC 5A6> 6C2<
−HSYNC_ENC 5A6> 6B8<
−VSYNC_ENC 5A6> 6B8<
FIELD_ENC 5B6>
NP2_ENC 2A8<
NP1_ENC 2B8<
C_ENC 2C8<
1
2
1
2
JP5
C21
0.01µ
10% , 25V
CR1206
2
1
+
C20
4.7µ
10%, 15V
THTANT
VREF_EXT
3D1> VAA3
R21
6.8K
10% , 0.1W
CR1206
3 D1
ICL8069DCZR
TO92
2
1
2
EXTERNAL VOLTAGE REFERENCE
3C1> AGND3
3C1> AGND3
Y_ENC 2D8<
VREF
2
R5
200
0.5W, 10%
TH
3
1
RSET: DETERMINES DAC’s
FULLSCALE OUTPUT CURRENT
Application Note 9743
HMP8154EVAL1 Evaluation Board Schematic Diagrams
Application Note 9743
HMP8154EVAL1 Evaluation Board Schematic Diagrams
1B4> Y_ENC
R7
75.0
1%, 0.1W
CR1206
1
1
2
1B4> C_ENC
R19
75.0
1%, 0.1W
CR1206
1
1
2
1B4> NP1_ENC
R6
75.0
1%, 0.1W
CR1206
CR1210
CR1210
CR1210
CR1206
C13
DUMMY
10%, 25V
CR1206
1
1
2
2
BNCST
J3-1
2
BNCST
J4-1
2
BNCST
J5-1
2
BNCST
J6-1
CR1206
1
2
C16
330P
10%, 25V
CR1206
1
2
C17
330P
10%, 25V
CR1206
L11
2.2µ
10%, 30Q
1
2
L13
1.0µ
10%, 30Q
1
2
CR1210
CR1210
CR1210
1
2
C19
DUMMY
10%, 25V
CR1206
R11
0
10%, 0.1W
2
1
YOUT_RET
CR1206
C_OUT
C56
39P
10%, 25V
1
2
C42
DUMMY
10%, 25V
1
2
CR1206
CR1206
1
2
C41
330P
10%, 25V
CR1206
1
2
C40
330P
10%, 25V
CR1206
L2
1.0µ
10%, 30Q
1
2
L3
2.2µ
10%, 30Q
1
2
L4
1.0µ
10%, 30Q
1
2
CR1210
CR1210
CR1210
CR1206
C6
DUMMY
10%, 25V
CR1206
Y_OUT
CR1206
L12
1.0µ
10%, 30Q
1
2
CR1206
C45
DUMMY
10%, 25V
CR1206
(Continued)
C18
39P
10%, 25V
1
2
C15
DUMMY
10%, 25V
1
2
1
2
C57
DUMMY
10%, 25V
CR1206
R8
0
10%, 0.1W
2
1
COUT_RET
CR1206
NP1_OUT
C10
39P
10%, 25V
1
2
C8
DUMMY
10%, 25V
1
2
C7
82P
10%, 25V
1
2
2
3C1> AGND3
L7
1.0µ
10%, 30Q
1
2
C44
82P
10%, 25V
1
2
2
3C1> AGND3
L6
2.2µ
10%, 30Q
1
2
C14
82P
10%, 25V
1
2
2
3C1> AGND3
L5
1.0µ
10%, 30Q
1
2
CR1206
CR1206
1
2
C12
330P
10%, 25V
CR1206
1
2
C9
330P
10%, 25V
CR1206
1
2
C11
DUMMY
10%, 25V
CR1206
R10
0
10%, 0.1W
2
1
NP1O_RET
CR1206
1B4> NP2_ENC
R13
75.0
1%, 0.1W
CR1206
L10
2.2µ
10%, 30Q
1
2
L8
1.0µ
10%, 30Q
1
2
CR1210
CR1210
CR1210
1
2
CR1206
C30
DUMMY
10%, 25V
CR1206
NP2_OUT
C27
82P
10%, 25V
1
2
C28
DUMMY
10%, 25V
1
2
C29
82P
10%, 25V
1
2
2
1
3C1> AGND3
L9
1.0µ
10%, 30Q
1
2
CR1206
CR1206
1
2
C43
330P
10%, 25V
CR1206
1
2
C25
330P
10%, 25V
CR1206
1
2
C26
DUMMY
10%, 25V
CR1206
R12
0
10%, 0.1W
2
1
NP2O_RET
CR1206
NOTE: Caps valued "dummy" are not populated. Components may be added/changed to test alternate reconstruction filter circuits.
FIGURE 5. ANALOG OUTPUTS
9
Application Note 9743
HMP8154EVAL1 Evaluation Board Schematic Diagrams
(Continued)
L1
FERRITE_BEAD
TOL, 5A
1
2
VCC
VAA3 1B2< 1B8< 1D7<
3B4< 3C4<
TH
1
+
2
C2
15µ
10%, 15V
THTANT
GND
1
+
2
JP3
1
C3
15µ
10%, 15V
THTANT
1
2
C4
0.1µ
10%, 25V
CR1206
1
2
C5
0.01µ
10%, 25V
CR1206
AGND3 1A3< 1A6< 1A8<
1B3< 2A8< 2B8<
2C8< 3B4<
2
JP4
1
2
3D1> VAA3
1
2
C35
0.1µ
10%, 25V
CR1206
1
C32
0.1µ
10%, 25V
CR1206
1
2
C34
0.01µ
10%, 25V
CR1206
1
C50
0.01µ
10%, 25V
CR1206
1
2
C48
0.1µ
10%, 25V
CR1206
1
C49
0.1µ
10%, 25V
CR1206
1
2
CC47
0.01µ
10%, 25V
CR1206
1
C31
0.01µ
10%, 25V
CR1206
1
2
C51
0.1µ
10%, 25V
CR1206
1
C33
0.1µ
10%, 25V
CR1206
1
2
C36
0.01µ
10%, 25V
CR1206
3C1> AGND3
3D1> VAA3
1
2
2
2
2
2
2
C46
0.01µ
10%, 25V
CR1206
3C1> AGND3
VCC
1
2
C54
0.1µ
10%, 25V
CR1206
1
C1
4.7µ
10%, 15V
THTANT
1
+
2
C58
0.1µ
10%, 25V
CR1206
1
C24
4.7µ
10%, 15V
THTANT
1
2
C38
0.1µ
10%, 25V
CR1206
1
C59
0.1µ
10%, 25V
CR1206
1
2
C53
0.1µ
10%, 25V
CR1206
1
C55
0.1µ
10%, 25V
CR1206
1
2
C37
0.1µ
10%, 25V
CR1206
GND
GND
1
+
2
2
2
2
3C7> VEE
J7
VCC\R 4
4H30
J8
GND\R 4
4H30
J9
GND\R 4
4H30
J10
VEE\R 4 3A8< 5B7< 6A5< 6B5< 6C5<
4H30
FIGURE 6. POWER/GND
10
2
C39
0.1µ
10%, 25V
CR1206
11
1
2
FIGURE 7. BT.656 INPUT
J1-4
DSUB25ST J1-17
DSUB25ST
−BT<8>
BT<8>
−BT<9>
BT<9>
−BT CLK
2
2
3
4
8
9
18
19
2
13
14
2
10H125
U8
PLCC
1
5
10H125
U8
PLCC
1
7
10H125
U8
PLCC
1
10H125
U8
PLCC
1
15
8
9
17
DSUB25ST J1-21
DSUB25ST J1-8
DSUB25ST J1-20
DSUB25ST J1-7
DSUB25ST J1-19
DSUB25ST J1-6
DSUB25ST J1-18
DSUB25ST J1-5
5D4<
BT656_CLK
−BT<4>
BT<4>
−BT<5>
BT<5>
−BT<6>
BT<6>
−BT<7>
BT<7>
3
4
8
18
2
19
2
2
9
13
2
14
J1-2
10H125
U7
PLCC
1
17
10H125
U7
PLCC
1
5
10H125
U7
PLCC
1
7
10H125
U7
PLCC
1
15
DSUB25ST J1-25
DSUB25ST J1-12
DSUB25ST J1-24
DSUB25ST J1-11
DSUB25ST J1-23
DSUB25ST J1-10
DSUB25ST J1-22
DSUB25ST J1-9
BT_RET
BT_SHIELD
−BT<0>
BT<0>
−BT<1>
BT<1>
−BT<2>
BT<2>
−BT<3>
BT<3>
3
4
8
18
2
19
2
2
9
13
2
14
CR1206
R24
0
10%, 0.1W
1
2
CR1206
R23
0
10%, 0.1W
1
2
ECL TERMINATORS SHOWN IN FIGURE 9
4
5
6
7
DSUB25ST J1-15
DSUB25ST
DSUB25ST J1-13
DSUB25ST J1-M1
DSUB25ST J1-M2
0
1
2
3
BT656_PIX <9..0> 5D4<
10H125
U6
PLCC
1
17
10H125
U6
PLCC
1
5
10H125
U6
PLCC
1
7
10H125
U6
PLCC
1
15
GND
HMP8154EVAL1 Evaluation Board Schematic Diagrams
DSUB25ST J1-16
DSUB25ST J1-3
DSUB25ST J1-14
R1
100
10%, 0.1W
CR1206
DSUB25ST J1-1
BT CLK
VBB
Application Note 9743
(Continued)
Application Note 9743
HMP8154EVAL1 Evaluation Board Schematic Diagrams
PIX<23..0>
5D2> 1C6< 6D8<
PIXEL DATA
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
P1-5
P1-6
P1-7
P1-8
P1-9
P1-10
P1-11
P1-12
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
P1-15
P1-16
P1-17
P1-18
P1-19
P1-20
P1-21
P1-22
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
P1-29
P1-30
P1-31
P1-32
P1-33
P1-34
P1-35
P1-36
23
22
21
20
19
18
17
16
(Continued)
BT.656 INPUT ISOLATION BUS SWITCH4
4D6> BT656_CLK
4A1> BT656_PIX<9..0>
3
5
7
9
15
14
13
12
11
10
9
8
23
20
19
16
15
10
9
6
5
2
8
6
4
2
JP6
7
6
5
4
3
2
1
0
VCC
GND
PIXCLK
U9
SOIC
1
QS3384
9B
9A
B
8
8A
7B
7A
6B
6A
5B
5A
4B
4A
3B
3A
2B
2A
1B
1A
0B
0A
OEL OEH
1
5A6> 5B2> 1A6<
PIX<23..0>
9
11
13
15
22
21
18
17
14
11
8
7
4
3
5D6> 1C6< 6D8<
14
12
10
8
13
2
R20
6.8K
10%, 0.1W
1
2
CR1206
5B6> −BT656_EN
POWER AND GROUND
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
P1-1
P1-25
P1-26
P1-37
P1-50
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
P1-2
P1-13
P1-24
P1-27
P1-38
P1-49
PCLK_SMA
VCC
SMAST
J2-1
5A6> 5D2> 1A6<
1
GND
−BT656_EN
VEE 3C7>
2
R9
100
10%, 0.1W
CR1206
1
1
5C4<
2
R22
0
10%, 0.1W
1
2
R2
100
10%, 0.1W
CR1206
C52
330P
10%, 25V
CR1206
GND
CR1206
CONTROL
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
HDR2X25
PIXCLK
2
2
2
HDR2X25 P1-14
HDR2X25 P1-4
JP1
1
FIELD_ENC 1A4>
−HSYNC_ENC 1A4> 6B8<
−VSYNC_ENC 1A4> 6B8<
−BLANK_ENC 1A4> 6C2<
PIXCLK 5B2> 5D2> 1A6<
VIDCLK 1A6< 6A8<
SDATA 1A6< 7C7<
SCLK 1A6< 7C7<
−RESET 1B6< 7C7<
TTX 1B6<
P1-41
P1-28
P1-23
P1-40
P1-47
P1-48
P1-44
P1-43
P1-46
P1-3
NO CONNECTS
HDR2X25 P1-39
HDR2X25 P1-42
HDR2X25 P1-45
ALTERNATE CLOCK INPUT OR OUTPUT.
IF USED AS AN OUTPUT, IT HAS VERY
LIMITED DRIVE STRENGTH.
DIFFERENCES BETWEEN
EVAL1 AND EVAL2 CONNECTORS
PIN
EVAL2
4
N/C
VEE
14
VCC
BT656 Disable
39
Field Out
N/C
41
N/C
Field Out
FIGURE 8. EVM1 CONNECTOR AND CLOCKS
12
HERE
13
FIGURE 9. PUP/PUD TERMINATIONS
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
U11
10K
2%
0.1W
U12
10K
2%
0.1W
U13
10K
2%
0.1W
COMMON
R8
R7
R6
R5
R4
R3
R2
R1
R0
R-PACK
TSIP10
COMMON
R8
R7
R6
R5
R4
R3
R2
R1
R0
R-PACK
TSIP10
COMMON
R8
R7
R6
R5
R4
R3
R2
R1
R0
PULL UP AND PULL DOWN RESISTORS TO
PREVENT ENCODER’S UNDRIVEN INPUTS
FROM FLOATING.
VCC
7
6
5
4
3
2
1
0
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
15
R-PACK
TSIP10
1
2
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
COMMON
R-PACK
TSIP10
R8 U2
R7 560
R6 2%
R5 0.1W
R4
R3
R2
R1
R0
COMMON
R-PACK
TSIP10
R8 U1
R7 560
R6 2%
R5 0.1W
R4
R3
R2
R1
R0
COMMON
R-PACK
TSIP10
R8 U3
R7 560
R6 2%
R5 0.1W
R4
R3
R2
R1
R0
5
6
7
8
9
0
1
2
3
4
10
8
6
4
2
10
8
6
4
2
R-PACK
ISIP10
U4
100
2%
0.1W
R-PACK
ISIP10
U5
100
2%
0.1W
9
7
5
3
1
9
7
5
3
1
5
6
7
8
9
0
1
2
3
4
INLINE RESISTORS FOR ECL DIFFERENTIAL
TERMINATIONS, RT. VALUE REQUIRED DEPENDS
ON PULL DOWN RESISTOR OF DRIVER, RP.
APPROXIMATE VALID RANGE FOR TYPICAL RP:
1/25 RP < RT < 1/4 RP.
RT SHOULD ALSO BE CLOSE TO IMPEDANCE OF
CABLE.
4A5 4A2 −BT<9..0>
4B5 4B2 4A7
4C5 4C2 4B7
4C5 4C2 4B7
4B5 4B2 4A7
4A5 4A2 BT<9..0>
THE VEE PULL DOWN TSIP R-PACKS ARE NOT POPULATED.
ONLY INSTALL THEM IF THE DATA SOURCE
DOES NOT INCLUDE ECL PULL DOWN RESISTORS
ON ITS DRIVERS. INCLUDING THE PUDS ON
THIS BOARD MAY DEGRADE THE ENCODER’S
PERFORMANCE.
3C7> VEE
4C7 −BT_CLK
4D7 −BT_CLK
3C7> VEE
3C7> VEE
4A5 4A2 −BT<9..0>
4A5 4A2 BT<9..0>
HMP8154EVAL1 Evaluation Board Schematic Diagrams
5A6> VIDCLK
5A6> 1A4>
−VSYNC_ENC
−HSYNC_ENC
5A6> 1A4> V
CC
VCC
PIX<23..0>
5D6> 5D2>
R18
6.8K
10%, 0.1W
CR1206
5A6> 1A4> −BLANK_ENC
GND
Application Note 9743
(Continued)
14
FIGURE 10. PC I2C INTERFACE
1
2
1
2
R17
6.8K
10%, 0.1W
CR1206
R16
0
10%, 0.1W
CR1206
1
2
1
2
R25
820
10%, 0.1W
CR1206
1
2
CR1206
R26
6.8K
10%, 0.1W
1
2
TRANSISTOR Q1 OPEN COLLECTOR
USED AS THREE-STATE DRIVER.
HIGH ON OUTPUT ENABLE FORCES
DATA LINE LOW. OTHERWISE,
IT FLOATS HIGH.
R14
470
10%, 0.1W
CR1206
1
2
Q1
2N3704
TO92C
5
4
3
2
1
P2
P2
P2
P2
P2
MXKK5
MXKK5
MXKK5
MXKK5
MXKK5
CONNECTOR IS A MOLEX KK HEADER,
PART NUMBER 22-23-2051.
MATING TERMINAL HOUSING FOR CABLE END
IS PART NUMBER 22-01-3057. HOUSING REQUIRES
CONTACTS TOO. ALL ARE AVAILABLE FROM DIGI-KEY.
CAUTION: SOME MOLEX DOCUMENTATION SHOWS PIN 1
OF THE HEADER ALIGNED WITH PIN 5 OF THE HOUSING.
3
R15
6.8K
10%, 0.1W
CR1206
HMP8154EVAL1 Evaluation Board Schematic Diagrams
THE PARALLEL TERMINATION (R14 AND R25) FOR SCLK IS NOT
STANDARD PER THE I2C SPEC. (SPEC REQUIRES 4-10kW
TO VCC.) USING THIS TERMINATION TO INCREASE THE
DATA TURN ON TIME FOR SCLK CAUSED BY THE VERY LARGE
CAPACITANCE OF THE CABLE AND PC DRIVER. IT REQUIRES
5mA DRIVE. INCREASING THE RESISTOR VALUES LOWERS
THE CURRENT REQUIRED BUT INCREASES THE CABLE TO BOARD
IMPEDANCE MISMATCH AND NOISE.
GND
5A6> SCLK
5A6> SDATA
PC_RET
PC_DOE
5A6> −RESET
VCC
Application Note 9743
(Continued)
Application Note 9743
HMP8154EVAL1 Evaluation Board Parts List
ITEM
QTY
REFERENCE DESIGNATOR
1
8
C5, C21, C31, C34, C36, C46,
C47, C50
CAPACITOR_CR1206-0.01µ, 25V,
10%
VARIOUS
?
2
17
C4, C22, C23, C32, C33, C35,
C37-C39, C48, C49, C51, C53C55, C58, C59
CAPACITOR_CR1206-0.1µ, 25V, 10% VARIOUS
?
3
9
C9, C12, C16, C17, C25, C40,
C41, C43, C52
CAPACITOR_CR1206-330P, 25V,
10%
VARIOUS
?
4
4
C10, C18, C27, C56
CAPACITOR_CR1206-39P, 25V, 10%
VARIOUS
?
5
4
C7, C14, C29, C44
CAPACITOR_CR1206-82P, 25V, 10%
VARIOUS
?
37
12
C6, C8, C11, C13, C15, C19,
C26, C28, C30, C42, C45, C57
CAPACITOR_CR1206-DUMMY, 25V,
10%
NOT POPULATED
-
6
2
C2, C3
POLARCAP_THTANT-15µ, 15V, 10%
KEMET
T350E156K016AS
7
3
C1, C20, C24
POLARCAP_THTANT-4.7µ, 15V, 10% KEMET
T350B475K016AS
8
1
D1
DIODE_TO92-ICL8069DCZR
INTERSIL
ICL8069DCZR
9
4
J3-J6
COAX_BNCST
AMPHENOL-RF
31-5329
10
1
J2
COAX_SMAST
JOHNSON COMPON.
142-0701-201
34
4
J7-J10
EPOINT_4H30
PLATED THRU-HOLE
IN PCB
ARTWORK
12
1
J1
JCONNECTOR_DSUB25S
AMP
745967-7
13
1
J1
LOCKING_POST
AMP
206514-1
14
3
JP2, JP5, JP6
JUMPER2
BERG ELECTRONIC
69190-402
15
2
JP2, JP5
JUMPER_SHUNT
BERG ELECTRONIC
65474-010
16
3
JP1, JP3, JP4
ULOOP HEAVY GAUGE WIRE
BUS
17
8
L2, L4, L5, L7-L9, L12, L13
INDUCTOR_CR1210-1.0µ, 30Q, 10%
DALE
IMC1210-1.0UH-10
18
4
L3, L6, L10, L11
INDUCTOR_CR1210-2.2µ, 30Q, 10%
DALE
IMC1210-2.2UH-10
19
1
L1
INDUCTOR_THFERRITE_BEAD,5A,TOL
DEXTER MAGNET
ET AL
2743001111
20
1
P1
JCONNECTOR_HDR2X25
AMP
2-102973-5
38
1
P2
POST_MXKK5
MOLEX
22-23-2051
22
1
PCB
HMP815X_EVAL1
-
-
39
1
Q1
NPNBJT_TO92C-2N3704
NATIONAL SEMI
?
23
1
R5
POTENTIOM_TH-200, 0.5W, 10%
DALE
T93YA-200-10
24
8
R8, R10-R12, R16, R22-R24
RESISTOR_CR1206-0, 0.1W, 10%
VARIOUS
?
25
3
R1, R2, R9
RESISTOR_CR1206-100, 0.1W, 10%
VARIOUS
?
40
1
R14
RESISTOR_CR1206-470, 0.1W, 10%
VARIOUS
?
26
1
R4
RESISTOR_CR1206-51, 0.1W, 10%
VARIOUS
?
15
PART NAME
MANUFACTURER
PART NUMBER
Application Note 9743
HMP8154EVAL1 Evaluation Board Parts List
REFERENCE DESIGNATOR
(Continued)
ITEM
QTY
PART NAME
28
7
R3, R15, R17, R18, R20, R21,
R26
RESISTOR_CR1206-6.8K, 0.1W, 10% VARIOUS
?
41
1
R25
RESISTOR_CR1206-820, 0.1W, 10%
VARIOUS
?
29
4
R6, R7, R13, R19
ESISTOR_CR1206-93.1, 0.1W, 1%
VARIOUS
?
30
3
U6-U8
10H125_PLCC
MOTOROLA
MC10H125FN
31
1
U10
HMP8154_MQFP
INTERSIL
HMP8156CN OR
HMP8154CN
32
1
U9
QS3384_SOIC
QUALITY SEMI
QS3384SO
35
2
U4, U5
RESISTOR_ISIP10-100, 0.1W, 2%
VARIOUS
?
33
3
U11-U13
RESISTOR_TSIP10-10K, 0.1W, 2%
VARIOUS
?
36
3
U1-U3
RESISTOR_TSIP10-560, 0.1W, 2%
VARIOUS
?
HMP8154EVAL1 Evaluation Board Layout
FIGURE 11. SILK SCREEN TOP
16
MANUFACTURER
PART NUMBER
Application Note 9743
HMP8154EVAL1 Evaluation Board Layout
(Continued)
FIGURE 12. TOP LAYER COMPONENT SIDE
FIGURE 13. LAYER 2, GROUND
17
Application Note 9743
HMP8154EVAL1 Evaluation Board Layout
(Continued)
FIGURE 14. LAYER 3 VEE, VCC, VAA
FIGURE 15. BOTTOM LAYER SOLDER SIDE
18
Application Note 9743
HMP8154EVAL1 Evaluation Board Layout
(Continued)
FIGURE 16. SILK SCREEN BOTTOM
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
19
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