DATASHEET

ISL54212
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RECOMM nical Support C m/tsc
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Data Sheet
September
18, 2007
tersil.co
our Tech
contact ERSIL or www.in
T
1-888-IN
MP3/USB 2.0 High Speed Switch with
Negative Signal Handling
FN6556.0
Features
• High Speed (480Mbps) and Full Speed (12Mbps)
Signaling Capability per USB 2.0
The Intersil ISL54212 dual SPDT (Single Pole/Double
Throw) switches combine low distortion audio and accurate
USB 2.0 high speed data (480Mbps) signal switching in the
same low voltage device. When operated with a 2.5V to 5.5V
single supply these analog switches allow audio signal
swings below-ground, allowing the use of a common USB
and audio headphone connector in Personal Media Players
and other portable battery powered devices.
• Low Distortion Negative Signal Capability
• Control Pin to Open all Switches and Enter Low Power
State
• Low Distortion Headphone Audio Signals
- THD+N at 15mW into 32Load . . . . . . . . . . . . <0.06%
• Cross-talk Audio Channels (20Hz to 20kHz) . . . . . -110dB
The ISL54212 logic control pins are 1.8V compatible which
allows for control via a standard µcontroller. The part has an
audio enable control pin to open all the switches and put the
part in a low power state.
• Single Supply Operation (VDD) . . . . . . . . . . . . 2.5V to 5.5V
• -3dB Bandwidth USB Switches . . . . . . . . . . . . . . . 630MHz
• Available in µTQFN and TDFN Packages
The ISL54212 is available in a small 10 Ld 2.1mmx1.6mm
ultra-thin µTQFN package and a 10 Ld 3mmx3mm TDFN
package. It operates over a temperature range of -40 to
+85°C.
• Pb-Free (RoHS Compliant)
• Compliant with USB 2.0 Short Circuit Requirements
Without Additional External Components
Applications
Related Literature
• MP3 and Other Personal Media Players
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Cellular/Mobile Phones
• PDA’s
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
• Audio/USB Switching
Application Block Diagram
VDD
µCONTROLLER
USB AND HEADPHONE JACK
ISL54212
VBUS
IN
CTRL
LOGIC CIRCUITRY
4M
D-
COM-
D+
50k
COM+
USB
HIGH-SPEED
TRANSCEIVER
L
R
CODEC
50k
GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54212
‘
Pinouts
(Note 1)
ISL54212
(10 LD TDFN)
TOP VIEW
CTRL
ISL54212
(10 LD ΜTQFN)
TOP VIEW
10
D-
2
8
D+
COM -
3
7
L
COM +
4
6
R
1
IN
LOGIC
CONTROL
IN
2
COM -
4M
50k
10
CTRL
9
D-
3
8
D+
COM +
4
7
L
GND
5
6
R
LOGIC
CONTROL
50k
50k
50k
GND
5
1
4M
9
VDD
VDD
NOTE:
1. ISL54212 Switches shown for IN = Logic “1” and CTRL = Logic “1”.
Truth Table
Pin Descriptions
ISL54212
ISL54212
IN
CTRL
L, R
D+, D-
PIN NO.
NAME
0
X
OFF
ON
1
VDD
1
0
OFF
OFF
2
IN
1
1
ON
OFF
3
COM-
Voice and Data Common Pin
4
COM+
Voice and Data Common Pin
5
GND
6
R
Audio Right Input
7
L
Audio Left Input
8
D+
USB Differential Input
9
D-
USB Differential Input
10
CTRL
IN: Logic “0” when 0.5V, Logic “1” when 1.4V with 2.7V to 3.6V
supply.
CTRL: Logic “0” when 0.5V or Floating, Logic “1” when 1.4V with
2.7V to 3.6V supply.
FUNCTION
Power Supply
Digital Control Input
Ground Connection
Digital Control Input (Audio Enable)
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
ISL54212IRTZ
12Z
-40 to +85
10 Ld 3mmx3mm TDFN
L10.3x3A
ISL54212IRTZ-T*
12Z
-40 to +85
10 Ld 3mmx3mm TDFN Tape and Reel
L10.3x3A
ISL54212IRUZ-T*
FX
-40 to +85
10 Ld µTQFN
L10.2.1X1.6A
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
2
FN6556.0
September 18, 2007
ISL54212
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Input Voltages
D+, D-, L, R (Note 2) . . . . . . . . . . . . . . . . . - 2V to ((VDD) + 0.3V)
IN (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 5.5V
CTRL (Note 2) . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((VDD) + 0.3V)
Output Voltages
COM-, COM+ (Note 2) . . . . . . . . . . . . . . . . -2V to ((VDD) + 0.3V)
Continuous Current (Audio Switches). . . . . . . . . . . . . . . . . ±150mA
Peak Current (Audio Switches)
(Pulsed 1ms, 10% Duty Cycle, Max). . . . . . . . . . . . . . . . ±300mA
Continuous Current (USB Switches). . . . . . . . . . . . . . . . . . . ±40mA
Peak Current (USB Switches)
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±100mA
ESD Rating:
HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >7kV
MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >400V
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1.4kV
Thermal Resistance (Typical, Note 3)
JA (°C/W)
10 Ld TQFN Package . . . . . . . . . . . . . . . . . . . . . . .
130
10 Ld 3x3 TDFN Package. . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on D+, D-, L, R, COM-, COM+, CTRL, IN exceeding VDD or GND by specified amount are clamped. Limit current to maximum current
ratings.
3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V, VCTRLH = 1.4V,
VCTRLL = 0.5V, (Note 4), unless otherwise specified.
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 5, 8)
TYP
MAX
(Notes 5, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Audio Switches (L, R)
Analog Signal Range, VANALOG
VDD = 3.0V, IN = 1.4V, CTRL = 1.4V
Full
-1.5
-
1.5
V
ON Resistance, RON
VDD = 5.0V, IN = CTRL = VDD, ICOMx = 40mA, VL or
VR = -0.85V to 0.85V, (See Figure 3)
25
-
2.47
-

ON Resistance, RON
VDD = 4.2V, IN = CTRL = VDD, ICOMx = 40mA, VL or
VR = -0.85V to 0.85V, (See Figure 3)
25
-
2.50
-

ON Resistance, RON
VDD = 2.85V, IN = CTRL = VDD, ICOMx = 40mA, VL or
VR = -0.85V to 0.85V, (See Figure 3)
25
-
2.87
-

ON Resistance, RON
VDD = 3.0V, IN = 1.4V, CTRL = 1.4V, ICOMx = 40mA,
VL or VR = -0.85V to 0.85V, (See Figure 3)

RON Matching Between Channels,
RON
VDD = 3.0V, IN = 1.4V, CTRL = 1.4V, ICOMx = 40mA,
VL or VR = Voltage at max RON over signal range of
-0.85V to 0.85V, (Note 7)
RON Flatness, RFLAT(ON)
VDD = 3.0V, IN = 1.4V, CTRL = 1.4V, ICOMx = 40mA,
VL or VR = -0.85V to 0.85V, (Note 6)
Discharge Pull-Down Resistance,
RL, RR
VDD = 3.6V, IN = CTRL = 3.6V, VCOM- or
VCOM+ = -0.85V, 0.85V, VL or VR = -0.85V, 0.85V,
VD+ and VD- = floating, Measure current through the
discharge pull-down resistor and calculate resistance
value.
25
-
2.65
4.0
Full
-
-
5.5

25
-
0.02
0.33

Full
-
-
0.39

25
-
0.04
0.07

Full
-
-
0.09

25
-
50
-
k
USB Switches (D+, D-)
Analog Signal Range, VANALOG
VDD = 3.6V, IN = 0.5V, CTRL = 1.4V
Full
0
-
VDD
V
ON Resistance, RON
VDD = 5.0V, IN = 0V, CTRL = VDD, ICOMx = 1mA,
VD+ or VD- = 5V (See Figure 4)
+25
-
17.7
-

ON Resistance, RON
VDD = 4.2V, IN = 0V, CTRL = VDD, ICOMx = 1mA,
VD+ or VD- = 4.2V (See Figure 4)
+25
-
19.5
-

3
FN6556.0
September 18, 2007
ISL54212
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V, VCTRLH = 1.4V,
VCTRLL = 0.5V, (Note 4), unless otherwise specified. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 5, 8)
TYP
MAX
(Notes 5, 8) UNITS
ON Resistance, RON
VDD = 2.85V, IN = 0V, CTRL = VDD, ICOMx = 1mA,
VD+ or VD- = 2.85V (See Figure 4)
+25
-
26
-

ON Resistance, RON
VDD = 3.3V, IN = 0.5V, CTRL = 1.4V, ICOMx = 1mA,
VD+ or VD- = 3.3V (See Figure 4)
+25
-
23.5
38

Full
-
-
43

VDD = 3.6V, IN = 0.5V, CTRL = 1.4V, ICOMx = 40mA,
VD+ or VD- = 0V to 400mV (See Figure 4)
ON Resistance, RON
RON Matching Between Channels,
RON
VDD = 3.6V, IN = 0.5V, CTRL = 1.4V,
ICOMx = 40mA, VD+ or VD- = Voltage at max RONover
signal range of 0V to 400mV, (Note 7)
RON Flatness, RFLAT(ON)
VDD = 3.6V, IN = 0.5V, CTRL = 1.4V,
ICOMx = 40mA, VD+ or VD- = 0V to 400mV, (Note 6)
OFF Leakage Current, ID+(OFF) or
ID-(OFF)
VDD = 3.6V, IN = CTRL = 3.6V, VCOM- or
VCOM+ = 0.5V, 0V, VD+ or VD- = 0V, 0.5V, VL and
VR = float
ON Leakage Current, IDx
VDD = 3.3V, IN = 0.5V, CTRL = 0V or 3.3V, VD+ or
VD- = 2.0V, VCOM- ,VCOM+ , VL and VR = float
Turn-ON Time, tON
VDD = 2.7V, RL = 50, CL = 10pF, (See Figure 1)
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD
25
-
4.6
5

Full
-
-
6.5

25
-
0.06
0.5

Full
-
-
0.55

25
-
0.4
0.6

Full
-
-
1.0

25
-10
-
10
nA
Full
-70
-
70
nA
25
-10
2
10
nA
Full
-75
-
75
nA
25
-
67
-
ns
VDD = 2.7V, RL = 50, CL = 10pF, (See Figure 1)
25
-
48
-
ns
VDD = 2.7V, RL = 50, CL = 10pF, (See Figure 2)
25
-
18
-
ns
Skew, tSKEW
VDD = 3.3V, IN = 0V, CTRL = 3.3V, RL = 45,CL = 10pF,
tR = tF = 750ps at 480Mbps,
(Duty Cycle = 50%) (See Figure 7)
25
-
50
-
ps
Total Jitter, tJ
VDD = 3.3V, IN = 0V, CTRL = 3.3V, RL = 45,CL = 10pF,
tR = tF = 750ps at 480Mbps
25
-
210
-
ps
Propagation Delay, tPD
VDD = 3.3V, IN = 0V, CTRL = 3.3V, RL = 45,CL = 10pF,
See Figure 7)
25
-
250
-
ps
Crosstalk (Channel-to-Channel),
R to COM-, L to COM+
VDD = 3.3V, IN = CTRL = 3.3V, RL = 32,
f = 20Hz to 20kHz, VR or VL = 0.707VRMS (2VP-P),
(See Figure 6)
25
-
-110
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VDD = 3.0V, IN = CTRL = 3.0V, VL or
VR = 0.707VRMS (2VP-P), RL = 32
25
-
0.06
-
%
USB Switch -3dB Bandwidth
Signal = 0dBm, 0.2VDC offset, RL = 50,CL = 5pF
DYNAMIC CHARACTERISTICS
25
-
630
-
MHz
D+/D- OFF Capacitance, CD+(OFF), f = 1MHz, VDD = 3.3V, IN = CTRL = 3.3V,
CD-(OFF)
VD- or VD+ = VCOMx = 0V, (See Figure 5)
25
-
6
-
pF
L/R OFF Capacitance, CLOFF,
CROFF
f = 1MHz, VDD = 3.3V, IN = 0V, CTRL = 3.3V,
VL or VR = VCOMx = 0V, (See Figure 5)
25
-
9
-
pF
COM ON Capacitance, CCOM-(ON), f = 1MHz, VDD = 3.3V, IN = 0V, CTRL = 3.3V,
CCOM+(ON)
VD- or VD+ = VCOMx = 0V, (See Figure 5)
25
-
10
-
pF
Full
2.5
-
5.5
V
25
-
6
8
A
Full
-
-
10
A
25
-
6
-
A
POWER SUPPLY CHARACTERISTICS
Power Supply Range, VDD
Positive Supply Current, IDD
VDD = 3.6V, IN = 0V or 3.6V, CTRL = 3.6V
Positive Supply Current, IDD
VDD = 4.2V, IN = 0V or 4.2V, CTRL = 4.2V
Positive Supply Current, IDD
VDD = 5.0V, IN = 0V or 5.0V, CTRL = 5.0V
25
-
8
-
A
Positive Supply Current, IDD
(Low Power State)
VDD = 3.6V, IN = 3.6V, CTRL = 0V or float
25
-
1
7
nA
Full
-
-
140
nA
4
FN6556.0
September 18, 2007
ISL54212
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V, VCTRLH = 1.4V,
VCTRLL = 0.5V, (Note 4), unless otherwise specified. (Continued)
PARAMETER
TEMP
MIN
(°C) (Notes 5, 8)
TEST CONDITIONS
TYP
MAX
(Notes 5, 8) UNITS
DIGITAL INPUT CHARACTERISTICS
Voltage Low, VINL , VCTRLL
VDD = 2.7V to 3.6V
Full
-
-
0.5
V
Voltage High, VINH, VCTRLH
VDD = 2.7V to 3.6V
Full
1.4
-
-
V
Input Current, IINL, IINH
VDD = 3.6V, IN = 0V or 3.6V, CTRL = 0V
25
-10
2.5
10
nA
Full
-50
-
50
nA
Input Current, ICTRLL
VDD = 3.6V, IN = 0V, CTRL = 0V
25
-15
10
15
nA
Input Current, ICTRLH
VDD = 3.6V, IN = 0V, CTRL = 3.6V
CTRL Pull-Down Resistor, RCTRL
VDD = 3.6V, IN = 0V, CTRL = 3.6V
Full
-50
-
50
nA
25
-1.1
1.0
1.1
A
Full
-2
-
2
A
25
-
4
-
M
NOTES:
4. VLOGIC = Input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
7. RON matching between channels is calculated by subtracting the channel with the highest max RON value from the channel with lowest max
RON value, between L and R or between D+ and D-.
8. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested.
Test Circuits and Waveforms
VDD
LOGIC
INPUT
50%
0V
VINPUT
tOFF
SWITCH
VINPUT
INPUT
SWITCH
INPUT
C
CTRL
VOUT
AUDIO or USB
COMx
IN
VOUT
90%
SWITCH
OUTPUT
VDD
tr <20ns
tf <20ns
90%
VIN
GND
0V
RL
50
CL
10pF
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
-----------------------------V OUT = V
(INPUT) R + R
L
 ON 
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
5
FN6556.0
September 18, 2007
ISL54212
Test Circuits and Waveforms (Continued)
VDD
C
CTRL
VINPUT
VDD
LOGIC
INPUT
D- or D+
0V
SWITCH
OUTPUT
CL
10pF
RL
50
IN
GND
VIN
VOUT
VOUT
COMx
L or R
90%
0V
tD
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. BREAK-BEFORE-MAKE TIME
VDD
VDD
C
C
RON = V1/100mA
RON = V1/40mA
CTRL
CTRL
D- OR D+
L OR R
VD- OR D+
VL OR R
IN
V1
100mA
VDD
IN
V1
40mA
COMx
0V
COMx
GND
GND
Repeat test for all switches.
Repeat test for all switches.
FIGURE 3. AUDIO RON TEST CIRCUIT
6
FIGURE 4. USB RON TEST CIRCUIT
FN6556.0
September 18, 2007
ISL54212
Test Circuits and Waveforms (Continued)
VDD
VDD
C
C
CTRL
CTRL
AUDIO OR USB
SIGNAL
GENERATOR
L OR R
IN
IMPEDANCE
ANALYZER
IN
VDD
0V or
VDD
32
COMx
COMx
GND
R OR L
COMx
ANALYZER
NC
GND
RL
Repeat test for all switches.
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 5. CAPACITANCE TEST CIRCUIT
FIGURE 6. AUDIO CROSSTALK TEST CIRCUIT
VDD
tri
C
90%
DIN+
DIN-
10%
50%
CTRL
0V
tskew_i
90%
15.8
50%
10%
tfi
tro
DIN+
OUT-
10%
COM+
DIN-
15.8
OUT+
D+
143
CL
COM-
45
OUT-
DCL
143
90%
OUT+
IN
45
50%
tskew_o
50%
90%
tf0
10%
GND
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals.
|tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals.
|tskew_0| Change in Skew through the Switch for Output Signals.
|tskew_i| Change in Skew through the Switch for Input Signals.
FIGURE 7A. MEASUREMENT POINTS
FIGURE 7B. TEST CIRCUIT
FIGURE 7. SKEW TEST
7
FN6556.0
September 18, 2007
ISL54212
Application Block Diagram
VDD
µCONTROLLER
USB AND HEADPHONE JACK
VBUS
IN
ISL54212
CTRL
LOGIC CIRCUITRY
4M
D-
COM-
D+
50k
COM+
USB
HIGH-SPEED
TRANSCEIVER
L
R
CODEC
50k
GND
LOGIC CONTROL VIA MICRO-PROCESSOR
Detailed Description
The ISL54212 device is a dual single pole/double throw
(SPDT) analog switch device that can operate from a single
DC power supply in the range of 2.5V to 5.5V. It was
designed to function as a dual 2 to 1 multiplexer to select
between USB differential data signals and audio L and R
stereo signals. It comes in tiny µTQFN and TDFN packages
for use in MP3 players, PDAs, cell phones, and other
personal media players.
The part consists of two 3 audio switches and two 5 USB
switches. The audio switches can accept signals that swing
below ground. They were designed to pass audio left and
right stereo signals, that are ground referenced, with minimal
distortion. The USB switches were designed to pass
high-speed USB differential data signals with minimal edge
and phase distortion.
The ISL54212 was specifically designed for MP3 players,
cell phones and other personal media player applications
that need to combine the audio headphone jack and the
USB data connector into a single shared connector, thereby
saving space and component cost. Typical application block
diagram of this functionality is shown above.
The ISL54212 has a single logic control pin (IN) that selects
between the audio switches and the USB switches. This pin
can be driven Low or High to switch between the audio
CODEC drivers and USB transceiver of the MP3 player or
cellphone. The ISL54212 also contains a logic control pin
(CTRL) that when driven Low while IN is High, opens all
switches and puts the part into a low power state, drawing
typically 1nA of IDD current.
8
A detailed description of the two types of switches is
provided in the sections following. The USB transmission
and audio playback are intended to be mutually exclusive
operations.
Audio Switches
The two audio switches (L, R) are 3 switches that can pass
signals that swing below ground by as much as 1.5V. They
were designed to pass ground reference stereo signals with
minimal insertion loss and very low distortion. Crosstalk
between the audio switches over the audio band is < -110dB.
Over a signal range of ±1V (0.707Vrms) with VDD >2.7V,
these switches have an extremely low rON resistance
variation. They can pass ground referenced audio signals
with very low distortion (<0.06% THD+N) when delivering
15.6mW into a 32headphone speaker load. See Figures 8,
9, 10 and 11 THD+N performance curves.
These switches are uni-directional switches. The audio
drivers should be connected at the L and R side of the switch
(pin 7 and pin 8) and the speaker loads should be connected
at the COM side of the switch (pin 3 and pin 4).
The audio switches are active (turned ON) whenever the IN
voltage is 1.4V and the CTRL voltage to 1.4V.
Note: Whenever the audio switches are ON the USB
transceivers need to be in the high impedance.
USB Switches
The two USB switches (D+, D-) are bidirectional switches
that can pass rail-to-rail signals. When powered with a 3.6V
supply these switches have a nominal r(ON) of 4.6 over the
FN6556.0
September 18, 2007
ISL54212
signal range of 0V to 400mV with a r(ON) flatness of 0.4.
The r(ON) matching between the D+ and D- switches over
this signal range is only 0.06 ensuring minimal impact by
the switches to USB high speed signal transitions. As the
signal level increases the r(ON) resistance increases. At
signal level of 3.3V the switch resistance is nominally 23.
The USB switches were specifically designed to pass USB
2.0 high-speed (480Mbps) differential signals typically in the
range of 0V to 400mV. They have low capacitance and high
bandwidth to pass the USB high-speed signals with
minimum edge and phase distortion to meet USB 2.0 high
speed signal quality specifications. See the high-speed eye
diagram in Figure 15.
The USB switches can also pass USB full-speed signals
(12Mbps) with minimal distortion and meet all the USB
requirements for USB 2.0 full-speed signaling. See the
full-speed eye diagrams in Figures 12, 13 and 14.
The maximum signal range for the USB switches is from
-1.5V to VDD. The signal voltage at D- and D+ should not be
allow to exceed the VDD voltage rail or go below ground by
more than -1.5V.
The USB switches are active (turned ON) whenever the IN
voltage is 0.5V.
Note: Whenever the USB switches are ON the audio drivers
of the CODEC need to be at AC or DC ground or floating to
keep from interfering with the data transmission.
ISL54212 Operation
The sections that follow will discuss using the ISL54212 in the
typical application shown in the block diagram on page 8.
VDD SUPPLY
The DC power supply connected at VDD (pin 1) provides the
required bias voltage for proper switch operation. The part
can operate with a supply voltage in the range of 2.5V to
5.5V.
In a typical USB/Audio application for portable battery
powered devices the VDD voltage will come from a battery or
an LDO and be in the range of 2.7V to 3.6V. For best
possible USB full-speed operation (12Mbps) it is
recommended that the VDD voltage be 2.5V in order to get
a USB data signal level above 2.5V.
LOGIC CONTROL
The state of the ISL54212 device is determined by the
voltage at the IN pin (pin 2) and the CTRL pin (pin 10). Refer
to truth-table on page 2 of the data sheet. These logic pins
are 1.8V logic compatible when VDD is in the range of 2.7V
to 3.6V and can be controlled by a standard µprocessor.
9
The CTRL pin is internally pulled low through a 4Mresistor to
ground and can be tri-stated by the µprocessor. The CTRL
control pin is only active when IN is logic “1”.
The IN pin does not have an internal pull-down resistor and
must not be allowed to float. It must be driven High or Low.
Logic control voltage levels:
IN = Logic “0” (Low) when IN 0.5V
IN = Logic “1” (High) when IN 1.4V
CTRL = Logic “0” (Low) when 0.5V or floating
CTRL = Logic “1” (High) when 1.4V
Audio Mode
If the IN pin = Logic “1” and CTRL pin = Logic “1,” the part
will be in the Audio mode. In Audio mode the L (left) and R
(right) 3 audio switches are ON and the D- and D+ 5 USB
switches are OFF.
When nothing is plugged into the common connector or a
headphone is plugged into the common connector, the
µprocessor will sense that there is no voltage at the VBUS
pin of the connector and will drive and hold the IN control pin
of the ISL54212 high. As long as the CTRL = Logic “1,” the
ISL54212 part will be in the audio mode and the audio
drivers of the media player can drive the headphones and
play music.
USB Mode
If the IN pin = Logic “0” and CTRL pin = Logic “0” or Logic “1”
the part will go into USB mode. In USB mode, the D- and D+
5 switches are ON and the L and R 3 audio switches are
OFF.
When a USB cable from a computer or USB hub is
connected at the common connector, the µprocessor will
sense the presence of the 5V VBUS and drive the IN pin
voltage low. The ISL54212 part will go into the USB mode. In
USB mode, the computer or USB hub transceiver and the
MP3 player or cell phone USB transceiver are connected
and digital data will be able to be transmitted back and forth.
When the USB cable is disconnected, the processor will
sense that the 5V VBUS voltage is no longer connected and
will drive the IN pin high and put the part back into the Audio
or Low Power mode.
Low Power Mode
If the IN pin = Logic “1” and CTRL pin = Logic “0,” the part will
be in the Low Power mode. In the Low Power mode, the audio
switches and the USB switches are OFF. In this state, the
device draws typically 1nA of current.
FN6556.0
September 18, 2007
ISL54212
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
0.4
0.11
0.10
THD+N (%)
VDD = 2.6V
0.08
0.07
VDD = 2.7V
0.06
0.2
2.5VP-P
0.1
VDD = 3.6V
VDD = 3V
0.05
2VP-P
1VP-P
0
0.04
20
200
2k
FREQUENCY (Hz)
20
20k
200
2k
FREQUENCY (Hz)
20k
FIGURE 9. THD+N vs SIGNAL LEVELS vs FREQUENCY
FIGURE 8. THD+N vs SUPPLY VOLTAGE vs FREQUENCY
0.5
0.5
RLOAD = 32
FREQ = 1kHz
VDD = 3V
0.4
RLOAD = 32
FREQ = 1kHz
VDD = 3V
0.4
0.3
THD+N (%)
THD+N (%)
3VP-P
0.3
0.09
THD+N (%)
RLOAD = 32
VDD = 3V
RLOAD = 32
VLOAD = 0.707VRMS
0.2
0.3
0.2
0.1
0.1
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE (VP-P)
FIGURE 10. THD+N vs OUTPUT VOLTAGE
10
3.5
0
10
20
30
40
50
OUTPUT POWER (mW)
FIGURE 11. THD+N vs OUTPUT POWER
FN6556.0
September 18, 2007
ISL54212
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
(Continued)
VOLTAGE SCALE (0.5V/DIV)
VDD = 5.5V
TIME SCALE (10ns/DIV)
FIGURE 12. EYE PATTERN: 12MBps WITH SWITCHES IN THE SIGNAL PATH
VOLTAGE SCALE (0.5V/DIV)
VDD = 3.3V
TIME SCALE (10ns/DIV)
FIGURE 13. EYE PATTERN: 12MBps WITH SWITCHES IN THE SIGNAL PATH
11
FN6556.0
September 18, 2007
ISL54212
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
(Continued)
VOLTAGE SCALE (0.5V/DIV)
VDD = 2.5V
TIME SCALE (10ns/DIV)
FIGURE 14. EYE PATTERN: 12MBps WITH SWITCHES IN THE SIGNAL PATH
VOLTAGE SCALE (0.1V/DIV)
VDD = 3.3V
TIME SCALE (0.2ns/DIV)
FIGURE 15. EYE PATTERN: 480MBps USB SIGNAL WITH SWITCHES IN THE SIGNAL PATH
12
FN6556.0
September 18, 2007
ISL54212
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
1
Die Characteristics
USB SWITCH
0
SUBSTRATE POTENTIAL (POWERED UP):
-1
NORMALIZED GAIN (dB)
(Continued)
GND (TDFN Paddle Connection: Tie to GND or Float)
-2
TRANSISTOR COUNT:
-3
98
-4
PROCESS:
Submicron CMOS
RL = 50
VIN = 0.2VP-P to 2VP-P
1M
10M
100M
FREQUENCY (Hz)
1G
FIGURE 16. FREQUENCY RESPONSE
13
FN6556.0
September 18, 2007
ISL54212
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
6
INDEX AREA
2X
A
L10.2.1x1.6A
B
N
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
MILLIMETERS
E
SYMBOL
0.10 C
1
2X
2
0.10 C
TOP VIEW
C
A
SEATING PLANE
1
MAX
0.55
-
A1
-
-
0.05
-
0.127 REF
-
b
0.15
0.20
0.25
5
D
2.05
2.10
2.15
-
E
1.55
1.60
1.65
-
A1
SIDE VIEW
k
0.20
-
-
L
0.35
0.40
0.45
4xk
2
NX L
N
0.50 BSC
-
NX b
2
Nd
4
3
Ne
1
3
0
-
12
NOTES:
5
BOTTOM VIEW
CL
NX (b)
(A1)
L
5
e
SECTION "C-C"
TERMINAL TIP
C C
4
Rev. 3 6/06
0.10 M C A B
0.05 M C
3
(ND-1) X e
-
10

e
-
N
(DATUM B)
N-1
NOTES
0.50
e
(DATUM A)
PIN #1 ID
NOMINAL
0.45
A3
0.10 C
0.05 C
MIN
A
FOR ODD TERMINAL/SIDE
b
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. Same as JEDEC MO-255UABD except:
No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm
"L" MAX dimension = 0.45 not 0.42mm.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
2.50
1.75
0.05 MIN
L
2.00
0.80
0.275
0.10 MIN
DETAIL “A” PIN 1 ID
0.25
0.50
LAND PATTERN 10
14
FN6556.0
September 18, 2007
ISL54212
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C A
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
E
B
//
A
C
SEATING
PLANE
D2
(DATUM B)
6
INDEX
AREA
0.10 C
0.08 C
A3
SIDE VIEW
7
8
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
0.20 REF
b
0.20
0.25
0.30
1
5, 8
D
2.95
3.0
3.05
-
D2
2.25
2.30
2.35
7, 8
E
2.95
3.0
3.05
-
E2
1.45
1.50
1.55
7, 8
e
0.50 BSC
-
k
0.25
-
-
-
L
0.25
0.30
0.35
8
N
10
2
Nd
5
3
Rev. 3 3/06
NOTES:
2
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
NX k
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
E2
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10 M C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
CL
NX (b)
NOMINAL
D2/2
(DATUM A)
8
MIN
A3
6
INDEX
AREA
TOP VIEW
SYMBOL
(A1)
L1
5
9 L
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN6556.0
September 18, 2007
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