Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com Installation and Operation of Intersil’s ISL98001 Analog Front End Evaluation System ©2005, Intersil Corp. Page 1/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com Note To simplify installation and prevent unnecessary Windows messages during installation, do not connect the USB cable to the ISL98001 Evaluation Board until the software installation is complete. PC Requirements Operating System: Tested under Windows XP (service pack 2) and Windows 2000. Windows 98 and ME not currently supported. Hardware Requirements: USB Port, CD-ROM drive for install files, minimum 10MB free hard disk space. Software Installation Launch the “ISL98001 Installer.exe” file on the CD ROM and follow the instructions. The default installation will add an “Intersil” directory to the “Start Menu/Programs” tree. That directory will contain a shortcut to the ISL98001 executable and an uninstaller. The main program files will be installed in the Program Files/ISL98001 directory. The USB driver file windrvr6.sys will be placed into C:\WINDOWS\system32\drivers and ISL98001.inf will be installed under C:\WINDOWS\INF. Press “Next” to continue. ©2005, Intersil Corp. Page 2/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com By default, the installer will put the evaluation software under c:\Program Files\ISL98001 directory. To us a different directory, select the “Browse” button. Press “Next” to continue. ©2005, Intersil Corp. Page 3/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com Press “Next” to create the Intersil folder in the Start Menu. Press the “Install” button to copy all the necessary files onto the PC. ©2005, Intersil Corp. Page 4/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com Connecting the Evaluation Board After installation of the ISL98001 software, re-boot the PC if requested. Apply power to the ISL98001 Evaluation Board with the provided 5V power supply. Connect the USB cable to the ISL98001 Evaluation Board. The Microsoft windows operating system will see the ISL98001 Evaluation Board as a new device, and will try to load appropriate driver for it. Windows XP may pop up this message: If you see this box, select “Yes, now and every time I connect a device” and click on “Next”. If you elect not to select “Yes, now and every time I connect a device”, you may see this requester whenever the device is reconnected after being disconnected. ©2005, Intersil Corp. Page 5/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com The following screen will then appear: Press Next (“Install the software automatically”). The Hardware Wizard will try to locate and install the driver for the ISL98001: ©2005, Intersil Corp. Page 6/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com Click Finish to complete the installation. On XP systems, a pop-up message may display the status of the ISL98001 hardware. ©2005, Intersil Corp. Page 7/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com Hardware Setup By default, the ISL98001 Evaluation board is configured for an input video resolution of 1280x1024@60Hz on the VGA1 connector. The quickest way to verify operation is this: • Connect a monitor with a DVI input to the DVI output connector • Connect a 1280x1024@60Hz RGB video source to VGA1 • Connect the 5V power supply to the power connector At this point, the evaluation board’s FPGA will format the data from the ISL98001 and generate SXGA video timing on the DVI output connector. The incoming SXGA image should appear on the DVI monitor. Additional video modes and AFE configuration options are available using the ISL98001 evaluation software through the USB interface. ©2005, Intersil Corp. Page 8/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com Starting the Software Launch the software (default location is Start/Programs/Intersil/ISL98001). After the program has launched, you should see the following screen: Click on the “Read All Registers” button in the lower left screen. All of the register values from the ISL98001 on the evaluation board should appear as shown in the next image. If the register values are not read correctly, proceed to the Troubleshooting section of this document. ©2005, Intersil Corp. Page 9/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com To change a register value, simply change the hexadecimal number in the appropriate box. To change both digits of the 8 bit hex number, select both digits with the mouse (or double click inside the text box) , then quickly type both digits of the desired value. If you type too slowly (more than 1 second between the first and second digit), the first digit typed will become the lower nibble, and the higher nibble will be 0. To only change one nibble using the keyboard, select the high nibble or the low nibble and type the new hexadecimal value. You can also change the register values using the keyboard: • Increment by 1: Up Arrow • Decrement by 1: Down Arrow • Increment by 16 (increment high nibble by 1): Page Up • Decrement by 16 (decrement high nibble by 1): Page Up ©2005, Intersil Corp. Page 10/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com This version of the software adds “GangGain” and ‘GangOffset” checkboxes. When one or both of these boxes are checked, changing the gain (or offset) of one color will simultaneously change the gain (or offset) of the other 2 colors. There is also a “YPbPr to RGB CSC…” button. This button displays the status of a YPbPr to RGB color space converter in the evaluation board’s FPGA. Clicking on the button toggles the state. There is more information about the color space converter in the next section. Video Input Configuration The ISL98001 evaluation platform does not automatically detect the video mode of the incoming video signal. To obtain the correct image on the DVI monitor, the software needs to be told the format of the incoming video signal. This is done using the Video Mode box, which is opened by selecting “Select Input Video Mode” from the options menu. Using the drop down menu, select the resolution and refresh rate that matches the resolution and refresh rate of the video signal to be digitized. The input connector can also be selected at this time. The ISL98001 evaluation board has a YPbPr to RGB color space converter (CSC) inside the FPGA. The CSC allows YPbPr/component video signals to be displayed on TVs that expect RGB format. If you are using such a TV, checking the “Auto Enable YPbPr to RGB Color Space Converter for Comp. Inputs” will automatically turn on the CSC when using a component or composite input. ©2005, Intersil Corp. Page 11/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com Note that while there is a “composite” video connection, the ISL98001 AFE does not support composite video decoding. It will simply digitize the composite video signal through the AFE’s video channel. It is possible to take that digitized composite signal and perform digital decoding of the composite signal after it is digitized, but that is beyond the function of this evaluation system. ©2005, Intersil Corp. Page 12/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com Operation The DVI monitor should now be displaying the image being received by the AFE. At this point, all the registers of the ISL98001 can be adjusted. For example, the PLL Phase register (0x10) can be adjusted to find the optimum sampling phases for the signal. The gain control registers (0x06 – 0x08) and the offset control registers (0x09 – 0x0B) can be adjusted for contrast and brightness control. The Automatic Black Level Compensation (ABLC, register 0x17) function can be disabled to compare the image with and without ABLC Please refer to the ISL98001 datasheet for more information on the ISL98001 and its configuration options. Notes • • • • All registers can be read by pressing the “Read All Registers” button. Registers 0x00 – 0x02 are read-only. The HTOTAL value is not latched by the ISL98001 until the LSB (0x0F) is written (i.e. writes to the MSB only will not change the HTOTAL used by the ISL98001). The box at the bottom of the display can be used to read or write any register, including some production test registers. These registers are not needed in normal operation of the Analog Front End and are therefore not documented. ©2005, Intersil Corp. Page 13/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com DE Adjust If the image on the DVI monitor is clipped, the following window allows the Data Enable (DE) signal to be adjusted to change the position of the frame: ©2005, Intersil Corp. Page 14/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com Troubleshooting USB Driver Installation After rebooting the PC, please verify that the following files are in the following locations: • windrvr6.sys in C:\WINDOWS\system32\Driver • ISL98001.inf in C:\WINDOWS\INF • ISL98001.exe in C:\Program Files\ISL98001 USB Port The software should be able to communicate with the evaluation board as soon as it is launched. If there is a communication problem, the following dialog box will be displayed: • • If you see this dialog, open the Windows Control Panel. Double-click on the “System” icon and select the “Hardware” tab, then click on Device Manager: There should be a “Jungo” entry, with an ISL98001 sub category. This indicates the driver is properly installed and is communicating with the evaluation board. If this is not visible, or there are any error messages, take the following actions until the problem is resolved: • Verify that the evaluation board has power and that the USB cable is connected between the evaluation board and the PC. ©2005, Intersil Corp. Page 15/16 Ver. 1.1, 12/19/05 Intersil Corporation 1001 Murphy Ranch Rd Milpitas, CA 95035 Tel: 408-432-8888 http://www.intersil.com • • • • Power off then power on the evaluation board. You should hear 2 tones from the PC’s speakers when the USB device is enumerated. Close all instances of the ISL98001 application, reset the microcontroller (the switch is next to the USB connector), and restart the software. If none of this works, try installing the software on a different PC to verify correction operation of the evaluation board and software. Note: The ISL98001 Evaluation Board has a Vendor ID (VID) of 0x09AA and Product ID (PID) of 0x1004. If the USB connection is functioning, but no image is displayed on the DVI monitor, take the following steps: • Make sure the input video mode (resolution, refresh rate) matches the Input Video Mode selection in the software. • Close the software, reset the ISL98001, reset the microcontroller, and restart the software. • Try a different video resolution • The Sil164 DVI transmitter used in the evaluation system is compatible with most DVI input monitors. However there some monitors have non-standard DVI receiver implementations that can cause incompatibilities in the DVI link. To rule this scenario out, try a different model monitor. ©2005, Intersil Corp. Page 16/16 Ver. 1.1, 12/19/05 Vb4 6 11 18 20 29 35 4 Va Va Va Va Va Va Vbypass Vb9 9 Vbypass Vb16 16 Vbypass 7 R_IN_1 12 G_IN_1 14 19 SOG_IN_1 B_IN_1 AVdd_3.3V RED1 1 6 2 7 3 8 4 11 9 12 13 14 15 5 10 R1 22 GREEN1 0.1uF R2 75 BLUE1 RGBgnd1 5V_VGA1 C13 0.01uF C15 0.01uF C17 0.01uF C2 DDC_SDA1 HSYNC1 VSYNC1 DDC_SCL1 DDC_SDA1 (3) HSYNC1 VSYNC1 DDC_SCL1 (3) R4 75 R3 22 C3 0.1uF 10 nF R5 4.7K R151 500 C4 R6 22 VGA1-HD-15HF 0.1uF RGBgnd1 (2) R_IN_2 22 R_IN_2 (2) RGBgnd2 25 RGBgnd2 (2) G_IN_2 24 G_IN_2 HS1 26 28 33 SOG_IN_2 B_IN_2 HSYNC_IN_1 HS2 34 HSYNC_IN_2 VS1 44 VSYNC_IN_1 VS2 45 VSYNC_IN_2 3 5 8 10 15 17 21 23 27 30 36 GNDa GNDa GNDa GNDa GNDa GNDa GNDa GNDa GNDa GNDa GNDa 37 GNDx C25 Y1 HSYNCOUT 1 DATACLKB 1 1 HSOUT 1 VSYNCOUT 1 VS2 VSYNC2 1 C9 22pF SW1 KN11B Bs7 Bs6 Bs5 Bs4 Bs3 Bs2 Bs1 Bs0 C10 25 Mhz 22pF GNDx 107 106 105 104 103 102 101 100 RS0 RS1 RS2 RS3 RS4 RS5 RS6 RS7 Gp0 Gp1 Gp2 Gp3 Gp4 Gp5 Gp6 Gp7 97 96 95 94 93 92 91 90 GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7 Gs0 Gs1 Gs2 Gs3 Gs4 Gs5 Gs6 Gs7 87 86 85 84 83 82 81 80 GS0 GS1 GS2 GS3 GS4 GS5 GS6 GS7 Bp0 Bp1 Bp2 Bp3 Bp4 Bp5 Bp6 Bp7 75 74 73 72 71 70 69 68 BP0 BP1 BP2 BP3 BP4 BP5 BP6 BP7 GNDd GNDd GNDd GNDd GNDd GNDd GNDd GNDd GNDd GNDd GNDd GNDd GNDd X98001LC JP24 SCL SDA C18 4.7 uF 1 2 SCL (7) SDA (7) Test Points 4 3 RP4 RP5 RP6 RP7 RS0 RS1 RS2 RS3 GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7 RP1 1 2 3 4 RP2 1 2 3 4 RP3 1 2 3 4 RP4 1 2 3 4 RP5 1 2 3 4 RP6 1 2 3 4 RP7 1 2 3 4 RP8 GS4 1 GS5 2 GS6 3 GS7 4 GS0 GS1 GS2 GS3 BP0 BP1 BP2 BP3 BP4 BP5 BP6 BP7 BS0 BS1 BS2 BS3 BS4 BS5 BS6 BS7 RP9 1 2 3 4 RP10 1 2 3 4 RP11 1 2 3 4 RP12 1 2 3 4 RP13 1 2 VSYNCOUT 3 HSYNCOUT 4 RP14 VSOUT 1 HSOUT 2 DATACLKB 3 DATACLK4 RP_D0 8 RP_D1 7 RP_D2 6 RP_D3 5 33 Ohm RP_D4 8 RP_D5 7 RP_D6 6 RP_D7 5 33 Ohm D RP_D[7..0] RP_D[7..0] (3,5) RS_D0 8 RS_D1 7 RS_D2 6 RS_D3 5 33 Ohm RS_D4 8 RS_D5 7 RS_D6 6 RS_D7 5 33 Ohm RS_D[7..0] GP_D0 8 GP_D1 7 GP_D2 6 GP_D3 5 33 Ohm GP_D4 8 GP_D5 7 GP_D6 6 GP_D7 5 33 Ohm GS_D0 8 GS_D1 7 GS_D2 6 GS_D3 5 33 Ohm GS_D4 8 GS_D5 7 GS_D6 6 GS_D7 5 33 Ohm RS_D[7..0] (3,5) C GP_D[7..0] GP_D[7..0] (3,5) GS_D[7..0] GS_D[7..0] (3,5) BP_D0 8 BP_D1 7 BP_D2 6 BP_D3 5 33 Ohm BP_D4 8 BP_D5 7 BP_D6 6 BP_D7 5 33 Ohm B BP_D[7..0] BS_D0 8 BS_D1 7 BS_D2 6 BS_D3 5 33 Ohm BS_D4 8 BS_D5 7 BS_D6 6 BS_D7 5 33 Ohm BP_D[7..0] (3,5) BS_D[7..0] 8 7 VSYNCOUT_S 6 HSYNCOUT_S 5 33 Ohm VSOUT_S 8 HSOUT_S 7 DATACLKB_S 6 DATACLK_S 5 33 Ohm BS_D[7..0] (3,5) VSYNCOUT_S (3,5) HSYNCOUT_S (3,5) VSOUT_S (3,5) HSOUT_S (3,5) DATACLKB_S (3,5) DATACLK_S (3,5) DVdd Title ISL98001 Evaluation Board XTALCLKOUT (5) R154 4.7K Size B Date: 5 RP0 RP1 RP2 RP3 RS4 RS5 RS6 RS7 123 DVss 120 110 108 98 88 78 76 66 53 51 43 32 TP2 R21 33 Ohm 1 HSYNC2 1 RGBgnd2 1 XRESET R20 100 1 119 118 117 116 115 114 113 112 109 79 52 64 0.1uF A JL6 124 DVdd 111 99 89 77 67 65 C19 54 Rs0 Rs1 Rs2 Rs3 Rs4 Rs5 Rs6 Rs7 55 56 57 58 59 60 61 62 R19 4.7K TP13 TP14 TP15 TP16 Vx SCL 1 VSOUT DATACLK 1 1 VS1 VSYNC1 1 1 HSYNC1 1 RED1 GREEN1 1 1 HSin2 VSin2 VS2 XVdd_3.3V 38 DVdd_3.3V DVdd_3.3V BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0 gnd2 BLUE1 RGBgnd1 1 GNDx SDA 1 R155 50K TP11 TP12 50 HSin1 VSin1 VS1 49 Rin1 XTALCLKout Gin1 SADDR Bin1 48 gnd1 3 2 1 47 (2) VIDEO_CLAMP_EXT TP7 RESETb JP44 CLOCKINVin AVss (2) PLL_COAST_EXT 46 (2) VSYNC2 41 VSYNC1 B XTALout (2) HSYNC2 40 R14 680 R17 680 R16 1K R18 1K ISL98001 XTALin (2) SOG_IN_2 (2) B_IN_2 HSYNC1 0.1uF 0.1uF 13 39 From Page 2 of schematics C16 0.1uF (4) 3.3REG Vd Vd Vd Vd Vd Vd VREGin Vd R7 75 C C14 0.1uF 1 Rp0 Rp1 Rp2 Rp3 Rp4 Rp5 Rp6 Rp7 NC1 NC2 NC3 Vcoreadc 1 2 63 128 127 126 125 0.1uF Default stuffing R28,R33 VSYNCOUT HSYNCOUT VSOUT HSOUT R28 0 Ohm 42 Note: R156,R157,R158 Do not stuff C1 JP1 U1 C12 10uF TP8 1 C157 Vpll FB7 31 DVss A_GND GNDx D R158 0 Ohm TP9 C150 2 0.1uF FB6 Vcore Vcore Vcore VREGout VREGout 1 VREGout RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7 C155 122 121 FB5 DATACLKB DATACLK TP1 R157 0 Ohm 2 TP10 1 1 R156 0 Ohm 3 DATACLKB DATACLK 4 VSYNCOUT HSYNCOUT VSOUT HSOUT 5 R33 0 Ohm 2 Document Number ISL98001 Tuesday, March 29, 2005 Rev 1.0 Sheet 1 1 of 7 A (1) RGBgnd2 5V_VGA2 DDC_SDA2 HSYNC2 VSYNC2 DDC_SCL2 DDC_SDA2 (3) HSYNC2 (1) VSYNC2 (1) DDC_SCL2 (3) R11 75 U31 COMPUTER RGB R15 31 30 29 28 27 32 IN0A NC7 IN0B NC6 IN0C GNDA 1 2 3 4 5 6 IN1A NC1 IN1B NC2 IN1C GNDB 7 IN2A 9 IN2B Pr1 PR1 RCA_COM 1 R173 75 C 4 Y1 Y1 RCA_COM 3 R174 75 6 PB1 COMPONENT VIDEO 1 Note: Put 75 Ohm termination close to U31 input as possible. Shield R,G, and B inputs with ground traces. Pb1 10 11 IN2C GNDC 12 13 14 15 16 8 IN3A NC3 IN3B NC4 IN3C GND 3 R175 75 From CYPRESS mP 2 PB2 COMPS1 1 R176 75 22 OUTB 20 3 PB2 COMPONENT VIDEO 2 1 1 1 PR2 Y2 PB2 COMPS1 1 1 PB1 R10 22 OUTC 19 S0 S1 18 17 HIZ ENABLE 26 25 NC5 VSM 24 21 R178 75 (1) VSYNC2 SOG_IN_2 (1) R13 OUTC 22 B_IN_2 (1) 0.1uF C MP_S0 MP_S1 -5V EL4342 (7) MP_S1 (7) MP_S0 20K JL43 2 1 XTAL 2 2 VBLANK To X980xx Channel 2 XTALN 24 ODD/EVEN 23 MP_ODD_EVEN_FIELD (7) 3 SYNCLOCK VERTOUT 22 VSYNC2 (1) 4 PDWN HOUT 21 HSYNC2 (1) 5 SDENB BACKPORCH 20 VIDEO_CLAMP_EXT (1) 6 SCL SYNCOUT 19 7 SDA VCCD 18 8 GNDD1 GNDD2 17 9 HIN GNDA2 16 10 SYNCIN VCCA2 15 11 VERTIN VCCA1 14 12 LEVEL GNDA1 13 24-Pin QSOP A R150 C20 0.1uF (7) ISL_SDA Pb2 G_IN_2 (1) 0.1uF JP4 1 3 OUTB C8 (7) ISL_SDENB# (7) ISL_SCL (1) HSYNC2 R_IN_2 (1) 0.1uF 1 R30 RCA_COM B PLL_COAST_EXT (1) AVdd_3.3V C163 0.1uF C164 0.1uF C165 0.1uF EL4511CU A COMPS1 R29 75 1 J11 RCA_Y 2 22 500 10 nF 22pF R32 100K To X980xx Channel 2 C5 R8 OUTA C7 C24 Y2 Y2 R177 75 6 OUTA C6 R31 10K RCA_COM J10C 23 Pr2 PR2 Q1 MPS3906 J10B Y2 D U23 RCA_COM 4 VSP (7) MP_P1 (7) MP_P0 5V J10A PR2 5V 32-Pin QFN RCA_COM B PB1 Test Points R12 4.7K 2 J9C Y1 1 RED2 R9 75 BLUE2 RGBgnd2 75 J9B PR1 Y1 1 GREEN2 VGA1-HD-15HF J9A Rin2 RED2 1 6 2 7 3 8 4 11 9 12 13 14 15 5 10 D Gin2 1 Bin2 JP2 1 1 2 PR1 3 BLUE2 4 GREEN2 1 5 Title ISL98001 Evaluation Board COMPOSITE VIDEO Size B Date: 5 4 3 2 Document Number ISL98001 Tuesday, March 29, 2005 Rev 1.0 Sheet 1 2 of 7 5 4 3 2 1 D D JP13 DATACLK_S (1,5) DATACLK_S 1 2 LA_POD_0 HDR15 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 HEADER 8x2/SM HDR17 1 3 5 7 9 11 13 15 C RP_D[7..0] RP_D[7..0] (1,5) RP_D0 RP_D1 RP_D2 RP_D3 RP_D4 RP_D5 RP_D6 RP_D7 2 4 6 8 10 12 14 16 LA_POD_2 HDR18 1 3 5 7 9 11 13 15 RS_D[7..0] RS_D[7..0] (1,5) RS_D0 RS_D1 RS_D2 RS_D3 RS_D4 RS_D5 RS_D6 RS_D7 HEADER 8x2/SM 2 4 6 8 10 12 14 16 HEADER 8x2/SM HDR16 1 3 5 7 9 11 13 15 BP_D[7..0] BP_D[7..0] (1,5) BP_D0 BP_D1 BP_D2 BP_D3 BP_D4 BP_D5 BP_D6 BP_D7 2 4 6 8 10 12 14 16 5V_VGA1 C22 0.1uF BS_D[7..0] BS_D[7..0] (1,5) BS_D0 BS_D1 BS_D2 BS_D3 BS_D4 BS_D5 BS_D6 BS_D7 1 2 3 4 LA_POD_1 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 HEADER 8x2/SM HDR23 B 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 VCC WP SCL SDA R22 4.7K 8 7 6 5 R23 4.7K DDC_SCL1 DDC_SDA1 DDC_SCL1 (1) DDC_SDA1 (1) 24LC02 + SMT C EDID EEPROM 1 5V_VGA2 HEADER 8x2/SM C28 0.1uF HDR21 U3 A0 A1 A2 Gnd GP_D[7..0] GP_D[7..0] (1,5) GP_D0 GP_D1 GP_D2 GP_D3 GP_D4 GP_D5 GP_D6 GP_D7 GS_D[7..0] GS_D[7..0] (1,5) GS_D0 GS_D1 GS_D2 GS_D3 GS_D4 GS_D5 GS_D6 GS_D7 LA_POD_3 HDR22 1 3 5 7 9 11 13 15 1 2 3 4 DATACLK_S (1,5) 2 4 6 8 10 12 14 16 U4 A0 A1 A2 Gnd VCC WP SCL SDA R25 4.7K 8 7 6 5 DDC_SCL2 DDC_SDA2 24LC02 + SMT DATACLKB_S (1,5) R26 4.7K DDC_SCL2 (2) DDC_SDA2 (2) Note: Place EDID EEPROM on bottom layer EDID EEPROM 2 HSOUT_S (1,5) VSOUT_S (1,5) HSYNCOUT_S (1,5) VSYNCOUT_S (1,5) HEADER 8x2/SM B LOGIC ANALYZER HEADERS HEADER 8x2/SM A A Title ISL98001 Evaluation Board Size B Date: 5 4 3 2 Document Number ISL98001 Tuesday, March 29, 2005 Rev 1.0 Sheet 1 3 of 7 5 4 3 2 1 5V 4 1 1.2V 1.2V 1 2.5V C167 1 Red Power ON LED C187 FPGA and DVI Tx 3.3V-Regulator R163 330 R34 1.8K ADJ 2 22uF 22uF 2 R44 390 D 3.3V 2.5V 3 2 1 3.3V Vin D U30 LM1117 Vo2Vo4 LM1117 3 U29 LED0 ADJ 0.1uF 4 D1 0.1uF 2 47uF Vin 1 C33 + 10uF Vo2Vo4 0.1uF C32 C36 + C35 3.3V 1.2V 2.5V ADJ R43 240 TO220 R27 1K 2 C166 FB 2 + C34 100uF 3.3V Xilinx FPGA VccAUX and VccCORE 3.3V 2 4 VOUT TAB ADJ D7 3.3V L2 VIN 1 1 3 1 5V 0 Ohm 5V POWER U8 LM317 R42 2 2 J6 2.1mm 1POWERIN XVdd_3.3V JL31 2 FB R164 1.1K R35 1.1K C168 0.01uF C26 0.01uF 1 1 TP4 L3 C38 0.1uF 3.3V TP5 L4 JL32 AVdd_3.3V C C63 2 FB 1 1 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C40 + C39 10uF 0.1uF C41 C42 C43 C44 C45 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF For FPGA Decoupling Capacitor 2 (1) 3.3REG C64 1 C DVdd_3.3V TP6 L5 JL33 1 ADJ VOUT TAB 0.1uF 2 4 R47 240 + C49 47uF + C51 10uF C50 C52 C53 0.1uF 0.1uF C54 0.1uF C55 0.1uF C56 0.1uF C57 U32 0.1uF CY_DIN0 (5,7) CY_DIN0 C58 (5) TDO For U1 Decoupling Capacitor (5) TMS 1K (5) TCK R48 390 (5,7) CY_PROG 5V C11 100 1 D0 VCCJ 20 2 NC1 VCCO 19 3 CLK VCCINT 18 TDO 4 TDI TDO 17 TMS 5 TMS NC6 16 TCK 6 TCK NC5 15 CY_PROG 7 CF NC4 14 CY_INITB 8 OE/RESET CEO 13 9 NC2 NC3 12 CE GND 11 CY_CLK (5,7) CY_CLK B R152 R188 0.1uF 0.1uF 2 1 TO220 3.3V FB 1 VIN 2 2 3 C169 1 5V U9 LM317 1 5V (5,7) CY_INITB 0.1uF R189 100 CY_DONE (5,7) CY_DONE BOOST V+ CAP+ OSC GND LV CAP- VOUT 8 7 6 5 C23 0.1uF L1 -5V FB R190 100 3 2 1 C190 1 ICL7660S B XCF02S_VO20 TP18 2 2 10uF 1 2 3 4 1 + C189 10 + Not Stuff 1 U34 TDI (5) Xilinx FPGA FLASH ROM JP41 10uF D9 LED -5V supply for EL4342 SW3 A A Title ISL98001 Evaluation Board Size B Date: 5 4 3 2 Document Number ISL98001LC Tuesday, March 29, 2005 Rev 1.0 Sheet 1 4 of 7 5 C I/O I/O I/O I/O I/O I/O I/O I/O GP_D0 GP_D1 GP_D2 GP_D3 GP_D4 GP_D5 GP_D6 GP_D7 15 16 18 19 20 21 22 24 I/O I/O I/O I/O I/O I/O I/O I/O GS_D0 GS_D1 GS_D2 GS_D3 GS_D4 GS_D5 GS_D6 GS_D7 26 27 28 29 33 34 35 36 I/O I/O I/O I/O I/O I/O I/O I/O 37 39 40 42 43 44 45 46 I/O I/O I/O I/O I/O I/O I/O I/O 31 48 50 51 52 I/O I/O I/O DCI_61 DCI_62 100 DCI_41 101 DCI_42 103 DONE 104 CCLK SP12 SP13 CY_DONE CY_CLK I/O I/O I/O I/O I/O I/O I/O I/O 90 92 93 94 95 96 97 102 CY_DIN1 CY_DIN0 DVOB_D4 DVOB_D5 DVOB_CLK0 DVOB_CLK1 DVOB_D6 DVOB_D7 76 77 78 79 80 85 86 87 RST_DVI DVOB_VSYNC DVOB_HSYNC DVOB_BLANK DVOB_D0 DVOB_D1 DVOB_D2 DVOB_D3 I/O I/O I/O I/O I/O I/O I/O I/O 63 64 65 67 68 71 72 74 BS_D0 BS_D1 BS_D2 BS_D3 BS_D4 BS_D5 BS_D6 BS_D7 I/O I/O I/O I/O I/O I/O I/O I/O I/O_BUSY I/O_INIT_B 81 83 CY_BUSY CY_INITB I/O_CS_B I/O_RDWR_B 57 58 SP8 SP9 SP10 SP11 DCI_51 DCI_52 61 62 55 54 56 M0 M1 M2 BS_D[7..0] SP20 SP19 I/O I/O I/O 154 152 150 SP18 I/O I/O I/O I/O I/O I/O I/O I/O 149 148 147 146 144 143 141 140 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 I/O I/O I/O I/O I/O I/O I/O I/O 139 138 137 135 133 132 131 130 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 I/O I/O I/O I/O I/O I/O I/O I/O 128 126 125 124 123 122 120 119 DVOB_D23 DVOB_D22 DVOB_D21 DVOB_D20 DVOB_D19 DVOB_D18 DVOB_D17 DVOB_D16 I/O I/O I/O I/O I/O I/O I/O I/O 117 116 115 114 113 111 109 108 DVOB_D15 DVOB_D14 DVOB_D13 DVOB_D12 DVOB_D11 DVOB_D10 DVOB_D9 DVOB_D8 DCI_32 DCI_31 107 106 SP15 SP14 Vcco_22 Vcco_21 Vcco_32 Vcco_31 153 136 127 110 Vcco_42 Vcco_41 Vcco_52 Vcco_51 98 84 73 60 TCK TDO R194 100 R195 100 TDI R196 100 TMS R197 100 WR# RD# WR# (7) RD# (7) ADDR[0..15] ADDR[0..15] 4 1 3 5 2 4 6 D CY_PROG (4,7) CY_CLK (4,7) CY_DIN0 (4,7) CY_DIN1 (7) CY_INITB CY_DONE CY_BUSY (7) CY_INITB (4,7) CY_DONE (4,7) CY_BUSY (7) U20B 2.5V 1.2V Cypress USB Address Bus DVOB_D[0..23] 17 38 69 89 VCCAUX VCCAUX VCCAUX VCCAUX 121 142 173 193 VCCAUX VCCAUX VCCAUX VCCAUX 1 8 14 25 30 41 47 53 59 66 75 82 91 99 DVOB_D[0..23] (6) DVI 24bits DataBus GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCINT 70 VCCINT 88 VCCINT 174 VCCINT 192 GND GND GND GND GND GND GND GND GND GND GND GND GND GND 105 112 118 129 134 145 151 157 163 170 179 186 195 202 C XC3S400_PQ208 RST_DVI R58 0 RST_DVI_MASTER (6) DVOB_CLK0 DVOB_CLK1 DVOB_BLANK DVOB_HSYNC DVOB_VSYNC DVOB_CLK0 (6) DVOB_CLK1 (6) DVOB_BLANK (6) DVOB_HSYNC (6) DVOB_VSYNC (6) DVI DE, Clock and Sync. 3.3V (7) (7) (7) (7) (7) (7) (7) (7) SP13 SP15 SP17 SP19 SP21 SP23 SP25 SP27 B 3.3V JP5 SP1 SP3 SP5 SP7 SP9 SP11 SP13 SP15 SP17 SP19 SP21 SP23 SP25 SP27 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 SP2 SP4 SP6 SP8 SP10 SP12 SP14 SP16 SP18 SP20 SP22 SP24 SP26 SP28 SP12 SP14 SP16 SP18 SP20 SP22 SP24 SP26 SP28 (7) (7) (7) (7) (7) (7) (7) (7) (7) A Title ISL98001 Evaluation Board Size B 3 JP42 CY_PROG CY_CLK CY_DIN0 CY_DIN1 XILINX-JTAG FPGA Date: 5 10K 10K 10K M0 M1 M2 3.3V BP_D[7..0] SP3 SP4 SP5 SP6 SP7 TDI TMS TCK TDO DCI_12 DCI_11 208 160 159 158 TDI TMS TCK TDO SP22 SP21 162 161 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 175 172 171 169 168 167 166 165 I/O I/O I/O I/O I/O I/O I/O I/O SP26 SP25 SP24 SP23 191 190 189 187 185 182 178 176 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 204 203 200 199 198 197 196 194 RP_D7 RP_D6 RP_D5 RP_D4 RP_D3 RP_D2 RP_D1 RP_D0 SP27 SP28 206 205 I/O GS_D[7..0] BP_D0 BP_D1 BP_D2 BP_D3 BP_D4 BP_D5 BP_D6 BP_D7 R191R192R193 1 2 3 4 5 6 7 8 9 XC3S400_PQ208 GP_D[7..0] A 1,3) BS_D[7..0] DCI_71 DCI_72 4 5 7 9 10 11 12 13 156 155 DCI_22 DCI_21 Vcco_71 Vcco_72 Vcco_61 Vcco_62 RS_D0 RS_D1 RS_D2 RS_D3 RS_D4 RS_D5 RS_D6 RS_D7 TDI (4) TMS (4) TCK (4) TDO (4) JP39 RS_D[7..0] B (1,3) BP_D[7..0] 2 3 Vcco_11 Vcco_12 Vcco_01 Vcco_02 HSWAP_EN 164 177 188 201 6 23 32 49 SP1 SP2 207 CY_PROG CLK3/I CLK2/I CLK1/I CLK0/I 3.3V PROG_B U20A (1,3) GS_D[7..0] 3.3V 3.3V 3.3V (1,3) GP_D[7..0] DATA[0..7] (7) TDI TMS TCK TDO Cypress USB Data Bus DATACLK_S XTALCLKOUT CY_CLKOUT DATACLKB_S DATACLK_S XTALCLKOUT CY_CLKOUT DATACLKB_S (1,3) RS_D[7..0] 1 DATA[0..7] 184 183 181 180 D 2 RP_D[7..0] (1,3) RP_D[7..0] (1,3) (1) (7) (1,3) 3 HSOUT_S VSOUT_S HSYNCOUT_S VSYNCOUT_S HSOUT_S VSOUT_S HSYNCOUT_S VSYNCOUT_S M0 M1 M2 (1,3) (1,3) (1,3) (1,3) 4 2 Document Number ISL98001LC Tuesday, March 29, 2005 Rev 1.0 Sheet 5 1 of 7 5 4 3 2 1 CON1 C1 C2 C3 C4 C5 3.3V 3.3V D R63 5K R67 5K MSEN/SOUT EXT_RES 10 PD 13 15 14 9 34 35 ISEL/RST# BSEL/SCL DSEL/SDA EDGE/CHG RESERVED GND DVOB_D23 DVOB_D22 DVOB_D21 DVOB_D20 DVOB_D19 DVOB_D18 DVOB_D17 DVOB_D16 DVOB_D15 DVOB_D14 DVOB_D13 DVOB_D12 36 37 38 39 40 41 42 43 44 45 46 47 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14/SYNCO D13/MAST D12/DUAL DVOB_D11 DVOB_D10 DVOB_D9 DVOB_D8 DVOB_D7 DVOB_D6 DVOB_D5 DVOB_D4 DVOB_D3 DVOB_D2 DVOB_D1 DVOB_D0 50 51 52 53 54 55 58 59 60 61 62 63 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 4 5 2 57 56 HSYNC/SYNC1 VSYNC DE GND IDCK+ PGND1 IDCKPGND2 AGND DK1 AGND NC AGND DK3 GND C B (5) (5) (5) (5) (5) DVOB_HSYNC DVOB_VSYNC DVOB_BLANK DVOB_CLK0 DVOB_CLK1 8 7 6 R24 5K DVI_TX2DVI_TX2+ 19 TX2+ TX2- 31 30 DVI_TX2+ DVI_TX2- TX1+ TX1- 28 27 DVI_TX1+ DVI_TX1- TX0+ TX0- 25 24 DVI_TX0+ DVI_TX0- TXC+ TXC- 22 21 DVI_TXC+ DVI_TXC- AVcc AVcc 23 29 PVCC1 PVCC2 18 49 DVI_TX2+ DVI_TX2- DVI_TX1DVI_TX1+ DVI_TX1DVI_TX1+ 5V DVI_5V DVI_TX1+ DVI_TX1- FB3 1 DVOB_D[0..23] (5) DVOB_D[0..23] R64 510 U11 11 (5) RST_DVI_MASTER DVI_TX2DVI_TX2+ VCC VCC VCC 1 12 33 VREF 3 DVI_TX0+ DVI_TX0- + C91 DVI_TX010uF DVI_TX0+ DVI_TX0DVI_TX0+ 2 R60 5K DVI_TXC+ DVI_TXC- 3.3V DVI_TXC+ DVI_TXC- DVI_TXC+ DVI_TXC- AVccU11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SHELL1 A Red A Gm A Blue A HS A RTN TX2TX2+ TX2/4 Shld TX4TX4+ DDC CLK DDC DATA A VS TX1TX1+ TX1/3 Shld TX3TX3+ +5V GND HP Detect TX0TX0+ TX0/5 Shld TX5TX5+ TXC Shld TXC+ TXCSHELL2 25 D C 26 MolexPN 74320-4000 FB1 C80 1nF C81 0.1uF C82 10uF C83 1nF C84 0.1uF C85 10uF C86 0.1uF C87 0.1uF Note: DVI Differential Pairs must be matched length DVI Connector PVccU11 3.3V C88 0.1uF C89 10uF B 16 17 48 20 26 32 64 C92 0.1uF SiI164 64pinTQFP DVI Tx A A Title ISL98001 Evaluation Board Size B Date: 5 4 3 2 Document Number ISL98001LC Tuesday, March 29, 2005 Rev 1.0 Sheet 1 6 of 7 5 4 3 2 1 3.3V 3.3V TP17 R41 1 To Xilinx FPGA (5) ADDR[0..15] R179 10K ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 R40 D5 1K C173 0.1uF C174 0.1uF C175 0.1uF C176 0.1uF C177 0.1uF C178 0.1uF C179 0.1uF To Xilinx FPGA 8 9 10 11 13 14 15 16 To X98001 2wire Interface 102 103 104 44 45 46 3.3V R169 R170 4.7K 4.7K SCL RDY0/ASEL RDY1/BSEL RDY2/AOE RDY3/BOE RDY4/SLWR RDY5/SLRD CY7C64613 SCL_MP 5 SCL SDA_MP 6 SDA 19 XIN 42 NCN42 B R171 10M Y2 12Mhz C181 22 pF 43 NCN43 XOUT 20 XOUT 2 51 EA 38 XCLKSEL 3.3V C182 22 pF 1 JL40 R172 10K 98 66 65 48 25 26 27 28 29 30 31 32 PB0/D0/GDA0 PB1/D1/GDA1 PB2/D2/GDA2 PB3/D3/GDA3 PB4/D4/GDA4 PB5/D5/GDA5 PB6/D6/GDA6 PB7/D7/GDA7 79 80 81 82 83 84 85 86 SW2 C183 69 RESET# 3.3V 18 AVCC SW PUSHBUTTON 0.1uF 21 C184 USBD+ USBDR167 1.5K USB_5V USBDN 5V+ D+ SHELL DGND 2 4 3.3V USB_CONNECTOR R200 To ISL59443IL 3.3V A0 A1 A2 Gnd 8 7 6 5 VCC WP SCL SDA C SCL_MP SDA_MP 24LC01 + SMT RxD0 TxD0 PD0/GDB0/BFI0 PD1/GDB1/BFI1 PD2/GDB2/BFI2 PD3/GDB3/BFI3 PD4/GDB4/BFI4 PD5/GDB5/BFI5 PD6/GDB6/BFI6 PD7/GDB7/BFI7 56 57 58 59 60 61 63 64 ISL_SDENB# ISL_SCL ISL_SDA CY_PROG CY_CLK CY_DIN0 PE0/ADR0 PE1/ADR1 PE2/ADR2 PE3/ADR3 PE4/ADR4 PE5/CTL3 PE6/CTL4 PE7/CTL5 88 89 90 91 92 93 94 95 CY_DONE CY_BUSY CY_DIN1 ADR5 24 3.3V SP24 SP25 SP26 SP27 USB Device IDs R198 R186 R187 (5) 10K 10K 10K (5) (5) (5) RP15 CY_INITB CY_PROG ISL_SDA ISL_SCL WR# (5) RD# (5) LED4 LED5 LED6 10K U33 1 2 3 4 CY_INITB C188 0.1uF 5 R185 10K MP_P0 (2) MP_P1 (2) 110 111 112 113 123 124 125 126 CTL0/AINFLAG CTL1/BINFLAG CTL2/AOFLAG 1 3 USBDP R166 24 R168 24 MP_S0 (2) MP_S1 (2) R184 10K PC0/RxD0/RDY0 PC1/TxD0/RDY1 PC2/INT0# PC3/INT1#/RDY3 PC4/T0/CTL1 PC5/T1/CTL3 PC6/WR#/CTL4 PC7/RD#/CTL5 XCLK RESET# D USBCON ISL_SDENB# (2) ISL_SCL (2) ISL_SDA (2) CY_PROG (4,5) CY_CLK (4,5) CY_DIN0 (4,5) 8 7 6 5 3.3V 4.7K 3.3V C30 0.1uF CY_INITB (4,5) CY_DONE (4,5) CY_BUSY (5) CY_DIN1 (5) SP28 (5) 1 2 3 4 To ISL59443IL To Xilinx FPGA for Configuration RAM U5 1 2 3 4 B A0 A1 A2 Gnd VCC WP SCL SDA 8 7 6 5 SCL_MP SDA_MP 24LC128 + SMT MP_ODD_EVEN_FIELD (2) Default Mode EEPROM 101 96 97 3.3V JP3 GND GND RSV22 GND GND RSV37 RSV39 GND GND GND RSV49 RSV50 RSV53 RSV54 GND GND RSV70 RSV71 GND GND RSV76 RSV77 GND GND RSV73 RSV74 GND XIN AGND SDA 3 12 22 23 35 37 39 40 47 52 49 50 53 54 62 67 70 71 72 78 76 77 87 99 73 74 119 R54 0 Ohm R53 0 Ohm R182 10K 7 USBD+ USBDDISCON# PA0/T0OUT PA1/T1OUT PA2/OE# PA3/CS# PA4/FWR# PA5/FRD# PA6/RxD0OUT PA7/RxD1OUT JP25 3 2 1 R181 10K LED0 Status LED 41 33 34 D0 D1 D2 D3 D4 D5 D6 D7 DATA[0..7] (5) DATA[0..7] WAKEUP# C180 0.1uF DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 C VCC VCC VCC VCC VCC VCC VCC VCC BKPT 4 17 36 55 68 75 100 109 LED0 R180 10K PSEN# 3.3V A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 3.3V 1K LED5 3.3V CLKOUT 2 1 128 127 122 121 120 118 117 116 115 114 108 107 106 105 U28 (1) D6 LED6 D (1) CY_CLKOUT (5) ADDR[0..15] D4 RxD0 TxD0 3 2 1 R39 1K LED4 CY7C64613_S128 0.1uF LED0 Status LED CYPRESS USB mP A A Title ISL98001 Evaluation Board Size B Date: 5 4 3 2 Document Number ISL98001LC Tuesday, March 29, 2005 Rev 1.0 Sheet 1 7 of 7