DATASHEET

EL4340, EL4342
®
Data Sheet
October 18, 2010
FN7421.3
500MHz Triple, Multiplexing Amplifiers
Features
The EL4340, EL4342 are fixed unity gain mux amps
featuring high slew rates and excellent bandwidth for video
switching. These devices feature a high impedance output
state (HIZ) that enables the outputs of multiple devices to be
wired together. A power-down mode (ENABLE) is included
to turn off un-needed circuitry in power sensitive
applications. The ENABLE pin, when pulled high, sets the
EL4340, EL4342 into standby power mode - consuming just
18mW. An added feature in the EL4340 is a latch enable
function (LE) that allows independent logic control using a
common logic bus.
• Triple 2:1 and 4:1 multiplexers for RGB
Ordering Information
• Typical supply currents 10mA/ch (EL4340) and 15.3mA/ch
(EL4342)
PART
NUMBER
(Notes 1, 2, 3)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
EL4340IUZ
EL4340IUZ 24 Ld QSOP
MDP0040
EL4342ILZA
4342ILZ
L32.5x6A
EL4340IUZ-EVAL
Evaluation Board
EL4342ILZA-EVAL
Evaluation Board
32 Ld 5x6 QFN
• Internally set gain-of-1
• High speed three-state outputs (HIZ)
• Power-down mode (ENABLE)
• Latch enable (EL4340)
• ±5V operation
• ±870 V/µs slew rate
• 500MHz bandwidth
• Pb-free (RoHS compliant)
Applications
• HDTV/DTV analog inputs
• Video projectors
• Computer monitors
• Set-top boxes
NOTES:
1. Add “-T13” or “-T7” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device
information page for EL4340, EL4342. For more information on
MSL please see techbrief TB363.
• Security video
• Broadcast video equipment
TABLE 1. CHANNEL SELECT LOGIC TABLE EL4340
S0
ENABLE
HIZ
LE
OUTPUT
0
0
0
0
INO (A, B, C)
1
0
0
0
IN1 (A, B, C)
X
1
X
X
Power-down
X
0
1
X
High Z
X
0
0
1
Last S0 State
Preserved
Related Literature
• AN1182, EL4340EVAL1 Evaluation Board User's Guide
• AN1193, ISL59445/EL4342E1 Evaluation Board User's
Guide
1
TABLE 2. CHANNEL SELECT LOGIC TABLE EL4342
S1
S0
ENABLE
HIZ
OUTPUT
0
0
0
0
IN0 (A, B, C)
0
1
0
0
IN1 (A, B, C)
1
0
0
0
IN2 (A, B, C)
1
1
0
0
IN3 (A, B, C)
X
X
1
X
Power-down
X
X
0
1
High Z
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005, 2006, 2010. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL4340, EL4342
Pinouts
EL4340
(24 LD QSOP)
TOP VIEW
IN0B
3
22 ENABLE
NIC
4
21 HIZ
GND B
5
IN0C
6
19 V+
NIC
7
18 OUTB
IN1A
8
NIC
9
26 HIZ
23 LE
27 IN0C
2
28 NIC
GND A
29 IN0B
24 NIC
30 NIC
1
31 IN0A
IN0A
32 GND A
EL4342
(32 LD QFN)
TOP VIEW
IN1A 1
25 ENABLE
NIC 2
24 NIC
IN1B 3
AV=1
AV=1
20 OUTA
22 OUTA
NIC 4
21 V-
IN1C 5
AV=1
GND B 6
THERMAL
PAD
17 OUTC
IN2A 7
AV=1
20 OUTB
19 OUTC
16 VAV=1
IN1B 10
NIC 8
AV=1
15 NIC
LATCHED ON HIGH LE
IN3C 16
NIC 15
IN3B 14
NIC 13
13 NIC
IN3A 12
IN1C 12
18 S0
17 S1
IN2C 10
14 S0
GND C 11
IN2B 9
GND C 11
THERMAL PAD INTERNALLY CONNECTED TO V-.
PAD MUST BE TIED TO VNIC = NO INTERNAL CONNECTION
NIC = NO INTERNAL CONNECTION
Functional Diagram EL4340
Functional Diagram EL4342
EN0
S0
EN0
DECODE
LE
23 V+
EN1
DL Q
C
IN0(A, B, C)
IN1(A, B, C)
DL Q
C
S0
EN1 IN0(A, B, C)
OUT
S1
AMPLIFIER BIAS
DECODE
IN1(A, B, C)
EN2
EN3
HIZ
OUT
IN2(A, B, C)
IN3(A, B, C)
AMPLIFIER BIAS
ENABLE
HIZ
A LOGIC HIGH ON LE WILL LATCH THE LAST S0 STATE.
THIS LOGIC STATE IS PRESERVED WHEN CYCLING HIZ
OR ENABLE FUNCTIONS.
2
ENABLE
FN7421.3
October 18, 2010
EL4340, EL4342
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Digital & Analog Input Current (Note 6) . . . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Resistance (Typical)
θJA (°C/W)θJC (°C/W)
32 Ld QFN Package (Notes 4, 5). . . . .
24 Ld QSOP Package (Note 4) . . . . . .
35
88
1.3 to 8
N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, Input Video = 1VP-P and RL = 500Ω to GND, CL = 5pF unless
otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
26
30
34
mA
39
46
50
mA
-32
-30
-24
mA
-48
-46
-36.5
mA
GENERAL
+IS Enabled
Enabled Supply Current (EL4340)
No load, VIN = 0V, Enable Low
Enabled Supply Current (EL4342)
-IS Enabled
Enabled Supply Current (EL4340)
No load, VIN = 0V, Enable Low
Enabled Supply Current (EL4342)
+IS Disabled
Disabled Supply Current (EL4340)
No load, VIN = 0V, Enable High
2.3
2.8
3.3
mA
Disabled Supply Current (EL4342)
No load, VIN = 0V, Enable High
3
3.5
4
mA
Disabled Supply Current
No load, VIN = 0V, Enable High
10
100
µA
VOUT
Positive and Negative Output Swing
VIN = ±3.5V, RL = 500Ω
±3.1
±3.4
V
IOUT
Output Current
RL = 10Ω to GND
±80
±135
mA
VOS
Output Offset Voltage (EL4340)
-15
7
VOS
Output Offset Voltage (EL4342)
-10
-IS Disabled
Ib
+10
mV
-3
µA
VIN = 0V
ROUT
HIZ Output Resistance
HIZ = Logic High
1.4
MΩ
ROUT
Enabled Output Resistance
HIZ = Logic Low
0.2
Ω
Input Resistance
VIN = ±3.5V
10
MΩ
Voltage Gain
VIN = ±1.5V, RL= 500Ω
Output Current in Three-state
VOUT = 0V
ACL or AV
ITRI
-2
mV
Input Bias Current
RIN
-1
+15
0.98
0.99
1.02
V/V
8
15
22
µA
LOGIC
VIH
Input High Voltage (Logic Inputs)
VIL
Input Low Voltage (Logic Inputs)
IIH
Input High Current (Logic Inputs)
VH = 5V
IIL
Input Low Current (Logic Inputs)
VL = 0V
3
2
215
V
0.8
V
270
320
µA
2
3
µA
FN7421.3
October 18, 2010
EL4340, EL4342
Electrical Specifications
PARAMETER
V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, Input Video = 1VP-P and RL = 500Ω to GND, CL = 5pF unless
otherwise specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC GENERAL
tS
0.1% Settling Time
Step = 1V
10
ns
PSRR (EL4340) Power Supply Rejection Ratio
DC, PSRR V+ and V- combined
52
72
dB
PSRR (EL4342) Power Supply Rejection Ratio
DC, PSRR V+ and V- combined
52
56
dB
75
dB
ISO
Channel Isolation
f = 10MHz, Ch-Ch X-Talk and Off-Isolation,
CL = 1.5pF
dG
Differential Gain Error
NTC-7, RL = 150, CL = 1.5pF
0.02
%
dP
Differential Phase Error
NTC-7, RL = 150, CL = 1.5pF
0.02
°
BW
-3dB Bandwidth
CL = 1.5pF
500
MHz
FBW
0.1dB Bandwidth
CL = 1.5pF
60
MHz
0.1dB Bandwidth
CL = 4.7pF
120
MHz
Slew Rate
25% to 75%, RL = 150Ω, Input Enabled,
CL = 1.5pF
±870
V/µs
SR
SWITCHING CHARACTERISTICS
Channel-to-Channel Switching Glitch
VIN = 0V, CL = 1.5pF
40
mVP-P
Enable Switching Glitch
VIN = 0V CL = 1.5pF
300
mVP-P
HIZ Switching Glitch
VIN = 0V CL = 1.5pF
200
mVP-P
Channel-to-Channel Switching Glitch
VIN = 0V CL = 1.5pF
20
mVP-P
Enable Switching Glitch
VIN = 0V CL = 1.5pF
200
mVP-P
HIZ Switching Glitch
VIN = 0V CL = 1.5pF
200
mVP-P
tSW-L-H
Channel Switching Time Low to High
1.2V logic threshold to 10% movement of
analog output
18
ns
tSW-H-L
Channel Switching Time High to Low
1.2V logic threshold to 10% movement of
analog output
20
ns
tr, tf
Rise and Fall Time
10% to 90%
1.1
ns
tpd
Propagation Delay
10% to 10%
0.9
ns
tLH
Latch Enable Hold time (EL4340 only)
LE = 0
10
ns
VGLITCH
EL4340
VGLITCH
EL4342
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
SOURCE POWER = -20dBm
NORMALIZED GAIN (dB)
8
5
4
CL = 16.5pF
6
CL = 11.5pF
4
CL = 7.3pF
CL = 6.2pF
2
0
-2
CL = 4.7pF
-4
CL = 2.2pF
-6
CL INCLUDES 1.5pF
BOARD CAPACITANCE
-8
-10
1
10
CL = 1.5pF
100
SOURCE POWER = -20dBm
3
NORMALIZED GAIN (dB)
10
1k
2
1
0
-1
RL = 100Ω
RL = 150Ω
-2
-3
RL = 500Ω
-4
-5
RL = 1kΩ
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 1. GAIN vs FREQUENCY VS CL
FIGURE 2. GAIN vs FREQUENCY VS RL
4
FN7421.3
October 18, 2010
EL4340, EL4342
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
NORMALIZED GAIN (dB)
0.1
100
SOURCE POWER = -20dBm
CL = 4.7pF
0.0
OUTPUT RESISTANCE (Ω)
0.2
-0.1
-0.2
CL = 1.5pF
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
1
1
0.1
0.1
1k
10
100
FREQUENCY (MHz)
10
10
100
1k
FIGURE 4. ROUT vs FREQUENCY
0.8
0.8
RL = 500Ω
CL = 1.5pF
0.6
0.4
0.2
0
-0.2
-0.4
RL = 500Ω
CL = 1.5pF
0.6
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1
FREQUENCY (MHz)
FIGURE 3. 0.1DB GAIN vs FREQUENCY
-0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-0.8
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 6. EL4342 TRANSIENT RESPONSE
FIGURE 5. EL4340 TRANSIENT RESPONSE
0
0
-10
-10
INPUT X TO OUTPUT Y
CROSSTALK
-20
-30
-30
-40
-40
-50
OFF ISOLATION
INPUT X TO OUTPUT X
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
0.1
1
10
100
FREQUENCY (MHz)
FIGURE 7. EL4340 CROSSTALK AND OFF-ISOLATION
5
INPUT X TO OUTPUT Y
CROSSTALK
-20
(dB)
(dB)
(Continued)
1k
-100
0.1
OFF ISOLATION
INPUT X TO OUTPUT X
1
10
100
1k
FREQUENCY (MHz)
FIGURE 8. EL4342 CROSSTALK AND OFF-ISOLATION
FN7421.3
October 18, 2010
EL4340, EL4342
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
20
20
PSRR (V+)
10
0
0
-10
-10
-20
PSRR (V-)
-30
-40
-50
PSRR (V+)
-20
PSRR (dB)
PSRR (dB)
10
PSRR (V-)
-30
-40
-50
-60
-60
-70
-70
-80
0.3
-80
0.3
1
10
1k
100
1k
FREQUENCY (MHz)
FIGURE 10. EL4342 PSRR CHANNELS A, B, C
VIN = 0V
VIN = 1V
1V/DIV
S0, S1
50Ω
TERM.
0
0
VOUT A, B, C
0
VOUT A, B, C
20ns/DIV
20ns/DIV
FIGURE 11. CHANNEL TO CHANNEL SWITCHING GLITCH
VIN = 0V
ENABLE
50Ω
TERM.
FIGURE 12. CHANNEL TO CHANNEL TRANSIENT RESPONSE
VIN = 1V
VIN = 0V
ENABLE
0
VIN = 1V
50Ω
TERM.
1V/DIV
1V/DIV
10
FIGURE 9. EL4340 PSRR CHANNELS A, B, C
0.5V/DIV
20mV/DIV
1
FREQUENCY (MHz)
S0, S1
50Ω
TERM.
1V/DIV
100
0
0
VOUT A, B, C
1V/DIV
100mV/DIV
(Continued)
0
20ns/DIV
FIGURE 13. ENABLE SWITCHING GLITCH VIN = 0V
6
0
VOUT A, B, C
20ns/DIV
FIGURE 14. ENABLE TRANSIENT RESPONSE VIN = 1V
FN7421.3
October 18, 2010
EL4340, EL4342
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
HIZ
HIZ
VIN = 0V
VIN = 1V
50Ω
TERM.
1V/DIV
1V/DIV
50Ω
TERM.
0
1V/DIV
0
200mv/DIV
(Continued)
0
VOUT A, B, C
VOUT A, B, C
0
10ns/DIV
10ns/DIV
FIGURE 15. HIZ SWITCHING GLITCH VIN = 0V
FIGURE 16. HIZ TRANSIENT RESPONSE VIN = 1V
60
3.0
POWER DISSIPATION (W)
VOLTAGE NOISE (nV/√HZ)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD-QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
50
40
30
20
10
0
100
1k
10k
2.5
2.857W
QFN32
QJA = 35°C/W
2.0
1.5
1.136W
1.0
QSOP24
QJA = 88°C/W
0.5
0
0
100k
FREQUENCY (Hz)
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 17. INPUT NOISE vs FREQUENCY (OUTPUT A, B, C)
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
POWER DISSIPATION (W)
1.2
1.0
870mW
0.8
0.6
0.4
QSOP24
θJA = 115°C/W
758mW
QFN32
θJA = 125°C/W
0.2
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 19. PACKAGE POWER DISSIPATION VS AMBIENT TEMPERATURE
7
FN7421.3
October 18, 2010
EL4340, EL4342
Pin Descriptions
EL4342
(32 LD QFN)
EL4340
(24 LD QSOP)
PIN
NAME
EQUIVALENT
CIRCUIT
1
8
IN1A
Circuit 1
2, 4, 8, 13, 15,
24, 28, 30
4, 7, 9, 13, 15,
24
NIC
3
10
IN1B
Circuit 1
Channel 1 input for output amplifier "B"
5
12
IN1C
Circuit 1
Channel 1 input for output amplifier "C"
6
5
GNDB
Circuit 4
Ground pin for output amplifier “B”
7
NA
IN2A
Circuit 1
Channel 2 input for output amplifier "A"
DESCRIPTION
Channel 1 input for output amplifier "A"
Not Internally Connected; it is recommended these pins be tied to ground to
minimize crosstalk.
9
NA
IN2B
Circuit 1
Channel 2 input for output amplifier "B"
10
NA
IN2C
Circuit 1
Channel 2 input for output amplifier "C"
11
11
GNDC
Circuit 4
Ground pin for output amplifier “C”
12
NA
IN3A
Circuit 1
Channel 3 input for output amplifier "A"
14
NA
IN3B
Circuit 1
Channel 3 input for output amplifier "B"
16
NA
IN3C
Circuit 1
Channel 3 input for output amplifier "C"
17
NA
S1
Circuit 2
Channel selection pin MSB (binary logic code)
18
14
S0
Circuit 2
Channel selection pin. LSB (binary logic code)
19
17
OUTC
Circuit 3
Output of amplifier “C”
20
18
OUTB
Circuit 3
Output of amplifier “B”
21
16
V-
Circuit 4
NegativPine power supply
22
20
OUTA
Circuit 3
Output of amplifier “A”
23
19
V+
Circuit 4
Positive power supply
25
22
ENABLE
Circuit 2
Device enable (active low). Internal pull-down resistor ensures the device will be
active with no connection to this pin. A logic High on this pin puts device into powerdown mode. In power-down mode only logic circuitry is active. All logic states are
preserved post power-down. This state is not recommended for logic control where
more than one MUX-amp share the same video output line.
-
23
LE
Circuit 2
Device latch enable on the EL4340. A logic high on LE will latch the last (S0, S1)
logic state. HIZ and ENABLE functions are not latched with the LE pin.
26
21
HIZ
Circuit 2
Output disable (active high). Internal pull-down resistor ensures the device will be
active with no connection to this pin. A logic high, puts the outputs in a high
impedance state. Use this state to control logic when more than one MUX-amp
share the same video output line.
27
6
IN0C
Circuit 1
Channel 0 for output amplifier "C"
29
3
IN0B
Circuit 1
Channel 0 for output amplifier "B"
31
1
IN0A
Circuit 1
Channel 0 for output amplifier "A"
32
2
GNDA
Circuit 4
Ground pin for output amplifier “A”
V+
V+
IN
LOGIC
+
1.2V
33k
V-
GNDC
VCIRCUIT 3
CIRCUIT 2
V+
GNDB
OUT
GND
V-
CIRCUIT 1
GNDA
V+
21k
THERMAL HEAT SINK PAD
CAPACITIVELY
COUPLED
ESD CLAMP
~1MΩ
VSUBSTRATE
VCIRCUIT 4
8
FN7421.3
October 18, 2010
EL4340, EL4342
split between the PCB capacitance and an external load
capacitor.
AC Test Circuits
EL4340, EL4342
Ground Connections
VIN
CL
5 PF
50Ω
OR
75Ω
For the best isolation and crosstalk rejection, all GND pins
and NIC pins must connect to the GND plane.
RL
500Ω
Control Signals
S0, S1, ENABLE, LE, HIZ - These are binary coded,
TTL/CMOS compatible control inputs. The S0, S1 pins select
the inputs. All three amplifiers are switched simultaneously
from their respective inputs. The ENABLE, LE, HIZ pins are
used to disable the part to save power, latch in the last logic
state and three-state the output amplifiers, respectively. For
control signal rise and fall times less than 10ns the use of
termination resistors close to the part will minimize transients
coupled to the output.
FIGURE 20A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
EL4340, EL4342
VIN
TEST
EQUIPMENT
RS
475Ω
CL
5 PF
50Ω
OR
75Ω
50Ω
OR
75Ω
50Ω
OR
75Ω
FIGURE 20B. TEST CIRCUIT FOR MEASURING WITH 50Ω OR
75Ω INPUT TERMINATED EQUIPMENT
EL4340, EL4342
VIN
The ESD protection circuits use internal diodes from all pins
the V+ and V- supplies. In addition, a dV/dT- triggered clamp
is connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the Pin Description
table. The dV/dT triggered clamp imposes a maximum
supply turn-on slew rate of 1V/µs. Damaging currents can
flow for power supply rates-of-rise in excess of 1V/µs, such
as during hot plugging. Under these conditions, additional
methods should be employed to ensure the rate of rise is not
exceeded.
TEST
EQUIPMENT
RS
50Ω OR 75Ω
CL
5pF
50Ω
OR
75Ω
Power-up Considerations
50Ω
OR
75Ω
FIGURE 20C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE
APPLICATION. BANDWIDTH AND LINEARITY
FOR RL LESS THAN 500Ω WILL BE DEGRADED.
FIGURE 20. TEST CIRCUITS
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic
input pins. Schottky diodes (Motorola MBR0550T or
equivalent) connected from V+ to ground and V- to ground
(Figure 21) will shunt damaging currents away from the
internal V+ and V- ESD diodes in the event that the V+
supply is applied to the device before the V- supply.
Figure 20A illustrates the optimum output load for testing AC
performance. Figure 20B illustrates the optimun output load
when connecting to 50Ω input terminated equipment.
Application Information
General
The EL4340, EL4342 triple 2:1 and 4:1 MUX amps are ideal
as the matrix element of high performance switchers and
routers. Key features include buffered high impedance
analog inputs and excellent AC performance at output loads
down to 150Ω for video cable-driving. The unity-gain current
feedback output amplifiers are stable operating into
capacitive loads and bandwidth is optimized with a load of
5pF in parallel with a 500Ω. Total output capacitance can be
V+ SUPPLY
SCHOTTKY
PROTECTION
LOGIC
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through
the ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and
analog inputs is needed to prevent damage during the time
the voltages on these inputs are more positive than V+.
V+
LOGIC
CONTROL
S0
POWER
GND
GND
SIGNAL
IN0
EXTERNAL
CIRCUITS
V+
V-
V+
V+
OUT
V+
V-
DE-COUPLING
CAPS
IN1
VV-
V-
V- SUPPLY
FIGURE 21. SCHOTTKY PROTECTION CIRCUIT
9
FN7421.3
October 18, 2010
EL4340, EL4342
HIZ State
An internal pull-down resistor ensures the device will be
active with no connection to the HIZ pin. The HIZ state is
established within approximately 15ns (Figure 16) by placing
a logic high (>2V) on the HIZ pin. If the HIZ state is selected,
the output is a high impedance 1.4MΩ with approximately
1.5pF in parallel with a 10µA bias current from the output.
Use this state when more than one mux shares a common
output.
In the HIZ state the output is three-stated, and maintains its
high Z even in the presence of high slew rates. The supply
current during this state is same as the active state.
ENABLE and Power-down States
The enable pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
ENABLE pin. The Power-down state is established within
approximately 80ns (Figure 14), if a logic high (>2V) is
placed on the ENABLE pin. In the Power-down state, the
output has no leakage but has a large variable capacitance
(on the order of 15pF), and is capable of being back-driven.
Under this condition, large incoming slew rates can cause
fault currents of tens of mA. Do not use this state as a high
impedance output when several MUX amps share the
same output line.
LE State
The EL4340 is equipped with a Latch Enable pin. A logic
high (>2V) on the LE pin latches the last logic state. This
logic state is preserved when cycling HIZ or ENABLE
functions.
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than
50mA. Adequate thermal heat sinking of the parts is also
required.
Application Example
Figure 22 illustrates the use of the EL4342, two ISL84517
SPST switches and one NC7ST00P5X NAND gate to mux 3
different component video signals and one RGB video
signal. The SPDT switches provide the sync signal for the
RGB video and disconnects the sync signal for the
component signal.
PC Board Layout
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
10
sharp corners, use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
degraded for traces greater than one inch, unless strip line
are used.
• Match channel-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• Maximize use of AC de-coupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e.
no split planes or PCB gaps under these lines). Avoid vias
in the signal I/O lines.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
• Minimum of 2 power supply de-coupling capacitors are
recommended (1000pF, 0.01µF) as close to the devices
as possible - Avoid vias between the cap and the device
because vias add unwanted inductance. Larger caps can
be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
• The NIC pins are placed on both sides of the input pins.
These pins are not internally connected to the die. It is
recommended these pins be tied to ground to minimize
crosstalk.
The QFN Package Requires Additional PCB Layout
Rules for the Thermal Pad
The thermal pad is electrically connected to V- supply
through the high resistance IC substrate. Its primary function
is to provide heat sinking for the IC. However, because of the
connection to the V- supply through the substrate, the
thermal pad must be tied to the V- supply to prevent
unwanted current flow to the thermal pad. Do not tie this pin
to GND as this could result in large back biased currents
flowing between GND and V-. The EL4342 uses the package
with pad dimensions of D2 = 2.48mm and E2 = 3.4mm.
Maximum AC performance is achieved if the thermal pad is
attached to a dedicated de-coupled layer in a multi-layered
PC board. In cases where a dedicated layer is not possible,
AC performance may be reduced at upper frequencies.
The thermal pad requirements are proportional to power
dissipation and ambient temperature. A dedicated layer
eliminates the need for individual thermal pad area. When a
dedicated layer is not possible a 1” x 1” pad area is sufficient
for the EL4342 that is dissipating 0.5W in +50°C ambient.
Pad area requirements should be evaluated on a case by
case basis.
FN7421.3
October 18, 2010
5V
OPTIONAL SCHOTTKY PROTECTION
Y1
Y2
31
Y3
7
R
12
1
11
Pb1
29
Pb2
3
Pb3
G
9
14
Pr1
27
Pr2
5
Pr3
10
16
B
R3
75Ω
R2
75Ω
R5
75Ω
R4
75Ω
R7
75Ω
R9
75Ω
R6
75Ω
IN2A
IN3A
23
1nF
1nF
21
VOUTA
22
OUTB
20
OUTC 19
INOB
IN1B
GNDA
32
IN2B
GNDB
6
IN3B
GNDC
11
NIC
2
NIC
NIC
4
8
NIC
13
NIC
15
NIC
24
NIC
28
NIC
30
HIZ
26
ENABLE
25
S0
18
INOC
IN1C
IN2C
IN3C
R11
75Ω
R10
75Ω
R8
75Ω
V+
R12
75Ω
QFN
R16
500Ω
S1 17
5V 0.1µF
ISL84517IH-T
H SYNC
1
V+
COM
V5V 0.1µF
ISL84517IH-T
V SYNC
1
COM
SOT-23
IN
4
V+
0.1µF
-5V
SOT-23
IN
4
5
1nF
1nF
NC
5
1nF
0.1µF
-5V
1nF
3
2
5V
0.1µF
NC7ST00P5X
V- 3
5V 5
NC 2
1
INPUT
FN7421.3
October 18, 2010
4
OUT
3
GND
-5V
1nF
INPUT 2
SC70
LOGIC INPUTS
FIGURE 22. APPLICATION SHOWING THREE YPBPR CHANNELS AND ONE RGB+HV CHANNEL
R18
500Ω
R17
500Ω
EL4340, EL4342
R1
75Ω
EL4342IL
INOA
IN1A
0.1µF 0.1µF
EL4340, EL4342
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L32.5x6A (One of 10 Packages in MDP0046)
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220)
A
MILLIMETERS
D
N
(N-1)
(N-2)
B
1
2
3
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
0.00
0.02
0.05
-
D
PIN #1
I.D. MARK
E
5.00 BSC
-
D2
2.48 REF
-
E
6.00 BSC
-
E2
(N/2)
2X
0.075 C
2X
0.075 C
0.45
b
0.17
-
0.50
0.55
-
0.22
0.27
-
c
0.20 REF
b
L
-
e
0.50 BSC
-
N
32 REF
4
ND
7 REF
6
NE
9 REF
5
0.10 M C A B
Rev 1 2/09
NOTES:
(N-2)
(N-1)
N
N LEADS
TOP VIEW
3.40 REF
L
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
PIN #1 I.D.
2. Tiebar view shown is a non-functional feature.
3
1
2
3
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
(E2)
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
(N/2)
NE 5
7. Inward end of terminal may be square or circular in shape with
radius (b/2) as shown.
7
(D2)
BOTTOM VIEW
0.10 C
e
C
(c)
SEATING
PLANE
0.08 C
N LEADS
& EXPOSED PAD
C
2
A
(L)
SEE DETAIL "X"
A1
SIDE VIEW
N LEADS
DETAIL X
12
FN7421.3
October 18, 2010
EL4340, EL4342
Quarter Size Outline Plastic Packages Family (QSOP)
MDP0040
A
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
INCHES
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
E
PIN #1
I.D. MARK
E1
1
(N/2)
B
0.010
C A B
e
H
C
SEATING
PLANE
0.007
0.004 C
b
C A B
A
0.068
0.068
0.068
Max.
-
A1
0.006
0.006
0.006
±0.002
-
A2
0.056
0.056
0.056
±0.004
-
b
0.010
0.010
0.010
±0.002
-
c
0.008
0.008
0.008
±0.001
-
D
0.193
0.341
0.390
±0.004
1, 3
E
0.236
0.236
0.236
±0.008
-
E1
0.154
0.154
0.154
±0.004
2, 3
e
0.025
0.025
0.025
Basic
-
L
0.025
0.025
0.025
±0.009
-
L1
0.041
0.041
0.041
Basic
-
N
16
24
28
Reference
Rev. F 2/07
NOTES:
L1
A
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
c
SEE DETAIL "X"
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN7421.3
October 18, 2010
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