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TERSIL
Data Sheet
September 21, 2005
1-888-IN
ISL59421
FN7458.1
865MHz Multiplexing Amplifier
Features
The ISL59421 is a 865MHz bandwidth multiplexing amplifier
designed primarily for video switching. This Mux amp has
user-settable gain and also features a high speed threestate function to enable the output of multiple devices to be
wired together. All logic inputs have pull-downs to ground
and may be left floating. The ENABLE pin, when pulled high,
sets the ISL59421 to the low current power-down mode for
power sensitive applications - consuming just 5mW.
• 865MHz (-3dB) Bandwidth (AV = 1, VOUT = 100mVP-P)
TABLE 1. CHANNEL SELECT LOGIC TABLE
S0
ENABLE
HIZ
OUTPUT
0
0
0
IN0
1
0
0
IN1
X
1
X
Power Down
X
0
1
High Z
• 350MHz (-3dB) Bandwidth (AV = 2, VOUT = 2VP-P)
• Slew Rate (AV = 1, RL = 500VOUT = 4V) . . . . .1417V/µs
• Slew Rate (AV = 2, RL = 500VOUT = 5V) . . . . .2008V/µs
• Adjustable Gain
• High Speed Three-state Output (HIZ)
• Low Current Power-Down . . . . . . . . . . . . . . . . . . . . .5mW
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• HDTV/DTV Analog Inputs
• Video Projectors
• Computer Monitors
• Set-top Boxes
Pinout
ISL59421
(10 Ld MSOP)
TOP VIEW
S0
1
GND
2
IN0
3
ENABLE
IN1
• Security Video
• Broadcast Video Equipment
10
IN-
9
OUT
8
V+
4
7
V-
5
6
HIZ
+
Functional Diagram
EN0
DECODE
Ordering Information
PART
PART NUMBER MARKING
IN-
S0
IN0
EN1
IN1
- OUT
+
AMPLIFIER BIAS
PACKAGE
TAPE &
REEL
PKG.
DWG. #
ISL59421IU
BBRAA
10 Ld MSOP
-
MDP0043
ISL59421IU-T7
BBRAA
10 Ld MSOP
7”
MDP0043
ISL59421IU-T13
BBRAA
10 Ld MSOP
13”
MDP0043
ISL59421IUZ
(Note)
BBSAA
10 Ld MSOP
(Pb-free)
-
MDP0043
ISL59421IUZ-T7
(Note)
BBSAA
10 Ld MSOP
(Pb-free)
7”
MDP0043
ISL59421IUZ-T13
(Note)
BBSAA
10 Ld MSOP
(Pb-free)
13”
MDP0043
HIZ
ENABLE
ENABLE pin must be low in order to activate the HIZ state
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59421
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/s
IN- Input Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, RL = 500 to GND unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL
±IS Enabled
Supply Current
No load, VIN = 0V, ENABLE Low
12.5
14.5
20
mA
IS Disabled
Disabled Supply Current +
No load, VIN = 0V, ENABLE High
0.6
1
1.5
mA
Disabled Supply Current -
No load, VIN = 0V, ENABLE High
3
10
A
Positive Output Swing
VIN = 2V, RL = 500AV = 2
Negative Output Swing
VIN = -2V, RL = 500AV = 2
IOUT
Output Current
RL = 10 to GND
VOS
Output Offset Voltage
Ib+
Input Bias Current
IbRout
VOUT
3.5
3.9
V
-3
-2.8
V
±80
±130
±180
mA
-8
±2
8
mV
VIN = 0V
-4
-2.5
-1.5
A
Feedback Input Bias Current
VIN = 0V
-28
16
28
A
Output Resistance
HIZ = logic high, (DC), AV = 1
1.4
M
HIZ = logic low, (DC), AV = 1
0.2

10
M
RIN
Input Resistance
VIN = ±3.5V
ACL or AV
Voltage Gain
VIN = ±1.5V, RL = 500RF = RG = 600
1.99
ITRI
Output Current in Three-state
VOUT = 0V
-35
2
2.01
V/V
35
A
LOGIC
VH
Input High Voltage (Logic Inputs)
VL
Input Low Voltage (Logic Inputs)
IIH
Input High Current (Logic Inputs)
IIL
Input Low Current (Logic Inputs)
2
55
V
0.8
V
90
135
A
2
10
A
AC GENERAL
- 3dB BW
-3dB Bandwidth
2
AV = 1, RF = 357, VOUT = 100mVP-P,
CL = 4.9pF, CG = 0.6pF
865
MHz
AV = 2, RF = RG = 100, VOUT = 2VP-P,
CL = 6.3pF, CG = 0.6pF
350
MHz
FN7458.1
September 21, 2005
ISL59421
Electrical Specifications
PARAMETER
0.1dB BW
dG
dP
+SR
-SR
V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, RL = 500 to GND unless otherwise specified.
DESCRIPTION
0.1dB Bandwidth
Differential Gain Error
Differential Phase Error
Slew Rate
Slew Rate
CONDITIONS
MIN
TYP
MAX
UNIT
AV = 1, RF = 357, VOUT = 100mVP-P,
CL = 4.9pF, CG = 0.6pF
90
MHz
AV = 2, RF = RG = 100, VOUT = 2VP-P,
CL = 6.3pF, CG = 0.6pF
80
MHz
NTSC-7, RL = 150, CL = 4.9pF, AV = 1
0.01
%
NTSC-7, RL = 150, CL = 6.3pF, AV = 2
0.01
%
NTSC-7, RL = 150, CL = 4.9pF, AV = 1
0.02
°
NTSC-7, RL = 150, CL = 6.3pF, AV = 2
0.02
°
25% to 75%, AV = 1, VOUT = 4V, RL = 500,
CL = 6.5pF
1417
V/s
25% to 75%, AV = 2, VOUT = 5V, RL = 500,
CL = 6.5pF
2008
V/s
25% to 75%, AV = 1, VOUT = 4V, RL = 500,
CL = 6.5pF
1101
V/s
25% to 75%, AV = 2, VOUT = 5V, RL = 500,
CL = 6.5pF
1563
V/s
-68
dB
PSRR
Power Supply Rejection Ratio
DC, PSRR V+ and V- combined
-60
ISO
Channel Isolation
f = 10MHz, Ch-Ch X-Talk and Off Isolation,
CL = 6.3pF
75
dB
Channel-to-Channel Switching Glitch
VIN = 0V, CL = 6.3pF, AV = 2
26
mVP-P
Enable Switching Glitch
VIN = 0V, CL = 6.3pF, AV = 2
1280
mVP-P
HIZ Switching Glitch
VIN = 0V, CL= 6.3pF, AV =2
430
mVP-P
tSW-L-H
Channel Switching Time Low to High
1.2V logic threshold to 10% movement of
analog output
24
ns
tSW-H-L
Channel Switching Time High to Low
1.2V logic threshold to 10% movement of
analog output
19
ns
AV = 1, RF = 357, VOUT = 100mVP-P,
CL = 4.9pF, CG = 0.6pF
0.52
ns
AV = 2, RF = RG = 100, VOUT = 2VP-P,
CL = 6.3pF, CG = 0.6pF
1.11
ns
SWITCHING CHARACTERISTICS
VGLITCH
TRANSIENT RESPONSE
tR, tF
Rise & Fall Time, 10% to 90%
tS
0.1% Settling Time
AV = 2, RF = RG = 100, VOUT = 2VP-P,
CL = 6.3pF, CG = 0.6pF
4.7
ns
OS
Overshoot
AV = 1, RF = 357, VOUT = 100mVP-P,
CL = 4.9pF, CG = 0.6pF
5.95
%
AV = 2, RF = RG = 100, VOUT = 2VP-P,
CL = 6.3pF, CG = 0.6pF
16.56
%
AV = 1, RF = 357, VOUT = 100mVP-P,
CL = 4.9pF, CG = 0.6pF
0.43
ns
AV = 2, RF = RG = 100, VOUT = 2VP-P,
CL = 6.3pF, CG = 0.6pF
0.73
ns
AV = 1, RF = 357, VOUT = 100mVP-P,
CL = 4.9pF, CG = 0.6pF
0.55
ns
AV = 2, RF = RG = 100, VOUT = 2VP-P,
CL = 6.3pF, CG = 0.6pF
0.82
ns
tPLH
tPHL
Propagation Delay - Low to High,
10% to 10%
Propagation Delay- High to Low,
10% to 10%
3
FN7458.1
September 21, 2005
ISL59421
Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = 25°C, unless otherwise specified.
5
2
1
CL = 9.7pF
0
-1
CL = 7.2pF
-2
CL = 4.9pF
-3
CL = 1.6pF
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-4
-5
1
AV = 1
VOUT = 100mVP-P
3 CL = 4.9pF
RF = 357
2
4
NORMALIZED GAIN (dB)
3
NORMALIZED GAIN (dB)
5
AV = 1
VOUT = 100mVP-P
RF = 357
4
100
10
1
0
RL = 1k
RL = 500
-1
-2
RL = 150
-3
-4
-5
1000
RL = 75
1
10
FREQUENCY (MHz)
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL
5
5
3
2
1
0
CL = 9.7pF
-1
CL = 7.2pF
-2
CL = 6.3pF
-3
CL = 1.6pF
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-4
2
1
RL = 1k
0
RL = 500
-1
RL = 150
-2
RL = 75
-3
-4
-5
1
AV = 2
VOUT = 2VP-P
CL= 4.9pF
RG = RF = 100
4
NORMALIZED GAIN (dB)
3
NORMALIZED GAIN (dB)
FIGURE 2. SMALL SIGNAL GAIN vs FREQUENCY vs RL
AV = 2
VOUT = 2VP-P
RG = RF = 100
4
100
10
-5
1000
1
10
FREQUENCY (MHz)
1000
100
FREQUENCY (MHz)
FIGURE 3. LARGE SIGNAL GAIN vs FREQUENCY vs CL
FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs RL
0.2
0.2
0.1
0.1
CL = 9.7pF
0
-0.1
-0.2
CL = 7.2pF
-0.3
-0.4
CL = 4.9pF
AV = 1
VOUT = 100mVP-P
RF = 357
-0.5
-0.6
CL = 1.6pF
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-0.7
-0.8
1
RL=1k
0
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
1000
100
FREQUENCY (MHz)
RL = 500
-0.1
-0.2
-0.3
RL = 150
-0.4
-0.5
AV = 1
VOUT = 100mVP-P
CL = 4.9pF
RF = 357
-0.6
-0.7
-0.8
100
10
1000
FREQUENCY (MHz)
FIGURE 5. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs CL
4
1
RL = 75
10
100
1000
FREQUENCY (MHz)
FIGURE 6. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs RL
FN7458.1
September 21, 2005
ISL59421
Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = 25°C, unless otherwise specified. (Continued)
0.2
0.2
0.1
0.1
0
CL = 9.7pF
-0.1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
0
CL = 7.2pF
-0.2
CL = 6.3pF
-0.3
CL = 1.6pF
-0.4
AV = 2
VOUT = 2VP-P
RG = RF = 100
-0.5
-0.6
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-0.7
RL = 500
-0.2
-0.3
-0.4
-0.5
AV = 2
VOUT = 2VP-P
CL = 4.9pF
RG = RF = 100
-0.6
-0.7
-0.8
1
RL = 1k
-0.1
100
10
-0.8
1
1000
RL = 75
10
FREQUENCY (MHz)
FIGURE 8. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs RL
-10
20
-30
-40
-50
-20
(dB)
PSRR (dB)
-10
AV = 2
VIN = 1VP-P
CL = 4.9pF
RG = RF = 100
-20
AV = 2
VIN = 200mVP-P
CL = 4.9pF
RG = RF = 100
0
-30
-60
CROSSTALK
-70
-40
-80
-50
PSRR (V+)
-60
-90
PSRR (V-)
-70
-80
0.3
1
10
OFF ISOLATION
-100
100
1000
-110
0.001
0.01
0.1
3
6 10
100
500
FIGURE 10. CROSSTALK AND OFF ISOLATION
FIGURE 9. PSRR CHANNELS
24
1
FREQUENCY (MHz)
FREQUENCY (MHz)
60
AV = 1, RF = 500
INPUT VOLTAGE NOISE (nV/Hz)
-IIN CURRENT NOISE (pA/Hz)
1000
100
FREQUENCY (MHz)
FIGURE 7. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs CL
10
RL = 150
20
16
12
8
4
AV = 1, RF = 500
50
40
30
20
10
0
0.1
1
10
FREQUENCY (kHz)
FIGURE 11. INPUT NOISE vs FREQUENCY
5
100
0
0.1
1
10
100
FREQUENCY (kHz)
FIGURE 12. INPUT NOISE vs FREQUENCY
FN7458.1
September 21, 2005
ISL59421
Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = 25°C, unless otherwise specified. (Continued)
S0
1V/DIV
1V/DIV
S0
0
1V/DIV
20mV/DIV
0
0
VOUT
VOUT
0
20ns/DIV
20ns/DIV
FIGURE 13. CHANNEL TO CHANNEL SWITCHING GLITCH
VIN = 0V, AV = 2
FIGURE 14. CHANNEL TO CHANNEL TRANSIENT RESPONSE
VIN = 1V, AV = 2
Enable
1V/DIV
1V/DIV
Enable
0
1V/DIV
400mV/DIV
0
VOUT
0
VOUT
0
20ns/DIV
20ns/DIV
FIGURE 15. ENABLE SWITCHING GLITCH VIN = 0V, AV = 2
FIGURE 16. ENABLE TRANSIENT RESPONSE VIN = 1V, AV = 2
HIZ
1V/DIV
1V/DIV
HIZ
0
0
1V/DIV
200mV/DIV
0
VOUT
VOUT
0
20ns/DIV
FIGURE 17. HIZ SWITCHING GLITCH VIN = 0V, AV = 2
6
20ns/DIV
FIGURE 18. HIZ TRANSIENT RESPONSE VIN = 1V, AV = 2
FN7458.1
September 21, 2005
ISL59421
Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = 25°C, unless otherwise specified. (Continued)
160
80
2
1.6
OUTPUT VOLTAGE (V)
120
OUTPUT VOLTAGE (mV)
2.4
AV = 1
CL = 4.9pF
RF = 357
RL = 500
40
0
-40
-80
1.2
0.8
0.4
AV = 2
CL = 6.3pF
RG = RF = 100
RL = 500
0
-120
-0.4
-160
-0.8
TIME (4ns/DIV)
TIME (4ns/DIV)
FIGURE 19. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 20. LARGE SIGNAL TRANSIENT RESPONSE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.6
1
870mW
0.8
0.7

M
JA
=
0.6
0.5
POWER DISSIPATION (W)
POWER DISSIPATION (W)
0.9
SO
P
10
11
5°
C/
W
0.4
0.3
0.2
0.5
486mW
0.4

JA
0.3
M
SO
P
10
=2
06
°C
/W
0.2
0.1
0.1
0
0
0
25
50
75 85
100
0
125
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
100
AV = 1, VOUT = 100mVP-P
OUTPUT RESISTANCE ()
AV = 2, VOUT = 2VP-P
10
AV = 1
1
0.1
0.1
1
AV = 2
10
100
1000
FREQUENCY (MHz)
FIGURE 23. ROUT vs FREQUENCY
7
FN7458.1
September 21, 2005
ISL59421
Pin Descriptions
PIN NUMBER
PIN NAME
EQUIVALENT
CIRCUIT
1
S0
Circuit 2
Channel selection pin LSB (binary logic code)
2
GND
Circuit 4
Ground pin
3
IN0
Circuit 1
Input for channel 0
4
ENABLE
Circuit 2
Device enable (active low); there are internal pull-down resistors, so the device will be active with
no connection; "HI" puts device into power-down mode
5
IN1
Circuit 1
Input for channel 1
6
HIZ
Circuit 2
Output disable (active high); there are internal pull-down resistors, so the device will be active with
no connection; “HI” puts the output in high impedance state
7
V-
Circuit 4
Negative power supply
8
V+
Circuit 4
Positive power supply
9
OUT
Circuit 3
Output
10
IN-
Circuit 1
Inverting input of output amplifier
DESCRIPTION
V+
V+
IN
21K
LOGIC PIN
33K
V-
+
1.2V
-
GND.
V-
CIRCUIT 1.
CIRCUIT 2.
V+
V+
OUT
CAPACITIVELY
COUPLED
ESD CLAMP
GND
V-
VCIRCUIT 4.
CIRCUIT 3.
AC Test Circuits
ISL59421
RG
ISL59421
RF
RG
Av = 1, 2
50
or
75
CL
Av = 1, 2
TEST EQUIPMENT
RS
VIN
RF
475
or
462.5
50
or
75
50
or
75
FIGURE 24A. TEST CIRCUIT FOR MEASURING WITH A 50 OR
75 INPUT TERMINATED EQUIPMENT.
50
or
75
TEST EQUIPMENT
RS
VIN
CL
475
or
462.5
50
or
75
50
or
75
FIGURE 24B. TEST CIRCUIT FOR MEASURING WITH A 50 OR 75
INPUT TERMINATED EQUIPMENT.
NOTE: Figure 24A illustrates the optimum output load when connecting to input terminated equipment. Figure 24B illustrates back loaded test circuit
for video cable applications.
8
FN7458.1
September 21, 2005
ISL59421
Application Circuits
357
*CL = CT + COUT
VIN
VOUT
+
50
0.6pF
CT
1.6pF
CG
COUT
3.3pF
RL = 500
PC BOARD
CAPACITANCE
0.4pF < CG < 0.7pF
*CL: TOTAL LOAD CAPACITANCE
CT: TRACE CAPACITANCE
COUT: OUTPUT CAPACITANCE
FIGURE 25A. GAIN OF 1 APPLICATION CIRCUIT
100
*CL = CT + COUT
100
VIN
+
50
0.6pF
CG
VOUT
CT
1.6pF
COUT
4.7pF
RL = 500
PC BOARD
CAPACITANCE
0.4pF < CG < 0.7pF
FIGURE 25B. GAIN OF 2 APPLICATION CIRCUIT
Application Information
Capacitance at the Output
Parasitic Effects on Frequency Performance
The output amplifier is optimized for capacitance to ground
(CL) directly on the output pin. Increased capacitance
causes higher peaking with an increase in bandwidth. The
optimum range for most applications is ~1.0pF to ~6pF. The
optimum value can be achieved through a combination of
PC board trace capacitance (CT) and an external capacitor
(COUT). A good method to maintain control over the output
pin capacitance is to minimize the trace length (CT) to the
next component, and include a discrete surface mount
capacitor (COUT) directly at the output pin.
Capacitance at the Inverting Input
Feedback Resistor Values
The AC performance of current-feedback amplifiers in the
non-inverting gain configuration is strongly affected by stray
capacitance at the inverting input. Stray capacitance from
the inverting input pin to the output (CF), and to ground (CG),
increase gain peaking and bandwidth. Large values of either
capacitance can cause oscillation. The ISL59421 has been
optimized for a 0.4pF to 0.7pF capacitance (CG).
Capacitance (CF) to the output should be minimized. To
achieve optimum performance the feedback network
resistor(s) must be placed as close to the device as possible.
Trace lengths greater than 1/4 inch combined with resistor
pad capacitance can result in inverting input to ground
capacitance approaching 1pF. Inverting input and output
traces should not run parallel to each other. Small size
surface mount resistors (604 or smaller) are recommended.
The AC performance of the output amplifier is optimized with
the feedback resistor network (RF, RG) values
recommended in the application circuits. The amplifier
bandwidth and gain peaking are directly affected by the
value(s) of the feedback resistor(s) in unity gain and gain >1
configurations. Transient response performance can be
tailored simply by changing these resistor values. Generally,
lower values of RF and RG increase bandwidth and gain
peaking. This has the effect of decreasing rise/fall times and
increasing overshoot.
General
The ISL59421 is a 2:1 mux that is ideal as a matrix element
in high performance switchers and routers. The ISL59421 is
optimized to drive 5pF in parallel with a 500 load. The
capacitance can be split between the PCB capacitance an
and external load capacitance. Its low input capacitance and
high input resistance provide excellent 50 or 75
terminations.
9
Ground Connections
For the best isolation and crosstalk rejection, the GND pin
and NIC pins must connect to the GND plane.
FN7458.1
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ISL59421
analog inputs is needed to prevent damage during the time
the voltages on these inputs are more positive than V+.
Control Signals
S0, ENABLE, HIZ - These pins are TTL/CMOS compatible
control inputs. The S0 pin selects which one of the inputs
connect to the output. The ENABLE, HIZ pins are used to
disable the part to save power and three-state the output
amplifiers, respectively. For control signal rise and fall times
less than 10ns the use of termination resistors close to the
part will minimize transients coupled to the output.
HIZ State
An internal pull-down resistor connected to the HIZ pin
ensures the device will be active with no connection to the
HIZ pin. The HIZ state is established within approximately
30ns (Figure 18) by placing a logic high (>2V) on the HIZ
pin. If the HIZ state is selected, the output is a high
impedance 1.4M. Use this state to control the logic when
more than one mux shares a common output.
Power-Up Considerations
The ESD protection circuits use internal diodes from all pins
the V+ and V- supplies. In addition, a dV/dT- triggered clamp
is connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the Pin Description
table. The dV/dT triggered clamp imposes a maximum
supply turn-on slew rate of 1V/µs. Damaging currents can
flow for power supply rates-of-rise in excess of 1V/µs, such
as during hot plugging. Under these conditions, additional
methods should be employed to ensure the rate of rise is not
exceeded.
In the HIZ state the output is three-stated, and maintains its
high Z even in the presence of high slew rates. The supply
current during this state is basically the same as the active
state.
ENABLE & Power Down States
The enable pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
ENABLE pin. The Power Down state is established when a
logic high (>2V) is placed on the ENABLE pin. In the Power
Down state, the output has no leakage but has a large
capacitance (on the order of 15pF), and is capable of being
back-driven. Under this condition, large incoming slew rates
can cause fault currents of tens of mA. Do not use this
state as a high Z state for applications driving more than
one mux on a common output.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic
input pins. Schottky diodes (Motorola MBR0550T or
equivalent) connected from V+ to ground and V- to ground
(Figure 26) will shunt damaging currents away from the
internal V+ and V- ESD diodes in the event that the V+
supply is applied to the device before the V- supply.
Limiting the Output Current
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through
the ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and
V+ SUPPLY
SCHOTTKY
PROTECTION
LOGIC
No output short circuit current limit exists on this part. All
applications need to limit the output current to less than
50mA. Adequate thermal heat sinking of the parts is also
required.
V+
LOGIC
CONTROL
S0
POWER
GND
GND
SIGNAL
IN0
EXTERNAL
CIRCUITS
V+
V-
V+
V+
V+
OUT
V-
DE-COUPLING
CAPS
IN1
VV-
V-
V- SUPPLY
FIGURE 26. SCHOTTKY PROTECTION CIRCUIT
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ISL59421
PC Board Layout
The frequency response of this circuit depends greatly on
the care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners, use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
degraded for traces greater than one inch, unless strip
lines are used.
• Match channel-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• Maximize use of AC de-coupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e.
no split planes or PCB gaps under these lines). Avoid vias
in the signal I/O lines.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
• Minimum of 2 power supply de-coupling capacitors are
recommended (1000pF, 0.01µF) as close to the device as
possible. Avoid vias between the cap and the device
because vias add unwanted inductance. Larger caps can
be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
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ISL59421
10 Ld MSOP Package Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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