DATASHEET

ISL59440
®
Data Sheet
October 10, 2007
FN6162.2
400MHz Multiplexing Amplifier
Features
The ISL59440 is a 400MHz bandwidth 4:1 multiplexing
amplifier designed primarily for video switching. This Muxamp has user-settable gain and also features a high speed
three-state function to enable the output of multiple devices to
be wired together. All logic inputs have pull-downs to ground
and may be left floating. The ENABLE pin, when pulled high,
sets the ISL59440 to the low current power-down mode for
power sensitive applications - consuming just 5mW.
• 411MHz (-3dB) Bandwidth (AV = 1, VOUT = 100mVP-P)
TABLE 1. CHANNEL SELECT LOGIC TABLE
• 200MHz (-3dB) Bandwidth (AV = 2, VOUT = 2VP-P)
• Slew Rate (AV = 1, RL = 500Ω, VOUT = 4V) . . . . .1053V/µs
• Slew Rate (AV = 2, RL = 500Ω, VOUT = 5V) . . . . .1470V/µs
• Adjustable Gain
• High Speed Three-state Output (HIZ)
• Low Current Power-down. . . . . . . . . . . . . . . . . . . . . .5mW
S1
S0
ENABLE
HIZ
OUTPUT
0
0
0
0
IN0
0
1
0
0
IN1
Applications
1
0
0
0
IN2
• HDTV/DTV Analog Inputs
• Video Projectors
1
1
0
0
IN3
X
X
1
X
Power Down
X
X
0
1
High Z
• Pb-Free Available (RoHS Compliant)
• Computer Monitors
• Set-top Boxes
Pinout
• Security Video
ISL59440
(16 LD QSOP)
TOP VIEW
• Broadcast Video Equipment
NIC
1
16 ENABLE
IN0
2
15 HIZ
Ordering Information
PART NUMBER
NIC
3
IN1
4
GND
5
12 V+
IN2
6
11
NIC
7
10 S1
IN3
8
9
14
+
13 OUT
S0
IN-
ISL59440IA*
59440 IA
16 Ld QSOP
MDP0040
ISL59440IAZ*
(Note)
59440 IAZ
16 Ld QSOP
(Pb-free)
MDP0040
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
IN0
EN1
DECODE
PKG. DWG.
#
*Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
V-
EN0
S1
PACKAGE
IN-
Functional Diagram
S0
PART MARKING
IN1
IN2
EN2
- OUT
+
IN3
EN3
AMPLIFIER BIAS
HIZ
ENABLE
ENABLE pin must be low in order to activate the HIZ state
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005, 2007. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59440
Absolute Maximum Ratings (TA = 25°C)
Thermal Information
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/μs
IN- Input Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . -40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . -40°C to +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Curves
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
2. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, RL = 500Ω to GND unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
(Note 2)
TYP
MAX
(Note 2)
UNIT
GENERAL
±IS Enabled
Supply Current
No load, VIN = 0V, ENABLE Low
12.5
14.5
16.5
mA
IS Disabled
Disabled Supply Current I+
No load, VIN = 0V, ENABLE High
0.5
1
1.5
mA
Disabled Supply Current I-
No load, VIN = 0V, ENABLE High
3
10
μA
VOUT
Positive and Negative Output Swing
VIN = ±2V, RL = 500Ω, AV = 2
IOUT
Output Current
RL = 10Ω to GND
VOS
Output Offset Voltage
Ib+
Input Bias Current
Ib-
Feedback Bias Current
ROUT
Output Resistance
VIN = 0V
±3.5
±3.9
V
80
130
mA
-12
4
+12
mV
-4
2.5
-1.5
μA
7
15
-15
μA
HIZ = logic high, (DC), AV =1
1.4
MΩ
HIZ = logic low, (DC), AV =1
0.2
Ω
RIN
Input Resistance
VIN = 3.5V
10
MΩ
CIN
Input Capacitance
VIN = 224mVRMS, AV = 1
0.9
pF
ACL or AV
Voltage Gain
RF = RG = 500Ω, VOUT = ±3V
ITRI
Output Current in Three-state
VOUT = 0V
1.990
2.005
2.020
V/V
-20
6
20
μA
LOGIC
VH
Input High Voltage (Logic Inputs)
VL
Input Low Voltage (Logic Inputs)
IIH
Input High Current (Logic Inputs)
55
IIL
Input Low Current (Logic Inputs)
-10
2
V
0.8
V
90
135
μA
0
10
μA
AC GENERAL
- 3dB BW
-3dB Bandwidth
2
AV = 1, RF = 332Ω, VOUT = 200mVP-P,
CL = 1.6pF, CG = 0.6pF
400
MHz
AV = 2, RF = RG = 511Ω, VOUT = 2VP-P,
CL = 5.5pF, CG = 0.6pF
200
MHz
FN6162.2
October 10, 2007
ISL59440
Electrical Specifications
PARAMETER
0.1dB BW
dG
V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, RL = 500Ω to GND unless otherwise specified. (Continued)
DESCRIPTION
0.1dB Bandwidth
Differential Gain Error
CONDITIONS
MIN
(Note 2)
TYP
MAX
(Note 2)
UNIT
AV = 1, RF = 332Ω, VOUT = 200mVP-P,
CL = 1.6pF, CG = 0.6pF
22
MHz
AV = 2, RF = RG = 511Ω, VOUT = 2VP-P,
CL = 5.5pF, CG = 0.6pF
62
MHz
NTC-7, RL = 150, CL = 1.6pF, AV = 1
0.01
%
NTC-7, RL = 150, CL = 5.5pF, AV = 2
0.05
%
0.02
°
dP
Differential Phase Error
NTC-7, RL = 150, CL = 1.6pF, AV = 1
NTC-7, RL = 150, CL = 5.5pF, AV = 2
0.02
°
+SR
Slew Rate
25% to 75%, AV = 1, VOUT = 4V, RL = 500Ω,
CL = 1.6pF
1053
V/μs
25% to 75%, AV = 2, VOUT = 5V, RL = 500Ω,
CL = 5.5pF
1470
V/μs
25% to 75%, AV = 1, VOUT = 4V, RL = 500Ω,
CL = 1.6pF
925
V/μs
25% to 75%, AV = 2, VOUT = 5V, RL = 500Ω,
CL= 5.5pF
1309
V/μs
-58
dB
-SR
Slew Rate
PSRR
Power Supply Rejection Ratio
DC, PSRR V+ and V- combined
-50
ISO
Channel Isolation
f = 10MHz, Ch-Ch crosstalk and off-isolation,
CL = 5.5pF
75
dB
Channel-to-Channel Switching Glitch
VIN = 0V, CL = 5.5pF, AV = 2
1
mVP-P
ENABLE Switching Glitch
VIN = 0V, CL = 5.5pF, AV = 2
800
mVP-P
HIZ Switching Glitch
VIN = 0V, CL= 5.5pF, AV = 2
375
mVP-P
tSW-L-H
Channel Switching Time Low to High
1.2V logic threshold to 10% movement of analog
output
25
ns
tSW-H-L
Channel Switching Time High to Low
1.2V logic threshold to 10% movement of analog
output
20
ns
AV = 1, RF = 332Ω, VOUT = 100mVP-P,
CL = 1.6pF, CG = 0.6pF
0.65
ns
AV = 2, RF = RG = 511Ω, VOUT = 2VP-P,
CL = 5.5pF, CG = 0.6pF
1.51
ns
SWITCHING CHARACTERISTICS
VGLITCH
TRANSIENT RESPONSE
tR, tF
Rise and Fall Time, 10% to 90%
tS
0.1% Settling Time
AV = 2, RF = RG = 511Ω, VOUT = 2VP-P,
CL = 5.5pF, CG = 0.6pF
9.0
ns
OS
Overshoot
AV = 1, RF = 332Ω, VOUT = 100mVP-P,
CL = 1.6pF, CG = 0.6pF
17.85
%
AV = 2, RF = RG = 511Ω, VOUT = 2VP-P,
CL = 5.5pF, CG = 0.6pF
12.65
%
AV = 1, RF = 332Ω, VOUT = 100mVP-P,
CL = 1.6pF, CG = 0.6pF
0.54
ns
AV = 2, RF = RG = 511Ω, VOUT = 2VP-P,
CL = 5.5pF, CG = 0.6pF
0.99
ns
AV = 1, RF = 332Ω, VOUT = 100mVP-P,
CL = 1.6pF, CG = 0.6pF
0.57
ns
AV = 2, RF = RG = 511Ω, VOUT = 2VP-P,
CL = 5.5pF, CG = 0.6pF
1.02
ns
tPLH
tPHL
Propagation Delay - Low to High,
10% to 10%
Propagation Delay- High to Low,
10% to 10%
3
FN6162.2
October 10, 2007
ISL59440
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified.
5
NORMALIZED GAIN (dB)
3
5
CL = 9.7pF
AV = 1
VOUT = 200mVP-P
RF = 332Ω
4
CL = 7.2pF
2
3
NORMALIZED GAIN (dB)
4
CL = 5.5pF
1
0
CL = 1.6pF
-1
-2
-3
-4
CL INCLUDES 1.6pF
BOARD CAPACITANCE
RL = 1kΩ
1
0
-1
RL = 150Ω
-2
RL = 75Ω
-3
10M
100M
-5
1M
1G
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
3
4
3
1
0
CL = 9.7pF
-1
CL = 7.2pF
-2
CL = 5.5pF
-3
CL = 1.6pF
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-5
1M
100M
10M
2
AV = 2
VOUT = 2VP-P
CL = 5.5pF
RG = RF = 511Ω
1
RL = 75Ω
0
-1
-2
RL = 150Ω
-3
-5
1G
RL = 1kΩ
RL = 75Ω
-4
1M
FREQUENCY (Hz)
10M
100M
RL = 500Ω
1G
FREQUENCY (Hz)
FIGURE 3. LARGE SIGNAL GAIN vs FREQUENCY vs CL
FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs RL
0.8
0.8
A =1
0.7 V V
OUT = 200mVP-P
RF = 332Ω
0.6
CL = 1.6pF
CL = 9.7pF
CL = 5.5pF
0.5
0.4
0.3
0.2
0.1
0
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-0.1
-0.2
1M
100M
10M
1G
FREQUENCY (Hz)
FIGURE 5. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs CL
4
AV = 1
RL = 75Ω
VOUT = 200mVP-P
0.6 CL = 1.6pF
RL = 150Ω
0.5 RF = 332Ω
0.7
CL = 7.2pF
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
1G
5
AV = 2
VOUT = 2VP-P
RG = RF = 511Ω
2
-4
100M
FIGURE 2. SMALL SIGNAL GAIN vs FREQUENCY vs RL
NORMALIZED GAIN (dB)
4
10M
FREQUENCY (Hz)
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL
5
RL = 500Ω
-4
-5
1M
2
AV = 1
VOUT = 200mVP-P
CL= 1.6pF
RF = 332Ω
0.4
RL = 1kΩ
RL = 500Ω
0.3
0.2
0.1
0
-0.1
-0.2
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 6. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs RL
FN6162.2
October 10, 2007
ISL59440
0.2
0.5
0.1
0.4
0
0.3
CL = 9.7pF
-0.1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified.
CL = 7.2pF
-0.2
CL = 5.5pF
-0.3
CL = 1.6pF
-0.4
AV = 2
VOUT = 2VP-P
RG = RF = 511Ω
-0.5
-0.6
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-0.7
1M
AV = 2
VOUT = 2VP-P
CL = 5.5pF
RG = RF = 511Ω
0.2
RL = 75Ω
RL = 150Ω
0.1
0
-0.1
RL = 500Ω
-0.2
-0.3
RL = 1kΩ
-0.4
-0.8
100M
10M
-0.5
1G
1M
10M
FREQUENCY (Hz)
FIGURE 8. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs RL
20
-10
AV = 2
10 V = 200mV
IN
P-P
0 CL = 5.5pF
RG = RF = 511Ω
-10
-20
-30
-40
-20
AV = 2
VIN = 1VP-P
CL = 5.5pF
RG = RF = 511Ω
-50
(dB)
PSRR (dB)
1G
100M
FREQUENCY (Hz)
FIGURE 7. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs CL
-30
-40
-60
CROSSTALK
-70
-50
-80
PSRR (V+)
-60
-90
-70
PSRR (V-)
-80
0.3M
1M
10M
100M
OFF ISOLATION
-100
-110
0.001M
1G
0.01M
0.1M
FREQUENCY (Hz)
24
1M 3M 6M10M
100M 500M
FREQUENCY (Hz)
FIGURE 9. PSRR CHANNELS
FIGURE 10. CROSSTALK AND OFF ISOLATION
60
AV = 1, RF = 500Ω
INPUT VOLTAGE NOISE (nV/√Hz)
-IIN CURRENT NOISE (pA/√Hz)
(Continued)
20
16
12
8
AV = 1, RF = 500Ω
50
40
30
20
10
4
0
0
0.1k
1k
10k
FREQUENCY (Hz)
FIGURE 11. INPUT NOISE vs FREQUENCY
5
100k
0.1k
1k
10k
100k
FREQUENCY (Hz)
FIGURE 12. INPUT NOISE vs FREQUENCY
FN6162.2
October 10, 2007
ISL59440
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified.
S0, S1
1V/DIV
1V/DIV
S0, S1
0
0
VOUT
1V/DIV
10mV/DIV
0
VOUT
0
20ns/DIV
FIGURE 13. CHANNEL TO CHANNEL SWITCHING GLITCH
VIN = 0V, AV = 2
20ns/DIV
FIGURE 14. CHANNEL TO CHANNEL TRANSIENT RESPONSE
VIN = 1V, AV = 2
ENABLE
1V/DIV
1V/DIV
ENABLE
0
2V/DIV
20mV/DIV
0
VOUT
0
0
VOUT
20ns/DIV
20ns/DIV
FIGURE 15. ENABLE SWITCHING GLITCH VIN = 0V, AV = 2
FIGURE 16. ENABLE TRANSIENT RESPONSE VIN = 1V, AV = 2
HIZ
1V/DIV
1V/DIV
HIZ
0
1V/DIV
0
200mV/DIV
(Continued)
0
VOUT
VOUT
0
20ns/DIV
FIGURE 17. HIZ SWITCHING GLITCH VIN = 0V, AV = 2
6
20ns/DIV
FIGURE 18. HIZ TRANSIENT RESPONSE VIN = 1V, AV = 2
FN6162.2
October 10, 2007
ISL59440
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified.
160
80
2.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
2.4
AV = 1
CL = 1.6pF
RF = 332Ω
RL = 500Ω
120
40
0
-40
-80
1.6
1.2
0.8
0.4
AV = 2
CL= 5.5pF
RG = RF = 511Ω
RL = 500Ω
0
-0.4
-120
-160
-0.8
TIME (4ns/DIV)
TIME (4ns/DIV)
FIGURE 19. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 20. LARGE SIGNAL TRANSIENT RESPONSE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
1.2
1.2
1.0
POWER DISSIPATION (W)
POWER DISSIPATION (W)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
893mW
1.0
QS
θ
OP
JA
16
=1
12
°C
/W
0.8
0.6
(Continued)
0.4
0.2
0
0.8
633mW
0.6
θJ
0.4
QS
O
A =1
58
P1
°C
6
/W
0.2
0
0
25
50
75 85
100
125
150
0
AMBIENT TEMPERATURE (°C)
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
100
AV = 1, VOUT = 100mVP-P
OUTPUT RESISTANCE (Ω)
AV = 2, VOUT = 2VP-P
10
AV = 2
AV = 1
1
0.1
0.1M
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 23. ROUT vs FREQUENCY
7
FN6162.2
October 10, 2007
ISL59440
Pin Descriptions
EQUIVALENT
CIRCUIT
PIN NUMBER
PIN NAME
DESCRIPTION
1, 3, 7
NIC
2
IN0
Circuit 1
Input for Channel 0
4
IN1
Circuit 1
Input for Channel 1
5
GND
Circuit 4
Ground pin
6
IN2
Circuit 1
Input for Channel 2
8
IN3
Circuit 1
Input for Channel 3
9
S0
Circuit 2
Channel selection pin LSB (binary logic code)
10
S1
Circuit 2
Channel selection pin MSB (binary logic code)
11
V-
Circuit 4
Negative power supply
12
V+
Circuit 4
Positive power supply
13
OUT
Circuit 3
Output
14
IN-
Circuit 1
Inverting input of output amplifier
15
HIZ
Circuit 2
Output disable (active high); there are internal pull-down resistors, so the device will be active with
no connection; “HI” puts the output in high impedance state.
16
ENABLE
Circuit 2
Device enable (active low); there are internal pull-down resistors, so the device will be active with
no connection; "HI" puts device into power-down mode.
Not Internally Connected; it is recommended this pin be tied to ground to minimize crosstalk.
V+
V+
IN
21k
LOGIC PIN
33k
V-
+
1.2V
-
GND.
V-
CIRCUIT 1.
CIRCUIT 2.
V+
V+
OUT
CAPACITIVELY
COUPLED
ESD CLAMP
GND
VVCIRCUIT 3.
CIRCUIT 4.
AC Test Circuits
ISL59440
RG
RF
RG
AV = 1, 2
VIN
50Ω
OR
75Ω
TEST
EQUIPMENT
RS
CL
475Ω
OR
462.5Ω
50Ω
OR
75Ω
50Ω
OR
75Ω
FIGURE 24A. TEST CIRCUIT FOR MEASURING WITH A 50Ω OR
75Ω INPUT TERMINATED EQUIPMENT
VIN
50Ω
OR
75Ω
ISL59440
RF
AV = 1, 2
RS
CL
50Ω OR 75Ω
TEST
EQUIPMENT
50Ω
OR
75Ω
FIGURE 24B. BACKLOADED TEST CIRCUIT FOR VIDEO
CABLE APPLICATION. BANDWIDTH AND
LINEARITY FOR RL LESS THAN 500Ω WILL BE
DEGRADED.
NOTE: Figure 24A illustrates the optimum output load when connecting to input terminated equipment. Figure 24B illustrates
backloaded test circuit for video cable applications.
8
FN6162.2
October 10, 2007
ISL59440
Application Circuits
CF
332Ω
*CL = CT + COUT
VIN
VOUT
+
50Ω
0.6pF
CT
1.6pF
Cg
COUT
0pF
RL = 500Ω
PC BOARD
CAPACITANCE
*CL: TOTAL LOAD CAPACITANCE
0.4pF < CG < 0.7pF
CT: TRACE CAPACITANCE
COUT: OUTPUT CAPACITANCE
FIGURE 25A. GAIN OF 1 APPLICATION CIRCUIT
511Ω
*CL = CT + COUT
511Ω
VIN
+
50Ω
0.6pF
CG
VOUT
CT
COUT
1.6pF
3.9pF
RL = 500Ω
PC BOARD
CAPACITANCE
0.4pF < CG < 0.7pF
FIGURE 25B. GAIN OF 2 APPLICATION CIRCUIT
Application Information
General
The ISL59440 is a 4:1 mux that is ideal as a matrix element
in high performance switchers and routers. The ISL59440 is
optimized to drive 5pF in parallel with a 500Ω load. The
capacitance can be split between the PCB capacitance and
an external load capacitance. Its low input capacitance and
high input resistance provides excellent 50Ω or 75Ω
terminations.
Parasitic Effects on Frequency Performance
CAPACITANCE AT THE INVERTING INPUT
The AC performance of current-feedback amplifiers in the
non-inverting gain configuration is strongly effected by stray
capacitance at the inverting input. Stray capacitance from
the inverting input pin to the output (CF), and to ground (CG),
increase gain peaking and bandwidth. Large values of either
capacitance can cause oscillation. The ISL59440 has been
optimized for a 0.4pF to 0.7pF capacitance (CG).
Capacitance (CF) to the output should be minimized. To
achieve optimum performance the feedback network
resistor(s) must be placed as close to the device as possible.
Trace lengths greater than 1/4 inch combined with resistor
pad capacitance can result in inverting input to ground
capacitance approaching 1pF. Inverting input and output
9
traces should not run parallel to each other. Small size
surface mount resistors (604 or smaller) are recommended.
CAPACITANCE AT THE OUTPUT
The output amplifier is optimized for capacitance to ground
(CL) directly on the output pin. Increased capacitance
causes higher peaking with an increase in bandwidth. The
optimum range for most applications is ~1.0pF to ~6pF. The
optimum value can be achieved through a combination of
PC board trace capacitance (CT) and an external capacitor
(COUT). A good method to maintain control over the output
pin capacitance is to minimize the trace length (CT) to the
next component, and include a discrete surface mount
capacitor (COUT) directly at the output pin.
FEEDBACK RESISTOR VALUES
The AC performance of the output amplifier is optimized with
the feedback resistor network (RF, RG) values
recommended in the application circuits. The amplifier
bandwidth and gain peaking are directly effected by the
value(s) of the feedback resistor(s) in unity gain and gain >1
configurations. Transient response performance can be
tailored simply by changing these resistor values. Generally,
lower values of RF and RG increase bandwidth and gain
peaking. This has the effect of decreasing rise/fall times and
increasing overshoot.
FN6162.2
October 10, 2007
ISL59440
GROUND CONNECTIONS
HIZ STATE
For the best isolation and crosstalk rejection, the GND pin
and NIC pins must connect to the GND plane.
An internal pull-down resistor connected to the HIZ pin
ensures the device will be active with no connection to the
HIZ pin. The HIZ state is established within approximately
30ns (Figure 18) by placing a logic high (> 2V) on the HIZ
pin. If the HIZ state is selected, the output is a high
impedance 1.4MΩ. Use this state to control the logic when
more than one mux shares a common output.
CONTROL SIGNALS
S0, S1, ENABLE, HIZ - These pins are TTL/CMOS
compatible control inputs. The S0 pin selects which one of
the inputs connect to the output. The ENABLE, HIZ pins are
used to disable the part to save power and three-state the
output amplifiers, respectively. For control signal rise and fall
times less than 10ns the use of termination resistors close to
the part will minimize transients coupled to the output.
In the HIZ state the output is three-stated, and maintains its
high Z even in the presence of high slew rates. The supply
current during this state is basically the same as the active
state.
POWER-UP CONSIDERATIONS
ENABLE AND POWER DOWN STATES
The ESD protection circuits use internal diodes from all pins
the V+ and V- supplies. In addition, a dV/dT- triggered clamp
is connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the “Pin
Descriptions” on page 8. The dV/dT triggered clamp
imposes a maximum supply turn-on slew rate of 1V/µs.
Damaging currents can flow for power supply rates-of-rise in
excess of 1V/µs, such as during hot plugging. Under these
conditions, additional methods should be employed to
ensure the rate of rise is not exceeded.
The enable pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
ENABLE pin. The Power Down state is established when a
logic high (>2V) is placed on the ENABLE pin. In the Power
Down state, the output has no leakage but has a large
capacitance (on the order of 15pF), and is capable of being
back-driven. Under this condition, large incoming slew rates
can cause fault currents of tens of mA. Do not use this
state as a high Z state for applications driving more than
one mux on a common output.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic
input pins. Schottky diodes (Motorola MBR0550T or
equivalent) connected from V+ to ground and V- to ground
(Figure 26) will shunt damaging currents away from the
internal V+ and V- ESD diodes in the event that the V+
supply is applied to the device before the V- supply.
LIMITING THE OUTPUT CURRENT
No output short circuit current limit exists on this part. All
applications need to limit the output current to less than
50mA. Adequate thermal heat sinking of the parts is also
required.
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through
the ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and
analog inputs is needed to prevent damage during the time
the voltages on these inputs are more positive than V+.
V+ SUPPLY
SCHOTTKY
PROTECTION
LOGIC
V+
LOGIC
CONTROL
S0
POWER
GND
GND
EXTERNAL
CIRCUITS
V+
V-
V+
V+
SIGNAL
IN0
V+
OUT
V-
DE-COUPLING
CAPS
IN1
VV-
V-
V- SUPPLY
FIGURE 26. SCHOTTKY PROTECTION CIRCUIT
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FN6162.2
October 10, 2007
ISL59440
PC Board Layout
The frequency response of this circuit depends greatly on
the care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended.
• Match channel-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• Maximize use of AC de-coupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e.
no split planes or PCB gaps under these lines). Avoid vias
in the signal I/O lines.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
• Minimum of 2 power supply de-coupling capacitors are
recommended (1000pF, 0.01µF) as close to the device as
possible - Avoid vias between the cap and the device
because vias add unwanted inductance. Larger caps can
be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
• The NIC pins are placed on both sides of the input pins.
These pins are not internally connected to the die. It is
recommended these pins be tied to ground to minimize
crosstalk.
11
FN6162.2
October 10, 2007
ISL59440
Quarter Size Outline Plastic Packages Family (QSOP)
MDP0040
A
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
INCHES
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
E
PIN #1
I.D. MARK
E1
1
(N/2)
A
0.068
0.068
0.068
Max.
-
A1
0.006
0.006
0.006
±0.002
-
A2
0.056
0.056
0.056
±0.004
-
b
0.010
0.010
0.010
±0.002
-
c
0.008
0.008
0.008
±0.001
-
D
0.193
0.341
0.390
±0.004
1, 3
E
0.236
0.236
0.236
±0.008
-
E1
0.154
0.154
0.154
±0.004
2, 3
e
0.025
0.025
0.025
Basic
-
L
0.025
0.025
0.025
±0.009
-
L1
0.041
0.041
0.041
Basic
-
N
16
24
28
Reference
-
B
0.010
C A B
e
H
C
SEATING
PLANE
0.007
0.004 C
b
C A B
Rev. F 2/07
NOTES:
L1
A
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
c
SEE DETAIL "X"
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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12
FN6162.2
October 10, 2007
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