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Data
January 5, 2007
1-888Sheet
ISL59442
FN7452.4
1GHz, 4 x 1 Multiplexing Amplifier
Features
The ISL59442 is a single-output 4:1 MUX-amp. The
MUX-amp has a fixed gain of 1 and a 1GHz bandwidth. The
device contains logic inputs for channel selection (S0, S1),
and a three-state output control (HIZ) for individual
selection of MUX amps that share a common video output
line. All logic inputs have pull-downs to ground and may be
left floating.
• 1GHz (-3dB) Bandwidth (VOUT = 200mVP-P)
TABLE 1. TRUTH TABLE
• 235MHz (-3dB) Bandwidth (VOUT = 2VP-P)
• Slew Rate (RL = 525VOUT = 5V) . . . . . . . . . . . . 1452V/s
• High Speed Three-state Output (HIZ)
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
HIZ
S1
S0
OUT
0
0
0
IN0
0
0
1
IN1
0
1
0
IN2
0
1
1
IN3
• Set-top Boxes
1
X
X
HIZ
• Security Video
• HDTV/DTV Analog Inputs
• Video Projectors
• Computer Monitors
• Broadcast Video Equipment
Pinout
ISL59442
(14 LD SO)
TOP VIEW
Functional Diagram
EN0
IN0 1
14 V+
NIC 2
13 S0
IN1 3
12 S1
S0
EN1
GND 4
S1
OUT
IN1
DECODE
EN2
11 HIZ
EN3
IN2 5
IN0
IN2
IN3
10 OUT
A=1
NIC 6
9 NIC
HIZ
IN3 7
8 V-
Ordering Information
PART NUMBER
PART MARKING
ISL59442IB
59442IB
TAPE & REEL
-
PACKAGE
14 Ld SOIC
PKG. DWG. #
MDP0027
ISL59442IB-T7
59442IB
7”
14 Ld SOIC
MDP0027
ISL59442IB-T13
59442IB
13”
14 Ld SOIC
MDP0027
ISL59442IBZ (Note)
59442IBZ
-
14 Ld SOIC (Pb-free)
MDP0027
ISL59442IBZ-T7 (Note)
59442IBZ
7”
14 Ld SOIC (Pb-free)
MDP0027
ISL59442IBZ-T13 (Note)
59442IBZ
13”
14 Ld SOIC (Pb-free)
MDP0027
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas LLC 2005-2007. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59442
Absolute Maximum Ratings (TA = +25°C)
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . . -40°C to 85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/s
Digital and Analog Input Current (Note 1) . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . .3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, Input Video = 1VP-P and RL = 500 to GND, VHIZ = 0.8V,
Unless Otherwise Specified
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
No load, VHIZ = 0.8V
14.5
18
20
mA
No load, VHIZ = 2.0V
12
15.5
17.5
mA
GENERAL
IS
Supply Current (VOUT = 0V)
VOUT
Positive and Negative Output Swing
VIN = ±3.5V, RL = 500
±3.2
±3.44
IOUT
Output Current
RL = 10 to GND
±80
±120
±180
mA
VOS
Output Offset Voltage
-2
9
20
mV
Ib
Input Bias Current
VIN = 0V
-5
-2.5
-1
A
Rout
Output Resistance
HIZ = logic high, (DC)
1.4
M
HIZ = logic low, (DC)
0.2

10
M
RIN
Input Resistance
VIN = ±3.5V
ACL or AV
Voltage Gain
VIN = ±1.5V, RL = 500
ITRI
Output Current in Three-state
VOUT = 0V
V
0.999
1.001
1.003
V/V
-35
6
35
A
LOGIC
VH
Input High Voltage (Logic Inputs)
VL
Input Low Voltage (Logic Inputs)
IIH
Input High Current (Logic Inputs)
IIL
Input Low Current (Logic Inputs)
2
50
V
90
0.8
V
150
A
2
A
VOUT = 200mVP-P, CL = 1.6pF
1.0
GHz
VOUT = 2VP-P, CL = 23.6pF, RS = 25
235
MHz
VOUT = 200mVP-P, CL = 1.6pF
100
MHz
VOUT = 2VP-P, CL = 23.6pF, RS = 25
35
MHz
AC GENERAL
-3dB BW
0.1dB BW
-3dB Bandwidth
0.1dB Bandwidth
dG
Differential Gain Error
NTC-7, RL = 150
0.01
%
dP
Differential Phase Error
NTC-7, RL = 150
0.02
°
+SR
Slew Rate
25% to 75%, VOUT = 5V,
RL = 525, CL = 23.6pF
1452
V/s
-SR
Slew Rate
25% to 75%, VOUT = 5V,
RL = 525, CL = 23.6pF
1124
V/s
2
FN7452.4
January 5, 2007
ISL59442
Electrical Specifications
PARAMETER
V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, Input Video = 1VP-P and RL = 500 to GND, VHIZ = 0.8V,
Unless Otherwise Specified (Continued)
DESCRIPTION
CONDITIONS
PSRR
Power Supply Rejection Ratio
DC, PSRR V+ and V- combined
V± = ±4.5V to ±5.5V
ISO
Channel Isolation
f = 10MHz, Ch-Ch X-Talk and Off Isolation,
CL = 1.6pF
MIN
TYP
MAX
UNIT
-50
-57
dB
75
dB
2
mVP-P
135
mVP-P
SWITCHING CHARACTERISTICS
VGLITCH
Channel-to-Channel Switching Glitch VIN = 0V, CL = 23.6pF, RS = 25
HIZ Switching Glitch
VIN = 0V, CL = 23.6pF, RS = 25
tSW-L-H
Channel Switching Time Low to High 1.2V logic threshold to 10% movement of
analog output
30
ns
tSW-H-L
Channel Switching Time High to Low 1.2V logic threshold to 10% movement of
analog output
28
ns
VOUT = 200mVP-P, CL = 1.6pF
0.69
ns
VOUT = 2VP-P, CL = 23.6pF, RS = 25
1.4
ns
TRANSIENT RESPONSE
tr, tf
Rise and Fall Time, 10% to 90%
tS
0.1% Settling Time
VOUT = 2VP-P, CL = 23.6pF, RS = 25
6.6
ns
tPLH
Propagation Delay - Low to High,
10% to 10%
VOUT = 200mVP-P, CL = 1.6pF
0.46
ns
VOUT = 2VP-P, CL = 23.6pF, RS = 25
0.92
ns
Propagation Delay- High to Low,
10% to 10%
VOUT = 200mVP-P, CL = 1.6pF
0.52
ns
VOUT = 2VP-P, CL = 23.6pF, RS = 25
0.97
ns
Overshoot
VOUT = 200mVP-P, CL = 1.6pF
8.3
%
VOUT = 2VP-P, CL = 23.6pF, RS = 25
13.3
%
tPHL
OS
Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = +25°C, unless otherwise specified.
5
5
3
NORMALIZED GAIN (dB)
4 VOUT = 200mVP-P
CL = 1.6pF
3
VOUT = 200mVP-P
CL = 9.7pF
2
NORMALIZED GAIN (dB)
4
CL = 7.2pF
1
0
-1
CL = 5.5pF
-2
CL = 1.6pF
-3
-4
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-5
0.001
RL = 1k
2
1
RL = 500
0
-1
-2
RL = 150
-3
RL = 75
-4
0.01
0.1
1 1.5
FREQUENCY (GHz)
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL
3
-5
0.001
0.01
0.1
1 1.5
FREQUENCY (GHz)
FIGURE 2. SMALL SIGNAL GAIN vs FREQUENCY vs RL
FN7452.4
January 5, 2007
ISL59442
Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = +25°C, unless otherwise specified.
5
4
5
VOUT = 2VP-P
RS = 25
4
3
2
1
CL = 11.6pF
CL = 16.6pF
0
-1
-2
CL = 23.6pF
-3
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-5
0.001
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
3
-4
2
1
RL = 1k
0
RL = 75
-1
-2
RL = 500
-3
RL = 150
-4
CL = 28.6pF
0.01
VOUT = 2VP-P
CL = 23.6pF
RS = 25
0.1
-5
0.001
1 1.5
0.01
FREQUENCY (GHz)
0.5
0.2
0.1
0.0
CL = 7.2pF
0.2
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
0.3
CL = 5.5pF
0.1
0
-0.1
-0.2
-0.3
-0.4
CL = 1.6pF
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-0.5
0.001
0.01
0.1
-0.1
-0.2
-0.3
RL = 1k
-0.4
-0.5
RL = 500
-0.6
-0.7
-0.8
0.001
1 1.5
1 1.5
0.1
0.5
0.4
0.4
CL = 16.6pF
0.2
0.1
0
-0.1
CL = 23.6pF
VOUT = 2VP-P
RS = 25
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-0.5
0.001
CL = 28.6pF
0.01
0.1
0.3
VOUT = 2VP-P
CL = 23.6pF
RS = 25
RL = 1k
RL = 500
0.2
0.1
RL = 150
0
RL = 75
-0.1
-0.2
-0.3
-0.4
1 1.5
FREQUENCY (GHz)
FIGURE 7. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs CL
4
NORMALIZED GAIN (dB)
CL = 11.6pF
0.3
NORMALIZED GAIN (dB)
0.01
FIGURE 6. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs RL
0.5
-0.4
RL = 75
FREQUENCY (GHz)
FIGURE 5. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs CL
-0.3
RL = 150
VOUT = 200mVP-P
CL = 1.6pF
FREQUENCY (GHz)
-0.2
1 1.5
FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs RL
CL = 9.7pF
VOUT = 200mVP-P
0.1
FREQUENCY (GHz)
FIGURE 3. LARGE SIGNAL GAIN vs FREQUENCY vs CL
0.4
(Continued)
-0.5
0.001
0.01
0.1
1 1.5
FREQUENCY (GHz)
FIGURE 8. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs RL
FN7452.4
January 5, 2007
ISL59442
Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = +25°C, unless otherwise specified.
(Continued)
-10
20
10
0
VIN = 200mVP-P
CL = 23.6pF
RS = 25
-30
-40
-10
-50
-20
(dB)
PSRR (dB)
VIN = 1VP-P
CL = 23.6pF
RS = 25
-20
-30
-60
CROSSTALK
-70
-40
-80
-50
PSRR (V+)
-90
-60
PSRR (V-)
-70
-80
0.3M
1M
10M
OFF ISOLATION
-100
100M
1G
-110
0.001
0.01
1
0.1
3
6 10
100
500
FREQUENCY (MHz)
FREQUENCY (Hz)
FIGURE 10. CROSSTALK AND OFF ISOLATION
FIGURE 9. PSRR CHANNELS
100
60
INPUT VOLTAGE NOISE (nV/Hz)
OUTPUT RESISTANCE ()
VOUT = 100mVP-P
10
1
RF = 500
50
40
30
20
10
0.1
0.1M
1M
10M
100M
0
1G
1k
0.1k
FREQUENCY (Hz)
FREQUENCY (Hz)
0
0
THD (dBc)
-30
HARMONIC DISTORTION (dBc)
V+ = 5V, V- = -5V
-10 VOUT = 2VP-P
WORST CHANNEL
-20
RL = 75
-40
RL = 150
-60
-70
-80
-90
RL = 350
0.1M
1M
100k
FIGURE 12. INPUT NOISE vs FREQUENCY
FIGURE 11. ROUT vs FREQUENCY
-50
10k
10M
FREQUENCY (Hz)
-30
H2, RL = 75
H3, RL = 75
H2, RL = 150
-40
-50
H2, RL = 350
-60
-70
H3, RL = 150
-80
-90
100M
FIGURE 13. THD vs FREQUENCY
5
V+ = 5V, V- = -5V
-10 VOUT = 2VP-P
WORST CHANNEL
-20
1G
-100
0.1M
H3, RL = 350
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 14. HARMONIC DISTORTION vs FREQUENCY
FN7452.4
January 5, 2007
ISL59442
Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = +25°C, unless otherwise specified.
S0, S1
1V/DIV
1V/DIV
S0, S1
0
500mV/DIV
20mV/DIV
0
0
VOUT
VOUT
0
20ns/DIV
20ns/DIV
FIGURE 15. CHANNEL TO CHANNEL SWITCHING GLITCH
VIN = 0V, RS = 25, CL = 23.6pF
FIGURE 16. CHANNEL TO CHANNEL TRANSIENT RESPONSE
VIN = 1V, RS = 25, CL = 23.6pF
HIZ
1V/DIV
1V/DIV
HIZ
0
400mV/DIV
100mV/DIV
0
0
VOUT
VOUT
0
20ns/DIV
20ns/DIV
FIGURE 17. HIZ SWITCHING GLITCH VIN = 0V, RS = 25,
CL = 23.6pF
FIGURE 18. HIZ TRANSIENT RESPONSE VIN = 1V, RS = 25,
CL = 23.6pF
160
2.4
CL = 1.6pF
RL = 500
120
80
2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
(Continued)
40
0
-40
-80
1.6
1.2
0.8
0.4
0
-0.4
-120
-160
-0.8
TIME (4ns/DIV)
FIGURE 19. SMALL SIGNAL TRANSIENT RESPONSE
6
CL = 23.6pF
RS = 25
RL = 500
TIME (4ns/DIV)
FIGURE 20. LARGE SIGNAL TRANSIENT RESPONSE
FN7452.4
January 5, 2007
ISL59442
Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = +25°C, unless otherwise specified.
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
0.9
1.136W
1.2
1

JA
0.8
SO
=8
8°
C
0.6
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1.4
(Continued)
14
/W
0.4
0.2
0.8
0.7
833mW
0.6

0.5
JA
=
SO
12
0.4
14
0°
C
0.3
/W
0.2
0.1
0
0
25
50
75 85
100
125
0
150
0
AMBIENT TEMPERATURE (°C)
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Pin Descriptions
PIN NUMBER
PIN NAME
EQUIVALENT
CIRCUIT
1
IN0
Circuit 1
2, 6, 9
NIC
3
IN1
Circuit 1
Input for channel 1
4
GND
Circuit 4
Ground pin
5
IN2
Circuit 1
Input for channel 2
7
IN3
Circuit 1
Input for channel 3
8
V-
Circuit 4
Negative power supply
10
OUT
Circuit 3
Output
11
HIZ
Circuit 2
Output disable (active high); there are internal pull-down resistors, so the
device will be active with no connection; "HI" puts the output in high
impedance state.
12
S1
Circuit 2
Channel selection pin MSB (binary logic code)
13
S0
Circuit 2
Channel selection pin LSB (binary logic code)
14
V+
Circuit 4
Positive power supply
DESCRIPTION
Input for channel 0
Not Internally Connected; it is recommended this pin be tied to ground to
minimize crosstalk.
V+
IN
V+
LOGIC PIN
33k
V-
+
1.2V
-
GND.
V-
CIRCUIT 1.
CIRCUIT 2.
V+
OUT
V-
CIRCUIT 3.
7
21k
V+
GND
CAPACITIVELY
COUPLED
ESD CLAMP
VCIRCUIT 4.
FN7452.4
January 5, 2007
ISL59442
AC Test Circuits
ISL59442
ISL59442
VIN
CL
2pF
50
or
75
RL
500
TEST EQUIPMENT
RS
VIN
50
or
75
CL
2pF
475
50
or
75
50
or
75
FIGURE 23B. TEST CIRCUIT FOR MEASURING WITH A 50 OR 75
FIGURE 23A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
INPUT TERMINATED EQUIPMENT
ISL59442
TEST EQUIPMENT
RS
VIN
50
or
75
CL
2pF
50 or 75
50
or
75
FIGURE 23C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500 WILL BE
DEGRADED
NOTE: Figure 23A illustrates the optimum output load for testing AC performance. Figure 23B illustrates the optimum output load when connecting
to input terminated equipment. Figure 23C illustrates back loaded test circuit for video cable.
Application Circuits
*CL = CT + COUT
VIN
VOUT
+
COUT
CT
1.6pF
50
0pF
RL = 500
*CL: TOTAL LOAD CAPACITANCE
CT: TRACE CAPACITANCE
COUT: OUTPUT CAPACITANCE
FIGURE 24A. SMALL SIGNAL 200mVP-P APPLICATION CIRCUIT
RS
25
VIN
+
50
1.6pF
CT
VOUT
COUT
22pF
RL = 500
CL = CT + COUT
FIGURE 24B. LARGE SIGNAL 2VP-P APPLICATION CIRCUIT
8
FN7452.4
January 5, 2007
ISL59442
Application Information
Power-Up Considerations
The ESD protection circuits use internal diodes from all pins the
V+ and V- supplies. In addition, a dV/dT- triggered clamp is
connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the Pin Description
table. The dV/dT triggered clamp imposes a maximum supply
turn-on slew rate of 1V/µs. Damaging currents can flow for
power supply rates-of-rise in excess of 1V/µs, such as during
hot plugging. Under these conditions, additional methods
should be employed to ensure the rate of rise is not exceeded.
General
The ISL59442 is a 4:1 mux that is ideal as a matrix element in
high performance switchers and routers. The ISL59442 is
optimized to drive a 2pF in parallel with a 500 load. The
capacitance can be split between the PCB capacitance an and
external load capacitance. Their low input capacitance and high
input resistance provide excellent 50 or 75 terminations.
Capacitance at the Output
The output amplifier is optimized for capacitance to ground
(CL) directly on the output pin. Increased capacitance
causes higher peaking with an increase in bandwidth. The
optimum range for most applications is ~1.0pF to ~6pF. The
optimum value can be achieved through a combination of
PC board trace capacitance (CT) and an external capacitor
(COUT). A good method to maintain control over the output
pin capacitance is to minimize the trace length (CT) to the
next component, and include a discrete surface mount
capacitor (COUT) directly at the output pin.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic
input pins. Schottky diodes (Motorola MBR0550T or
equivalent) connected from V+ to ground and V- to ground
(Figure 25) will shunt damaging currents away from the
internal V+ and V- ESD diodes in the event that the V+
supply is applied to the device before the V- supply.
For large signal applications where overshoot is important
the circuit in Figure 24B should be used. The series resistor
(RS) and capacitor (CL) form a low pass network that limits
system bandwidth and reduces overshoot. The component
values shown result in a typical pulse response shown in
Figure 20.
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through
the ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and
analog inputs is needed to prevent damage during the time
the voltages on these inputs are more positive than V+.
Ground Connections
HIZ State
For the best isolation and crosstalk rejection, the GND pin
and NIC pins must connect to the GND plane. The NIC pins
are placed on both sides of the input pins. These pins are
not internally connected to the die. It is recommended this
pin be tied to ground to minimize crosstalk.
An internal pull-down resistor connected to the HIZ pin ensures
the device will be active with no connection to the HIZ pin. The
HIZ state is established within approximately 30ns by placing a
logic high (>2V) on the HIZ pin. If the HIZ state is selected, the
output is a high impedance 1.4M. Use this state to control the
logic when more than one mux shares a common output.
Control Signals
In the HIZ state the output is three-stated, and maintains its
high Z even in the presence of high slew rates. The supply
current during this state is basically the same as the active
state.
S0, S1, HIZ - These pins are, TTL/CMOS compatible control
inputs. The S0, S1 pins select which one of the inputs
connect to the output. The HIZ pin is used to three-state the
output amplifiers. For control signal rise and fall times less
than 10nsec the use of termination resistors close to the part
will minimize transients coupled to the output.
V+ SUPPLY
SCHOTTKY
PROTECTION
LOGIC
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than 50mA.
Adequate thermal heat sinking of the parts is also required.
V+
LOGIC
CONTROL
S0
POWER
GND
GND
SIGNAL
IN0
EXTERNAL
CIRCUITS
V+
V-
V+
V+
V+
OUT
V-
DE-COUPLING
CAPS
IN1
VV-
V-
V- SUPPLY
FIGURE 25. SCHOTTKY PROTECTION CIRCUIT
9
FN7452.4
January 5, 2007
ISL59442
PC Board Layout
The frequency response of this circuit depends greatly on
the care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners, use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
degraded for traces greater than one inch, unless strip
lines are used.
• Match channel-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• Maximize use of AC de-coupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e.
no split planes or PCB gaps under these lines). Avoid vias
in the signal I/O lines.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
• Minimum of 2 power supply de-coupling capacitors are
recommended (1000pF, 0.01µF) as close to the devices
as possible. Avoid vias between the cap and the device
because vias add unwanted inductance. Larger caps can
be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
• The NIC pins are placed on both sides of the input pins.
These pins are not internally connected to the die. It is
recommended these pins be tied to ground to minimize
crosstalk.
10
FN7452.4
January 5, 2007
ISL59442
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
SO-8
SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
N
8
14
16
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN7452.4
January 5, 2007
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