an1235

ISL59481EVAL1 Evaluation Board
User’s Guide
®
Application Note
Introduction
The ISL59481EVAL1 evaluation board contains the ISL59481
Dual 4:1 RGB MUX amp and associated components needed
to implement an 8:1 RGB+H/V sync video multiplexer. The 8
video input ports, and single output port are accessed using
standard 15 pin VGA female connectors. The I/O connectors
are compatible with most VGA, SVGA and XGA video
sources and video monitors with VGA cable interfaces. A
typical application would use the ISL59481EVAL1 board to
multiplex anywhere from 2 to 8 PC’s or laptops to a single
video monitor or projector.
Evaluation Board Description and Key Features
The multiplexing of the RGB video is performed by the
ISL59481. Multiplexing the H and V sync signals is
accomplished using two ISL84051 8:1 analog switches. The
ISL59481 Video MUX and the analog H and V sync
multiplexers have the same input channel select logic
coding, and are parallel-connected to form a single 3 input
binary coded interface (S0, S1, S2). The evaluation board
contains three different channel select options via jumpers
on the board. Switches on the board enable direct logic
control in binary format. The on-board oscillator and 4-bit
counter can be connected to provide a continuous channel-
February 2, 2006
AN1235.0
by-channel scan of as few as 2 input channels up to all 8. An
added option allows the user to disconnect the auto-scan
oscillator and use the on-board momentary-contact switch to
manually scan through the selected channels.
Reference Documents
• ISL59481 Data Sheet, FN7456
Getting Started
The evaluation board should have the same appearance as
the silk screen shown in Figure 1. Prior to applying power,
connect the source input VGA cables and the evaluation
board output VGA cable to the respective video
components. The evaluation board, as supplied, is designed
for 75Ω source impedances and requires a 75Ω termination
impedance in the output display device.
Applying Power to the Evaluation Board
The following safeguards will ensure correct power-up.
1. Limit the current on ±5V supplies to 250mA.
2. Turn on the power supplies after the power cables are
attached to the evaluation board.
Power supply protection Schottky diodes are included on the
±5V supplies to prevent damage due to reverse polarity.
Evaluation Board Jumper, Cable Header, and Switch Descriptions
COMPONENT
DESCRIPTION
JUMPERS
J1
Selects channel select via single-step momentary contact switch S4, or auto mode using on-board oscillator
J-S0
Selects S0 logic input to manual control via switch S0 or through external control ribbon cable header
J-S1
Selects S1 logic input to manual control via switch S1 or through external control ribbon cable header
J-S2
Selects S2 logic input to manual control via switch S2 or through external control ribbon cable header
HEADERS
EN
External MUX enable: Internal pull-down (logic 0) enables RGB+H/V output, logic high disables RGB and H/V sync output
S0
External S0 channel select logic input
S1
External S1 channel select logic input
S2
External S2 channel select logic input
SWITCHES
S0
Manual channel select logic input S0
S1
Manual channel select logic input S1
S2
Manual channel select logic input S2
S3
Momentary contact channel select step control
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1235
FIGURE 1. ISL59481EVAL1 TOP VIEW
Testing the Evaluation Board
Testing the video and sync signal paths is accomplished
using 1 or more RGB+H/V test video sources and a video
monitor as the measurement device. Before powering the
board, connect the jumpers as follows:
2
1. Connect jumpers J-S0, J-S1 and J-S2 to the MANUAL
position (center to right post).
2. Connect jumper J1 to the single-step position (center to
left post).
AN1235.0
February 2, 2006
Application Note 1235
The following tests should be performed in the order shown.
Power Supply Tests
1. Connect an ammeter in series with the +5V and -5V
supply.
2. Connect power supplies to the respective +5V, -5V and
ground banana jacks.
set to 2.3 to compensate for the interstage and output
impedance matching loss. Two methods of gain adjustment
are provided. Increasing gain to compensate for cable
attenuation can be accomplished using the EL5364 Rf and
Rg gain resistors. Gain reduction is best achieved using the
divider network Rs and Rt. Capacitor pads (Cnp) are
provided to adjust the frequency response of the amplifier.
3. Set supplies to +5V; ±50mV and -5V; ±50mV. Supply
power to the board.
4. Measure +5V supply current = +110mA ±20mA
ISL59481
RS, 75Ω
+1
VIN
5. Measure -5V supply current = -100mA ±20mA
Channel Select Logic and Video Performance Test
1. Calibrate the video test source with the video monitor by
connecting the source(s) to the video monitor and
selecting a display suitable for verifying correct
luminance, display resolution and H/V sync lock. The test
display in the following evaluation board tests should be
identical to the test display.
2. Re-connect the video monitor to the VIDEO_OUT VGA
connector on the evaluation board.
3. Connect the video test source to IN0. Additional video
sources can speed up the verification process. If more
than 1 test source is available connect each in sequential
fashion to IN1, IN2 etc.
4. Set switches S0, S1 and S2 to the GND position and
apply power.
5. After ~3s the test display supplied to IN0 should appear
on the test monitor exactly as it appeared in step 1.
Cnp*
75Ω
1/3 EL5364
Rt,
499Ω
Rg
432Ω
75Ω
+
-
VOUT
Rf
562Ω
* Cnp is not populated and is provided for
frequency response adjustment
FIGURE 2. VIDEO SIGNAL PATH
Channel Select Logic
The ISL59481 RGB MUX and the H/V sync MUX share the
same 1 of 8 input channel select logic inputs (S0, S1, S2).
The channel select logic is shown in Table 1. Three methods
of channel select logic control are provided using jumpers.
TABLE 1. CHANNEL SELECT TRUTH TABLE
S2
S1
S0
VIDEO OUT
0
0
0
IN0
0
0
1
IN1
NOTE: The ~3s delay is a built in delay common in many display
devices to lock onto the H/V sync signals and adjust the picture prior
to enabling the display screen.
0
1
0
IN2
0
1
1
IN3
6. Perform the display test on the remaining video inputs by
moving the video input source to the appropriate input
according to the truth table in Table 1.
1
0
0
IN4
1
0
1
IN5
1
1
0
IN6
1
1
1
IN7
Auto-Scan Test
1. Connect scope probe to the J1 AUTO pin and observe a
logic level (0 to +5V) square wave with ~3s period.
2. Connect jumpers J-S0, J-S1, and J-S2 to the AUTO
position (center to left post).
3. Connect jumper J1 to the AUTO position and observe
that the display scans all the test sources connected to
the input channels (center to right post).
4. Connect jumper J1 to the single-step position and use the
momentary contact switch S4 to manually all the test
sources.
Test completed.
RGB Video Signal Path
Auto Sequencing Using the On-Board
Oscillator
An on-board 0.3Hz R-C oscillator (Figure 3) drives the
master clock of the 4-bit binary counter, which generates the
channel select logic inputs S0, S1 and S2. The default 6s
channel scan rate provides the time needed by the display to
sync-lock and adjust the picture prior to enabling the display.
The 2.2MΩ (R1) resistor value can be reduced to speed up
the channel scan time. Jumper J1 is provided to select either
the 6s auto-step timer, or the momentary contact switch for
manual stepping.
The video inputs are terminated with 75Ω resulting in an
overall RGB video path gain of 1 when using 75Ω video
source impedance and load terminations (Figure 2). The
RGB outputs contain series-connected 75Ω backtermination resistors for cable driving. The ISL59481
operates in unity gain, and the EL5364 triple op amp gain is
3
AN1235.0
February 2, 2006
Application Note 1235
J1
SINGLESTEP
AUTOSTEP
S4
MOMENTARY
CONTACT SWITCH
internal channel scan is enabled. The MANUAL position
connects the on-board SPDT switches (S0, S1, and S2) for
manual selection. A parallel-connected EXTERNAL
CONTROL ribbon cable header is provided for external
channel select control.
TO BINARY
COUNTER CLK
R1
2.2M
5
A wide range of auto-scan options can be selected by
connecting only 1 or 2 of the 3 jumpers to the internal logic,
with the remainder connected to the switch. For example,
connecting jumper J-S0 to the AUTO position and
connecting jumpers J-S1 and J-S2 to the MANUAL position
with the switches S1 and S2 to the logic 0 state limits the
channel scan to only 2 of the 8 channels (IN0 and IN1).
Moving a second jumper from the MANUAL position to the
AUTO position, increases the number of channels scanned
from 2 to 4. The complete list of channel scan jumper
options are shown in Table 2.
6
U4C
C1
1µF
FIGURE 3. CHANNEL SCAN OSCILLATOR
Internal and External Channel Select
Logic
J-S0, J-S1 and J-S2 are two-position jumpers that control
the method of channel selection. In the AUTO position, the
TABLE 2. CHANNEL SCAN SELECT LOGIC TABLE
JUMPER POSITION
SWITCH POSITION
CHANNELS SELECTED
CHANNELS
SCANNED
J-S2
J-S1
J-S0
S2
S1
S0
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
8
Auto
Auto
Auto
-
-
-
X
X
X
X
X
X
X
X
4
Manual
Auto
Auto
0
-
-
X
X
X
X
Manual
Auto
Auto
1
-
-
X
X
X
X
Auto
Manual
Auto
-
0
-
X
X
Auto
Manual
Auto
-
1
-
X
X
Auto
Auto
Manual
-
-
0
Auto
Auto
Manual
-
-
1
Manual Manual
Auto
0
0
-
Manual Manual
Auto
0
1
-
Manual Manual
Auto
1
0
-
Manual Manual
Auto
1
1
-
2
Auto
Manual Manual
-
0
0
Auto
Manual Manual
-
0
1
Auto
Manual Manual
-
1
0
Auto
Manual Manual
-
1
1
Manual
Auto
Manual
0
-
0
Manual
Auto
Manual
0
-
1
Manual
Auto
Manual
1
-
0
Manual
Auto
Manual
1
-
1
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
AN1235.0
February 2, 2006
Application Note 1235
10kΩ
75Ω
75Ω
10kΩ
75Ω
IN2C1
IN2B1
IN2A1
75Ω
IN3C1
IN3B1
IN3A1
75Ω
R
1
G
2
B
3
4
N.C.
NP
5
6
7
8
9
N.C.
10
N.C.
11
N.C.
12
H-Sync
13
14 V-Sync
15
N.C.
75Ω
75Ω
Input IN5
IN1X2
IN1-G
IN1-B
IN2-R
IN2-G
IN2-B
IN3-R
IN3-G
IN3-B
432Ω
562Ω
75Ω
IN1C1
IN1B1
IN1A1
75Ω
75Ω
Video Out
Input IN1
(IN1X1)
R
1
G
2
B
3
4
N.C.
5
6
7
8
N.C.
9
10
N.C.
11
N.C.
12
H-Sync
13
V-Sync
14
15
N.C.
Input IN2
(IN2X1)
R
1
G
2
B
3
4
N.C.
5
6
7
8
N.C.
9
10
N.C.
11
N.C.
12
H-Sync
13
V-Sync
14
15
N.C.
Input IN3
(IN3X1)
R
1
G
2
B
3
4
N.C.
5
6
7
8
N.C.
9
10
N.C.
11
N.C.
12
H-Sync
13
V-Sync
14
15
N.C.
ISL59481EVAL1 Schematic Diagram
-
U6A
EL5364
IN1B1 37
GND 39
IN1C1 38
IN2B1 41
IN2A1 40
IN5-G
IN1A2 32
IN5-R
+
IN0A2 30
IN4-R
8 IN0C1
IN0B2 29
IN4-G
9 IN0B1
IN0C2 28
IN4-B
V2+ 25
75Ω
24 OUTA2
EN2 26
12 IN1A1
23 V2-
11 GND
13 IN2B2
IN1-R
HIZ2 27
22 OUTB2
IN0C1
IN0B1
IN0A1
10 IN0A1
21 OUTC2
IN0-R
16 IN3A2
IN0-G
15 GND
Input IN0
(IN0X1)
14 IN2C2
IN0-B
Input IN4
IN0X2
75Ω
75Ω
75Ω
IN3-R
IN3-G
IN3-B
IN6-G
IN6-B
75Ω
R 1
G 2
B 3
75Ω
4
N.C.
5
6
7
8
9
N.C.
10
N.C. 11
N.C.
12
H-Sync 13
V-Sync 14
15
N.C.
GND 31
U1
ISL59481
7 HIZ1
1
2
3
4
N.C. 75Ω
5
6
7
8
9
N.C.
10
N.C.
11
N.C.
12
H-Sync
13
V-Sync
14
15
N.C.
GND 43
IN1B2 33
5 V1+
6 EN1
0Ω
499Ω
R
G
B
IN2C1 42
4 OUTA1
20 S0-2
75Ω
IN5-B
19 S1-2
-
U6C
75Ω
432Ω
75Ω
IN1C2 34
3 V1-
18 IN3C2
562Ω
75Ω
75Ω
NP
75Ω
IN6-R
GND 35
17 IN3B2
0Ω
499Ω
IN2A2 36
2 OUTB1
+
NP
IN3A1 44
1 OUTC1
-
U6B
IN3B1 45
75Ω
S1-1 47
0Ω
432Ω
IN3C1 46
NP
SO-1 48
499Ω
562Ω
75Ω
NP
+
75Ω
R
1
G 2
B
3
75Ω
4
N.C.
5
6
7
8
9
N.C.
10
N.C. 11
N.C.
12
H-Sync
13
V-Sync
14
15
N.C.
75Ω
13
V+ (+5V)
U4F
12
GND
V- (-5V)
EN
NO1
U4C
12 NO6
11 ADDC
6
LOGIC
7
8
U2
H-SYNC
NO7
NO5
INH
10 ADDB
V-
9 ADDA
GND
ISL84051
13 NO0
5
6
7
8
LOGIC
12 NO6
11 ADDC
10 ADDB
U3
V-SYNC
9 ADDA
ISL84051
J-S2
V+
0Ω 3
0Ω 9
GND
14 V+
U4A
U4B
U4D
2
10kΩ
4
10kΩ
0Ω 11
U4E
10kΩ
10
0Ω
10kΩ
Input IN6
(IN2X2)
75Ω
75Ω
75Ω
75Ω
75Ω
8
6
IN3A2
IN3B2
IN3C2
75Ω
IN2A2
IN2B2
IN2C2
Input IN7
(IN3X2)
N.C.
7
N.C.
N.C.
H-Sync
V-Sync
5
1µF
5
14 NO4
4
N.C.
2.2M
GND
J-S1
0Ω 1
Autostep
U4A
S4
Manual
13 NO0
N.C.
QD 11
8 GND
V-
J-S0
4
15 NO2
3
R
G
B
QC 12
INH
COM
16 V+
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
QB 13
74HC161D
J1
Singlestep
Auto
RCO 15
QA 14
U5
4.7k
NO5
14 NO4
N.C.
4.7k
16 V+
1 Reset
2 CLK
3 P0
4 P1
5 P2
6 P3
7 ENP
9 LD
10 ENT
V+
NO7
S2
3
1
N.C.
4.7k
COM
NO3
N.C.
N.C.
H-Sync
V-Sync
S1
4.7k
External
Control
NO1
15 NO2
N.C.
4.7k
EN
S0
S1
S2
16 V+
2
R
G
B
S0
4.7k
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
4.7k
NO3
74HC14D
5
AN1235.0
February 2, 2006
Application Note 1235
ISL59481EVAL1 Components List
COMPONENT
PWB
VALUE
TOLERANCE RATING
ISL59481EVAL1RE Intersil Corp.
VA PCB
COMPONENT
VALUE
TOLERANCE
RATING
N/A
J-S0, J-S1, J-S2, J1
CONN-HEADER,
1x3, BRKAWY
1X36, 0.1
N/A
N/A
N/A
DIODERECTIFIER, SMD
SOD-123, 2PIN
N/A
U1 - 8:1 RGB Video ISL59481IRZA
MUX
QFN48 Pb-Free
Intersil Corp.
N/A
D1, D2
U2, U3 - 8:1 Analog ISL84051IBZ
MUX
SOIC16 Pb-Free
Intersil Corp.
N/A
R3-R5, R55-58, R64-R66 RESISTOR, SMD, MBR0540T1-T
0805, DNP, DNP,
DNP, TF
U4 - Hex Inverter
SN74HC14D
SOIC14
N/A
N/A
R10-R12
RESISTOR, SMD, N/A
0603, 75Ω
N/A
U5 - 4-Bit Binary
Counter
SN74HC161D
SOIC16
N/A
N/A
R62, R67, R73
RESISTOR, SMD, 1%
0603, 432Ω
0.10W
U6 - Triple 600MHz EL5364ISZ SOIC16 Intersil Corp.
CFA Op Amp
Pb-Free
N/A
R63, R71, R72
RESISTOR, SMD, 1%
0603, 562Ω
0.10W
C4, C7
CAP, SMD, 0603
1000pF
25V
R6-R9, R16, R21-R29,
RESISTOR, SMD, 1%
R32, R35, R38, R43-R49 0805, 75Ω,
1/10W
C2, C5, C8-C13,
C21, C22
CAPACITOR, SMD, N/A
0603, 0.1µF
25V
R13-R15, R17-R20, R33, RESISTOR, SMD, N/A
R34, R39, R68-R70
0805, 0Ω,
1/10W
C3, C6
CAPACITOR, SMD, 10%, X5R
0805, 10µF
6.3V
R42, R50-R54.
RESISTOR, SMD, 5%
0805, 10k
1/10W
C1
CAPACITOR, SMD, 10%, X5R
0805, 2.2µF
16V
R1
RESISTOR, SMD, 5%
0805, 2.2M
1/8W
C14-C20
CAPACITOR, SMD, N/A
0805, DNP-PLACE
HOLDER
N/A
R2, R30, R31, R36, R37, RESISTOR, SMD, 5%
R40, R41
0805, 4.7k
1/10W
IN0-IN7,
VIDEO_OUT
CONN-SUB MINI D, N/A
15PIN,
RECEPTACLE, RT
ANGLE, FRONT
METAL SHELL
N/A
R59, R60, R61
RESISTOR, SMD, 5%
0805, 499
1/10W
+5V, -5V, EN, GND
N/A
CONN-JACK,
BANA-SSSDRLESS, VERTIC
N/A
S0-S2
SWITCHTOGGLE, THRU,
SPDT, 5 P, ON-N
N/A
N/A
J2
J2
CONN-HEADER,
4PIN, BRKAWY,
2.54mm, VERTICAL
S3
SWITCHPUSHBUTTON,
TH, 6mm, 4P,
ON/OFF,
N/A
12V, 0.05A
10%, X7R
40V, 0.5A
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
6
AN1235.0
February 2, 2006
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