DATASHEET

ISL59483
®
Data Sheet
May 21, 2007
Dual, 500MHz Triple, Multiplexing
Amplifiers
FN6394.2
Features
The ISL59483 contains a gain of 1 triple 4:1 MUX amplifier
(MUX1), and a second gain of 2 triple 4:1 MUX amplifier
(MUX2). Each feature high slew rate and excellent
bandwidth for RGB video switching. They contain separate
binary coded, channel select logic inputs (S0, S1), and
separate logic inputs for High Impedance output (HIZ) and
power-down (EN) modes. The HIZ state presents a high
impedance at the output so that both RGB MUX outputs can
be wired together to form an 8:1 RGB MUX amplifier or they
can be used in R-R, G-G, and B-B pairs to form a 4:1
differential input/output MUX. Separate power-down mode
controls (EN1, EN2) are included to turn off unneeded
circuitry in power sensitive applications. With both EN pins
pulled high, the ISL59483 enters a standby power mode,
consuming just 36mW.
• Separate gain of 1 and gain of 2, triple 4:1 multiplexers for
RGB
• Externally configurable for various video MUX circuits
including
- 8:1 RGB MUX with selectable gains of 1 or 2
- Two separate 4:1 RGB MUX with gains of 1 and 2
• High impedance outputs (HIZ)
• Power-down mode (EN)
• ±5V operation
• ±870V/µs slew rate (G = 1), ±1600V/µs slew rate (G = 2)
• 500MHz bandwidth
• Supply current 16mA/CH
• Pb-free plus anneal (RoHS compliant)
Applications
Ordering Information
• HDTV/DTV analog inputs
PART
NUMBER
(Note)
ISL59483IRZ
PART
MARKING
TAPE &
REEL
ISL59483 IRZ
-
48 Ld Exposed L48.7x7B
Pad 7x7 QFN
13”
48 Ld Exposed L48.7x7B
Pad 7x7 QFN
ISL59483IRZ-T13 ISL59483 IRZ
PACKAGE
(Pb-free)
PKG.
DWG. #
• Video projectors
• Computer monitors
• Set-top boxes
• Security video
• Broadcast video equipment
ISL59483EVAL1Z Evaluation PCB
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
TABLE 1. CHANNEL SELECT LOGIC TABLE ISL59483
S1-1, 2
S0-1, 2
EN1, EN2
HIZ1, 2
OUTPUT1, 2
0
0
0
0
IN0 (A, B, C)
0
1
0
0
IN1 (A, B, C)
1
0
0
0
IN2 (A, B, C)
1
1
0
0
IN3 (A, B, C)
X
X
1
X
Power-down
X
X
0
1
High Z
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006, 2007. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59483
Pinout
OUTC1 1
37 IN1B1
38 INIC1
39 GND
40 IN2A1
41 IN2B1
42 IN2C1
43 GND
44 IN3A1
45 IN3B1
46 IN3C1
47 S1-1
48 S0-1
ISL59483
(48 LD QFN)
TOP VIEW
+1
36 IN2A2
0
OUTB1 2
35 GND
+1
V1- 3
OUTA1 4
34 IN1C2
0
33 IN1B2
+1
0
V1+ 5
32 IN1A2
THERMAL
PAD
EN1 6
31 GND
HIZ1 7
30 IN0A2
IN0C1 8
29 IN0B2
IN0B1 9
28 IN0C2
IN0A1 10
27 HIZ2
+2
OUTB2 22
OUTC2 21
S0-2 20
S1-2 19
IN3C2 18
IN3B2 17
IN3A2 16
PAD MUST BE TIED TO V-
GND 15
CONNECTED TO V-
IN2C2 14
IN2B2 13
+2
0
+2
26 EN2
25 V2+
OUTA2 24
IN1A1B 12
THERMAL PAD INTERNALLY
0
0
V2- 23
GND 11
Functional Diagram ISL59483
EN0-1
S0-1
EN1-1
S1-1
IN0(A1, B1, C1)
IN1(A1, B1, C1)
DECODE1
EN2-1
IN2(A1, B1, C1)
x1
OUT(A1, B1, C1)
IN3(A1, B1, C1)
EN3-1
AMPLIFIER1 BIAS
HIZ1
EN1
EN0-2
S0-2
EN1-2
S1-2
IN0(A2, B2, C2)
IN1(A2, B2, C2)
DECODE2
EN2-2
IN2(A2, B2, C2)
OUT(A2, B2, C2)
x2
IN3(A2, B2, C2)
EN3-2
AMPLIFIER2 BIAS
HIZ2
EN2
2
FN6394.2
May 21, 2007
ISL59483
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Digital and Analog Input Current (Note 1) . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V1+ = V2+ = +5V, V1- = V2- = -5V, GND = 0V, TA = +25°C, Input Video = 1VP-P and RL = 500Ω to GND,
CL = 5pF unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL
+IS Enabled
Enabled Supply Current
No load, VIN = 0V, EN1, EN2 Low
75
92
100
mA
-IS Enabled
Enabled Supply Curren
No load, VIN = 0V, EN1, EN2 Low
-96
-87
-68
mA
+IS Disabled
Disabled Supply Current
No load, VIN = 0V, EN1, EN2 High
4
6.5
8
μA
-IS Disabled
Disabled Supply Current
No load, VIN = 0V, EN1, EN2 High
-200
-10
µA
MUX1: Positive and Negative Output Swing VIN = ±3.5V, RL = 500Ω
3.1
3.4
MUX2: Positive and Negative Output Swing VIN = ±2.5V; RL = 500Ω
3.8
4.0
IOUT
Output Current
RL = 10Ω to GND
80
125
VOS
MUX1: Output Offset Voltage
VIN = 0V
-10
2
14
mV
MUX2: Output Offset Voltage
VIN = 0V
-60
-25
20
mV
Input Bias Current
VIN = 0V
-10
-2
+10
µA
MUX1: HIZ Output Resistance
HIZ = Logic High
MUX2: HIZ Output Resistance
HIZ = Logic High
Enabled Output Resistance
HIZ = Logic Low
0.1
Ω
Input Resistance
VIN = ±3.5V
10
MΩ
MUX1: Voltage Gain
VIN = ±1.5V, RL= 500Ω
0.98
0.99
1.02
V/V
MUX2: Voltage Gain
VIN = ±1.5V, RL= 500Ω
1.94
1.99
2.04
V/V
MUX1: Output Current in High Impedance
State
VOUT = 0V
VOUT
Ib
ROUT
ROUT
RIN
ACL or AV
IHIZ
|V|
4.2
|mA|
1.2
700
1000
|V|
MΩ
1300
-9
Ω
µA
LOGIC
VIH
Input High Voltage (Logic Inputs)
VIL
Input Low Voltage (Logic Inputs)
IIH
Input High Current (Logic Inputs)
VH = 5V
200
IIL
Input Low Current (Logic Inputs)
VL = 0V
-10
3
2
V
0.8
V
270
320
µA
-1
+10
µA
FN6394.2
May 21, 2007
ISL59483
Electrical Specifications
PARAMETER
V1+ = V2+ = +5V, V1- = V2- = -5V, GND = 0V, TA = +25°C, Input Video = 1VP-P and RL = 500Ω to GND,
CL = 5pF unless otherwise specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC GENERAL
PSRR
MUX1: Power Supply Rejection Ratio
DC, PSRR V+ and V- combined
52
56
dB
MUX2: Power Supply Rejection Ratio
DC, PSRR V+ and V- combined
45
53
dB
ISO
Channel Isolation
f = 10MHz, Ch-Ch X-Talk and Off Isolation,
CL = 1.5pF
75
dB
dG
MUX1: Differential Gain Error
NTC-7, RL = 150, CL = 1.5pF
0.02
%
MUX2: Differential Gain Error
NTC-7, RL = 150, CL = 1.2pF
0.008
%
dP
MUX1: Differential Phase Error
NTC-7, RL = 150, CL = 1.5pF
0.02
°
MUX2: Differential Phase Error
NTC-7, RL = 150, CL = 1.2pF
0.01
°
Small Signal -3dB Bandwidth
VOUT = 0.2VP-P; CL = 1.5pF RL =500Ω
500
MHz
MUX1: 0.1dB Bandwidth
CL = 1.5pF RL = 500Ω
60
MHz
CL = 4.7pF RL = 500Ω
120
MHz
CL = 1.1pF RL = 500Ω
160
MHz
CL = 1.1pF RL = 150Ω
50
MHz
BW
FBW
FBW
SR
MUX2: 0.1dB Bandwidth
MUX1: Slew Rate
25% to 75%, RL = 150Ω, Input Enabled,
CL = 1.5pF
±870
V/µs
MUX2: Slew Rate
25% to 75%, RL = 150Ω, Input Enabled,
CL = 1.5pF
±1600
V/µs
SWITCHING CHARACTERISTICS
VGLITCH
MUX1:
Channel-to-Channel Switching Glitch
VIN = 0V CL = 1.2pF
40
mVP-P
EN Switching Glitch
VIN = 0V CL = 1.2pF
300
mVP-P
HIZ Switching Glitch
VIN = 0V CL = 1.2pF
200
mVP-P
Channel-to-Channel Switching Glitch
VIN = 0V, RL = 150Ω; CL = 2.1pF
15
mVP-P
EN Switching Glitch
VIN = 0V, RL = 150Ω; CL = 2.1pF
1800
mVP-P
HIZ Switching Glitch
VIN = 0V, RL = 150Ω; CL = 2.1pF
340
mVP-P
tSW-L-H
Channel Switching Time Low to High
1.2V logic threshold to 10% movement of
analog output
22
ns
tSW-H-L
Channel Switching Time High to Low
1.2V logic threshold to 10% movement of
analog output
25
ns
Rise and Fall Time
10% to 90%; VIN = 1V RL =500Ω
CL = 1.2pF
1.2
ns
10% to 90%; VIN = 0.1V RL=500Ω
CL=1.2pF
0.7
ns
22
ns
0.73
ns
VGLITCH
MUX2:
tr, tf
ts
0.1% Settling Time
VIN = 1V RL = 500Ω CL = 1.2pF
tpd
Propagation Delay
10% to 10%
4
FN6394.2
May 21, 2007
ISL59483
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
4
2
1
0
0
-2
CL= 4.6pF
-4
CL= 2.3pF
CL= 12.3pF
-6
CL= 1.5pF
-8
-10
-12
1M
RL=100Ω
-2
RL=150Ω
-3
10M
100M
-5
1G
1M
FREQUENCY (Hz)
10M
100M
FREQUENCY (Hz)
1G
FIGURE 2. MUX1: GAIN vs FREQUENCY vs RL
FIGURE 1. MUX1: GAIN vs FREQUENCY vs CL
10
10
8
6
CL = 7.4pF
CL = 6.2pF
4
CL = 4.5pF
2
0
CL = 3.3pF
-2
CL = 2.1pF
-4
CL = 1.1pF
-6
10M
100M
CL = 10.6pF
CL = 8.8pF
4
CL = 6.2pF
2
0
CL = 4.5pF
-2
CL = 3.3pF
-4
CL = 2.1pF
CL INCLUDES 0.6pF
BOARD CAPACITANCE
-8
-10
1M
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 3. MUX2: SMALL SIGNAL GAIN vs FREQUENCY vs
CL INTO 500Ω LOAD
0.1
CL = 0.6pF
-10
1G
FREQUENCY (Hz)
0.2
CL = 12.6pF
6
-6
CL = 0.6pF
-8
VOUT = 0.2VP-P
8
CL = 8.8pF
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
RL=0.5kΩ
RL=1kΩ
-1
-4
CL INCLUDES 0.3pF
BOARD CAPACITANCE
-14
-16
SOURCE POWER = -10dBm
INTO A 50Ω INPUT IMPEDANCE
CL= 6.3pF
NORMALIZED (dB)
NORMALIZED GAIN (dB)
CL= 7.3pF
SOURCE POWER = -14dBm
INTO A 50Ω INPUT IMPEDANCE
FIGURE 4. MUX2: SMALL SIGNAL GAIN vs FREQUENCY vs
CL INTO 150Ω LOAD
100
SOURCE POWER = -10dBm
INTO A 50Ω INPUT IMPEDANCE
CL=4.7pF
OUTPUT RESISTANCE (Ω)
NORMALIZED GAIN (dB)
0.0
-0.1
-0.2
-0.3
-0.4
CL=1.5pF
-0.5
-0.6
-0.7
-0.8
-0.9
10
1
CL INCLUDES 0.3pF
BOARD CAPACITANCE
-1.0
1M
10M
100M
FREQUENCY (Hz)
FIGURE 5. MUX1: 0.1dB GAIN vs FREQUENCY
5
1G
0.1
0.1k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 6. MUX1: ROUT vs FREQUENCY
FN6394.2
May 21, 2007
ISL59483
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
10
VOUT = 2VP-P
8
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
CL = 5.3pF
4
2
0
CL = 2.1pF
-2
-4
-6
CL INCLUDES 0.6pF
BOARD CAPACITANCE
-8
1M
CL = 0.6pF
10M
100M
VOUT = 2VP-P
8
CL = 8.8pF
6
-10
CL = 5.3pF
4
2
0
CL = 2.1pF
-2
CL = 0.6pF
-4
-6
CL INCLUDES 0.6pF
BOARD CAPACITANCE
-8
-10
1G
CL = 12.6pF
6
1M
10M
FIGURE 7. MUX2: LARGE SIGNAL GAIN vs FREQUENCY vs
CL INTO 500Ω LOAD
2
0.3
0.2
0
-1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
1
RL = 250Ω
-2
RL = 150Ω
-3
-4
-5
-6
VOUT = 0.2VP-P
RL = 150Ω
CL = 2.1pF
0.1
0.0
-0.1
RL = 500Ω
CL = 1.1pF
-0.2
-0.3
-0.4
-0.5
-7
-0.6
1M
10M
100M
-0.7
1M
1G
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. MUX2: GAIN vs FREQUENCY vs RL
FIGURE 10. MUX2: 0.1dB GAIN FLATNESS
10k
100
VSOURCE = 2VP-P
OUTPUT IMPEDANCE (Ω)
VSOURCE = 2VP-P
OUTPUT IMPEDANCE (Ω)
1G
FIGURE 8. MUX2: LARGE SIGNAL GAIN vs FREQUENCY vs
CL INTO 150Ω LOAD
RL = 1kΩ
RL = 500Ω
VOUT = 0.2VP-P
CL = 1.1pF
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
-8
(Continued)
10
10
1
0.1
0.1M
1M
10M
100M
FREQUENCY (Hz)
FIGURE 11. MUX2: ZOUT vs FREQUENCY - ENABLED
6
1G
1k
100
10
0.1M
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 12. MUX2: ZOUT vs FREQUENCY - HIZ
FN6394.2
May 21, 2007
ISL59483
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
-40
-20
-50
-30
-70
-80
(dB)
(dB)
-60
-80
-90
-100
-90
-100
-110
-110
-120
-120
-130
OFF ISOLATION
INPUT X TO OUTPUT X
-130
0.1M
1M
10M
FREQUENCY (Hz)
OFF ISOLATION RL = 500Ω
INPUT X TO OUTPUT X RL = 150Ω
-140
100M
1G
-150
0.1M
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 13. MUX1: CROSSTALK AND OFF ISOLATION
FIGURE 14. MUX 2: CROSSTALK AND OFF ISOLATION
60
60
50
50
VOLTAGE NOISE (nV/√Hz)
VOLTAGE NOISE (nV/√Hz)
CROSSTALK RL = 500Ω
INPUT X TO OUTPUT Y RL = 150Ω
-50
-70
-140
VIN = 0.796VP-P
-40
INPUT X TO OUTPUT Y
CROSSTALK
-60
(Continued)
40
30
20
10
40
30
20
10
0
100
1k
10k
0
100
100k
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 15. MUX1: INPUT NOISE vs FREQUENCY
FIGURE 16. MUX2: INPUT NOISE vs FREQUENCY
-50
-40
-45
VSOURCE = 0.5VP-P
-55
-50
-60
PSRR (dB)
PSSR (dB)
-55
-60
-65
PSRR (V-)
-70
-75
PSRR (V-)
-65
-70
-75
-80
PSRR (V+)
-80
PSRR (V+)
-85
-90
0.1M
-85
1M
FREQUENCY (Hz)
FIGURE 17. MUX 1: PSRR vs FREQUENCY
7
10M
0.1M
1M
10M
FREQUENCY (Hz)
FIGURE 18. MUX 2: PSRR vs FREQUENCY
FN6394.2
May 21, 2007
ISL59483
0.020
0.016
0.012
0.008
0.004
0.000
-0.004
-0.008
-0.012
-0.016
-0.020
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
-0.12
-0.14
-0.16
-0.18
-0.20
-4
-3
-2
-1
0
1
VOUT DC (V)
2
3
4
FIGURE 19. MUX 2: DIFFERENTIAL GAIN AND PHASE;
VOUT = 0.2VP-P, FO = 3.58MHz, RL = 500Ω
NORMALIZED PHASE (°) NORMALIZED GAIN (dB)
NORMALIZED PHASE (°) NORMALIZED GAIN (dB)
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
(Continued)
0.008
0.006
0.004
0.002
0.000
-0.002
-0.004
-0.006
-0.008
0.020
0.000
-0.020
-0.040
-0.060
-0.080
-0.100
-0.120
-0.140
-0.160
-0.180
-4
-3
-2
-1
0
1
VOUT DC (V)
2
3
4
FIGURE 20. MUX 2: DIFFERENTIAL GAIN AND PHASE;
VOUT = 0.2VP-P, FO = 3.58MHz, RL = 150Ω
0.8
VOUT = 0.2VP-P
RL=500Ω
CL=1.5pF
0.6
RL = 500Ω
CL = 1.1pF
0.2
0.4
VOUT (V)
VOUT (V)
0.2
0.0
-0.2
0.1
-0.4
0.0
-0.6
-0.8
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 21. MUX 1: SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 22. MUX 2: SMALL SIGNAL TRANSIENT RESPONSE;
RL = 500Ω
VOUT = 0.2VP-P
RL = 150Ω
CL = 2.1pF
VOUT (V)
0.2
0.1
0.0
TIME (5ns/DIV)
FIGURE 23. MUX 2: SMALL SIGNAL TRANSIENT RESPONSE; RL = 150Ω
8
FN6394.2
May 21, 2007
ISL59483
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
VOUT = 2VP-P
VOUT = 2VP-P
RL = 500Ω
CL = 1.1pF
RL = 150Ω
CL = 2.1pF
2.0
VOUT (V)
VOUT (V)
2.0
1.0
1.0
0.0
0.0
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 24. MUX2 : LARGE SIGNAL TRANSIENT RESPONSE;
RL = 500Ω
FIGURE 25. MUX 2: LARGE SIGNAL TRANSIENT RESPONSE;
RL = 150Ω
50
40
(Continued)
50
INPUT RISE, FALL TIMES
VOUT = 2VP-P
<175ps
VOUT = 1.4VP-P
INPUT RISE, FALL TIMES
<175ps
VOUT = 2VP-P
40
OVERSHOOT (%)
OVERSHOOT (%)
VOUT = 1.4VP-P
30
20
VOUT = 1VP-P
30
20
VOUT = 1VP-P
10
10
VOUT = 0.2VP-P
VOUT = 0.2VP-P
0
2
4
CL (pF)
6
8
FIGURE 26. MUX 2: PULSE OVERSHOOT vs VOUT, CL;
RL=500Ω
0
10
6
8
10
VIN = 0V
1V/DIV
1V/DIV
CL (pF)
S0, S1
50Ω
TERM.
0
0
VOUT A, B, C
20ns/DIV
FIGURE 28. MUX 1: CHANNEL TO CHANNEL SWITCHING
GLITCH VIN = 0V
9
20mV/DIV
0
20mV/DIV
4
FIGURE 27. MUX 2: PULSE OVERSHOOT vs VOUT, CL;
RL=150Ω
VIN = 0V
S0, S1
50Ω
TERM.
2
VOUT A, B, C
0
20ns/DIV
FIGURE 29. MUX 2: CHANNEL TO CHANNEL SWITCHING
GLITCH VIN = 0V
FN6394.2
May 21, 2007
ISL59483
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
VIN = 1V
0
0
1V/DIV
0.5V/DIV
0
VOUT A, B, C
0
VOUT A, B, C
20ns/DIV
20ns/DIV
FIGURE 30. MUX 1: CHANNEL TO CHANNEL TRANSIENT
RESPONSE VIN = 1V
ENABLE
50Ω
TERM.
FIGURE 31. MUX 2: CHANNEL TO CHANNEL TRANSIENT
RESPONSE VIN = 1V
ENABLE
50Ω
TERM.
0
VOUT A, B, C
1V/DIV
100mV/DIV
VIN = 0V
1V/DIV
1V/DIV
VIN = 0V
0
0
VOUT A, B, C
0
20ns/DIV
40ns/DIV
FIGURE 32. MUX 1: ENABLE SWITCHING GLITCH VIN = 0V
FIGURE 33. MUX 2: ENABLE SWITCHING GLITCH VIN = 0V
VIN = 1V
ENABLE
VIN = 1V
ENABLE
1V/DIV
50Ω
TERM.
1V/DIV
50Ω
TERM.
0
0
2V/DIV
0
1V/DIV
VIN = 1V
S0, S1
50Ω
TERM.
1V/DIV
1V/DIV
S0, S1
50Ω
TERM.
(Continued)
VOUT A, B, C
20ns/DIV
FIGURE 34. MUX 1: ENABLE TRANSIENT RESPONSE VIN = 1V
10
0
VOUT A, B, C
40ns/DIV
FIGURE 35. MUX 2: ENABLE TRANSIENT RESPONSE VIN = 1V
FN6394.2
May 21, 2007
ISL59483
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
HIZ
HIZ
VIN = 0V
1V/DIV
1V/DIV
0
200mv/DIV
0
200mv/DIV
VIN = 0V
50Ω
TERM.
50Ω
TERM.
0
VOUT A, B, C
0
VOUT A, B, C
20ns/DIV
10ns/DIV
FIGURE 36. MUX 1: HIZ SWITCHING GLITCH VIN = 0V
HIZ
FIGURE 37. MUX 2: HIZ SWITCHING GLITCH VIN = 0V
HIZ
VIN=1V
VIN = 1V
50Ω
TERM.
1V/DIV
1V/DIV
50Ω
TERM.
0
0
VOUT A, B, C
2V/DIV
1V/DIV
(Continued)
0
VOUT A, B, C
0
20ns/DIV
10ns/DIV
FIGURE 38. MUX 1: HIZ TRANSIENT RESPONSE VIN = 1V
FIGURE 39. MUX 2: HIZ TRANSIENT RESPONSE VIN = 1V
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
1.2
5
4.34W
POWER DISSIPATION (W)
POWER DISSIPATION (W)
6
QFN48
θJA =+23°C/
4
3
2
1
0
1.0
870mW
QFN48
θJA =+115°C/
0.8
0.6
0.4
0.2
0.0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 40. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
11
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 41. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN6394.2
May 21, 2007
ISL59483
Pin Description
ISL59483
(48 LD QFN)
PIN NAME
EQUIVALENT
CIRCUIT
1
OUTC1
Circuit 3
Output of amplifier C1
Output of amplifier B1
2
OUTB1
Circuit 3
3, 23
V1-, V2-
Circuit 4A
DESCRIPTION
Negative power supply #1 and #2
4
OUTA1
Circuit 3
5, 25
V1+, V2+
Circuit 4A
Circuit 2
Device enable (active low) with internal pull-down resistor. A logic High puts device into power-down
mode leaving the logic circuitry active. This state is not recommended for logic control where more
than one MUX-amp share the same video output line.
Circuit 2
Output disable (active high) with internal pull-down resistor. A logic high puts the output in a high
impedance state. Use this state when more than one MUX-amp share the same video output line.
Circuit 1
Channel 0 input for amplifier C1
6
EN1
26
EN2
7
HIZ1
27
HIZ2
8
IN0C1
Output of amplifier A1
Positive Power Supply #1 and #2
9
IN0B1
Circuit 1
Channel 0 input for amplifier B1
10
IN0A1
Circuit 1
Channel 0 input for amplifier A1
11
GND
Circuit 4A
12
IN1A1
Circuit 1
Channel 1 input for amplifier A1
13
IN2B2
Circuit 1
Channel 2 input for amplifier B2
14
IN2C2
Circuit 1
Channel 2 input for amplifier C2
15
GND
Circuit 4B
16
IN3A2
Circuit 1
Channel 3 input for amplifier A2
17
IN3B2
Circuit 1
Channel 3 input for amplifier B2
18
IN3C2
Circuit 1
Channel 3 input for amplifier C2
19, 47
S1-2, S1-1
Circuit 2
Channel select pin MSB (binary logic code) for amplifiers A2, B2, C2 (S1-2) and A1, B1, C1 (S1-1)
20, 48
S0-2, S0-1
Circuit 2
Channel select pin LSB (binary logic code) for amplifiers A2, B2, C2 (S0-2) and A1, B1, C1 (S0-1)
21
OUTC2
Circuit 2
Output of amplifier C2
22
OUTB2
Circuit 1
Output of amplifier B2
24
OUTA2
Circuit 1
Output of amplifier A2
28
IN0C2
Circuit 1
Channel 0 input for amplifier A2
29
IN0B2
Circuit 1
Channel 0 input for amplifier B2
30
IN0A2
Circuit 1
Channel 0 input for amplifier C2
31
GND
Circuit 4B
32
IN1A2
Circuit 1
Channel 1 input for amplifier A2
33
IN1B2
Circuit 1
Channel 1 input for amplifier B2
34
IN1C2
Circuit 1
Channel 1 input for amplifier C2
35
GND
Circuit 4B
36
IN2A2
Circuit 1
Channel 2 input for amplifier A2
37
IN1B1
Circuit 1
Channel 1 input for amplifier B1
38
IN1C1
Circuit 1
Channel 1 input for amplifier C1
39
GND
Circuit 4A
40
IN2A1
Circuit 1
Channel 2 input for amplifier A1
41
IN2B1
Circuit 1
Channel 2 input for amplifier B1
42
IN2C1
Circuit 1
Channel 2 input for amplifier C1
43
GND
Circuit 4A
44
IN3A1
Circuit 1
Channel 3 input for amplifier A1
45
IN3B1
Circuit 1
Channel 3 input for amplifier B1
46
IN3C1
Circuit 1
Channel 3 input for amplifier C1
12
Ground pin for amplifier A1
Ground pin for amplifier C2
Ground pin for amplifier A2
Ground pin for amplifier B2
Ground pin for amplifier B1
Ground pin for amplifier C1
FN6394.2
May 21, 2007
ISL59483
Pin Equivalent Circuits
V+
V+
21k
LOGIC PIN
IN
33k
+
1.2V
-
GND
V-
V-
V-
CIRCUIT 1
CIRCUIT 2
V1+
V2+
GNDA1
GNDA2
CAPACITIVELY
COUPLED
ESD CLAMP
GNDB1
V+
OUT
SUBSTRATE 1
CAPACITIVELY
COUPLED
ESD CLAMP
GNDB2
GNDC1
CIRCUIT 3
SUBSTRATE 2
V1-
V2~1MΩ
~1MΩ
GNDC2
V1-
V2CIRCUIT 4A
Application Information
AC Test Circuits
General
ISL59483
VIN
CL
5pF
50Ω
or
75Ω
RL
500Ω
FIGURE 42A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
TEST
EQUIPMENT
ISL59483
RS
VIN
50Ω
or
75Ω
CL
5pF
THERMAL HEAT SINK PAD
CIRCUIT 4B
The ISL59483 is ideal as the matrix element of high
performance switchers and routers. Key features include
high impedance buffered analog inputs and excellent AC
performance at output loads down to 150Ω for video cabledriving. The current feedback output amplifiers are stable
operating into capacitive loads and bandwidth is optimized
with a load of 5pF in parallel with a 500Ω. Total output
capacitance can be split between the PCB capacitance and
an external load capacitor.
Ground Connections
475Ω
50Ω
or
75Ω
50Ω
or
75Ω
For the best isolation and crosstalk rejection, all GND pins
must connect to the GND plane.
Power-up Considerations
FIGURE 42B. TEST CIRCUIT FOR MEASURING WITH 50Ω OR
75Ω INPUT TERMINATED EQUIPMENT
TEST
EQUIPMENT
ISL59483
RS
VIN
50Ω
or
75Ω
CL
5pF
50Ω or 75Ω
50Ω
or
75Ω
FIGURE 42C. BACKLOADED TEST CIRCUIT FOR VIDEO
CABLE APPLICATION. BANDWIDTH AND
LINEARITY FOR RL LESS THAN 500Ω WILL BE
DEGRADED.
FIGURE 42. TEST CIRCUITS
Figure 42A illustrates the optimum output load for testing AC
performance. Figure 42B illustrates the optimum output load
when connecting to 50Ω input terminated equipment.
13
The ESD protection circuits use internal diodes from all pins
the V+ and V- supplies. In addition, a dV/dT-triggered clamp
is connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the Pin Description
table. The dV/dT triggered clamp imposes a maximum
supply turn-on slew rate of 1V/µs. Damaging currents can
flow for power supply rates-of-rise in excess of 1V/µs, such
as during hot plugging. Under these conditions, additional
methods should be employed to ensure the rate of rise is not
exceeded.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic
input pins. Schottky diodes (Motorola MBR0550T or
equivalent) connected from V+ to ground and V- to ground
(Figure 43) will shunt damaging currents away from the
internal V+ and V- ESD diodes in the event that the V+
supply is applied to the device before the V- supply. One
Schottky can be used to protect both V+ power supply pins,
and a second for the protection of both V- pins.
FN6394.2
May 21, 2007
ISL59483
V+ SUPPLY
SCHOTTKY
PROTECTION
V+
LOGIC
LOGIC
CONTROL
S0
POWER
GND
EXTERNAL
CIRCUITS
V+
GND
V-
IN0
V+
V+
V+
SIGNAL
OUT
V-
DE-COUPLING
CAPS
IN1
VV-
V-
V- SUPPLY
FIGURE 43. SCHOTTKY PROTECTION CIRCUIT
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+ can result in damaging currents through the
ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and
analog inputs is needed to prevent damage during the time
the voltages on these inputs are more positive than V+.
HIZ State
Each internal 4:1 triple MUX-amp has a high impedance
output control pin (HIZ1 and HIZ2). Each has an internal pulldown resistor to set the output to the enabled state with no
connection to the HIZ pin. The HIZ state is established within
approximately 15ns by placing a logic high (>2V) on the HIZ
pin. If the HIZ state is selected, the MUX 1 output is a high
impedance 1.4MΩ with approximately 1.5pF in parallel with a
10μA bias current from the output. In the HIZ state the MUX 2
output impedance is ~900Ω. The supply current during this
state is the same as the active state.
EN and Power-down States
The EN pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
EN pin. The power-down state is established within
approximately 80ns if a logic high (>2V) is placed on the EN
pin. In the power-down state, supply current is reduced
significantly by shutting the three amplifiers off. The output
presents a high impedance to the output pin, however, there
is a risk that the disabled amplifier output can be back-driven
at signal voltage levels exceeding ~2VP-P. Under this
condition, large incoming slew rates can cause fault currents
of tens of mA. Therefore, the parallel connection of multiple
outputs is not recommended unless the application can
tolerate the limited power-down output impedance.
Output Capacitive Loading Considerations
High speed amplifiers may be sensitive to capacitance at the
output. Excessive pulse overshoot may result from the
combination of output slew rates approaching the amplifier
maximum and the presence of parasitic capacitance. In
applications where high slew rates are expected and PC board
output pin capacitance exceeds ~5pF, series connected
14
resistors (ranging from 10Ω to 75Ω) may be needed close to
the output pin in order to buffer the amplifer output stage from
the effects of capacitive loading. When paralleling the
amplifier outputs, resistance in series with MUX 1 output will
form a resistor divider with the 900Ω HIZ impedance of MUX 2
when MUX 1 is enabled and MUX 2 is in the HIZ state.
However, resistance in series with MUX 2 does not result in a
resistor divider with MUX 1 due to the 1.4MΩ HIZ impedance.
In all cases, series resistance will form a voltage divider with
any downstream load resistance, therefore the effects of
series resistance on throughput gain must be considered.
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than
50mA. Adequate thermal heat sinking of the parts is also
required.
PC Board Layout
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners. Use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
degraded for traces greater than one inch, unless
controlled impedance (50Ω or 75Ω) strip lines or
microstrips are used.
• Match channel to channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• Maximize use of AC de-coupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e.
no split planes or PCB gaps under these lines). Avoid vias
in the signal I/O lines.
FN6394.2
May 21, 2007
ISL59483
The thermal pad requirements are proportional to power
dissipation and ambient temperature. A dedicated layer
eliminates the need for individual thermal pad area. When a
dedicated layer is not possible, an isolated thermal pad on
another layer should be used. Pad area requirements should
be evaluated on a case by case basis.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
• When testing, use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
MUX Application Circuits
• A minimum of 2 power supply decoupling capacitors are
recommended (1000pF, 0.01µF) as close to the devices
as possible. Avoid vias between the cap and the device
because vias adds unwanted inductance. Larger caps can
be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
Each of the two 4:1 triple MUX amplifiers have their own
binary-coded, TTL compatible channel select logic inputs
(S0-1, 2, and S1-1, 2). All three amplifiers are switched
simultaneously from their respective inputs with S0-1 S1-1
controlling MUX 1, and S0-2, S1-2 controlling MUX 2.
• The NIC pins are placed on both sides of the input pins.
These pins are not internally connected to the die. It is
recommended these pins be tied to ground to minimize
crosstalk.
The HIZ control inputs (HIZ1, HIZ2) and device enable control
inputs (EN1 and EN2) control MUX 1 and MUX 2 in a similar
fashion. The individual control for each 4:1 triple MUX enables
external connections to configure the device for different MUX
applications.
The QFN Package Requires Additional PCB Layout
Rules for the Thermal Pad
8:1 RGB Dual Gain Video MUX
The thermal pad is electrically connected to V- supply
through the high resistance IC substrate. Its primary function
is to provide heat sinking for the IC. However, because of the
connection to the V1- and V2- supply pins through the
substrate, the thermal pad must be tied to the V- supply to
prevent unwanted current flow to the thermal pad. Do not tie
this pin to GND as this could result in large back biased
currents flowing between GND and the V- pins. Maximum
AC performance is achieved if the thermal pad is attached to
a dedicated decoupled layer in a multi-layered PC board. In
cases where a dedicated layer is not possible, AC
performance may be reduced at upper frequencies.
The triple input RGB 8:1 MUX (Figure 44) connects the RGB
amplifier output of MUX 1 to the parallel-connected RGB
amplifier output of MUX 2 to produce a single RGB video
output. Input channels CH0 to CH3 are assigned to MUX 1
and have a throughput gain of 1. Channels CH4 through
CH7 are assigned to MUX 2 and have a throughput gain of
2. Channels CH0 through CH3 are selected by setting S2
low, which forces HIZ1 low and HIZ2 high (enables MUX 1
and three-states MUX 2). Setting S2 high reverses the logic
inputs of HIZ1, HIZ2 and switches from MUX 1 to MUX 2,
enabling the selection of channels CH4 through CH7. The
channel select inputs are parallel connected (S0-1 to S0-2)
and S1-1 to S1-2) to form two logic controls, S0 and S1. The
logic control truth table is shown in Figure 44.
ISL59483
1/3 MUX-AMP1
IN0A1
CH0
IN1A1
CH1
IN2A1
CH2
CHANNEL SELECT TRUTH TABLE
OUTA1
8:1 VIDEO MUX
IN3A1
CH3
* ROUTA1
S0-1
CH0A - CH7A
S1-1
CHANNELS B & C
NOT SHOWN
CONTROL
LOGIC
OUTA
HIZ1
IN0A2
CH4
1/3 MUX-AMP2
IN1A2
CH5
CH6
IN2A2
CH7
IN3A2
+2
S0-2
S0
CHANNEL SELECT
LOGIC INPUTS
+1
S1-2
S1
CONTROL
LOGIC
OUTA2
* ROUTA2
S2
S1
S0
GAIN
OUTA, B, C
0
0
0
1
CH0A, B, C
0
0
1
1
CH1A, B, C
0
1
0
1
CH2A, B, C
0
1
1
1
CH3A, B, C
1
0
0
2
CH4A, B, C
1
0
1
2
CH5A, B ,C
1
1
0
2
CH6A, B, C
1
1
1
2
CH7A, B, C
HIZ2
S2
* OPTIONAL - DEPENDING ON PARASITIC CAPACITANCE
FIGURE 44. APPLICATION CIRCUIT FOR A DUAL GAIN 8:1 RGB VIDEO MUX
15
FN6394.2
May 21, 2007
ISL59483
4:1 RGB Dual Gain Video MUX
logic function is created by providing complememtary logic to
the HIZ1 and HIZ2 pins. Channels CH0 through CH3 are
selected by connecting the MUX 1 and MUX 2 S0-1, 2 and
S1-1, 2 channel select inputs together to form channel select
(S0 and S1), as shown in the truth table in Figure 10.
Connecting the MUX inputs and outputs in parallel allows the
8 channel ISL59483 to be used as a 4:1 RGB MUX with
selectable gains of 1 or 2 (Figure 10). In this example, the high
input impedance of the MUX enables each input video line to
be shared by any number of MUX input pins. The gain select
ISL59483
1/3 MUX-AMP1
IN0A1
CH0
IN1A1
CH1
IN2A1
CH2
+1
OUTA1
CHANNEL SELECT TRUTH TABLE
DUAL GAIN 4:1 VIDEO MUX
IN3A1
CH3
* ROUTA1
S0-1
CH0 - CH3
S1-1
CHANNELS B & C
NOT SHOWN
CONTROL
LOGIC
1/3 MUX-AMP2
IN1A2
IN2A2
+2
IN3A2
CHANNEL SELECT
AND GAIN SELECT
LOGIC INPUTS
S0-2
S0
S1
S1-2
GAIN
SELECT
HIZ2
CONTROL
LOGIC
S1
GAIN
SELECT
GAIN
OUTA, B, C
0
0
0
1
CH0A, B, C
0
0
0
1
CH1A, B, C
1
1
0
1
CH2A, B, C
1
1
0
1
CH3A, B, C
0
0
1
2
CH0A, B, C
0
0
1
2
CH1A, B, C
1
1
1
2
CH2A, B, C
1
1
1
2
CH3A, B, C
OUT
HIZ1
IN0A2
S1
OUTA2
* ROUTA2
* OPTIONAL - DEPENDING ON PARASITIC CAPACITANCE
FIGURE 45. APPLICATION CIRCUIT FOR DUAL GAIN 4:1 VIDEO MUX
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN6394.2
May 21, 2007
ISL59483
Package Outline Drawing
L48.7x7B
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 12/06
4X 5.5
7.00
A
44X 0.50
B
37
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
1
7.00
36
3.70
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40
TOP VIEW
4 0.25
BOTTOM VIEW
SEE DETAIL "X"
( 6 . 80 TYP )
(
3.70 )
C
0.10 C
BASE PLANE
0 . 85 ± 0 . 1
SEATING PLANE
0.08 C
SIDE VIEW
( 44X 0 . 5 )
C
0 . 2 REF
5
( 48X 0 . 25 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
17
FN6394.2
May 21, 2007
Similar pages