DATASHEET

DATASHEET
Intelligent Digital Amplifier and Sound Processor
D2-926xx
Features
The D2-926xx family of the DAE-3™ and DAE-3HT™ Digital
Audio Engine™ devices are complete System-on Chip (SoC)
multi-channel digital sound processors and Class-D amplifier
controllers.
• Advanced DAE-3™ Digital Audio Engine™ IC Family
- DAE-3™ Pin Compatible and Function/Feature
Compatible with the D2Audio™ DAE-6™ Device Family
- DAE-3HT™ - Identical DAE-3 performance, in
72-QFN package
The integrated DSP provides efficient and configurable audio
signal path processing including equalization, dynamic range
compression, mixing, and filtering that is completely
configurable via the Audio Canvas™ III high level programming
interface. The integrated PWM engine supports programmable
and dynamic control of audio output, enabling a variety of
multi-channel output configurations and output power
capacity. Internal noise shaping, an embedded asynchronous
sample rate converter, dynamic level-dependent timing, and
high resolution operation supports power stage audio
performances with SNR >110dB and THD+N < 0.01%.
The D2-926xx devices are provided in two package and feature
configurations which include the 128-pin DAE-3, and the72-pin
DAE-3HT. Both the DAE-3 and DAE-3HT provide identical
performance and enable an extremely flexible platform for
feature rich and cost-affordable quality audio solutions, which
benefit from the addition of Class-D amplifiers and DSP audio
processing.
The 12 integrated digital PWM controllers can be used in a
variety of multi-channel audio system configurations,
supporting powered as well as line outputs. Fully protected
amplifier control provides efficient and clean Class-D power
output support.
Applications
• DTV and Blu-ray Soundbar
• DVD and Blu-ray Home Theater Systems
• Home Theater in a Box (HTiB)
• Integrated DSP Digital Sound Processing
- Customizable audio path sound processing
- Fully configurable and routable audio signal paths and
hardware function assignment
- Fully Supported with Audio Canvas™ III Design Tool
• Flexible Audio Input and Output Configurations
- 12 Independent PWM Engine Channels
- 4 Independent Asynchronous I2S Digital Inputs
- Integrated high-performance stereo ADC (DAE-3 only)
- S/PDIF™ Digital Audio Inputs supporting
Linear IEC-61958 PCM or Compressed IEC-61937 Audio
- S/PDIF Digital Audio PCM Output
• Embedded 8-Channel Sample Rate Converter
• Real-Time Amplifier Control and Monitoring
- Supports Bridged, Half-Bridged, and Bridge-Tied Load (BTL)
Topologies, Using Discrete or Integrated Power Stages
- Complete Fault Protection with Automatic Recovery
• D2Audio™ SoundSuite™ Enhancement and Virtualization
• Enhanced Audio Processing Decoders And Virtualization
- Dolby® Digital/AC3
- Dolby® Pro Logic IIx
- Dolby® Virtual Speaker
- DTS®(SRS) TruSurround HD4™ , DTS®(SRS) WOW HD™,
DTS®(SRS) TruVolume™
• Audio Video Receiver (AVR)
• Multi-Channel Multi-Media (MM) Systems
• Multi-Room Distributed Audio (MRDA)
• Powered Speaker Systems
• Automotive Trunk/Amplified Solutions
May 17, 2016
FN6787.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2010-2012, 2016. All Rights Reserved
Intersil (and design) and D2Audio are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
D2-926xx
Ordering Information
PART
NUMBER
(Notes 3, 4)
DAE DEVICE
FAMILY
PART
MARKING
AUDIO PROCESSING
FEATURE SET SUPPORT
(Note 1)
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
D2-92633-LR
DAE-3
D2-92633-LR
Refer to Table 1
-10 to +85
128 Ld LQFP
Q128.14x14
D2-92634-LR
DAE-3
D2-92634-LR
Refer to Table 1
-10 to +85
128 Ld LQFP
Q128.14x14
D2-92683-QR (Note 2)
DAE-3HT
D2-92683-QR
Refer to Table 1
-10 to +85
72 Ld QFN
L72.10x10F
D2-92684-QR (Note 2)
DAE-3HT
D2-92684-QR
Refer to Table 1
-10 to +85
72 Ld QFN
L72.10x10F
NOTES:
1. The D2-926xx devices support multiple audio processing algorithms and decoders, and support is device-dependent. Refer to Table 1 on page 3 for
the supported features for each device part number.
2. Add “-T” suffix for 3k unit Tape and Reel option. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see product information page for D2-92633, D2-92634, D2-92683, D2-92684. For more information on
MSL, please see tech brief TB363.
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D2-926xx
DAE-3 Device Feature Set Offering
The D2-926xx family has specific part numbers to specify the features and algorithms supported in the device. All devices of the DAE-3
family include 8 audio input processing channels, up to 12 PWM output channels, an embedded 8-channel Sample Rate Converter
(SRC), and are fully supported with the Audio Canvas III™ design tool software. Additional features within each DAE-3 family part
number are shown in Table 1.
TABLE 1. DAE-3 DEVICE PART NUMBERS AND FEATURES
PART NUMBER
D2-92633-LR
DAE FAMILY
FEATURES
DAE-3
8 Channels of I2S or Left Justified Serial Digital Audio Inputs
128-Pin Package 8 Channels of I2S or Left Justified Serial Digital Audio Outputs
2 S/PDIF Digital Inputs
1 S/PDIF Digital Output
2 ADC Analog Audio Inputs
D2-92634-LR
DAE-3
8 Channels of I2S or Left Justified Serial Digital Audio Inputs
128-Pin Package 8 Channels of I2S or Left Justified Serial Digital Audio Outputs
2 S/PDIF Digital Inputs
1 S/PDIF Digital Output
2 ADC Analog Audio Inputs
LICENSED ALGORITHM SUPPORT (Note 5)
D2Audio™ SoundSuite™
DTS®(SRS) TruSurround HD4™
DTS®(SRS) WOWHD4™
DTS®(SRS) TruVolume™
D2Audio™ SoundSuite™
Dolby® Digital/AC3 Decoder
Dolby® Pro Logic IIx Surround
D2-92683-QR
DAE-3HT
72-Pin Package
8 Channels of I2S or Left Justified Serial Digital Audio Inputs, or
6 Channels of I2S or Left Justified Serial Digital Audio Inputs plus
2 Channels of I2S or Left Justified Serial Digital Audio Outputs
1 S/PDIF Digital Input
1 S/PDIF Digital Output
D2Audio™ SoundSuite™
DTS®(SRS) TruSurround HD4™
DTS®(SRS) WOWHD4™
DTS®(SRS) TruVolume™
D2-92684-QR
DAE-3HT
72-Pin Package
8 Channels of I2S or Left Justified Serial Digital Audio Inputs, or 6
Channels of I2S or Left Justified Serial Digital Audio Inputs plus 2
Channels of I2S or Left Justified Serial Digital Audio Outputs
1 S/PDIF Digital Input
1 S/PDIF Digital Output
D2Audio™ SoundSuite™
Dolby® Digital/AC3 Decoder
Dolby® Pro Logic IIx Surround
NOTE:
5. All DAE-3 family devices support D2Audio™ SoundSuite™ Audio Processing algorithms, and with license agreements executed with DTS®(SRS) Labs,
also support DTS®(SRS) TruSurround HD4™, DTS®(SRS) WOW HD™, and DTS®(SRS) TruVolume™
Device Designations
This datasheet applies to all of the DAE-3 device family, which includes both the DAE-3 and DAE-3HT. Functional specifications apply to
both designations of this family unless otherwise indicated.
Throughout this document the device names apply to all part numbers of their respective names as follows:
DAE DEVICE NAME
DAE DEVICE PART NUMBERS
PACKAGE PINS
DAE-3
D2-92633-LR, D2-92634-LR
128-Pin Package
DAE-3HT
D2-92683-QR, D2-92684-QR
72-Pin Package
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D2-926xx
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Device Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Audio Interface Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Two-Wire (I2C) Interface Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SPI™ Interface Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration DAE-3 (128-Pin Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Configuration DAE-3HT (72-Pin Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Description, DAE-3 (128-Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Description DAE-3HT (72-Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Block Diagram - DAE-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Functional Block Diagram - DAE-3HT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Rate Converters (SRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/PDIF Digital Audio Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC input (DAE-3 Devices Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Audio Amplifier Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Amplifier Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocks And PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Booting and Boot Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading and Writing Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Processing Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SoundSuite™ Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Third Party Virtualization and Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Processing Block Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Register Addressing Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Feature Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
23
23
25
25
25
26
26
26
26
26
27
27
27
28
29
30
30
30
31
31
DAE-3 And DAE-3HT Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pin Function Mapping Between Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I/O Pin Function Assignment Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Disclaimer for DTS®(SRS) Technology License Required Notice: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
L72.10x10F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Q128.14x14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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D2-926xx
Absolute Maximum Ratings
Thermal Information
(Note 10)
Supply Voltage
RVDD, PWMVDD, ADCVDD . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V
CVDD, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.4V
Input Voltage
Any Input but XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to RVDD +0.3V
XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to PLLVDD +0.3V
Input Current, Any Pin but Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 2000V
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . 750V
Latch-Up
(Pins 2, 4, 6, 7, 8, 9, 37 (72 Ld Package only) Tested per JESD78D
Class II, Level B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
(All Other pins Tested per JESD78D Class II, Level A) . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
128 Ld LQFP Package (Notes 6, 8) . . . . . .
39
6.5
72 Ld QFN Package (Notes 7, 9) . . . . . . . .
22
0.80
Maximum Storage Temperature. . . . . . . . . . . . . . . . . . . . -55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +85°C
Digital I/O Supply Voltage, PWMVDD . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3V
Core Supply Voltage, CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V
Analog Supply Voltage, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
7. JA is measured with the component mounted on a high effective thermal conductivity test board with direct attach of exposed pad to PCB.
8. For JC, the “case temp” location is taken at the package top center.
9. For JC, the “case temp” is measured on bottom of exposed pad.
10. Absolute Maximum parameters are not tested in production.
Electrical Specifications
TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages
referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum supply currents are
measured in full power down configuration.
SYMBOL
PARAMETER
TEST
CONDITIONS
MIN
(Note 14)
TYP
MAX
(Note 14)
UNIT
2.0
-
-
V
VIH
Digital Input High Logic Level (Note 11)
Relative to RVDD
Relative to RVDD
VIL
Digital Input Low Logic Level (Note 11)
-
-
0.8
V
VOH
High Level Output Drive Voltage
IOUT at - Pin Drive Strength Current. See “Pin Description, DAE-3 (128Pin)” on page 12, and “Pin Description DAE-3HT (72-Pin)” on page 17
RVDD - 0.4
-
-
V
VOL
Low Level Output Drive Voltage
IOUT at + Pin Drive Strength Current. See “Pin Description, DAE-3 (128Pin)” on page 12, and “Pin Description DAE-3HT (72-Pin)” on page 17
-
-
0.4
V
VIHX
High Level Input Drive Voltage XTALI Pin
0.7
-
PLLVDD
V
VILX
Low Level Input Drive Voltage XTALI Pin
-
-
0.3
V
IIN
Input Leakage Current (Note 12)
-
-
±10
µA
CIN
Input Capacitance
-
9
-
pF
PLLVDD - 0.3
-
-
V
VOHO
High Level Output Drive Voltage OSCOUT Pin
VOLO
Low Level Output Drive Voltage OSCOUT Pin
-
-
0.3
V
COUT
Output Capacitance
-
9
-
pF
tRST
nRESET Pulse Width
RVDD
Typical Digital I/O Pad Ring Supply
PWMVDD Typical PWM I/O Pad Ring Supply
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5
(Voltage)
-
10
-
ns
3.0
3.3
3.6
V
(Current, Active)
-
10
-
mA
(Current, Power-Down)
-
<1
-
mA
(Voltage)
3.0
3.3
3.6
V
(Current, Active)
-
5
-
mA
(Current, Power-Down)
-
<1
-
mA
FN6787.3
May 17, 2016
D2-926xx
Electrical Specifications
TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages
referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum supply currents are
measured in full power down configuration. (Continued)
SYMBOL
CVDD
PLLVDD
TEST
CONDITIONS
PARAMETER
Typical Core Supply
(Voltage)
TYP
MAX
(Note 14)
UNIT
1.7
1.8
1.9
V
(Current, Active)
-
300
-
mA
(Current, Power-Down)
-
15
-
mA
1.7
1.8
1.9
V
-
25
-
mA
mA
Typical PLL Analog Supply
(Voltage)
(Current, Active)
(Current, Power-Down)
ADCVDD
MIN
(Note 14)
-
10
-
3.0
3.3
3.6
V
-
12
-
mA
Crystal Frequency (Fundamental Mode Crystal)
20
24.576
24.822
(24.576 + 1%)
MHz
Duty Cycle
40
-
60
%
-
5
20
ms
Typical ADC Analog Supply
(Voltage)
(Current, Active, Power-Down)
CRYSTAL OSCILLATOR
Xo
Dt
tSTART
Start-Up Time (Start-Up Time is Oscillator Enabled
(with Valid Supply) to Stable Oscillation)
PLL
FVCO
FIN
VCO Frequency
80.00
294.912
297.86
MHz
Input Reference Frequency
20
-
24.822
(24.576 + 1%)
MHz
Feedback Dividers (Integer)
4
12
15
PLL Lock Time from any Input Change
-
2
-
ms
1.8V POWER-ON RESET
VEN
Reset Enabled Voltage Level
0.9
1.1
1.4
V
tREJ
POR Pulse Width Rejection (Note 14)
-
150
500
µs
tDIS
POR Minimum Output Pulse Width
-
5
-
µs
1.4
1.5
1.6
V
1.8V BROWNOUT DETECTION
Detect Level
tBOD1
tO1
Pulse Width Rejection
Minimum Output Pulse Width
100
-
ns
20
-
-
ns
2.5
2.7
2.9
V
3.3V BROWNOUT DETECTION
Detect Level
tBOD3
tO3
Pulse Width Rejection
Minimum Output Pulse Width
100
-
ns
20
-
-
ns
1.3
1.4
1.5
V
ADC PERFORMANCE SPECIFICATIONS (DAE-3 only)
VREF
ADCREF DC Level
IREF
ADCREF Load Current
VAIN
Analog Input Level
1.0 VP-P 1kHz
ADC Dynamic Range and SNR (Note 15)
(ADC + ADC Decimator performance only, DSP inactive, no digital sine wave input
audio processing, PWM outputs off, no pPWM switching)
reference level,
using firmware
ADC Dynamic Range and SNR (Note 15)
(DSP active and processing audio data, PWM active and driving from Audio
Canvas III™ rev
audio outputs, measurements using typical system-level amplifier
3.1.4 or newer.
equivalent as measurement environment)
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6
-
-
±20
µA
VREF - 0.6
-
VREF + 0.6
V
-
94
-
dB
-
83
-
dB
FN6787.3
May 17, 2016
D2-926xx
Electrical Specifications
TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages
referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum supply currents are
measured in full power down configuration. (Continued)
MIN
(Note 14)
TYP
MAX
(Note 14)
UNIT
THD+N
-
-80
-
dB
Gain Mismatch
-
0.1
-
dB
Crosstalk
-
-80
-
dB
Power Supply Rejection
-
-70
-
dB
SYMBOL
TEST
CONDITIONS
PARAMETER
NOTES:
11. All input pins except XTALI.
12. Input leakage applies to all pins except XTALO.
13. Power-down is with device in reset and clocks stopped.
14. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
15. Analog performance is system-design dependent and is affected by factors that include PCB layout, shielding and routing of analog traces, additional
components within the analog input path, and power supply isolation.
Serial Audio Interface Port Timing
grounds at 0.0V. All voltages referenced to ground.
SYMBOL
(Figure 1) TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All
MIN
(Note 14)
DESCRIPTION
TYP
MAX
(Note 14)
UNIT
12.5
MHz
tcSCLK
SCKRx Frequency - SCKR0, SCKR1
twSCLK
SCKRx Pulse Width (High and Low) - SCKR0, SCKR1
40
ns
tsLRCLK
LRCKRx Set-Up to SCLK Rising - LRCKR0, LRCKR1
20
ns
thLRCLK
LRCKRx Hold from SCLK Rising - LRCKR0, LRCKR1
20
ns
tsSDI
SDINx Set-Up to SCLK Rising - SDIN0, SDIN1
20
ns
thSDI
SDINx Hold from SCLK Rising - SDIN0, SDIN1
20
ns
tdSDO
SDOUTx Delay from SCLK Falling
20
tcSCLK
ns
twSCLK
SCKRx
thLRCLK
twSCLK
LRCLKRx
tsLRCLK
tsSDI
SDINx
tdSDO
thSDI
SDOUTx
FIGURE 1. SERIAL AUDIO INTERFACE PORT TIMING
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FN6787.3
May 17, 2016
D2-926xx
Two-Wire (I2C) Interface Port Timing
(Figure 2) TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All
grounds at 0.0V. All voltages referenced to ground.
SYMBOL
MIN
(Note 14)
DESCRIPTION
MAX
(Note 14)
UNIT
100
kHz
fSCL
SCL Frequency
tbuf
Bus Free Time Between Transmissions
4.7
µs
twlowSCLx
SCL Clock Low
4.7
µs
twhighSCLx
SCL Clock High
4.0
µs
tsSTA
Set-Up Time For a (Repeated) Start
4.7
µs
thSTA
Start Condition Hold Time
4.0
µs
thSDAx
SDA Hold From SCL Falling (Note 16)
0
µs
tsSDAx
SDA Set-Up Time to SCL Rising
250
ns
tdSDAx
SDA Output Delay Time From SCL Falling
3.5
µs
tr
Rise Time of Both SDA and SCL
1
µs
tf
Fall Time of Both SDA and SCL
300
ns
tsSTO
Set-Up Time For a Stop Condition
4.7
µs
NOTE:
16. Data must be held sufficient time to bridge the 300ns transition time of SCL.
twhighSCLx
tR
twlowSCLx
tF
SCLx
tsSTA
thSDAx
tsSDAx
tsSTO
tBUF
SDAx (INPUT)
thSTAx
SDAx (OUTPUT)
tdSDAx
FIGURE 2. I2C INTERFACE TIMING
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FN6787.3
May 17, 2016
D2-926xx
SPI™ Interface Port Timing
All voltages referenced to ground.
(Figure 3) TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V.
SYMBOL
MIN
(Note 14)
DESCRIPTION
MAX
(Note 14)
UNIT
8
ns
SPI MASTER MODE TIMING
tV
MOSI Valid From Clock Edge
tS
MISO Set-Up to Clock Edge
2
ns
tH
MISO Hold From Clock Edge
2
ns
tWI
nCS Minimum Width
3
3 system clocks
+ 2ns
SPI SLAVE MODE TIMING
tV
MISO Valid From Clock Edge
8
ns
tS
MOSI Set-Up to Clock Edge
2
ns
tH
MOSI Hold From Clock Edge
2
ns
tWI
nCS Minimum Width
3
3 system clocks
+ 2ns
SCK (CPHA = 1, CPOL = 0
SCK (CPHA = 0, CPOL = 0
tV
tV
MOSI
tS
tH
MISO (CPHA = 0
tWI
nCS
FIGURE 3. SPI TIMING
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FN6787.3
May 17, 2016
D2-926xx
Pin Configuration DAE-3 (128-Pin Package)
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10
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PWMVDD
PWM0
PWM1
PWM2
PWM3
PWMGND
PWMVDD
PWM4
PWM5
PWM6
PWM7
PWMGND
PWMVDD
PWM8
PWM9
PWM10
PWM11
PWM12
PWM13
PWMGND
PWMVDD
PWM14
PWM15
PWM16
PWM17
PWMGND
CVDD
CGND
RGND
RVDD
GPIO1
PROTECT2
PSCURR
PWMSYNC
PROTECT3
PROTECT4
PROTECT5
PROTECT6
PROTECT7
PUMPLO
PSSYNC
PSTEMP
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GPIO4
GPIO5
GPIO6
SDA1
SCL1
PROTECT9
SPDIFRX1
SPDIFRX0
SPDIFTX
TEST
IRQA
IRQB
IRQC
IRQD
TIO2
CVDD
CVDD
CGND
CGND
RGND
RVDD
PUMPHI
SC20
SRD2
SC21
SCK2
STD2
SC22
MCLK
SCK3
STD3
SC32
SC30
SC31
SRD3
STD0
SCK0
CVDD
CVDD
CGND
CGND
RGND
RVDD
SRD0
SC00
SC01
SC02
SCK
TIO1
MISO
MOSI
GPIO7
GPIO3
GPIO2
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
SCL0
SDA0
GPIO0
PROTECT0
PROTECT1
TIO0
nRESET
nRSTOUT
SRD1
SCK1
STD1
SC10
SC11
SC12
CVDD
CGND
RGND
RVDD
nCS
nTRST
ADCGND
AIN0
ADCREF
AIN1
ADCVDD
PLLAVDD
XTALO
XTALI
PLLTESTA
PLLTESTB
PLLAGND
OSCOUT
D2-92633, D2-92634
(128 LD LQFP)
TOP VIEW
FN6787.3
May 17, 2016
D2-926xx
Pin Configuration DAE-3HT (72-Pin Package)
SCL0/TEMP
SDA0/TEMPREF
PROTECT0
PROTECT1
TIO0/PSSYNC
nRESET
nRSTOUT
SCK1/MCLK
CVDD
CGND
RGND
RVDD
nSS
PLLAVDD
XTALO
XTALI
PLLAGND
PWMVDD
D2-92683, D2-92684
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
SCLK3 (SC20)
1
54
PWM0
SDIN3 (SRD2)
2
53
PWM1
LRCK3 (SC21)
3
52
PWM2
SCLK4 (SCK2)
4
51
PWM3
SDIO4 (STD2)
5
50
PWMGND
LRCK4 (SC22)
6
49
PWM4
SCLK12 (SCK3)
7
48
PWM5
SDIN2 (STD3)
8
47
PWM6
LRCK12 (SC32)
9
46
PWM7
SDIN1 (SRD3)
10
45
PWM8
CVDD
11
44
PWM9
CGND
12
43
PWM10
RGND
13
42
PWM11
RVDD
14
41
CVDD
24
25
26
27
28
29
30
31
32
33
34
35
36
PROTECT5
PROTECT6/
nMUTE
PROTECT7/
nOVRT
23
PROTECT4
22
PROTECT3
21
RVDD
PROTECT2
20
RGND
37
19
CGND
18
IRQD
MOSI
CVDD
RVDD
IRQC
38
IRQA
17
IRQB
MISO
TEST
RGND
SPDIFTX
CGND
39
SPDIFRX
40
16
SCL1
15
SDA1
SCK
TIO1/NTC
NOTE:
17. All pins pass Jedec II 100mA at +85°C, with exception of pins 2, 4, 6, 7, 8, 9, 37, which pass 50mA at +85°C
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FN6787.3
May 17, 2016
D2-926xx
Pin Description, DAE-3 (128-Pin)
TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
SC20
I/O
3.3
8
Serial Audio Interface 2, I2S0 SCLK
2
SRD2
I/O
3.3
4
Serial Audio Interface 2, I2S0 SDIN
3
SC21
I/O
3.3
8
Serial Audio Interface 2, I2S0 LRCK
4
SCK2
I/O
3.3
8
Serial Audio Interface 2, I2S1 SCLK
5
STD2
I/O
3.3
8
Serial Audio Interface 2, I2S1 SDIN
6
SC22
I/O
3.3
4
Serial Audio Interface 2, I2S1 LRCK
7
MCLK
O
3.3
16
I2S Serial Audio Master Clock output for external ADC/DAC components, drives low on reset and
is enabled by firmware assignment.
8
SCK3
I/O
3.3
8
Serial Audio Interface 3, I2S3 SCLK
9
STD3
I/O
3.3
8
Serial Audio Interface 3, I2S3 SDIN
10
SC32
I/O
3.3
8
Serial Audio Interface 3, I2S3 LRCK
11
SC30
I/O
3.3
8
Serial Audio Interface 3, I2S2 SCLK
12
SC31
I/O
3.3
8
Serial Audio Interface 3, I2S2 LRCK
13
SRD3
I/O
3.3
4
Serial Audio Interface 3, I2S2 SDIN
14
STD0
I/O
3.3
8
Serial Audio Interface 0, I2S SDAT0
15
SCK0
I/O
3.3
8
Serial Audio Interface 0, I2S LRCK0
16
CVDD
P
3.3
Core power, 1.8V
17
CVDD
P
3.3
Core power, 1.8V
18
CGND
P
3.3
Core ground
19
CGND
P
3.3
Core ground
20
RGND
P
3.3
Digital pad ring ground. Internally connected to PWMGND.
21
RVDD
P
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
22
SRD0
I/O
3.3
4
Serial Audio Interface 0, SDIO, Defaults to input, and may be configured as GPIO by firmware.
23
SC00
I/O
3.3
8
Serial Audio Interface 0, SDIO, Defaults to input, and may be configured as GPIO by firmware.
24
SC01
I/O
3.3
8
Serial Audio Interface 0, I2S SDAT1
25
SC02
I/O
3.3
8
Serial Audio Interface 0, I2S LRCK1
26
SCK
I/O
3.3
4
SPI clock I/O with hysteresis input.
27
TIO1
I/O
3.3
16
Timer I/O Port 1. Operation and assignment is controlled by firmware. Leave unconnected when
not in use.
28
MISO
I/O
3.3
4
SPI master input, slave output data signal.
29
MOSI
I/O
3.3
4
SPI master output, slave input data signal.
30
GPIO7
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
31
GPIO3
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
32
GPIO2
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
33
GPIO4
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
PIN
PIN
NAME
(Note 18)
1
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12
DESCRIPTION
FN6787.3
May 17, 2016
D2-926xx
Pin Description, DAE-3 (128-Pin) (Continued)
TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
GPIO5
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
35
GPIO6
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
36
SDA1
I/O
3.3
8 - OD
Two-Wire Serial data Port 1. Bidirectional signal used by both the master and slave controllers for
data transport.
37
SCL1
I/O
3.3
8 - OD
Two-Wire Serial clock Port 1. Bidirectional signal is used by both the master and slave controllers
for clock signaling.
38
PROTECT9
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel
assignment is defined by firmware.)
39
SPDIFRX1
I
3.3
S/PDIF Digital audio data input 1
40
SPDIFRX0
I
3.3
S/PDIF Digital audio data input 0
41
SPDIFTX
O
3.3
42
TEST
I
3.3
Factory test use only. Must be tied low.
43
IRQA
I
3.3
Interrupt request Port A, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
44
IRQB
I
3.3
Interrupt request Port B, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
45
IRQC
I
3.3
Interrupt request Port C, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
46
IRQD
I
3.3
Interrupt request Port D, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
47
TIO2
I/O
3.3
48
CVDD
P
3.3
Core power, 1.8V
49
CVDD
P
3.3
Core power, 1.8V
50
CGND
P
3.3
Core ground
51
CGND
P
3.3
Core ground
52
RGND
P
3.3
Digital pad ring ground. Internally connected to PWMGND.
53
RVDD
P
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
54
PUMPHI
I/O
3.3
16
Assignable I/O. Function and operation defined by firmware.
55
PUMPLO
I/O
3.3
16
Assignable I/O. Function and operation defined by firmware.
56
PSSYNC
I/O
3.3
16
Synchronizing output signal to switching power supply. (Operates under specification of firmware
and resets to high impedance inactive state when not used.)
57
PSTEMP
I/O
3.3
4
Assignable I/O. Function and operation defined by firmware.
58
PSCURR
I/O
3.3
4
Assignable I/O. Function and operation defined by firmware.
59
PWMSYNC
I/O
3.3
16
PWM synchronization port. (Function and operation is defined by firmware.)
60
PROTECT3
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel
assignment is defined by firmware.)
PIN
PIN
NAME
(Note 18)
34
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13
4
16
DESCRIPTION
S/PDIF Digital audio output. (Audio content and audio processing signal flow is dependent upon
firmware, driving stereo output up to 192kHz.)
Timer I/O Port 2. Operation and assignment is controlled by firmware. Leave unconnected when
not in use.
FN6787.3
May 17, 2016
D2-926xx
Pin Description, DAE-3 (128-Pin) (Continued)
TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
PROTECT4
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel
assignment is defined by firmware.)
62
PROTECT5
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel
assignment is defined by firmware.)
63
PROTECT6
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel
assignment is defined by firmware.)
64
PROTECT7
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel
assignment is defined by firmware.)
65
PROTECT2
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel
assignment is defined by firmware.)
66
GPIO1
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
67
RVDD
P
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
68
RGND
P
3.3
Digital pad ring ground. Internally connected to PWMGND.
69
CGND
P
3.3
Core ground
70
CVDD
P
3.3
Core power, 1.8V
71
PWMGND
P
3.3
PWM output pin ground. Internally connected to RGND.
72
PWM17
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
73
PWM16
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
74
PWM15
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
75
PWM14
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
76
PWMVDD
P
3.3
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to
RVDD.
77
PWMGND
P
3.3
PWM output pin ground. Internally connected to RGND.
78
PWM13
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
79
PWM12
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
80
PWM11
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
81
PWM10
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
82
PWM9
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
83
PWM8
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
84
PWMVDD
P
3.3
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to
RVDD.
85
PWMGND
P
3.3
PWM output pin ground. Internally connected to RGND.
86
PWM7
I/O
3.3
PIN
PIN
NAME
(Note 18)
61
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14
8 or 16
DESCRIPTION
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
FN6787.3
May 17, 2016
D2-926xx
Pin Description, DAE-3 (128-Pin) (Continued)
TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
PWM6
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
88
PWM5
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
89
PWM4
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
90
PWMVDD
P
3.3
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected
to RVDD.
91
PWMGND
P
3.3
PWM output pin ground. Internally connected to RGND.
92
PWM3
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
93
PWM2
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
94
PWM1
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
95
PWM0
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
96
PWMVDD
P
3.3
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to
RVDD.
97
OSCOUT
P
1.8
Analog oscillator output to slave D2-926xx devices. OSCOUT drives a buffered version of the
crystal oscillator signal from the XTALI pin.
98
PLLAGND
P
1.8
PLL Analog ground
99
PLLTESTB
O
1.8
Factory test use only. Must be tied low.
100
PLLTESTA
O
1.8
Factory test use only. Must be tied low.
101
XTALI
P
1.8
Crystal oscillator analog input port. An external clock source would be driven into the this port. In
multi-D2-926xx systems, the OSCOUT from the master D2-926xx would drive the XTALI pin.
102
XTALO
P
1.8
Crystal oscillator analog output port. When using an external clock source, this pin must be open.
XTALO does not have a drive strength specification.
103
PLLAVDD
P
1.8
PLL Analog power, 1.8V
104
ADCVDD
P
3.3
Analog power for internal ADC, 3.3V
105
AIN1
I
3.3
Analog input 1 to internal ADC
106
ADCREF
O
3.3
Analog voltage reference output. Must be de-coupled to analog ground with 1µF capacitor.
107
AIN0
I
3.3
Analog input 0 to internal ADC
108
ADCGND
P
3.3
Analog ground for internal ADC
109
nTRST
I
3.3
Factory test only. Must be tied high at all times.
110
nCS
I/O
3.3
111
RVDD
P
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
112
RGND
P
3.3
Digital pad ring ground. Internally connected to PWMGND.
113
CGND
P
3.3
Core ground
114
CVDD
P
3.3
Core power, 1.8V
115
SC12
I/O
3.3
8
Serial Audio Interface 1, LRCK
116
SC11
I/O
3.3
8
Serial Audio Interface 1, SDAT3
PIN
PIN
NAME
(Note 18)
87
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15
4
DESCRIPTION
SPI slave select I/O.
FN6787.3
May 17, 2016
D2-926xx
Pin Description, DAE-3 (128-Pin) (Continued)
TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
SC10
I/O
3.3
8
Serial Audio Interface 1, data (Assignment by firmware control.)
118
STD1
I/O
3.3
8
Serial Audio Interface 1, SDAT2
119
SCK1
I/O
3.3
8
Serial Audio Interface 1, SCK
120
SRD1
I/O
3.3
4
Serial Audio Interface 1, data (Assignment by firmware control.)
121
nRSTOUT
O
3.3
16 - OD
122
nRESET
I
3.3
123
TIO0
I/O
3.3
16
Timer I/O Port 0. Operation and assignment is controlled by firmware. Leave unconnected when
not in use.
124
PROTECT1
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel
assignment is defined by firmware.)
125
PROTECT0
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel
assignment is defined by firmware.)
126
GPIO0
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
127
SDA0
I/O
3.3
8 - OD
Two-Wire Serial data Port 0. Bidirectional signal used by both the master and slave controllers for
data transport.
128
SCL0
I/O
3.3
8 - OD
Two-Wire Serial clock Port 0. Bidirectional signal is used by both the master and slave controllers
for clock signaling.
PIN
PIN
NAME
(Note 18)
117
DESCRIPTION
Active low open-drain reset output. Pin drives low from POR generator, 3.3V brownout detector
going active, or from 1.8V brownout detector going active. This output should be used to initiate a
system reset to the nRESET pin upon brownout event detection.
Active low reset input with hysteresis. Activates system level reset when pulled low, initializing all
internal logic and program operations. System latches boot mode selection of the IRQ input pins
on the rising edge.
NOTES:
18. Unless otherwise specified, all pin names are active high. Those that are active low have an “n” prefix.
19. All power and ground pins of same names are to be tied together to all other pins of their same name. (i.e., CVDD pins to be tied together, CGND pins
to be tied together, RVDD pins to be tied together, and RGND pins to be tied together.) CGND and RGND are to be tied together on board. RGND and
PWMGND pins are also internally connected and are to be tied together.
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16
FN6787.3
May 17, 2016
D2-926xx
Pin Description DAE-3HT (72-Pin)
PIN
PIN
NAME
(Note 18)
TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
DESCRIPTION
1
SCLK3
(SC20)
In
3.3
8
Bit clock, I2S Port 3, audio input channels 5-6. (I2S Port 3 is 1 of 3 input-only ports, providing
channels 5-6 input audio content.)
2
SDIN3
(SRD2)
In
3.3
4
Audio data, I2S Port 3, audio input channels 5-6 (I2S Port 3 is 1 of 3 input-only ports, providing
channels 5-6 input audio content.)
3
LRCK3
(SC21)
In
3.3
8
L/R clock, I2S Port 3, audio input channels 5-6 (I2S Port 3 is 1 of 3 input-only ports, providing
channels 5-6 input audio content.)
4
SCLK4
(SCK2)
In
3.3
8
Bit clock, I2S Port 4, audio input channels 7-8, or audio output channels 1-2. (I2S Port 4 is either
an I2S input port, or and I2S output port. Selection of input or output is defined by firmware. When
used as input, Port 4 provides channel 7-8 input audio content. When used as an output, Port 4
provides the 2 channels of I2S output audio.)
5
SDIO4
(STD2)
I/O
3.3
8
Audio data, I2S Port 4, input channels 7-8, or output channels 1-2. (I2S Port 4 is either an I2S input
port, or and I2S output port. Selection of input or output is defined by firmware. When used as
input, Port 4 provides channel 7-8 input audio content. When used as an output, Port 4 provides
the 2 channels of I2S output audio.)
6
LRCK4
(SC22)
In
3.3
4
L/R clock, I2S Port 4, audio input channels 7-8, or audio output channels 1-2. (I2S Port 4 is either
an I2S input port, or and I2S output port. Selection of input or output is defined by firmware. When
used as input, Port 4 provides channel 7-8 input audio content. When used as an output, Port 4
provides the 2 channels of I2S output audio.)
7
SCLK12
(SCK3)
In
3.3
8
Bit clock, I2S ports 1 and 2, audio input channels 1-4 (I2S ports 1 and 2 are 2 of the 3 input-only
ports, providing channels 1-4 input audio content.)
8
SDIN2
(STD3)
In
3.3
8
Audio data, I2S Port 2, audio input channels 3-4 (I2S ports 1 and 2 are 2 of the 3 input-only ports,
providing channels 1-4 input audio content.)
9
LRCK12
(SC32)
In
3.3
8
L/R clock, I2S ports 1 and 2, audio input channels 1-4 (I2S ports 1 and 2 are 2 of the 3 input-only
ports, providing channels 1-4 input audio content.)
10
SDIN1
(SRD3)
In
3.3
8
Audio data, I2S Port 1, audio input channels 1-2 (I2S ports 1 and 2 are 2 of the 3 input-only ports,
providing channels 1-4 input audio content.)
11
CVDD
P
3.3
Core power, 1.8V
12
CGND
G
3.3
Core ground
13
RGND
G
3.3
Digital pad ring ground. Internally connected to PWMGND.
14
RVDD
P
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
15
SCK
I/O
3.3
4
SPI clock I/O with hysteresis input.
16
TIO1/NTC
I/O
3.3
16
Timer I/O Port 1, or assignable NTC temperature sensing common I/O. Operation and assignment
is controlled by firmware. Leave unconnected when not in use.
17
MISO
I/O
3.3
4
SPI master input, slave output data signal.
18
MOSI
I/O
3.3
4
SPI master output, slave input data signal.
19
SDA1
I/O
3.3
8 - OD
Two-Wire Serial (I2C) data Port 1. Primary control interface data signal used for device boot and
control. Bidirectional port for both master and slave controllers operation.
20
SCL1
I/O
3.3
8 - OD
Two-Wire Serial (I2C) clock Port 1. Primary control interface clock signal used for device boot and
control. Bidirectional port for both master and slave controllers operation.
21
SPDIFRX
In
3.3
S/PDIF Digital audio data input
22
SPDIFTX
O
3.3
S/PDIF Digital audio output. (Audio content and audio processing signal flow is dependent upon
firmware, driving stereo output up to 192kHz.)
23
TEST
In
3.3
Factory test use only. Must be tied low.
24
IRQA
In
3.3
Interrupt request Port A, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
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FN6787.3
May 17, 2016
D2-926xx
Pin Description DAE-3HT (72-Pin) (Continued)
DRIVE
STRENGTH
(mA)
PIN
PIN
NAME
(Note 18)
TYPE
VOLTAGE
LEVEL
(V)
25
IRQB
In
3.3
Interrupt request Port B, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
26
IRQC
In
3.3
Interrupt request Port C, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
27
IRQD
In
3.3
Interrupt request Port D, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
28
CVDD
P
3.3
Core power, 1.8V
29
CGND
G
3.3
Core ground
30
RGND
G
3.3
Digital pad ring ground. Internally connected to PWMGND.
31
RVDD
P
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers. Internally connected to PWMVDD.
32
PROTECT3
In
3.3
4
PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel
assignment, and optional GPIO is defined by firmware.)
33
PROTECT4
In
3.3
4
PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel
assignment, and optional GPIO is defined by firmware.)
34
PROTECT5
In
3.3
4
PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel
assignment, and optional GPIO is defined by firmware.)
35
PROTECT6
/nMUTE
I/O
3.3
4
PWM protection input with hysteresis, or optional mute output. (One of 8 protection inputs.
Specific function, channel assignment, and/or optional GPIO is defined by firmware.)
36
PROTECT7
/nOVRT
In
3.3
4
PWM protection input with hysteresis, or optional over-temperature monitor input. (One of 8
protection inputs. Specific function, channel assignment, and/or optional GPIO is defined by
firmware.)
37
PROTECT2
In
3.3
4
PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel
assignment, and optional GPIO is defined by firmware.)
38
RVDD
P
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers. Internally connected to PWMVDD.
39
RGND
G
3.3
Digital pad ring ground. Internally connected to PWMGND.
40
CGND
G
3.3
Core ground
41
CVDD
P
3.3
Core power, 1.8V
42
PWM11
O
3.3
8 or 16
PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
43
PWM10
O
3.3
8 or 16
PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
44
PWM9
O
3.3
8 or 16
PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
45
PWM8
O
3.3
8 or 16
PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
46
PWM7
O
3.3
8 or 16
PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
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DESCRIPTION
FN6787.3
May 17, 2016
D2-926xx
Pin Description DAE-3HT (72-Pin) (Continued)
TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
PWM6
O
3.3
8 or 16
PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
48
PWM5
O
3.3
8 or 16
PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
49
PWM4
O
3.3
8 or 16
PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
50
PWMGND
O
3.3
51
PWM3
O
3.3
8 or 16
PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
52
PWM2
O
3.3
8 or 16
PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
53
PWM1
O
3.3
8 or 16
PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
54
PWM0
O
3.3
8 or 16
PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
55
PWMVDD
P
3.3
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to
RVDD.
56
PLLAGND
G
1.8
PLL Analog ground
57
XTALI
In
1.8
Crystal oscillator analog input port. When using an external clock source, the external clock is
driven into the this port.
58
XTALO
O
1.8
Crystal oscillator analog output port. When using an external clock source, this pin must be open.
XTALO does not have a drive strength specification.
59
PLLAVDD
P
1.8
PLL Analog power, 1.8V
60
nSS
O
3.3
61
RVDD
P
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers. Internally connected to PWMVDD.
62
RGND
G
3.3
Digital pad ring ground. Internally connected to PWMGND.
63
CGND
G
3.3
Core ground
64
CVDD
P
3.3
Core power, 1.8V
65
SCK1
/MCLK
I/O
3.3
8
66
nRSTOUT
O
3.3
16 - OD
67
nRESET
In
3.3
68
TIO0
/PSSYNC
I/O
3.3
PIN
PIN
NAME
(Note 18)
47
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19
DESCRIPTION
PWM output pin power ground
4
SPI slave select I/O.
Assignable general purpose I/O, or MCLK output. Operation and assignment is controlled by
firmware. Assigns as default output for MCLK when enabled through firmware.
Active low open drain reset output. Pin drives low from POR generator, 3.3V brownout detector
going active, or from 1.8V brownout detector going active. This output should be used to initiate a
system reset to the nRESET pin upon brownout event detection.
Active low reset input with hysteresis. Activates system level reset when pulled low, initializing all
internal logic and program operations. System latches boot mode selection of the IRQ input pins
on the rising edge.
16
Timer I/O Port 0, or power supply sync output. Operation and assignment is controlled by
firmware. Leave unconnected when not in use.
FN6787.3
May 17, 2016
D2-926xx
Pin Description DAE-3HT (72-Pin) (Continued)
TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
PROTECT1
In
3.3
4
PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel
assignment, and optional GPIO is defined by firmware.)
70
PROTECT0
In
3.3
4
PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel
assignment, and optional GPIO is defined by firmware.)
71
SDA0
/TEMPREF
I/O
3.3
8 - OD
Two-Wire Serial data Port 0, or assignable I/O. Available for NTC temperature sensing reference
as assignable I/O. Function is assigned by firmware.
72
SCL0
/TEMPNTC
I/O
3.3
8 - OD
Two-Wire Serial clock Port 0, assignable I/O. Available for NTC temperature sensing reference as
assignable I/O. Function is assigned by firmware.
PIN
PIN
NAME
(Note 18)
69
DESCRIPTION
NOTES:
20. Unless otherwise specified, all pin names are active high. Those that are active low have an “n” prefix.
21. All power and ground pins of same names are to be tied together to all other pins of their same name. (i.e., CVDD pins to be tied together, CGND pins
to be tied together, RVDD pins to be tied together, and RGND pins to be tied together.) CGND and RGND are to be tied together on board. RGND and
PWMGND pins are also internally connected and are to be tied together.
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20
FN6787.3
May 17, 2016
D2-926xx
Functional Block Diagram - DAE-3
FIGURE 4. DAE-3 IC FUNCTIONAL BLOCK DIAGRAM
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21
FN6787.3
May 17, 2016
D2-926xx
Functional Block Diagram - DAE-3HT
FIGURE 5. DAE-3HT IC FUNCTIONAL BLOCK DIAGRAM
Submit Document Feedback
22
FN6787.3
May 17, 2016
D2-926xx
Functional Description
The DAE-3 supports a Class-D amplifier system built around
internal audio processing blocks and amplifier system hardware
functions.
Introduction
The DAE-3 family of ICs provide the core functionality, amplifier
control, and complete audio signal processing for D2Audio
Class-D amplifier solutions. The devices are highly
programmable with all system features and functionality totally
defined by firmware, that includes complete definition of audio
processing, signal flow, digital audio I/O, and amplifier hardware
interface control.
The Audio Canvas III software design tool supports building of the
firmware for the DAE-3 family devices. Using Audio Canvas III, the
designer is able to fully define audio processing and hardware
function features with I/O assignments, and build complete
production-ready firmware for the DAE-3 devices.
DAE-3 DEVICE DESIGNATIONS
The DAE-3 device family includes both the DAE-3 and DAE-3HT
ICs. Functional specifications are identical to both designations
of this family unless otherwise indicated.
The family device names apply to these part numbers:
DAE FAMILY
DEVICE NAME
DAE PART
NUMBERS
PACKAGE
PINS
DAE-3
D2-92633-LR
D2-92634-LR
128-Pin Package
DAE-3HT
D2-92683-QR
D2-92684-QR
72-Pin Package
The DAE-3 devices are completely pin-compatible with the DAE-6
devices, allowing full flexibility for function vs cost trade-off,
providing cost-effective solutions for applications of varying
end-user features and capabilities.
The DAE-3HT devices are identical to the DAE-3 but are provided
in a smaller 72-pin package with features and I/O mapped to
pins supported in that package.
AUDIO CANVAS III SUPPORT
Audio Canvas III is a powerful design tool that lets the designer
define audio processing and build a signal flow customized to the
user’s specifications. It fully supports the DAE-3 family including
configuring the DAE family hardware I/O features and pin
assignments. The designer can define the entire audio signal
flow and architecture without signal flow limitations to any
specific system. Capabilities include drag-and-drop of individual
audio processing blocks that can be inserted into the signal flow,
ability to connect and re-route signal flow, and live update
capability to build and download the new audio architecture
directly into the operating amplifier.
The DAE-3 family of ICs supports a wide variety of signal flows
and audio processing options that are fully programmable and
are completely defined by the system firmware and system
architecture.
The firmware is built by the Audio Canvas III software, enabling
full audio processing and amplifier hardware feature definition
by the designer.
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In addition to audio processing blocks and signal flow that are
user-selectable, system functions of hardware are configurable
that include PWM timing control, channel configuration and
assignment, protection and monitoring features, clock
configurations, and other audio system features. Choices and
settings are defined using the Audio Canvas III design tool
software which builds the unique DAE firmware for each
particular system design.
DSP
The majority of the audio processing functions and hardware
feature implementations operate through firmware running
within the DSP core. The core is a 24-bit fixed-point Digital Signal
Processor, with its own DMA, interrupt control, memory spaces,
and control interfaces.
Sample Rate Converters (SRC)
DAE-3 family supports internal asynchronous sample rate
conversion to align input audio streams to a single rate
compatible with the DSP processing rate and PWM switch rate.
The family has 4 independent rate estimators, allowing up to 4
asynchronous stereo inputs (8 channels) to be sample rate
converted and processed simultaneously. The sample rate
converter has a measured SNR that exceeds 140dB and a
THD+N that exceeds -125dB.
Serial Digital Audio Interface
SERIAL DIGITAL AUDIO INPUTS
The DAE-3 families include 4 Serial Audio Interface (SAI) digital
audio input ports supporting up to 8 audio channels.
• The DAE-3 supports four independent SAI ports. All 4 ports
operate asynchronously to receive audio from 4 independent
audio sources, and each of the 4 ports has its own clock and
frame inputs. SAI Port 3 (the 4th port) of the DAE-3 has
multiplexed inputs to select that port’s audio from the SAI
input or from the on-chip ADC.
• The DAE-3HT devices support either 4 SAI input ports, or when
its fourth port is used as an audio output, support 3 SAI input
ports.
Each SAI port supports the digital audio industry I2S standard
which is capable of carrying up to 24-bit Linear PCM audio words
per subframe IEC60958, or compressed digital audio (Dolby®
Digital, AAC, MPEG, etc.) packing per the IEC61937 specification.
The SAI port also supports Left-Justified formatted Linear PCM or
compressed digital audio. These ports support sample rates from
32kHz to 192kHz.
SAI data formats are shown in Figure 6 on page 24. For I2S
format, the left channel data is read when LRCK is low. For the
Left-Justified format, the left channel data is read when LRCK is
high. Either format requires data to be valid on the rising edge of
SCLK and sent MSB-first on SDIN with 32 bits of data per
channel. Each set of digital inputs runs asynchronously to the
others and may accept different sample rates and formats.
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Input audio may be received from the S/PDIF input for 2 audio
input channels, concurrent with and asynchronous from audio
that is also being presented to SAI inputs for other audio input
channels. Routing through the SRC synchronizes this audio from
multiple sources for synchronous audio processing within the
DAE audio processing paths.
SERIAL DIGITAL AUDIO OUTPUTS
Up to 4 SAI ports (up to 8 channels) are supported in the DAE-3
families.
• The DAE-3 supports 4 independent I2S output ports for a total
of 8 channels of audio.
• the DAE-3HT supports 1 I2S output port (2 channels) and that
port is configured to operate as either an input port or as an
output port.
Use and channel assignment to the SAI outputs is configured
using the Audio Canvas III software. Any of the DAE device’s 12
audio processing channels may be assigned to any of the
available SAI output channels. Audio Canvas III also assigns use
of the 4th SAI port as in input or output for the DAE-3HT.
Left Channel
LRCLKx
Right Channel
SCLKx
Serial
Data
MSB
-1
-2
+3
-3
+2
+1
LSB
MSB
-1
-2
-3
+3
+2
+1
LSB
MSB
I2S Format
LRCLKx
Right Channel
Left Channel
SCLKx
Serial
Data
MSB
-1
-2
-3
-4
+3
+2
+1
LSB
MSB
-1
-2
-3
-4
+3
+2
+1
LSB
MSB
-1
Left-Justified
FIGURE 6. SAI PORT SUPPORTED DATA FORMATS FOR DELIVERY OF LINEAR PCM OR COMPRESSED AUDIO DATA
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FN6787.3
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D2-926xx
S/PDIF Digital Audio Interface
ADC input (DAE-3 Devices Only)
The device families include a S/PDIF Digital receiver and
transmitter.
The DAE-3 devices contains a high-performance Analog-to-Digital
Converter (ADC) that connects to input analog sources with a
minimum of interface circuitry. The ADC is included in the DAE-3
devices only. It is not supported in the DAE-3HT devices.
• The DAE-3 devices (128 pin packaged devices) include an
on-chip multiplexer supporting switching of input from 2
different S/PDIF input pins. Input selection determines which
pin routes to the S/PDIF receiver.
• The DAE-3HT devices (72 pin packaged devices) support one
input pin only and do not use multiplex switching.
All of the devices in the family include a S/PDIF Digital
transmitter.
S/PDIF RECEIVER
The S/PDIF receiver input pins are 3.3V CMOS input level
compatible, requiring external circuitry to condition the serial
input. The receiver contains an input transition detector, digital
PLL clock recovery, and a decoder to separate audio, channel
status, and user data. Only the first 24-Channel status bits are
supported. The receiver constantly monitors the incoming data
stream to detect the IEC61937-1 packet headers, and if found,
captures the Pc and Pd data words into registers. The receiver
meets the jitter tolerance specified in IEC60958-4.
S/PDIF is typically used for receiving compressed
(IEC61937-compliant) as well as stereo PCM (IEC60958compliant) audio data. This interface also supports receipt of
compressed audio data that is not compliant with the IEC61937
specification, but instead meets the IEC60958 specification.
S/PDIF receive data is routed through the SRC, providing a time
synchronized audio input stream for use within any of the DAE
audio processing channels. Audio may be presented on the
S/PDIF input asynchronous to audio also being presented to the
I2S Serial Digital inputs such that after routing through the SRC,
are synchronous time aligned for internal DAE audio processing.
S/PDIF TRANSMITTER
The transmitter complies with the consumer applications defined
in IEC60958-3. The transmitter supports 24-bit audio data, 24-bit
user data, and 30-bit channel status data. S/PDIF output is linear
PCM only and is non-compressed. Routing of compressed audio
that is presented to the DAE inputs must be decoded by the DAE
and its firmware before the selected channels may be routed to
the S/PDIF outputs.
Audio routing to the S/PDIF transmitter is defined by the signal
flow built by the Audio Canvas III software. That software
supports assigning any of the audio processing channels to the 2
(L/R) channels of the S/PDIF output. Because all timing of the
internal audio processing is synchronous to the internal DSP and
processing channels, the S/PDIF audio output is also
synchronous to that internal timing.
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At a bandwidth of 20kHz at nominal voltage and temperature,
the ADC input of the DAE-3 provides a typical THD+N
(unweighted) value of -81dB and a typical SNR/Dynamic Range
of 83dB. These typical performances are based on a 1.0VP-P 1
kHz sine wave input reference level, using a representative
system-level amplifier environment processing digital audio data
and producing PWM amplifier outputs.
Analog performance is affected by factors that include PCB
layout, shielding and routing of analog traces, additional
components within the analog input path, and proper power
supply isolation techniques.
The ADC master clock is supplied from the low jitter PLL of the
D2-926xx. The ADC operates synchronous to the DSP processing
which minimizes noise pickup.
PWM Audio Amplifier Outputs
The DAE-3 family devices include an integrated 12-channel PWM
engine. Each engine is independently programmable for timing,
output pin assignment and audio processing path source.
PWM operation is defined by firmware. The Audio Canvas III
design tool provides the selection for audio channel assignment
routing, protection enabling, timing, and PWM output pin
mapping, then uses these selections to build the firmware that
controls the PWM outputs. Some features such as dead-band
timing are also adjustable in real-time through the control
interface.
Programmability enable use of multiple PWM output topologies,
which supporting system designs of a broad range of output
stages. Output topologies include integrated power stages, or
discrete implementations using N+N or P+N for half-bridge,
full-bridge or bridged-tied-load power stages. The PWM outputs
may be used for powered outputs, and may also be used for
driving line-level or headphone outputs.
The 12 PWM channels are mapped to the PWM output pins by
firmware register assignment. Both DAE-3 and DAE-3HT include
12 PWM engines, and their available pins are:
• DAE-3 - 18 assignable and mappable pins
• DAE-3HT- 12 assignable and mappable pins
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Amplifier Protection
The core firmware that operates the DAE-3 family devices
supports protection options to prevent damage from faults
present in class-D amplifier designs. This protection is also
effective against user-induced faults such as clipping, output
overload, or output shorts, including both shorted outputs or
short-to-ground faults.
Protection features and their details are firmware dependent.
The Audio Canvas III program provides selection for assignment
and use of certain protection methods, using the selections for
building the system firmware.
GRACEFUL OVERCURRENT AND SHORT CIRCUIT
Per-channel PWM protection is supported through individual
protection input pins. These PROTECT pins are primarily intended
for protecting the PWM powered output stages and operation is
firmware controlled. The protection input signal is typically
generated by sensing circuits within power stages and can
include sensing for detecting current, temperature, or voltage
fault conditions.
Overcurrent sensing requires a current sensor in the power
device to be protected, usually a powered PWM output. The
typical sensor asserts its fault signal that is routed to the
PROTECT pins of the DAE device.
The D2-926xx devices observe the overcurrent protection inputs
and provides graceful protection for the assigned output stages.
Hardware may be configured to provide immediate current
reduction, cycle-by-cycle output clipping, output signal control,
and output stage deactivation depending on the severity and
duration of high current events. The combination of hardware
features and firmware monitoring allows the system to
differentiate between an overcurrent situation or a more serious
short circuit condition, and supports the managed protection
within the DAE amplifier systems.
Timers provides programmed I/O control of features that are
event or timing dependent. Their hardware pins are assigned to
system features, and operation is controlled through firmware.
Timer pins are configurable based on the features supported
within the system firmware. Choice and operation of their
assigned features is selected through the Audio Canvas III
software that builds the firmware for the specific system project.
POWER SUPPLY SYNCHRONIZATION
The PSSYNC pin provides a power supply synchronization signal
for switching power supplies. This synchronizing of power supply
switching with the PWM switching rate eliminates audio output
tones generated if the switching power supply is not locked to the
amplifier switching.
Firmware settings configure PSSYNC to the desired frequency
needed by the system switching regulator. The Audio Canvas III
software supports selection of use and frequency of this output.
Clocks And PLL
The PLL block operation is completely managed by the system
firmware. The clock generation contains a low jitter PLL critical
for low noise PWM output and a precise master clock source for
the ADC, sample rate conversion, and the audio data paths.
The PLL block includes a low noise crystal oscillator, clock
multipliers clock generation for all internal device timing, PWM
engine timing, and clock reference for use with assignable clock
outputs that include MCLK and PSSYNC outputs.
The system clock is provided by the crystal oscillator, using either
a fundamental mode crystal or a clock input to the XTALI pin. If
the clock input is used, it must be a 1.8V signal level. The input
signal on the XTALI pin is analog buffered and driven onto the
OSCOUT pin for use in driving the XTALI input of other D2-926xx
controllers, for supporting synchronous timing if multiple DAE
devices are used in a single application.
THERMAL PROTECTION
Reset and Initialization
Temperature monitoring may be used to provide warning,
shutdown, or managed output level reduction to attempt to
reduce heating effects at high load power. Multiple thermal
protection methods are supported within the DAE family
firmware. User choice of method and operation is
programmable, using the Audio Canvas III software to configure
settings and options.
The D2-926xx must be reset after power-up to begin proper
operation. In normal system hardware configurations, the reset
occurs automatically via the reset hardware circuitry. The chip
contains power rail sensors, brownout detectors, on the 3.3V and
1.8V power supplies. These brownout sensors will assert and hold
an internal Power-on Reset which will disable the device until the
power supplies are at a safe level for the DSP to start. These same
brownout sensors will detect a power supply voltage droop while
the system is active and provide a safe amplifier shutdown.
Hardware I/O Features
The DAE-3 and DAE-3HT provides programmable I/O pins used
for various hardware functions of the system design. Pin
functions are defined by the product firmware and configured
with the Audio Canvas III software.
GENERAL-PURPOSE I/O AND TIMERS
General Purpose I/O (GPIO) pins are available for system use
with the DAE-3 and are assignable by choice selection in the
Audio Canvas III software. The DAE-3 supports pins assignable to
various hardware features, while the DAE-3HT shares functions
of some of its available device pins providing feature choices in a
lower pin-count package.
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Power Sequencing
The CVDD and RVDD (including PWMVDD) supplies should be
brought up together to avoid high current transients that could
fold back a power supply regulator. The ADCVDD and PLLVDD
may be brought up separately. Best practice would be for all
supplies to feed from regulators with a common power source.
Typically this can be achieved by using a single 5V power source
and regulating the 3.3V and 1.8V supplies from that 5V source.
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Reset
D2-926xx has one reset input: the nRESET pin. The nRESET input
pin (active low, non-reset high) is effectively a power-on system
reset. All internal state logic is initialized by nRESET. While reset
is active the system is held in the reset condition which is defined
as all internal reset signals being active, the crystal oscillator is
running, and the PLL disabled. At the de-assertion of nRESET, the
chip will capture the boot mode selection from the IRQ[D:A] pins
and begin the boot process.
The nRSTOUT pin is an active low open drain reset output. This
pin drives low from the internal power-on-reset generator, 3.3V
brownout detector going active, or from 1.8V brownout detector
going active. This output should be used to initiate a system
reset, and to also connect to the nRESET pin to initiate a DAE
reset upon brownout event detection.
Booting and Boot Modes
D2-926xx includes a fully-programmable DSP with internal boot
ROM. The boot ROM’s primary function is to download a
second-stage boot image from one of several possible sources.
The system requires external firmware to boot the internal DSP.
Internal ROM within the DAE-3 initiates the boot process to read
the boot records and firmware, to load into the internal DAE-3
memory. The boot ROM code is designed to handle both
encrypted and non-encrypted boot images from any of the boot
modes shown in Table 2.
The specific boot mode is selected based on the state of the
IRQD, IRQC, IRQB, and IRQA pins at the time of reset
de-assertion. The mode is selected by a hardware pull-up or
pull-down connection to each of the four boot mode (IRQ[D:A])
pins. (Modes not listed are reserved.)
Control Interfaces
I2C 2-WIRE INTERFACE
The D2-926xx family ICs have two separate I2C 2-wire
compatible ports. Port 1 is used as the external controller
interface, and Port 0 is used for booting from an external
EEPROMs or compatible chips. Both I2C interfaces are
multi-master capable.
SERIAL PERIPHERAL INTERFACE (SPI™)
The Serial Peripheral Interface (SPI) is provides an alternate boot
source interface such as an SPI Flash. The SPI port is used only
for boot operation. Register control of the system firmware is not
implemented through the SPI interface.
TABLE 2. BOOT MODES
MODE
IRQ[D:A]
DAE M/S
XTALI RANGE
INTERFACE SPEED
DESCRIPTION
I2C Port 1 slave to external master, boot at address 88
0
0000
Slave
N/A
per Master
1
0001
Master
24.576MHz
400kb/s
I2C Port 0 master to I2C EEPROM slave
2
0010
Master
24.576MHz
1.53MHz
SPI port master to SPI Flash slave
3-F
-
-
-
-
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Reserved
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Reading and Writing Control Registers
8. Transmit data lower byte
DAE control is provided through the I2C port, using registers and
9. I2C STOP command
memory spaces that are defined within the firmware. After
booting and initialization, this control port provides continuous
read and write access for control and monitoring of the amplifier
system. Register addresses are dynamic based on the audio path
signal flow and hardware options selected for the particular
project. Address locations are generated for each system through
a header file from the Audio Canvas III design tool that maps the
address location to each parameter of the system.
All reads to registers require two steps. First, the master must
send a dummy write which consist of sending a Start, followed by
the device address with the write bit set, and three register
address bytes. Next, the master must send a repeated Start,
following with the device address with the read/write bit set to
read, and then read the next three data bytes. The master must
Acknowledge (ACK) the first two read bytes and send a Not
Acknowledge (NACK) on the third byte received and a Stop
condition to complete the transaction. The device's control
interface acknowledges each byte by pulling SDA low on the bit
immediately following each write byte. The device read function,
as shown in Figure 8, executes the following 11 steps as the I2C
bus master:
The I2C port is used for reading and writing the control data. The
highest-order byte of the register address (bits 23:16) determines
the internal address space used for control read or write access,
and the remaining 16 bits (bits 15:0) describe the actual address
within that space.
1. I2C START command
All reads or writes to registers (shown in Figures 7 and 8) begin
with a Start Condition, followed by the Device Address byte, three
Register Address bytes, three Data bytes and a Stop Condition.
Register writes through the I2C interface are initiated by setting
the read/write bit that is within the device address byte. The
device write function as, shown in Figure 7, executes the
following 9 steps as the I2C bus master:
2. Transmit device I2C address with W
3. Transmit mode byte
4. Transmit upper memory address byte
5. Transmit lower memory address byte
6. Repeat START command
1. I2C START command
7. Transmit device I2C address with R
2. Transmit device I2C address with W
8. Receive data upper byte
3. Transmit mode byte
9. Receive data middle byte
4. Transmit upper memory address byte
10. Receive data lower byte
5. Transmit lower memory address byte
11. I2C STOP command or NACK
6. Transmit data upper byte
7. Transmit data middle byte
ACK
DEVICE-ADDR
ACK
ACK
REGISTER [23:16]
START
REGISTER [15:8]
REGISTER [7:0]
R/W
ACK
Write Sequence
REGISTER [7:0]
ACK
DATA [23:16]
ACK
DATA [15:8]
ACK
DATA [7:0]
STOP
FIGURE 7. I2C WRITE SEQUENCE OPERATION
Step 1
ACK
DEVICE-ADDR
START
Read Sequence
ACK
REGISTER [23:16]
ACK
REGISTER [15:8]
R/W
ACK
MASTER
ACK
ACK
DEVICE-ADDR
REPEAT
START
REGISTER [7:0]
DATA [23:16]
MASTER
ACK
DATA [15:8]
R/W
ACK
REPEAT
START
NACK
DATA [7:0]
STOP
Step 2
FIGURE 8. I2C READ SEQUENCE OPERATION
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FN6787.3
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D2-926xx
Audio Processing
Audio processing is totally defined by the system firmware and
signal flow. Audio processing blocks are implemented using the
Audio Canvas III design tool software. This tool includes an
extensive library of audio processing functions that are
developed for operating in the DAE-3 and DAE-3HT device
families.
The Audio Canvas III software provides the interface to define
and build a complete audio sound processing system. Drag-anddrop inserting of its included audio processing blocks enables
building a customized signal flow, by placing audio algorithms
into customized firmware for executing on the DAE devices.
Audio Processing Algorithms
Audio processing algorithms include all of these following
functions. Multiples of each are permitted, and there is no limit
to the order or interconnect of the algorithm blocks. Upon
completion of defining the audio processing path, the Audio
Canvas III software incorporates the blocks and builds the final
system firmware for loading onto and running the DAE devices.
Details and equations for each parameter are provided in the
Audio Canvas III User’s Manual.
INPUT SOURCE SELECTION
A source selection register defines input channel assignment of
audio presented to the DAE device’s audio input ports.
VOLUME
Volume control blocks provide level and trim adjustments within
the signal flow. Continuous adjustment through programmable
gain ranges supports attenuation to -100dB and gain to +24dB. A
single 24-bit register value provides gain setting and also
supports selectable audio phase inversion.
SHARED VOLUME
Shared Volume blocks implement multiple channels of level
attenuation. The number of channels is configurable and a single
24-bit register value equally controls all channel levels. Volume is
continuously adjustable from unity gain to -100dB.
MIXERS
Mixers provide individually-adjustable inputs that are summed
together and passed to their output. Each input mixing level is
controlled with its own 24-bit register that provides continuous
adjustment from unity gain to -100dB, along with full audio path
cut-off and optional input phase inversion supporting sum and
difference mixers. Audio block choices include 2-input, 4-input,
and configurable N-input mixers accommodating as many inputs
as desired.
ROUTER
Routers perform independent channel routing assignment,
connecting any input to any output. Number of channels is
configurable with up to 64 inputs and 12 outputs.
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STEREO A/B SWITCH
The A/B Switch provides stereo routing selection to switching
either of 2 pairs of stereo inputs to its output. It operates as a
double-pole, double-throw type of switch to the audio flow.
TONE CONTROL
Tone Controls are shelving filters providing independent of gain
and frequency adjustment for bass and treble tone settings.
Frequency and gain are continuously and independently
adjustable for both the bass and treble settings, supporting gain
ranges of -14 to +14 dB.
PARAMETRIC EQUALIZERS
Parametric Equalizer (EQ) blocks provide an adjustable bandpass
or band-reject frequency response. With frequency-domain
parameter settings of frequency, gain, and bandwidth or Q,
parameters are continuously and independently adjustable. EQs
are provided as individual audio blocks, and as blocks with
groups of 3-Band and 5-Band EQs.
BIQUAD FILTER (FREQUENCY DOMAIN
CONFIGURATION)
The Biquad block is a frequency-domain-parameter-entry biquad
filter implemented as a second-order biquad algorithm, providing
configurable high-pass, low-pass, and all-pass filtering functions.
First or second filter order may be selected, and parameter
setting entries of frequency and damping coefficient are
continuously adjustable. Bypass and polarity phase inversion is
also supported.
BIQUAD FILTER (Z-DOMAIN CONFIGURATION)
The z-Domain Biquad is a second order biquad digital algorithm
that operates from direct entry of z-transform coefficients. The
filter supports individual user entry coefficients enabling nearly
any second order filter synthesis per cascadable block.
FILTER - CROSSOVER
The Crossover Filter blocks provide high-pass or low-pass filtering
using frequency domain adjustment settings. Blocks are
implemented from 2 cascaded second-order biquad elements,
with selections that directly implement Linkwitz-Riley,
Butterworth, or Bessel filter presets. Slope setting is adjustable
from 6, 12, 18 or 24dB per octave, frequency and damping
coefficients are continuously adjustable, and bypass, active or
mute functions are supported.
FIR FILTER
The FIR filter is a configurable n-tap finite impulse response filter
implementation. The number of taps and their coefficient values
are defined in the audio signal flow simply through a
user-generated list of tap coefficients for the FIR structure.
EXCURSION CONTROL
Excursion Control is a specialized algorithm that dynamically
controls audio based on frequency and level. Excursion Control
boosts the low frequency response to compensate for
physically-limited low-frequency capabilities of small
loudspeakers and subwoofers at low listening levels. As listening
levels rise, it dynamically adjusts its boost enabling an optimum
sub-woofer listening experience at all loudness levels.
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DELAY
MONO MIXER
Delay Blocks introduce an adjustable delay of a channel's audio
data. Buffer size is fully user-configurable, supporting adjustment
over a range as small as milliseconds, to over 1 second.
A Mono Mixer is a threshold-gating mixer that routes the sum of
either or both of its 2 inputs into its output, based on a control
level input. This threshold-controlled mixing supports processing
of input audio that may be mono on both Left and Right, or
containing content on only one of Left or Right. This summed
audio then passes equally to stereo processing and output
system channels.
COMPRESSOR
Compressors provide threshold-dependent level adjustments,
implementing dynamic attenuation at configurable rates as the
control signal level increases. Headroom level is configurable,
supporting adjustable threshold ranges. Ratio, threshold, and
attack/release times are also fully adjustable. Compressors
incorporate a side chain input for algorithm control, supporting
compressing or limiting operation from inputs independent of
the processed channel audio signal flow.
COMPRESSOR/EXPANDER
The Expander Compressor implements dynamic low level signal
expansion, or an upward compression to audio levels. The
Expander Compressor implements dynamic low level signal
expansion for an upward compression to audio levels. Adjustable
settings include gate threshold and ratio, expansion threshold,
ratio, and expansion gain limit, and attack and release times.
ENVELOPE VOLTAGE CONTROLLED AMPLIFIER
The Envelope VCA processes its control input to establish an
amplitude envelope signal representing the audio path input
level. The Envelope VCA uses its side chain input to establish an
amplitude envelope of the audio level. Controls are similar to
that of the Compressor Block.
DITHER GENERATOR
The Dither Block generates a random noise (dither) pattern at a
shaped-spectrum low level. This noise is available to sum into the
audio path using a mixer, pushing up low-order bits of low-level
audio. This process enables improved uniform audio quality
when digital bit depth truncation is required because of
interfacing equipment. Audio signal flow data is normally
processed and output in digital format as 24 bits from the
channels assigned to the SAI digital outputs.
HARMONICS GENERATOR
The Harmonics Generator provides a harmonic spectrum content
from audio presented to its input. Harmonic order and amplitude
is programmable, supporting customized audio processing
features.
SoundSuite™ Processing
The Reverb Block is a 2-channel stereo reverb processor. It
provides adjustable reverb time and damping settings, and its
built-in mixer includes adjustments for both dry and wet audio
levels.
The D2Audio SoundSuite™ audio processing provides a full set of
enhancements to audio that greatly add to the quality and
listening experience of sound in wide scopes of consumer
devices. The SoundSuite algorithms use psycho-acoustic
processing that create a rich-sounding environment from small
speakers, and synthesizes the sound and quality equivalent to
more complex systems. It is especially suited to consumer
products that include televisions, docking stations, and mini hi-fi
stereo products. SoundSuite Processing includes:
CHIME GENERATOR
• D2Audio™ WideSound™
The Chime Generator contains 3 oscillators, each with adjustable
frequency and gain. When triggered, the oscillators initially
produce full programmed output levels that then decrease at
their programmable decay time rate.
• D2Audio™ WideSound™ x4
RMS LEVEL METER
D2Audio™ SoundSuite™ algorithms are completely supported
with all part numbers of the DAE-3 and DAE-3HT families.
REVERB
RMS Meters provide real-time indication of the signal levels
through the audio processing path. Visible in the Audio Canvas III
signal flow, they provide continuous level indication. Measured
data in the meter's registers may also be read by system
controllers for monitoring levels in a final production system.
FADE-PAN
The Fade-Pan control provides level adjustment of 4 input
channels to 4 output channels. Implementation includes a
Rear/Front fade adjustment, and a Left/Right balance
adjustment. Controls are continuously adjustable, providing unity
gain at mid-point settings, and attenuating output levels of its
channels as the respective control is adjusted away from that
channel's direction.
• D2Audio™ DeepBass™
• D2Audio™ Mono2Stereo™
Third Party Virtualization and Enhancements
Enhancement processing and virtualization algorithms from
third-party technology providers are available to add to Audio
Canvas III. As permitted through license agreements from the
providers, these algorithms are supplied to the designer where
they integrate into the Audio Canvas III software, and appear as
additional audio block choices.
Depending on device part number and design-specific firmware
definitions, the DAE-3 device supports a variety of processing,
decoding, virtualization, and pre/post processing feature sets.
Features and processing support is shown in Table 1 on page 3.
Audio Processing Block Controls
Each audio processing block is assigned its own registers
providing adjustment controls for the parameters associated
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30
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D2-926xx
with its audio function. Some blocks use one register only, while
other blocks with multiple control settings may use multiple
registers for each control. The parameter equations for all of the
audio blocks are provided in the Audio Canvas III User’s Manual.
Dynamic Register Addressing Architecture
AUDIO I/O CONFIGURATION
This configuration allow choice selection of which audio
processing channels are assigned to the S/PDIF and I2S digital
outputs. It also supports choice of input port assignments to the
audio input channels.
Audio Canvas III supports building of any signal flow with no
restriction of the order of occurrence of any audio block, or any
limit to repeated deleting or addition during signal flow editing.
As audio algorithm blocks are edited, added, or removed, the
user-space memory addresses for each register will change.
However, each instance of each block has its own unique label
identifier where that identifier is clearly known and visible on the
signal flow workspace.
FAULT INDICATION
Because each and every algorithm is assigned its own dedicated
register for its parameter settings, the Audio Canvas III generates
a variable-to-address mapping for each build of each project. This
mapping is provided as a text file in a header file format that can
be directly included within a system controller’s software build.
As multiple iterations of a signal flow are created during the
design process, a new header file is created matching each
revision. Simply including the header file within the system
controller compile automatically passes these new register
addresses without need for repeated system code editing.
Third party decoding of compressed formats is supported based
on the particular device part number. By default, when a device is
used that supports the licensed technology, its supported
decoding is enabled. Choices allow building of firmware to
selectively include or exclude the available decoding algorithms.
Hardware Feature Functions
In addition to the core firmware that runs the DAE devices to
operate the amplifier, several feature-specific options are
supported for use in the amplifier system. These optional
features are configurable and may be chosen or bypassed.
Configuration is set using the Audio Canvas III software, where
based on chosen settings, the firmware will include each function
along with the hardware I/O assigned to its function.
The DAE-3 supports pins assignable to various hardware
features, while the DAE-3HT shares choices between functions
with some of its available pins providing feature choices in a
lower pin-count package.
These hardware feature algorithms include:
AM AVOIDANCE MODE
AM Avoidance Mode allows selecting the PWM switching
frequency to move its harmonics away from the frequency of an
AM radio station, reducing possible station interference. The
algorithm is optional and selection is controlled through a
register setting that is created with the system firmware.
MCLK CLOCK OUTPUT
The MCLK output provides the I2S clock to external digital audio
circuits or devices. The MCLK output is optional, and when
enables is selectable between 2 frequencies.
PSSYNC CLOCK OUTPUT
The PSSYNC signal is used for synchronizing switching power
converters used in the amplifier. Providing a synchronizing
frequency that is a multiple or sub-multiple of the PWM switching
rate eliminates possibility of in-band audio frequency generation
from close but asynchronous clocks. The output is optional, and
when enabled supports 6 frequency multiple choices.
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31
An optional output may be assigned to provide a control signal to
a system controller or other hardware within the amplifier upon
detection of protection or fault conditions. The feature may be
enabled or disabled, and when enabled, allows choosing an
available I/O pin for providing this output.
DECODER SELECTION
FORMAT CHANGE NOTIFICATION
The Format Change Notification feature allow assigning an I/O
pin to provide hardware indication when a change of decoded
format types is detected. This supports dynamic audio path
allocation by the system controller when audio content changes
to or from PCM and an encoded format. The feature is disabled
by default, but when enabled, allows assignment of the I/O pin to
signal this state. An additional setting allows choosing an audio
muting time delay between format changes.
IDLE POWER MANAGEMENT
The Idle Power Management feature allows controlled audio
PWM output shutdown after a time period has elapsed with no
audio detected above a threshold level. The feature is disabled by
default and when enabled allows choice of threshold time and
signal level, and assignment of an I/O pin that can be used to
signal other operations in the amplifier.
MASTER VOLUME ENCODER
The Master Volume Encoder feature allows assigning of I/O pins
to a quadrature-type encoder that can be used as a mechanical
volume control. The feature is disabled by default, but when
enabled allows choice of volume control algorithm association in
the audio signal flow, and choice of the I/O pins.
PWM OUTPUT CONFIGURATION
The PWM Output Configuration functions support assignment of
PWM output pins to each of the 12 PWM engines. It allows pin
polarity selection, and choice of enabling or disabling each PWM
engine.
PWM OUTPUT TIMING
The PWM Output Timing controls enable per-channel adjustment
of each PWM output timing. Controls included dead time,
minimum pulse width, and stagger settings between channels.
POWER DOWN OUTPUT
The Power Down Output feature supports setting an output pin
that can connect to power stages, for manually shutting down
power stages during fault detection and system startup. When
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enabled, the algorithm supports specification entry of the I/O pin
to be used for the function.
TEMPERATURE SENSING
A thermal protection algorithm supports use of NTC resistors
placed in heat-sensitive areas of the amplifier. The algorithms
run and provide real-time temperature measurement.
Temperature values are available in firmware registers for
reading by a system controller, and set-points in the algorithm
can be used to trigger a controlled-attenuation level reduction or
fault shutdown.
THERMAL MANAGEMENT
An additional thermal protection algorithm supports a high
temperature warning input to trigger controlled-attenuation level
reduction. Rate of change and delay are programmable when the
feature is enabled.
DAE-3 And DAE-3HT Differences
The DAE-3 device family includes both the DAE-3 and DAE-3HT.
Functional specifications are identical to both designations of
this family. However, the DAE-3HT, provided in its smaller 72-pin
package supports system and assignable functions that are
mapped to the pins supported in that package. Complete pin
functions of all pins of both devices of the DAE-3 family are listed
in the Pin Description Tables.
Pin Function Mapping Between Devices
Table 3 lists the pin numbers, names and functions for both the
DAE-3 and DAE-3HT devices, and provides a mapping of the pin
functions between those devices.
TABLE 3. DAE-3 AND DAE-3HT PIN AND I/O COMPARISON TABLE
PIN NUMBERS
PIN NAMES
DESCRIPTION AND FUNCTION
DAE-3
DAE-3HT
DAE-3
DAE-3HT
1
1
SC20
SCLK3
(SC20)
I2S Input Port 1 SCLK
DAE-3
I2S Port 3 Input Channels 5-6 SCLK
DAE-3HT
2
2
SRD2
SDIN3
(SRD2)
I2S Data Port 1, Input Channels 1-2
I2S Port 3 Input Channels 5-6 Audio Input Data
3
3
SC21
LRCK3
(SC21)
I2S Input Port 1 LRCK
I2S Port 3 Input Channels 5-6 LRCK
4
4
SCK2
SCLK4
(SCK2)
I2S Input Port 2 SCLK
I2S Port 4 Input Channels 7-8, or Output Channels 12 SCLK
5
5
STD2
SDIO4
(STD2)
I2S Data Port 2, Input Channels 3-4
I2S Port 4 Input Channels 7-8, or Output Channels 12 Audio Data
6
6
SC22
LRCK4
(SC22)
I2S Input Port 2 LRCK
I2S Port 4 Input Channels 7-8, or Output Channels 12 LRCK
8
7
SCK3
SCLK12
(SCK3)
I2S Input Port 3 SCLK
I2S Ports 1 and 2 Input Channels 1-4 SCLK
9
8
STD3
SDIN2
(STD3)
I2S Data Port 4, Input Channels 7-8
I2S Port 2 Input Channels 3-4 Audio Data
10
9
SC32
LRCK12
(SC32)
I2S Input Port 4 LRCK
I2S Ports 1 and 2 Input Channels 1-4 LRCK
13
10
SRD3
SDIN1
(SRD3)
I2S Data Port 3, Input Channels 5-6
I2S Port 1 Input Channels 1-2 Audio Data
36
19
SDA1
SDA1
2-Wire (I2C) Data Port (Controller Port)
2-Wire (I2C) Data Port (Controller Port)
2-Wire (I2C) Clock Port (Controller Port)
2-Wire (I2C) Clock Port (Controller Port)
I2S Output Port SCLK
Assignable GPIO or MCLK Output
37
20
SCL1
SCL1
119
65
SCK1
SCK1
/MCLK
123
68
TIO0
127
71
SDA0
SDA0
2-Wire (I2C) Data Port
/TEMPREF
Assignable I/O, NTC Temp Sense Reference
128
72
SCL0
SCL0
2-Wire (I2C) Clock Port
/TEMPNTC
Assignable I/O, NTC Temp Sense NTC
27
16
TIO1
125
70
PROTECT0 PROTECT0 PWM Channel 0 Protect Input
PWM Channel 0 Protect Input
124
69
PROTECT1 PROTECT1 PWM Channel 1 Protect Input
PWM Channel 1 Protect Input
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TIO0
Timer I/O Port 0.
/PSSYNC
TIO1
/NTC
32
Timer I/O Port 1, NTC Temp Sense Common
Timer I/O Port 0, or Assignable Power Supply Sync
Output
Assignable I/O, NTC Temp Sense Common
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TABLE 3. DAE-3 AND DAE-3HT PIN AND I/O COMPARISON TABLE (Continued)
PIN NUMBERS
PIN NAMES
DAE-3
DESCRIPTION AND FUNCTION
DAE-3
DAE-3HT
65
37
PROTECT2 PROTECT2 PWM Channel 2 Protect Input
DAE-3HT
DAE-3
DAE-3HT
60
32
PROTECT3 PROTECT3 PWM Channel 3 Protect Input
PWM Channel 3 Protect Input
61
33
PROTECT4 PROTECT4 PWM Channel 4 Protect Input
PWM Channel 4 Protect Input
PWM Channel 2 Protect Input
62
34
PROTECT5 PROTECT5 PWM Channel 5 Protect Input
PWM Channel 5 Protect Input
63
35
PROTECT6 PROTECT6 PWM Channel 6 Protect Input
/nMUTE
Assignable PWM Protect Input, or Mute Output
64
36
PROTECT7 PROTECT7 PWM Channel 7 Protect Input
/nOVRT
Assignable PWM Protect Input, or Over-Temperature
Monitor Input
95
54
PWM0
PWM0
PWM output pin. (One of 18 PWM output pins.
Channel and operation assignment is defined by
firmware.)
PWM output pin. (One of 12 PWM output pins.
Channel and operation assignment is defined by
firmware.)
I/O Pin Function Assignment Comparison
Pin I/O functions and their assignments are supported through
user selections of the Audio Canvas III software that builds the
DAE-3 or DAE-3HT firmware. The designer has the option of
choosing the offered features and allocating I/O pins to those
features based on individual system design needs.
The differences of pin functions are shown in the preceding table,
but the following provides additional detail to certain of these
pins and functions as to their available features and assignment.
PWM OUTPUT PINS
• The DAE-3 has 18 PWM pins that are assignable to any of the
DAE-3’s 12 PWM channels.
• The DAE-3HT has 12 PWM pins that are assignable to any of
the DAE-3’s 12 PWM channels.
I2S DIGITAL INPUTS AND OUTPUTS
• The DAE-3 supports 8 audio INPUT channels through 4 I2S
serial digital audio input ports. Port assignments are
established with the firmware built with the Audio Canvas III
software for the DAE-3 devices.
• The DAE-3 supports 8 audio OUTPUT channels through 4 I2S
serial digital audio output ports. Port and channel assignments
are established through user selection with the firmware built
with the Audio Canvas III software for the DAE-3 devices.
MCLK
• The DAE-3 utilizes a dedicated pin for the MCLK output. That
pin is available only for MCLK. User selection determines if
MCLK is present on this pin or if its output is off.
• The DAE-3HT provides a user selection to choose whether to
enable the MCLK output. This pin (the SCK1/MCLK pin)
becomes assigned to MCLK when MCLK is enabled. When
MCLK is disabled, the SDK1/MCLK pin becomes available for
assignment to other hardware I/O functions.
PROTECTION INPUT PINS
• The DAE-3 provides 9 protect input pins, where the first 8 are
allocated to the first 8 PWM engines. The last of the 9 is a
dedicated input for monitoring an over-temperature warning
control signal from power stages or other monitoring switches.
• The DAE-3HT provides 8 protect input pins. These pins are all
assignable to be used as the protect input for their default
PWM engine, or when not used for that protection become
available for use with other pin-assignable hardware I/O
functions. All selection is established through the user
interface of the Audio Canvas III design tool program.
• The DAE-3HT supports a user choice of either:
- 8 audio INPUT channels through 4 I2S serial digital audio
input ports, and no I2S OUTPUTS, or
- 6 INPUT channels through 3 I2S ports with 1 I2S OUTPUT
supporting 2 audio channels.
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
May 17, 2016
FN6787.3
Updated entire datasheet applying Intersil’s new standards.
Updated the Ordering Information table on page 2.
Added Note 2.
Replaced Products verbiage with About Intersil verbiage.
Added Dolby and DTS disclaimers.
July 3, 2012
FN6787.2
Complete datasheet rewrite to add DAE-3HT devices to the DAE-3 family.
- Revisions and additions to accommodate additions for DAE-3HT to DAE-3/DAE-3HT family.
- Complete rewrite of page 1 description and features, and complete rewrite of all functional description content.
(Rewrites do not change function of DAE-3 devices, but provide more accurate explanation of device use.)
- No changes to DAE-3 specifications other than: Addition and revision of ADC specifications and updates of
supporting detail for ADC. All other DAE-3 specifications unless noted by DAE-3HT specific designations are
identical to those of DAE-3.
- Updates to DAE-3 high-level and detail block diagrams, and addition of diagrams for DAE-3HT.
- Removal of ADC and DSD plots.
- Removal of all HDA interface, HDMI interface, DSD, and SCI references and descriptions.
- Removal of D2-92613-LR and D2-92625-LR part numbers which are being discontinued. (Their features are
fully supported in the D2-92633-LR part number and the removed part numbers are not needed.)
POD Q128.14x14 updated to latest revision - Changed title from “Thin Plastic Quad Flatpack Package (LQFP)”
to “Low Plastic Quad Flatpack Package (LQFP)”
POD L72.10x10F updated to latest revision - Changed bottom view to reflect correct pin 1 corner and pin
numbering. Also cleaned up details Y and Z
May 3, 2011
FN6787.1
Rewrite of datasheet. Fixes to incorrect (pin 109) connection description, removal of unnecessary descriptive
content and structure.
-Updated datasheet to latest corporate document format and applied standards as follows:
Ordering information added audio processing column, added device support note, numbered notes, lead finish
matching intrepid.
Added Tjc to Thermal Information and corresponding note on page 5
Added Compliance note on page 6 referencing MIN and MAX columns of Electrical Spec Tables
-Updated Block Diagram on page 1 - complete re-draw.
-Removed D2-92643 part number from DAE-3 Device Feature Set Offering Table 1 on page 2 (this is not an
available ordering part number)
-Corrected pin 109 (nTRST) description error on page 14 to indicate that it must be pulled high at all times.
(internally-requested error correction). Changed from: "Hardware test mode control. For D2Audio use only. Must
be tied high or low." To: "Factory test only. Must be tied high at all times."
-Removed outdated high level system diagrams,
-Removed all (outdated and non-applicable) reference design examples,
-Removed unnecessary HDA connection diagrams
-Removed trademarks section/paragraph. Explicit listing not required/sufficiently covered through other
means.
April 1, 2010
FN6787.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
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Disclaimer for Dolby Technology License Required Notice:
Intersil may distribute Dolby™ technology separately from its D2Audio™ integrated circuits. Dolby™ technology would be embedded in
firmware to be loaded onto and executed by Dolby™ enabled D2Audio™ integrated circuits. Supply of this implementation of Dolby
technology does not convey a license nor imply a right under any patent or any other industrial or intellectual property right of Dolby
Laboratories to use this implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for
such use is required from Dolby Laboratories. In some cases the Dolby™ technology may include at least one Dolby™ Pro Logic™
decoder. The party receiving this implementation must be licensed for at least one of the three Dolby Laboratories Licensing
Corporation (“Dolby”) technologies contained in this implementation. If the party receiving this implementation is not a Licensee for all
three of the Dolby technologies contained in this implementation then the party may only use the unlicensed technology(ies) contained
on the implementation for internal testing and evaluation purposes.”
Disclaimer for DTS®(SRS) Technology License Required Notice:
NOTICE OF LICENSE REQUIREMENT: Supply of this implementation of DTS technology to DTS Product Licensees directly or through a
distributor does not incur a royalty payment or convey a license, exhaust DTS’ rights in the implementation, or imply a right under any
patent or any other industrial or intellectual property right of DTS to use, offer for sale, sell, or import such implementation in any
finished end-user or ready-to-use final product. A license from and royalty payment to DTS is required prior to and for such use.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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Package Outline Drawing
L72.10x10F
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 4/12
10.00
6
PIN 1
INDEX AREA
A
6
PIN 1
INDEX AREA
4X 8.50
B
55
72
1
54
68X 0.50
EXP. DAP
7.70 SQ.
10.00
(4X)
37
0.15
18
36
TOP VIEW
19
72X 0.25
BOTTOM VIEW
SEE DETAIL "Z"
4
0.10 M C A B
SEE DETAIL "X"
0.90 MAX
0.10 C
C
0.08 C
SEATING PLANE
68X 0.50
(0.75)
72X 0.25
9.80 SQ
C
0 . 2 REF
5
37
7.70 SQ
(0.40)
0 . 00 MIN.
0 . 05 MAX.
DETAIL “Y”
36
(0.271)
72X 0.60
DETAIL "Z"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
Package outline compliant to JESD-MO220.
either a mold or mark feature.
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Low Plastic Quad Flatpack Packages (LQFP)
Q128.14x14
4X
128 LEAD LOW PLASTIC QUAD FLATPACK PACKAGE 0.4 MM PITCH
0.2 Y T-U Z
MILLIMETERS
D
PIN 1
97
Z
128
1
96
U
T
E
E1
SYMBOL
MIN
A
-
A1
0.05
A2
1.35
1.40
b
0.13
b1
0.13
33
64
D1
0.2 H T-U Z
4X
DETAIL F
H
NOTES
-
0.15
-
1.45
-
0.16
0.23
4
-
0.19
-
c
0.09
-
0.20
-
0.09
-
0.16
-
D
16 BSC
-
D1
14 BSC
3
E
16 BSC
-
E1
14 BSC
3
0.45
L1
65
MAX
1.60
c1
L
32
NOM
0.60
0.75
1.00 REF
-
R1
0.08
-
-
-
R2
0.08
-
0.20
-
S
0.20
-
-
-
0
0°
3.5°
7°
-
01
0°
-
-
-
02
11°
12°
13°
-
03
11°
12°
13°
-
N
128
e
0.40 BSC
Rev. 1 7/11
NOTES:
128X b
Y
124X
e
SEATING PLANE
0.07 M Y T-U
b1
c1
c
0.05
PLATING
02
b
01
A
R1
A2
R2
A1
0.080 Y
03
S
1. Dimensions are in millimeters. Dimensions in ( ) for
Reference Only.
2. Dimensions and tolerances per AMSEY14.5M-1994.
3. Dimensions D1 and E1 are excluding mold protrusion.
Allowable protrusion is 0.25 per side. Dimensions D1
and E1 are exclusive of mold mismatch and determined by datum plane H.
4. Dimension b does not include dambar protrusion.
Allowable dambar protrusion shall not cause the lead
width to exceed the maximum b dimension by more
than 0.08mm. Dambar cannot be located at the lower
radius or the foot. Minimum space between protrusion
and an adjacent lead is 0.07 mm.
0
L
(L1)
0.25 GAUGE
PLANE
DETAIL F
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