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TAS5411-Q1
SLOS921A – DECEMBER 2015 – REVISED DECEMBER 2015
TAS5411-Q1 8-W Mono Automotive Class-D Audio Amplifier With Load Dump and I2C
Diagnostics
1 Features
2 Applications
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Mono BTL Class-D Power Amplifier
8-W Output Power at 10% THD+N Into 4 Ω
4.5-V to 18-V Operating Range
83% Efficiency Into 4 Ω
Differential Analog Input
Speaker Guard™ Speaker Protection With
Adjustable Power Limiter
75-dB Power-Supply Rejection Ratio (PSRR)
Load Diagnostic Functions:
– Open and Shorted Output Load
– Output-to-Power and -Ground Shorts
Protection and Monitoring Functions:
– Short-Circuit Protection
– 40-V Load-Dump Protection per ISO-7637-2
– Output DC Level Detection While Music Is
Playing
– Overtemperature Protection
– Over- and Undervoltage Protection
Thermally Enhanced 16-Pin HTSSOP (PWP)
Package With PowerPAD™ Package (Pad Down)
Designed for Automotive EMC Requirements
Qualified According to AEC-Q100 Grade 2
ISO9000: 2002 TS16949 Certified
–40°C to 125°C Ambient Temperature Range
Automotive Emergency Call (eCall) Amplifier
Telematics Systems
Instrument Cluster Systems
3 Description
The TAS5411-Q1 is a mono class-D audio amplifier,
ideal for use in automotive emergency call (eCall),
telematics, and instrument cluster applications. The
device provides up to 8 W into 4 Ω at less than 10%
THD+N from a 14.4-Vdc automotive battery. The
wide operating voltage range and excellent efficiency
make the device ideal for start-stop support or
running from a backup battery when required. The
integrated load-dump protection reduces external
voltage clamp cost and size, and the onboard load
diagnostics report the status of the speaker through
I2C.
Device Information(1)
PART NUMBER
PACKAGE
TAS5411-Q1
HTSSOP (16)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Efficiency
Simplified Block Diagram
IN_P
IN_N
100%
I2C
90%
80%
OUTP
TAS5411-Q1
70%
LC
OUTN
Efficiency
System
µP
BODY SIZE (NOM)
5.00 mm × 4.40 mm
60%
50%
40%
30%
20%
Device Efficiency
System Efficiency
10%
0
0
1
2
3
4
5
Output Power (W)
6
7
8
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5411-Q1
SLOS921A – DECEMBER 2015 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
5
5
6
8
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Timing Requirements for I2C Interface Signals.........
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 11
9.3 Feature Description................................................. 11
9.4 Device Functional Modes........................................ 17
9.5 Register Maps ......................................................... 18
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ............................................... 20
11 Power Supply Recommendations ..................... 23
12 Layout................................................................... 24
12.1 Layout Guidelines ................................................. 24
12.2 Layout Examples................................................... 24
13 Device and Documentation Support ................. 26
13.1
13.2
13.3
13.4
13.5
13.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
27
27
27
27
14 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2015) to Revision A
•
2
Page
Changed the device status from Product Preview to Production Data .................................................................................. 1
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5 Device Comparison Table
PART NUMBER
OUTPUT POWER
OVERCURRENT SHUTDOWN
TAS5411-Q1
8W
2.4 A
TAS5421-Q1
22 W
3.5 A
6 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP PowerPAD Package
Top View
GND
1
16
GND
STANDBY
2
15
PVDD
BYP
3
14
FAULT
SDA
4
13
BSTP
SCL
5
12
OUTP
IN_P
6
11
OUTN
IN_N
7
10
BSTN
MUTE
8
9
GND
Thermal
Pad
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
BSTN
10
AI
Bootstrap for negative-output high-side FET
BSTP
13
AI
Bootstrap for positive-output high-side FET
BYP
3
PBY
Voltage-regulator bypass-capacitor pin
FAULT
14
DO
Active-low open-drain output used to report faults
1
GND
9
GND
Ground
16
IN_N
7
AI
Inverting analog input
IN_P
6
AI
Non-inverting analog input
MUTE
8
DI
Mute input, active-high (no internal pullup or pulldown)
OUTN
11
PO
Output (–)
OUTP
12
PO
Output (+)
PVDD
15
PWR
SCL
5
DI
I2C clock
SDA
4
DI/DO
I2C data
STANDBY
2
DI
Active-low STANDBY pin (no internal pullup or pulldown)
—
Must be soldered to ground
Thermal pad
(1)
Power supply
DI = digital input, DO = digital output, AI = analog input, PWR = power supply, PBY = power bypass, PO = power output, GND = ground
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7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)
Input voltage
(1)
DC supply voltage range, V(PVDD)
Relative to GND
Pulsed supply voltage range, V(PVDD_MAX)
t ≤ 400 ms exposure
MIN
MAX
–0.3
30
–1
40
Supply voltage ramp rate, ΔV(PVDD_RAMP)
15
For SCL, SDA, STANDBY pins
Relative to GND
–0.3
5
For IN_N, IN_P, and MUTE pins
Relative to GND
–0.3
6.5
DC current on PVDD, GND and OUTx pins, I(PVDD), IO
Current
Maximum current, on all input pins, I(IN_MAX)
±4
(2)
±1
Maximum sink current for open-drain pin, I(IN_ODMAX)
7
UNIT
V
V/ms
V
A
mA
Junction temperature, TJ
-40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See the Table 11 section for information on analog input voltage and ac coupling.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
4
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±3500
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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7.3 Recommended Operating Conditions
V(PVDD_OP)
Supply voltage range relative to GND.
Includes ac transients, requires proper
decoupling. (1)
4-Ω ±20% load (or higher)
V(PVDD_RIPPLE)
Maximum ripple on PVDD
V(PVDD) < 8 V
V(AIN) (2)
Analog audio input-signal level
AC-coupled input voltage
V(IH_STANDBY)
STANDBY pin input voltage for logic-level
high
V(IL_STANDBY)
STANDBY pin input voltage for logic-level low
MIN
NOM
MAX
4.5
14.4
18
0
UNIT
V
1
Vpp
0.25–1 (3)
Vrms
2
V
0.7
V
2.1
5.5
V
V(IH_SCL)
SCL pin input voltage for logic-level high
R(PU_I2C) = 4.7-kΩ pullup, supply voltage =
3.3 V or 5 V
V(IH_SDA)
SDA pin input voltage for logic-level high
R(PU_I2C) = 4.7-kΩ pullup, supply voltage =
3.3 V or 5 V
2.1
5.5
V
V(IL_SCL)
SCL pin input voltage for logic-level low
R(PU_I2C) = 4.7-kΩ pullup, supply voltage =
3.3 V or 5 V
–0.5
1.1
V
V(IL_SDA)
SDA pin input voltage for logic-level low
R(PU_I2C) = 4.7-kΩ pullup, supply voltage =
3.3 V or 5 V
–0.5
1.1
V
R(L)
Nominal speaker load impedance
When using low-impedance loads, do not
exceed overcurrent limit.
2
4
16
Ω
V(PU)
Pullup voltage supply (for open-drain logic
outputs)
3
3.3
3.6
V
R(PU_EXT)
External pullup resistor on open-drain logic
outputs
50
kΩ
R(PU_I2C)
I2C pullup resistance on SDA and SCL pins
10
kΩ
C(PVDD)
External capacitor on the PVDD pin, typical
value ± 20% (1)
C(BYP)
External capacitor on the BYP pin, typical
value ± 10%
C(OUT)
External capacitance to GND on OUT_X pins
C(IN)
External capacitance to analog input pin in
series with input signal
1
μF
C(BSTN), C(BSTP)
External boostrap capacitor, typical value ±
20%
220
nF
TA
Operating ambient temperature
(1)
(2)
(3)
Resistor connected between open-drain logic
output and V(PU) supply.
10
1
4.7
10
μF
1
μF
μF
4
–40
125
°C
See the Power Supply Recommendations section.
Signal input for full unclipped output with gains of 36 dB, 32 dB, 26 dB, and 20 dB
Maximum recommended input voltage is determined by the gain setting.
7.4 Thermal Information
TAS5411-Q1
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
39.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
24.9
°C/W
RθJB
Junction-to-board thermal resistance
20
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
19.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W/ch, AES17 filter, default I2C settings (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CURRENT
PVDD idle current
In PLAY mode, no audio present
PVDD standby current
STANDBY mode, MUTE = 0 V
16
5
4 Ω, THD+N ≤ 1%, 1 kHz, TC = 75°C
6
4 Ω, THD+N = 10%, 1 kHz, TC = 75°C
8
mA
20
μA
OUTPUT POWER
Output power per channel
Power efficiency
4 Ω, P(O) = 8 W (10% THD)
W
83%
AUDIO PERFORMANCE
Noise voltage at output
G = 20 dB, zero input, and A-weighting
65
μV
Common-mode rejection ratio
f = 1 kHz, 100 mVrms referenced to GND, G = 20 dB
63
dB
Power-supply rejection ratio
PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz
75
dB
Total harmonic distortion + noise
P(O) = 1 W, f = 1 kHz
Switching frequency
Switching frequency selectable for AM interference
avoidance
Internal common-mode input bias voltage
Internal bias applied to IN_N, IN_P pins
Voltage gain (VO / VIN)
Source impedance = 0 Ω, P(O) = 1 W
0.05%
400
kHz
500
3
V
19
20
21
25
26
27
31
32
33
35
36
37
dB
PWM OUTPUT STAGE
FET drain-to-source resistance
TJ = 25°C
Output offset voltage
Zero input signal, G = 20 dB
180
mΩ
±25
mV
22.5
V
PVDD OVERVOLTAGE (OV) PROTECTION
PVDD overvoltage-shutdown set
19.5
PVDD overvoltage-shutdown hysteresis
21
0.6
V
PVDD UNDERVOLTAGE (UV) PROTECTION
PVDD undervoltage-shutdown set
3.6
PVDD undervoltage-shutdown hysteresis
4
4.4
0.25
V
V
BYP
BYP pin voltage
6.4
6.9
7.4
V
4.1
V
POWER-ON RESET (POR)
PVDD voltage for POR
PVDD recovery hysteresis voltage for POR
6
0.3
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Electrical Characteristics (continued)
TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W/ch, AES17 filter, default I2C settings (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
155
170
°C
15
°C
2.4
A
OVERTEMPERATURE (OT) PROTECTION
Junction temperature for overtemperature shutdown
Junction temperature overtemperature shutdown
hystersis
OVERCURRENT (OC) SHUTDOWN PROTECTION
Maximum current (peak output current)
STANDBY PIN
STANDBY pin current
0.1
0.2
μA
700
ms
DC DETECT
DC detect threshold
2.9
DC detect step response time
V
FAULT REPORT
FAULT pin output voltage for logic-level high (open-drain
logic output)
External 47-kΩ pullup resistor to 3.3 V
FAULT pin output voltage for logic-level low (open-drain
logic output)
External 47-kΩ pullup resistor to 3.3 V
2.4
V
0.5
V
200
Ω
LOAD DIAGNOSTICS
Resistance to detect a short from OUT pin(s) to PVDD or
ground
Open-circuit detection threshold
Including speaker wires
70
95
120
Ω
Short-circuit detection threshold
Including speaker wires
0.9
1.2
1.5
Ω
SDA pin output voltage for logic-level high
R(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V
2.4
SDA pin output voltage for logic-level low
3-mA sink current
I2C
Capacitance for SCL and SDA pins
V
0.4
V
10
pF
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7.6 Timing Requirements for I2C Interface Signals
over recommended operating conditions (unless otherwise noted)
MIN
NOM
MAX
UNIT
f(SCL)
SCL clock frequency
400
kHz
tr
Rise time for both SDA and SCL signals
300
ns
tf
Fall time for both SDA and SCL signals
300
tw(H)
SCL pulse duration, high
0.6
μs
tw(L)
SCL pulse duration, low
1.3
μs
tsu(2)
Setup time for START condition
0.6
μs
th(2)
START condition hold time before generation of first clock pulse
0.6
μs
tsu(1)
Data setup time
100
ns
th(1)
Data hold time
0 (1)
ns
tsu(3)
Setup time for STOP condition
0.6
μs
C(B)
Load capacitance for each bus line
(1)
400
ns
pF
A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
tw(H)
tw(L)
tr
tf
SCL
tsu(1)
th(1)
SDA
T0027-03
Figure 1. SCL and SDA Timing
SCL
t(buf)
th(2)
tsu(2)
tsu(3)
SDA
Start
Condition
Stop
Condition
T0028-02
Figure 2. Timing for Start and Stop Conditions
8
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7.7 Typical Characteristics
PVDD = 14.4 V, TA = 25ºC, P(O) = 1 W, 1-kHz input, default I2C settings (unless otherwise noted)
10%
100%
90%
80%
1%
60%
THD+N
Efficiency
70%
50%
40%
0.1%
30%
20%
Device Efficiency
System Efficiency
10%
0.01%
0.1
0
0
1
2
f(SW) = 400 kHz
3
4
5
Output Power (W)
6
7
8
1
Output Power (W)
D001
TA = 25ºC
D002
V(PVDD) = 14.4 V
Figure 3. Efficiency vs Output Power
Figure 4. THD+N vs Output Power
10%
1.6
5-W Data
1-W Data
1.4
1%
1.2
1
THD+N
Power Dissipation (W)
10
0.8
0.1%
0.6
0.01%
0.4
0.2
0
0
1
2
3
4
5
Output Power (W)
6
7
8
0.001%
10
100
D003
0
-20
-20
-40
-40
-60
-60
-80
-100
D004
-80
-100
-120
-120
-140
-140
-160
-160
-180
10k
Figure 6. THD+N vs Frequency
0
Noise (dBV)
Noise (dBV)
Figure 5. Power Dissipation vs Output Power
1k
Frequency (Hz)
-180
0
2k
4k
6k
8k 10k 12k 14k 16k 18k 20k 22k 24k
Frequency (Hz)
D005
0
2k
Figure 7. Noise FFT With –60-dB Output
4k
6k
8k 10k 12k 14k 16k 18k 20k 22k 24k
Frequency (Hz)
D006
Figure 8. Noise FFT With 1-W Output
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Typical Characteristics (continued)
PVDD = 14.4 V, TA = 25ºC, P(O) = 1 W, 1-kHz input, default I2C settings (unless otherwise noted)
3
Overcurrent Threshold (A)
2.5
2
1.5
1
0.5
0
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
D007
Figure 9. Overcurrent Threshold Versus Temperature
8 Parameter Measurement Information
The parameters for the TAS5411-Q1 device were measured using the circuit in Figure 17.
10
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9 Detailed Description
9.1 Overview
The TAS5411-Q1 device is a mono analog-input audio amplifier for use in the automotive environment. The
design uses an ultra-efficient class-D technology developed by Texas Instruments, but with features added for
the automotive industry. This technology allows for reduced power consumption, reduced heat, and reduced
peak currents in the electrical system. The device realizes an audio sound system design with smaller size and
lower weight than traditional class-AB solutions.
There are seven core design blocks:
• PWM
• Gate drive
• Power FETs
• Diagnostics
• Protection
• Power supply
• I2C serial communication bus
9.2 Functional Block Diagram
Overcurrent Detection
Protection
Control
SDA
2
I C
SCL
DC Detection
Thermal Protection
Biases
and
References
Voltage Protection
GVDD
LDO
Regulator
BYP
GVDD
Short-to-Ground
PVDD
Control
Diagnostics
Control
FAULT
PVDD
BSTN
Short-to-Power
Shorted Load
Open Load
MUTE
STANDBY
IN_N
Gain
Control
Speaker
Guard
Preamplifier
IN_P
Pulse
Width
Modulator
(PWM)
Gate
Drive
OUTN
GVDD
GND
BSTP
PVDD
GND
Gate
Drive
OUTP
GND
9.3 Feature Description
9.3.1 Analog Audio Input and Preamplifier
The differential input stage of the amplifier cancels common-mode noise that appears on the inputs. For a
differential audio source, connect the positive lead to IN_P and the negative lead to IN_N. The inputs must be
ac-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages. For good
transient performance, the impedance seen at each of the two differential inputs should be the same.
The gain setting impacts the analog input impedance of the amplifier. See Table 1 for typical values.
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Table 1. Input Impedance and Gain
GAIN
INPUT IMPEDANCE
20 dB
60 kΩ ± 20%
26 dB
30 kΩ ± 20%
32 dB
15 kΩ ± 20%
36 dB
9 kΩ ± 20%
9.3.2 Pulse-Width Modulator (PWM)
The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is
the critical stage that defines the class-D architecture. In the TAS5411-Q1 device, the modulator is an advanced
design with high bandwidth, low noise, low distortion, and excellent stability.
The pulse-width modulation scheme allows increased efficiency at low power. Each output is switching from 0 V
to PVDD. The OUTP and OUTN pins are in phase with each other with no input, so that there is little or no
current in the speaker. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive
output voltages. The duty cycle of OUTN is greater than 50% and that of OUTP is less than 50% for negative
output voltages. The voltage across the load is at 0 V through most of the switching period, reducing power loss.
OUTP
OUTN
No Output
0V
OUTP – OUTN
Speaker
Current
0A
OUTP
OUTN
Positive Output
OUTP – OUTN
PVDD
0V
Speaker
Current
0A
OUTP
OUTN
Negative Output
OUTP – OUTN
0V
–PVDD
0A
Speaker
Current
Figure 10. BD Mode Modulation
12
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9.3.3 Gate Drive
The gate driver accepts the low-voltage PWM signal and level-shifts it to drive a high-current, full-bridge, power
FET stage. The device uses proprietary techniques to optimize EMI and audio performance.
9.3.4 Power FETs
The BTL output comprises four matched N-channel FETs for high efficiency and maximum power transfer to the
load. By design, the FETs withstand large voltage transients during a load-dump event.
9.3.5 Load Diagnostics
The device incorporates load diagnostic circuitry designed for detecting and determining the status of output
connections. The device supports the following diagnostics:
• Short to GND
• Short to PVDD
• Short across load
• Open load
The device reports the presence of any of the short or open conditions to the system via I2C register read.
9.3.5.1 Load Diagnostics
The load diagnostic function runs on de-assertion of STANDBY or when the device is in a fault state (dc detect,
overcurrent, overvoltage, undervoltage, or overtemperature). During this test, the outputs are in a Hi-Z state. The
device determines whether the output is a short to GND, short to PVDD, open load, or shorted load. The load
diagnostic biases the output, which therefore requires limiting the capacitance value for proper functioning; see
the Recommended Operating Conditions. The load diagnostic test takes approximately 229 ms to run. Note that
the check phase repeats up to 5 times if a fault is present or a large capacitor to GND is present on the output.
On detection of an open load, the output still operates. On detection of any other fault condition, the output goes
into a Hi-Z state, and the device checks the load continuously until removal of the fault condition. After detection
of a normal output condition, the audio output starts. The load diagnostics run after every other overvoltage (OV)
event. The load diagnostic for open load only has I2C reporting. All other faults have I2C and FAULT pin
assertion.
The device performs load diagnostic tests as shown in Figure 11.
Figure 12 illustrates how the diagnostics determine the load based on output conditions.
Discharge
(75 ms)
Ramp Up
(52 ms)
Check
(50 ms)
Ramp Down
(52 ms)
Figure 11. Load Diagnostics Sequence of Events
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Output Conditions
Load Diagnostics
Open Load
Open Load Detected
OL Max
Normal or Open Load
Open Load (OL)
May Be Detected
Detection Threshold
OL Min
Normal
Load
Play Mode
SL Max
Shorted Load (SL)
Detection Threshold
Normal or Shorted Load
May Be Detected
SL Min
Shorted
Load
Shorted Load
Detected
Figure 12. Load Diagnostic Reporting Thresholds
9.3.5.2 Faults During Load Diagnostics
If the device detects a fault (overtemperature, overvoltage, undervoltage) during the load diagnostics test, the
device exits the load diagnostics, which may result in a pop or click on the output.
9.3.6 Protection and Monitoring
• Overcurrent Shutdown (OCSD)—The overcurrent shutdown forces the output into Hi-Z. The device asserts
the FAULT pin and updates the I2C register.
• DC Detect—This circuit checks for a dc offset continuously during normal operation at the output of the
amplifier. If a dc offset occurs, the device asserts the FAULT pin and updates the I2C register. Note that the
dc detection threshold follows PVDD changes.
• Overtemperature Shutdown (OTSD)—The device shuts down when the die junction temperature reaches
the overtemperature threshold. The device asserts the FAULT pin and updates I2C register. Recovery is
automatic when the temperature returns to a safe level.
• Undervoltage (UV)—The undervoltage (UV) protection detects low voltages on PVDD. In the event of an
undervoltage condition, the device asserts the FAULT pin and resets the I2C register.
• Power-On Reset (POR)—Power-on reset (POR) occurs when PVDD drops below the POR threshold. A POR
event causes the I2C bus to go into a high-impedance state. After recovery from the POR event, the device
restarts automatically with default I2C register settings. The I2C is active as long as the device is not in POR.
• Overvoltage (OV) and Load Dump—OV protection detects high voltages on PVDD. If PVDD reaches the
overvoltage threshold, the device asserts the FAULT pin and updates the I2C register. The device can
withstand 40-V load-dump voltage spikes.
• protection circuitry limits the output voltage to the value selected in I2C register 0x03. This value determines
both the positive and negative limits. One can use this feature to improve battery life or protect the speaker
from exceeding its excursion limits.
• Adjacent-Pin Shorts—The device design is such that shorts between adjacent pins do not cause damage.
9.3.7 I2C Serial Communication Bus
The device communicates with the system processor via the I2C serial communication bus as an I2C slave-only
device. The processor can poll the device via I2C to determine the operating status. All reports of fault conditions
and detections are via I2C. The system can also set numerous features and operating conditions via the I2C
interface. The I2C interface is active approximately 1 ms after the STANDBY pin is high.
14
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The I2C interface controls the following device features:
• Changing the gain setting to 20 dB, 26 dB, 32 dB, or 36 dB
• Controlling the peak voltage value of the SpeakerGuard protection circuitry
• Reporting load diagnostic results
• Changing of the switching frequency for AM radio avoidance
9.3.7.1 I2C Bus Protocol
The device has a bidirectional serial control interface that is compatible with the Inter IC (I2C) bus protocol and
supports 400-kbps data transfer rates for random and sequential write and read operations. This is a slave-only
device that does not support a multimaster bus environment or wait-state insertion. The master device uses the
I2C control interface to program the registers of the device and to read device status.
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data transfer on the bus is serial, one bit at a time. The transfer of address and data is in byte (8-bit)
format with the most-significant bit (MSB) transferred first. In addition, the receiving device acknowledges each
byte transferred on the bus with an acknowledge bit. Each transfer operation begins with the master device
driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus
uses transitions on the data pin (SDA) while the clock is HIGH to indicate start and stop conditions. A HIGH-toLOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit
transitions must occur within the low time of the clock period. Figure 13 shows these conditions. The master
generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and
then waits for an acknowledge condition. The device holds SDA LOW during the acknowledge clock period to
indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. The address
for each device is a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same
signals via a bidirectional bus using a wired-AND connection. The SDA and SCL signals require the use of an
external pullup resistor to set the HIGH level for the bus. There is no limit on the number of bytes that the
communicating devices can transmit between start and stop conditions. After transfer of the last word, the master
generates a stop condition to release the bus.
SDA
R/
A
W
7-Bit Slave Address
7
6
5
4
3
2
1
0
8-Bit Register Address (N)
7
6
5
4
3
2
1
0
8-Bit Register Data For
Address (N)
A
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-02
2
Figure 13. Typical I C Sequence
To communicate with the device, the I2C master uses addresses shown in Figure 13. Transmission of read and
write data can be by single-byte or multiple-byte data transfers.
9.3.7.2 Random Write
As shown in Figure 14, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte
corresponding to the internal memory address being accessed. After receiving the address byte, the device
again responds with an acknowledge bit. Next, the master device transmits the data byte for writing to the
memory address being accessed. After receiving the data byte, the device again responds with an acknowledge
bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.
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Start
Condition
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Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
A5
A4
2
I C Device Address and
Read/Write Bit
A3
A2
A1
Acknowledge
A0 ACK D7
D6
D5
Subaddress
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
T0036-05
Figure 14. Random Write Transfer
9.3.7.3 Random Read
As shown in Figure 15, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, the master device
performs both a write and a following read. Initially, the master device performs a write to transfer the address
byte of the internal memory address to be read. As a result, the read/write bit is a 0. After receiving the address
and the read/write bit, the device responds with an acknowledge bit. In addition, after sending the internal
memory address byte, the master device transmits another start condition followed by the device address and
the read/write bit again. This time, the read/write bit is a 1, indicating a read transfer. After receiving the address
and the read/write bit, the device again responds with an acknowledge bit. Next, the device transmits the data
byte from the memory address being read. After receiving the data byte, the master device transmits a notacknowledge followed by a stop condition to complete the single-byte data-read transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
Acknowledge
A6
2
I C Device Address and
Read/Write Bit
A5
A4
A0 ACK
Not
Acknowledge
Acknowledge
A6
A5
A1
A0 R/W ACK D7
D6
2
Subaddress
D1
D0 ACK
Stop
Condition
Data Byte
I C Device Address and
Read/Write Bit
T0036-03
Figure 15. Random Read Transfer
9.3.7.4 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that the TAS5411-Q1
device transmits multiple data bytes to the master device as shown in Figure 16. Except for the last data byte,
the master device responds with an acknowledge bit after receiving each data byte and automatically increments
the I2C subaddress by 1. After receiving the last data byte, the master device transmits a not-acknowledge
followed by a stop condition to complete the transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
2
A0 R/W ACK A7
I C Device Address and
Read/Write Bit
Acknowledge
A6
A5
Subaddress
A0 ACK
A6
2
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-07
Figure 16. Sequential Read Transfer
16
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9.4 Device Functional Modes
9.4.1 Hardware Control Pins
There are three discrete hardware pins for real-time control and indication of device status.
FAULT pin: This active-low open-drain output pin indicates the presence of a fault condition which requires
the device to go into the Hi-Z mode. On assertion of this pin, the device has protected itself and the system
from potential damage. The system can read the exact nature of the fault via I2C with the exception of PVDD
undervoltage faults below POR, in which case the I2C bus is no longer operational.
STANDBY pin: Assertion of this active-low pin sends the device into a complete shutdown, limiting the
current draw.
MUTE pin: On assertion of this active-high pin, the device is in mute mode. The output pins stop switching
and audio does not pass from the input to the output. To place the device back into play mode, it is
necessary to deassert this pin.
9.4.2 EMI Considerations
Automotive-level EMI performance depends on both careful integrated-circuit design and good system-level
design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the
design.
The design has minimal parasitic inductances due to the short leads on the package. This dramatically reduces
the EMI that results from current passing from the die to the system PCB. The design incorporates circuitry that
optimizes output transitions that cause EMI.
9.4.3 Operating Modes and Faults
The following tables list operating modes and faults.
Table 2. Operating Modes
STATE NAME
OUTPUT
OSCILLATOR
I2C
Standby
Hi-Z, floating
Stopped
Stopped
Load diagnostic
DC biased
Active
Active
Fault and mute
Hi-Z, floating
Active
Active
Play
Switching with audio
Active
Active
Table 3. Faults and Actions
FAULT
EVENT
FAULT EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
Voltage fault
All
I2C + FAULT pin
OTSD
Thermal fault
Hi-Z, mute, play
OC fault
Output channel
fault
Play
POR
UV or OV
Not applicable
Load dump (1)
DC detect
ACTION
TYPE
FAULT pin
(1)
CLEARING
Standby
Hard mute (no ramp)
Hi-Z
Self-clearing
I2C + FAULT pin
Load diagnostic –
short
Load diagnostic –
open
ACTION
RESULT
Hi-Z, rerun
diagnostics
Diagnostic
Hi-Z
None
I2C
None
Clears on next
diagnostic
cycle
Tested in accordance with ISO7637-1
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9.5 Register Maps
Table 4. I2C Address
FIXED ADDRESS
DESCRIPTION
READ/WRITE BIT
I2C ADDRESS
MSB
6
5
4
3
2
1
LSB
1
1
0
1
1
0
0
0
0xD8
1
1
0
1
1
0
0
1
0xD9
I2C write
2
I C read
Table 5. I2C Address Register Definitions
ADDRESS
R/W
0x01
R
Latched fault register
REGISTER DESCRIPTION
0x02
R
Status and load diagnostics register
0x03
R/W
Control register
Table 6. Fault Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
No protection-created faults, default value
FUNCTION
–
–
–
–
–
–
–
1
Reserved
–
–
–
–
–
–
1
–
Reserved
–
–
–
–
–
1
–
–
A load-diagnostics fault has occurred.
–
–
–
–
1
–
–
–
Overcurrent shutdown has occurred.
–
–
–
1
–
–
–
–
PVDD undervoltage has occurred.
–
–
1
–
–
–
–
–
PVDD overvoltage has occurred.
–
1
–
–
–
–
–
–
DC offset protection has occurred.
1
–
–
–
–
–
–
–
Overtemperature shutdown has occurred.
Table 7. Status and Load Diagnostic Register (0x02)
18
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
No speaker-diagnostic-created faults, default value
FUNCTION
–
–
–
–
–
–
–
1
Output short to PVDD is present.
–
–
–
–
–
–
1
–
Output short to ground is present.
–
–
–
–
–
1
–
–
Open load is present.
–
–
–
–
1
–
–
–
Shorted load is present.
–
–
–
1
–
–
–
–
In a fault condition
–
–
1
–
–
–
–
–
Performing load diagnostics
–
1
–
–
–
–
–
–
In mute mode
1
–
–
–
–
–
–
–
In play mode
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Table 8. Control Register (0x03)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
1
1
1
1
0
0
0
26-dB gain, switching frequency set to 400 kHz, SpeakerGuard protection
circuitry disabled
–
–
–
–
–
–
–
1
Switching frequency set to 500 khz
–
–
–
–
–
1
1
-
Reserved
–
–
1
1
0
–
–
–
SpeakerGuard protection circuitry set to 14-V peak output
–
–
1
0
1
–
–
–
SpeakerGuard protection circuitry set to 11.8-V peak output
–
–
1
0
0
–
–
–
SpeakerGuard protection circuitry set to 9.8-V peak output
–
–
0
1
1
–
–
–
SpeakerGuard protection circuitry set to 8.4-V peak output
–
–
0
1
0
–
–
–
SpeakerGuard protection circuitry set to 7-V peak output
–
–
0
0
1
–
–
–
SpeakerGuard protection circuitry set to 5.9-V peak output
–
–
0
0
0
–
–
–
SpeakerGuard protection circuitry set to 5-V peak output
0
0
–
–
–
–
–
–
Gain set to 20 dB
1
0
–
–
–
–
–
–
Gain set to 32 dB
1
1
–
–
–
–
–
–
Gain set to 36 dB
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The device is a mono high-efficiency class-D audio amplifier. Typical use of the device is to amplify an audio
input to drive a speaker. The intent of its use is for a bridge-tied load (BTL) application, not for support of a
single-ended configuration. This section presents how to use the device in the application, including what
external components are necessary and how to connect unused pins.
10.2 Typical Application
L1
PVDD
10uH
C5
4.7µF
C4
4.7µF
C3
0.082µF
C8
330µF
C2
2200pF
C7
10µF
C6
0.1µF
C9
IN_P
1µF
R5
49.9k
U1
R6
49.9k
6
IN_P
PVDD
L2
15
C10
C16
7
IN_N
BSTP
IN_N
1µF
5
4
SCL
SDA
2
8
14
STANDBY
MUTE
FAULT
3
C20
1µF
SCL
SDA
STANDBY
MUTE
FAULT
BYP
OUTP
12
OUTN
11
BSTN
10
GND
GND
GND
PAD
0.22µF
R4
5.6
C13
16
9
1
C14
470pF
0.22µF
C15
TAS5411QPWPRQ1
OUTP
15µH 2.7A
13
C11
2.2uF
C12
0.01µF
470pF
R7
5.6
L3
OUTM
15µH 2.7A
C17
2.2uF
C18
0.01µF
Figure 17. TAS5411-Q1 Typical Application Schematic
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Typical Application (continued)
10.2.1 Design Requirements
Use the following for the design requirements:
• Power Supplies
The device needs only a single power supply compliant with the recommended operation range. The device
is designed to work with either a vehicle battery or regulated power supply such as from a backup battery.
• Communication
The device communicates with the system controller with both discrete hardware control pins and with I2C.
The device is an I2C slave and thus requires a master. If a master I2C-compliant device is not present in the
system, it is still possible to use the device, but only with the default settings. Diagnostic information is limited
to the discrete reporting FAULT pin.
• External Components
Table 9 lists the components required for the device.
Table 9. Supporting Components
EVM DESIGNATOR
QUANITY
VALUE
SIZE
DESCRIPTION
USE IN APPLICATION
C7
1
10 μF ± 10%
1206
X7R ceramic capacitor, 25-V
Power supply
C8
1
330 μF ± 20%
10 mm
Low-ESR aluminum capacitor, 25-V
Power supply
C9, C16, C20
3
1 μF ± 10%
0805
X7R ceramic capacitor, 25-V
Analog audio input filter, bypass
C10, C14
2
0.22 μF ± 10%
0603
X7R ceramic capacitor, 25-V
Bootstrap capacitors
C11, C17
2
2.2 μF ± 10%
0805
X7R ceramic capacitor, 25-V
Amplifier output filtering
C13, C15
2
470 pF ± 10%
0603
X7R ceramic capacitor, 250-V
Amplifier output snubbers
C6
1
0.1 μF ± 10%
0603
X7R ceramic capacitor, 25-V
Power supply
C2
1
2200 pF ± 10%
0603
X7R ceramic capacitor, 50-V
Power supply
C3
1
0.082 μF ± 10%
0603
X7R ceramic capacitor, 25-V
Power supply
C4, C5
2
4.7 μF ± 10%
1206
X7R ceramic capacitor, 25-V
Power supply
C12, C18
2
0.01 μF ± 10%
0603
X7R ceramic capacitor, 25-V
Output EMI filtering
L1
1
10 μH ± 20%
13.5 mm ×13.5
mm
Shielded ferrite inductor
Power supply
L2, L3
1
15 μH ± 20%
7 mm × 7 mm
Metal alloy inductor
Amplifier output filtering
R5, R6
2
49.9 kΩ ± 1%
0805
Resistors, 0.125-W
Analog audio input filter
R4, R7
2
5.6 Ω ± 5%
0805
Resistors, 0.125-W
Output snubbers
10.2.1.1 Amplifier Output Filtering
Output FETs drive the amplifier outputs in an H-bridge configuration. These transistors are either fully off or on.
The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio
signal. The amplifier outputs require a low-pass filter to filter out the PWM modulation carrier frequency. People
frequently call this filter the L-C filter, due to the presence of an inductive element L and a capacitive element C
to make up the 2-pole low-pass filter. The L-C filter attenuates the carrier frequency, reducing electromagnetic
emissions and smoothing the current waveform which the load draws from the power supply. See the Class-D
LC Filter Design application report, SLOA119, for a detailed description on proper component selection and
design of an L-C filter based on the desired load and response.
10.2.1.2 Amplifier Output Snubbers
A snubber is an RC network placed at the output of the amplifier to dampen ringing or overshoot on the PWM
output waveform. Overshoot and ringing have several negative impacts including: potential EMI sources,
degraded audio performance, and overvoltage stress of the output FETs or board components. For more
information on the use and design of output snubbers, see the Class-D Output Snubber Design Guide,
SLOA201.
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10.2.1.3 Bootstrap Capacitors
The output stage uses dual NMOS transistors; therefore, the circuit requires bootstrap capacitors for the high
side of each output to turn on correctly. The required capacitor connection is from BSTN to OUTN and from
BSTP to OUTP as shown in Figure 17.
10.2.1.4 Analog Audio Input Filter
The circuit requires an input capacitor to allow biasing of the amplifier put to the proper dc level. The input
capacitor and the input impedance of the amplifier form a high-pass filter with a –3-dB corner frequency
determined by the equation: f = 1 / (2πR(i)C(i)), where R(i) is the input impedance of the device based on the gain
setting and C(i) is the input capacitor value. Table 10 lists largest recommended input capacitor values. Use a
capacitor which matches the application need for the lowest frequency but does not exceed the values listed.
Table 10. Recommended Input AC-Coupling Capacitors
GAIN (dB)
TYPICAL INPUT IMPEDANCE
(kΩ)
INPUT CAPACITANCE (µF)
HIGH-PASS FILTER (Hz)
20
60
1
2.7
1.5
1.8
26
30
1
5.3
3.3
1.6
32
15
5.6
2.3
36
9
10
1.8
10.2.2 Detailed Design Procedure
Use the following steps for the design procedure:
• Step 1: Hardware Schematic Design: Using the Typical Application Schematic as a guide, integrate the
hardware into the system schematic.
• Step 2: Following the recommended layout guidelines, integrate the device and its supporting components
into the system PCB file.
• Step 3: Thermal Design: The device has an exposed thermal pad which requires proper soldering. For more
information, see the Semiconductor and IC Package Thermal Metrics, SPRA953, and the PowerPAD
Thermally Enhanced Package, SLMA002G, application reports.
• Step 4: Develop software: The EVM User's Guide, SLOU431, has detailed instructions for how to set up the
device, interpret diagnostic information, and so forth. For information about control registers, see the Register
Maps section.
10.2.2.1 Unused Pin Connections
Even if unused, always connect pins to a fixed rail; do not leave them floating. Floating input pins represent an
ESD risk, so adhere to the following guidance for each pin.
10.2.2.1.1 MUTE Pin
If the MUTE pin is unused in the application, connect it to GND through a high-impedance resistor.
10.2.2.1.2 STANDBY Pin
If the STANDBY pin is unused in the application, connect it to a low-voltage rail such as 3.3 V or 5 V through a
high-impedance resistor.
10.2.2.1.3 I2C Pins (SDA and SCL)
If there is no microcontroller in the system, use of the device without I2C communication is possible. In this
situation, connect the SDA and SCL pins to 3.3 V.
10.2.2.1.4 Terminating Unused Outputs
If the FAULT pin does not report to a system microcontroller in the application, connect it to GND.
22
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10.2.2.1.5 Using a Single-Ended Audio Input
When using a single-ended audio source, ac-ground the negative input through a capacitor equal in value to the
input capacitor on the positive input, and apply the audio source to the positive input. For best performance, the
ac ground should be at the audio source instead of at the device input if possible.
10.2.3 Application Curves
See the graphs listed in Table 11 for the application performance plots.
Table 11. Table of Graphs
GRAPH
FIGURE NO.
Efficiency vs Output Power
Figure 3
THD+N vs Output Power
Figure 4
Output Power vs PVDD
Figure 5
THD+N vs Frequency
Figure 6
Noise FFT With –60-dB Output
Figure 7
Noise FFT With 1-W Output
Figure 8
Overcurrent Threshold vs Temperature
Figure 9
11 Power Supply Recommendations
A car battery that can have a large voltage range most commonly provides power for the device. PVDD, a filtered
battery voltage, is the supply for the output FETs and the low-side FET gate driver. Good power-supply
decoupling is necessary, especially at low voltage and temperature levels. To meet the PVDD specifications in
the Electrical Characteristics section, TI uses 10-µF and 0.1-µF ceramic capacitors near the PVDD pin along with
a larger bulk 330-µF electrolytic decoupling capacitor.
An internal linear regulator, which powers the analog circuitry, provides the voltage on the BYP pin. This supply
requires an external bypass ceramic capacitor at the BYP pin.
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12 Layout
12.1 Layout Guidelines
The EVM layout optimizes for thermal dissipation and EMC performance. The TAS5411-Q1 device has a thermal
pad down, and good thermal conduction and dissipation require adequate copper area. Layout also affects EMC
performance. TAS5411Q1EVM illustrations form the basis for the layout discussions.
12.2 Layout Examples
12.2.1 Top Layer
The red boxes around number 1 are the copper ground on the top layer. Soldered directly to the thermal pad,
this ground is the first significant thermal dissipation needed. There are vias that go to the other layers for further
thermal relief, but vias have high thermal resistance. TI recommends that use of this top layer be mostly for
thermal dissipation. A further recommendation is short routes from output pins to the second-order LC filter for
EMC suppression. The number 2 arrow indicates these short routes. The shorter the distance, the less EMC
radiates. A short route from the PVDD pin to the LC filter from the battery or power source, as indicated by the
number 3 arrow, also improves EMC suppression. The red box around number 4 indicates the ground plane that
is common to both OUTP and OUTN. Place the capacitors of the LC filter in this common ground plane to help
with common-mode noise and short ground loops.
Figure 18. Top Layer
24
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Layout Examples (continued)
12.2.2 Second Layer – Signal Layer
If possible, route the I2C and the positive and negative input traces close together and cover with ground plane,
keeping the signals from noise.
Figure 19. Signal Layer
12.2.3 Third Layer – Power Layer
There is no need for a power plane, but TI recommends a wide single PVDD trace to keep the switching noise to
a minimum and provide enough current to the device. The wide trace provides a low-impedance path from the
power source to the PVDD pin and from the GND pin to the source return. Suppression of switching noise (ripple
voltage) on both the positive and return (ground) paths requires a low impedance.
Figure 20. Power Layer
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Layout Examples (continued)
12.2.4 Bottom Layer – Ground Layer
The device has an exposed thermal pad on the bottom side for improved thermal performance. Conducting heat
from the thermal pad to other layers requires thermal vias. Because the bottom layer is the secondary heat
exchange surface to ambient, the thermal vias area must have low thermal resistance, that is, no signal vias or
traces that can increase thermal resistance from the thermal vias to the bottom copper.
Figure 21. Bottom Layer
13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• AN-1737 Managing EMI in Class D Audio Applications, SNAA050
• Class-D LC Filter Design, SLOA119
• Class-D Output Snubber Design Guide, SLOA201
• Guidelines for Measuring Audio Power Amplifier Performance, SLOA068
• PowerPAD Thermally Enhanced Package, SLMA002G
• TAS5411Q1EVM User's Guide, SLOU431
• TAS5421-Q1 22-W Mono Automotive Digital-Audio Amplifier With Load Dump and I2C Diagnostics, SLOS814
26
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13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
TAS5411QPWPRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
PWP
16
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
TAS5411
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Dec-2015
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TAS5411QPWPRQ1
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
16
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5411QPWPRQ1
HTSSOP
PWP
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
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