DATASHEET

EL5224, EL5324, EL5424
®
Data Sheet
May 11, 2005
12MHz Rail-to-Rail Buffers + 100mA VCOM
Amplifier
The EL5224, EL5324, and EL5424 feature 8, 10, and 12 low
power buffers, respectively, and one high power output
amplifier. They are designed primarily for buffering column
driver reference voltages in TFT-LCD applications as well as
generation of the VCOM supply. Each low power buffer
features a -3dB bandwidth of 12MHz and features rail-to-rail
input/output capability. The high power buffer can drive
100mA and swings to within 2V of each rail.
The 8-channel EL5224 is available in 24-pin QFN and 24-pin
HTSSOP packages, the 10-channel EL5324 is available in
32-pin QFN and 28-pin HTSSOP packages, and the
12-channel EL5424 is available in the 32-pin QFN package.
They are specified for operation over the full -40°C to +85°C
temperature range.
FN7004.3
Features
• 8, 10, and 12 channel versions
• 12MHz -3dB buffer bandwidth
• 150mA VCOM buffer
• Operating supply voltage from 4.5V to 16.5V
• Low supply current - 6mA total (8-channel version)
• Rail-to-rail input/output swing (buffers only)
• QFN package - just 0.9mm high
• Pb-Free available (RoHS compliant)
Applications
• TFT-LCD column driver buffering and VCOM supply
• Electronics notebooks
• Computer monitors
• Electronics games
• Touch-screen displays
• Portable instrumentation
Ordering Information (Continued)
Ordering Information
PART NUMBER
PACKAGE
TAPE &
REEL
PKG. DWG. #
EL5224IL
24-Pin QFN
EL5224IL-T7
24-Pin QFN
7”
MDP0046
EL5224IL-T13
24-Pin QFN
13”
MDP0046
EL5224ILZ
(See Note)
MDP0046
24-Pin QFN
(Pb-free)
MDP0046
PART NUMBER
EL5324ILZ-T13
(See Note)
PACKAGE
32-Pin QFN
(Pb-free)
TAPE &
REEL
PKG. DWG. #
13”
MDP0046
EL5324IRE
28-Pin HTSSOP
-
MDP0048
EL5324IRE-T7
28-Pin HTSSOP
7”
MDP0048
EL5324IRE-T13
28-Pin HTSSOP
13”
MDP0048
28-Pin HTSSOP
(Pb-free)
-
MDP0048
EL5224ILZ-T7
(See Note)
24-Pin QFN
(Pb-free)
7”
MDP0046
EL5324IREZ
(See Note)
EL5224ILZ-T13
(See Note)
24-Pin QFN
(Pb-free)
13”
MDP0046
EL5324IREZ-T7
(See Note)
28-Pin HTSSOP
(Pb-free)
7”
MDP0048
EL5224IRE
24-Pin HTSSOP
-
MDP0048
MDP0048
24-Pin HTSSOP
7”
MDP0048
28-Pin HTSSOP
(Pb-free)
13”
EL5224IRE-T7
EL5324IREZ-T13
(See Note)
EL5224IRE-T13
24-Pin HTSSOP
13”
MDP0048
EL5224IREZ
(See Note)
24-Pin HTSSOP
(Pb-free)
-
MDP0048
EL5424IL
32-Pin QFN
EL5424IL-T7
32-Pin QFN
7”
MDP0046
MDP0046
EL5424IL-T13
32-Pin QFN
13”
MDP0046
32-Pin QFN
(Pb-free)
EL5224IREZ-T7
(See Note)
24-Pin HTSSOP
(Pb-free)
7”
MDP0048
EL5424ILZ
(See Note)
EL5224IREZ-T13
(See Note)
24-Pin HTSSOP
(Pb-free)
13”
MDP0048
EL5424ILZ-T7
(See Note)
32-Pin QFN
(Pb-free)
7”
MDP0046
MDP0046
EL5424ILZ-T13
(See Note)
32-Pin QFN
(Pb-free)
13”
MDP0046
EL5324IL
32-Pin QFN
EL5324IL-T7
32-Pin QFN
7”
MDP0046
EL5324IL-T13
32-Pin QFN
13”
MDP0046
EL5324ILZ
(See Note)
32-Pin QFN
(Pb-free)
EL5324ILZ-T7
(See Note)
32-Pin QFN
(Pb-free)
1
MDP0046
7”
MDP0046
MDP0046
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5224, EL5324, EL5424
Pinouts
EL5324
(28-PIN HTSSOP)
TOP VIEW
EL5224
(24-PIN HTSSOP)
TOP VIEW
VIN1 1
24 VOUT1
VIN1 1
28 VOUT1
VIN2 2
23 VOUT2
VIN2 2
27 VOUT2
VIN3 3
22 VOUT3
VIN3 3
26 VOUT3
21 VOUT4
VIN4 4
25 VOUT4
20 VS-
VIN5 5
VIN4 4
THERMAL
PAD
VS+ 5
24 VOUT5
THERMAL
PAD
23 VS-
VIN5 6
19 VOUT5
VS+ 6
VIN6 7
18 VOUT6
VIN6 7
22 VOUT6
VIN7 8
17 VOUT7
VIN7 8
21 VOUT7
VIN8 9
16 VOUT8
VIN8 9
20 VOUT8
VSA+ 10
15 VSA-
VIN9 10
19 VOUT9
VINA+ 11
14 VINA-
VIN10 11
18 VOUT10
13 VOUTA
VSA+ 12
17 VSA-
VINA+ 13
16 VINA15 VOUTA
NC 14
21 VOUT1
22 NC
24 VIN2
26 VOUT2*
27 VOUT1
28 VOUT0
29 NC
30 VIN0
31 VIN1
32 VIN2*
23 VIN1
EL5224
(24-PIN QFN)
TOP VIEW
EL5324 & EL5424
(32-PIN QFN)
TOP VIEW
20 VOUT2
NC 12
VIN3 1
25 VOUT3
VIN3 1
19 VOUT3
VIN4 2
24 VOUT4
VIN4 2
18 VOUT4
VIN5 3
23 VOUT5
VS+ 3
THERMAL
PAD
15 VOUT6
VIN7 6
20 VOUT7
VIN7 6
14 VOUT7
VIN8 7
19 VOUT8
VIN8 7
13 VOUT8
VIN9 8
18 VOUT9
VIN10 9
17 VOUT10
2
VOUT11* 16
VSA- 15
VINA- 14
VOUTA 13
VINA+ 12
VIN11* 10
VSA+ 11
*Not available in EL5324
16 VOUT5
VSA- 12
VIN6 5
VIN6 5
VINA- 11
21 VOUT6
THERMAL
PAD
VOUTA 10
VIN5 4
VINA+ 9
22 VS-
VSA+ 8
VS+ 4
17 VS-
EL5224, EL5324, EL5424
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V, VS+ +0.5V
Maximum Continuous Output Current (VOUT0-9) . . . . . . . . . . 30mA
Maximum Continuous Output Current (VOUTA). . . . . . . . . . . 150mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
VS+ = +15V, VS- = 0, RL = 10kΩ, RF = RG = 20kΩ, CL = 10pF to 0V, Gain of VCOM = -1, and TA = 25°C Unless
Otherwise Specified
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
14
mV
INPUT CHARACTERISTICS (REFERENCE BUFFERS)
VOS
Input Offset Voltage
VCM = 0V
2
TCVOS
Average Offset Voltage Drift
(Note 1)
5
IB
Input Bias Current
VCM = 0V
2
RIN
Input Impedance
CIN
Input Capacitance
AV
Voltage Gain
µV/°C
50
1
GΩ
1.35
1V ≤ VOUT ≤ 14V
0.992
nA
pF
1.008
V/V
4
mV
INPUT CHARACTERISTICS (VCOM BUFFER)
VOS
Input Offset Voltage
VCM = 7.5V
1
TCVOS
Average Offset Voltage Drift
(Note 1)
3
IB
Input Bias Current
VCM = 7.5V
2
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
1.35
pF
VREG
Load Regulation
VCOM = 6V, -100mA < IL < 100mA
-20
µV/°C
100
nA
+20
mV
150
mV
OUTPUT CHARACTERISTICS (REFERENCE BUFFERS)
VOL
Output Swing Low
IL = 7.5mA
VOH
Output Swing High
IL = 7.5mA
ISC
Short Circuit Current
50
14.85
14.95
V
120
140
mA
OUTPUT CHARACTERISTICS (VCOM BUFFER)
VOL
Output Swing Low
50Ω to 7.5V
VOH
Output Swing High
50Ω to 7.5V
ISC
Short Circuit Current
1
13.5
1.5
V
14
V
160
mA
POWER SUPPLY PERFORMANCE
PSRR
IS
Power Supply Rejection Ratio
Total Supply Current
Reference buffer VS from 5V to 15V
55
80
dB
VCOM buffer, VS from 5V to 15V
60
100
dB
EL5224 (no load)
5
6.8
8
mA
EL5324 (no load)
6
7.8
9.5
mA
EL5424 (no load)
7
8.8
11
mA
7
DYNAMIC PERFORMANCE (BUFFER AMPLIFIERS)
SR
Slew Rate (Note 2)
-4V ≤ VOUT ≤ 4V, 20% to 80%
15
V/µs
tS
Settling to +0.1% (AV = +1)
(AV = +1), VO = 2V step
250
ns
BW
-3dB Bandwidth
RL = 10kΩ, CL = 10pF
12
MHz
3
EL5224, EL5324, EL5424
Electrical Specifications
VS+ = +15V, VS- = 0, RL = 10kΩ, RF = RG = 20kΩ, CL = 10pF to 0V, Gain of VCOM = -1, and TA = 25°C Unless
Otherwise Specified (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
GBWP
Gain-Bandwidth Product
RL = 10kΩ, CL = 10pF
8
MHz
PM
Phase Margin
RL = 10kΩ, CL = 10pF
50
°
CS
Channel Separation
f = 5MHz
75
dB
NOTES:
1. Measured over operating temperature range
2. Slew rate is measured on rising and falling edges
Pin Descriptions
24-PIN HTSSOP
24-PIN QFN
32-PIN QFN
28-PIN HTSSOP
PIN NAME
1
23
31
1
VIN1
PIN FUNCTION
2
24
32 (Note 1)
2
VIN2
Input
3
1
1
3
VIN3
Input
4
2
2
4
VIN4
Input
5
3
4
6
VS+
Power
6
4
3
5
VIN5
Input
7
5
5
7
VIN6
Input
8
6
6
8
VIN7
Input
9
7
7
9
VIN8
Input
Input
10
8
11
12
VSA+
Power
11
9
12
13
VINA+
Positive input of VCOM
12
22
29
14
NC
13
10
13
15
VOUTA
14
11
14
16
VINA-
Negative input of VCOM
15
12
15
17
VSA-
Power
16
13
19
20
VOUT8
Output
17
14
20
21
VOUT7
Output
18
15
21
22
VOUT6
Output
19
16
23
24
VOUT5
Output
20
17
22
23
VS-
Power
21
18
24
25
VOUT4
Output
22
19
25
26
VOUT3
Output
23
20
26 (Note 1)
27
VOUT2
Output
24
21
27
28
VOUT1
Output
8
10
VIN9
Input
9
11
NOTE:
1. Not available in EL5324IL
4
Not connected
Output of VCOM
VIN10
Input
10 (Note 1)
VIN11
Input
16 (Note 1)
VOUT11
Output
17
18
VOUT10
Output
18
19
VOUT9
Output
28
VOUT0
Output
30
VIN0
Input
EL5224, EL5324, EL5424
Typical Performance Curves
20
VS=±7.5V
CL=10pF
10
NORMALIZED MAGNITUDE (dB)
NORMALIZED MAGNITUDE (dB)
20
10kΩ
1kΩ
0
-10
150Ω
562Ω
-20
-30
100K
1M
10M
VS=±7.5V
RL=10kΩ
100pF
0
-10
-20
FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS RL
(BUFFER)
100M
600
VS=±7.5V
OUTPUT IMPEDANCE (Ω)
PSRR+
80
PSRR (dB)
10M
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS CL
(BUFFER)
100
PSRR-
40
20
0
1K
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
60
12pF
47pF
-30
100K
100M
1000pF
10
10K
100K
1M
VS=±7.5V
TA=25°C
480
360
240
120
0
100K
10M
FREQUENCY (Hz)
1M
10M
100M
FREQUENCY (Hz)
FIGURE 3. PSRR vs FREQUENCY (BUFFER)
FIGURE 4. OUTPUT IMPEDANCE vs FREQUENCY (BUFFER)
100
70
OVERSHOOT (%)
VOLTAGE NOISE (nV/√Hz)
80
10
60
VS=±7.5V
RL=10kΩ
VIN=100mV
50
40
30
20
10
1
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 5. INPUT NOISE SPECIAL DENSITY vs FREQUENCY
(BUFFER)
5
0
10
100
1K
CAPACITANCE (pF)
FIGURE 6. OVERSHOOT vs LOAD CAPACITANCE (BUFFER)
EL5224, EL5324, EL5424
Typical Performance Curves (Continued)
10
STEP SIZE (V)
6
0.018
VS=±7.5V
RL=10kΩ
CL=12pF
VS=±5V
RL=10kΩ
VIN=2VP-P
0.016
THD + NOISE (%)
8
4
2
0
-2
-4
-6
0.014
0.012
0.01
0.008
-8
-10
200 250 300 350 400 450 500 550 600 650
0.006
1K
10K
SETTLING TIME (ns)
FIGURE 7. SETTLING TIME vs STEP SIZE (BUFFER)
FIGURE 8. TOTAL HARMONIC DISTORTION + NOISE vs
FREQUENCY (BUFFER)
4
NORMALIZED MAGNITUDE (dB)
12
10
VOP-P (V)
8
6
4
2
100K
FREQUENCY (Hz)
VS=±5V
RL=10kΩ
0
10K
100K
1M
AV=5
2
AV=1
0
-2
-4
VS=±7.5V
CL=1µF
-6
100
10M
FREQUENCY (Hz)
100K
1M
FREQUENCY (Hz)
FIGURE 10. FREQUENCY RESPONSE (VCOM)
FIGURE 9. OUTPUT SWING vs FREQUENCY (BUFFER)
5mA/DIV
0mA
10K
1K
5mA
5mA/DIV
0mA
5mA
RS=0Ω
CL=200pF
RS=10Ω
CL=1nF
0V
500mV/DIV
RS=10Ω
CL=4.7nF
RS=10Ω
CL=1nF
M=1µs/DIV
VS=±7.5V
VIN=0V
FIGURE 11. TRANSIENT LOAD REGULATION - SOURCING
(BUFFER)
6
0V
500mV/DIV
M=1µs/DIV
VS=±7.5V
VIN=0V
RS=0Ω
CL=200pF
RS=10Ω
CL=4.7nF
FIGURE 12. TRANSIENT LOAD REGULATION - SINKING
(BUFFER)
EL5224, EL5324, EL5424
Typical Performance Curves (Continued)
M=4µs/DIV, VS=±7.5V, VIN=0V
M=4µs/DIV, VS=±7.5V, VIN=0V
0mA
100mA/DIV
-100mA
100mA
0mA
0V
20mV/DIV
0V
20mV/DIV
CL=1µF
CL=1µF
FIGURE 13. TRANSIENT LOAD REGULATION - SOURCING
(VCOM)
100mA/DIV
FIGURE 14. TRANSIENT LOAD REGULATION - SINKING
(VCOM)
VS=±7.5V, RL=10kΩ, CL=12pF
VS=±7.5V
1V/DIV
50mV/DIV
1µs/DIV
200ns/DIV
FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE
(BUFFER)
FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE
(BUFFER)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD, QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
0.8
2.857W
758mW
2.5 2.703W
POWER DISSIPATION (W)
POWER DISSIPATION (W)
3
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE
LAYER) TEST BOARD
QFN32
θJA=35°C/W
2
1.5
QFN24
θJA=37°C/W
1
0.5
0.7
714mW
0.6
QFN32
θJA=132°C/W
0.5
QFN24
θJA=140°C/W
0.4
0.3
0.2
0.1
0
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 17. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
7
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
EL5224, EL5324, EL5424
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD. HTSSOP EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
1
3.333W
3
3.030W
2.5
HTSSOP28
θJA=30°C/W
2
HTSSOP24
θJA=33°C/W
1.5
1
0.5
0
909mW
0.9
POWER DISSIPATION (W)
POWER DISSIPATION (W)
3.5
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.8 833mW
0.7
HTSSOP28
θJA=110°C/W
0.6
0.5
HTSSOP24
θJA=120°C/W
0.4
0.3
0.2
0.1
0
25
50
75 85 100
125
150
0
0
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Applications Information
Correct operation is guaranteed for a supply range of 4.5V to
16.5V.
VS=±5V
TA=25°C
VIN=10VP-P
5V
OUTPUT
The EL5224, EL5324, and EL5424 unity gain buffers and
100mA VCOM amplifier are fabricated using a high voltage
CMOS process. The buffers exhibit rail-to-rail input and
output capability and has low power consumption (600µA
per buffer). When driving a load of 10kΩ and 12pF, the
buffers have a -3dB bandwidth of 12MHz and exhibits
18V/µs slew rate. The VCOM amplifier exhibits rail-to-rail
input. The output can be driving to within 2V of each supply
rail. With a 1µF capacitance load, the GBWP is about 1MHz.
10µs
INPUT
5V
Product Description
FIGURE 21. OPERATION WITH RAIL-TO-RAIL INPUT AND
OUTPUT
The Use of the Buffers
SHORT-CIRCUIT CURRENT LIMIT
The output swings of the buffers typically extend to within
100mV of positive and negative supply rails with load
currents of 5mA. Decreasing load currents will extend the
output voltage range even closer to the supply rails.
Figure 21 shows the input and output waveforms for the
device. Operation is from ±5V supply with a 10kΩ load
connected to GND. The input is a 10VP-P sinusoid. The
output voltage is approximately 9.985VP-P.
The buffers will limit the short circuit current to ±120mA if the
output is directly shorted to the positive or the negative
supply. If an output is shorted indefinitely, the power
dissipation could easily increase such that the device may
be damaged. Maximum reliability is maintained if the output
continuous current never exceeds ±30mA. This limit is set by
the design of the internal metal interconnects.
OUTPUT PHASE REVERSAL
The buffers are immune to phase reversal as long as the
input voltage is limited from VS- -0.5V to VS+ +0.5V.
Figure 22 shows a photo of the output of the device with the
input voltage driven beyond the supply rails. Although the
device's output will not change phase, the input's
overvoltage should be avoided. If an input voltage exceeds
supply voltage by more than 0.6V, electrostatic protection
diodes placed in the input stage of the device begin to
conduct and overvoltage damage could occur.
8
EL5224, EL5324, EL5424
VBOOST
1V
10µs
R1
IPCOM
+
INCOM
R2
VS=±2.5V
TA=25°C
VIN=6VP-P
1V
FIGURE 22. OPERATION WITH BEYOND-THE-RAILS INPUT
UNUSED BUFFERS
The VCOM amplifier is designed to control the voltage on the
back plate of an LCD display. This plate is capacitively
coupled to the pixel drive voltage which alternately cycles
positive and negative at the line rate for the display. Thus the
amplifier must be capable of sourcing and sinking capacitive
pulses of current, which can occasionally be quite large (a
few 100mA for typical applications).
A simple use of the VCOM amplifier is as a voltage follower,
as illustrated in Figure 23. Here, a voltage, corresponding to
the mid-DAC potential, is generated by a resistive divider
and buffered by the amplifier. The amplifier's stability is
designed to be dominated by the load capacitance, thus for
very short duration pulses (< 1µs) the output capacitor
supplies the current. For longer pulses the VCOM amplifier
supplies the current. By virtue of its high transconductance
which progressively increases as more current is drawn, it
can maintain regulation within 5mV as currents up to 100mA
are drawn, while consuming only 2mA of quiescent current.
9
VCOM
VSSCOM
1µF CERAMIC
LOW ESR
Alternatively, the back plate potential can be generated by a
DAC and the VCOM amplifier used to buffer the DAC
voltage, with gain if necessary. This is shown in Figure 24. In
this case, the effective transconductance of the feedback is
reduced, thus the amplifier will be more stable, but regulation
will be degraded by the feedback factor.
VBOOST
DRIVING CAPACITIVE LOADS
The Use of VCOM Amplifier
VCOM
FIGURE 23. VCOM USED AS A VOLTAGE BUFFER
It is recommended that any unused buffers have their inputs
tied to the ground plane.
The buffers can drive a wide range of capacitive loads. As
load capacitance increases, however, the -3dB bandwidth of
the device will decrease and the peaking increase. The
buffers drive 10pF loads in parallel with 10kΩ with just 1.5dB
of peaking, and 100pF with 6.4dB of peaking. If less peaking
is desired in these applications, a small series resistor
(usually between 5Ω and 50Ω) can be placed in series with
the output. However, this will obviously reduce the gain
slightly. Another method of reducing peaking is to add a
snubber circuit at the output. A snubber is a shunt load
consisting of a resistor in series with a capacitor. Values of
150Ω and 10nF are typical. The advantage of a snubber is
that it does not draw any DC load current or reduce the gain.
VDDCOM
FROM DAC
+
-
R1
VCOM
1µF CERAMIC
LOW ESR
R2
FIGURE 24. VCOM USED AS A BUFFER WITH GAIN
CHOICE OF OUTPUT CAPACITOR
A 1µF ceramic capacitor with low ESR is recommended for
this amplifier. (For example, GRM42_ 6X7R105K16). This
capacitor determines the stability of the amplifier. Reducing it
will make the amplifier less stable, and should be avoided.
With a 1µF capacitor, the unity gain bandwidth of the
amplifier is close to 1MHz when reasonable currents are
being drawn. (For lower load currents, the gain and hence
bandwidth progressively decreases.) This means the active
trans-conductance is:
2π × 1μF × 1MHz = 6.28S
This high transconductance indicates why it is important to
have a low ESR capacitor.
If:
ESR × 6.28 > 1
then the capacitor will not force the gain to roll off below
unity, and subsequent poles can affect stability. The
recommended capacitor has an ESR of 10mΩ, but to this
must be added the resistance of the board trace between the
capacitor and the sense connection - therefore this should
be kept short, as illustrated in Figure 21, by the diagonal line
to the capacitor. Also ground resistance between the
capacitor and the base of R2 must be kept to a minimum.
These constraints should be considered when laying out the
PCB.
EL5224, EL5324, EL5424
If the capacitor is increased above 1µF, stability is generally
improved and short pulses of current will cause a smaller
“perturbation” on the VCOM voltage. The speed of response
of the amplifier is however degraded as its bandwidth is
decreased. At capacitor values around 10µF, a subtle
interaction with internal DC gain boost circuitry will decrease
the phase margin and may give rise to some overshoot in
the response. The amplifier will remain stable though.
RESPONSE TO HIGH CURRENT SPIKES
The VCOM amplifier's output current is limited to 150mA.
This limit level, which is roughly the same for sourcing and
sinking, is included to maintain reliable operation of the part.
It does not necessarily prevent a large temperature rise if the
current is maintained. (In this case the whole chip may be
shut down by the thermal trip to protect functionality.) If the
display occasionally demands current pulses higher than
this limit, the reservoir capacitor will provide the excess and
the amplifier will top the reservoir capacitor back up once the
pulse has stopped. This will happen on the µs time scale in
practical systems and for pulses 2 or 3 times the current
limit, the VCOM voltage will have settled again before the
next line is processed.
Power Dissipation
With the high-output drive capability of the EL5224, EL5324,
and EL5424 buffer, it is possible to exceed the 125°C
“absolute-maximum junction temperature” under certain load
current conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if load conditions need to be modified for the
buffer to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX - T AMAX
P DMAX = --------------------------------------------Θ JA
where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
P DMAX = Σi × [ V S × I SMAX + ( V S + - V OUT i ) × I LOAD i ] +
[ V SA × I SAA + ( V SA + - V OUTA ) × I LA ]
10
when sourcing, and:
P DMAX = Σi × [ V S × I SMAX + ( V OUT i - V S - ) × I LOAD i ] +
[ V SA × I SAA + ( V SA + - V OUTA ) × I LA ]
when sinking.
where:
• i = 1 to total number of buffers
• VS = Total supply voltage of buffer
• VSA = Total supply voltage of VCOM
• ISMAX = Maximum quiescent current per channel
• ISA = Maximum quiescent current of VCOM
• VOUTi = Maximum output voltage of the application
• VOUTA = Maximum output voltage of VCOM
• ILOADi = Load current of buffer
• ILA = Load current of VCOM
If we set the two PDMAX equations equal to each other, we
can solve for the RLOAD's to avoid device overheat. The
package power dissipation curves provide a convenient way
to see if the device will overheat. The maximum safe power
dissipation can be found graphically, based on the package
type and the ambient temperature. By using the previous
equation, it is a simple matter to see if PDMAX exceeds the
device's power derating curves.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended, lead lengths
should be as short as possible, and the power supply pins
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the VS- and VSA- pins
are connected to ground, two 0.1µF ceramic capacitors
should be placed from VS+ and VSA+ pins to ground. A
4.7µF tantalum capacitor should then be connected from
VS+ and VSA+ pins to ground. One 4.7µF capacitor may be
used for multiple devices. This same capacitor combination
should be placed at each supply pin to ground if split
supplies are to be used. Internally, VS+ and VSA+ are
shorted together and VS- and VSA- are shorted together. To
avoid high current density, the VS+ pin and VSA+ pin must
be shorted in the PCB layout. Also, the VS- pin and VSA- pin
must be shorted in the PCB layout.
Important Note: The metal plane used for heat sinking of
the device is electrically connected to the negative
supply potential (VS- and VSA-). If VS- and VSA- are tied
to ground, the thermal pad can be connected to ground.
Otherwise, the thermal pad must be isolated from any
other power planes.
EL5224, EL5324, EL5424
Package Outline Drawing (HTSSOP)
11
EL5224, EL5324, EL5424
Package Outline Drawing (QFN)
NOTE: The package drawings shown here may not be the latest versions. For the latest revisions, please refer to the Intersil website at
www.intersil.com/design/packages/elantec
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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