DATASHEET

D2-24044
Features
The D2-24044 device is a high performance, integrated
Class-D amplifier power stage. The four power stage
outputs are configurable as four separate Half-Bridge
outputs, as two Full-Bridge outputs, or combinations of
Half-Bridge and Full-Bridge. Individual power stage
overload monitoring, on-chip temperature monitoring,
and common alert logic outputs provide protection to
integrate with the final system’s controller.
• All Digital Class-D Power Stage
• 4
-
Configurable Power Stage Outputs Supporting:
2 Channels, Bridged
4 Channels, Half-Bridge
2 Channels, Half-Bridge, plus 1 Channel Bridged
• Output Power (Bridged)
- 25W (8Ω, <1% THD)
- 30W (8Ω, <10% THD)
• Single HV Supply - Wide 9V-26V Range
- Gate Drive Supply Internally-Generated
• Individual Channel Protection Monitoring
• Temperature and Undervoltage Monitoring
• Efficient 38 Ld HTSSOP Package
Digital Amplifier Power Stage
HSBSA
HVDDA
nOVRT
nPDN
IREF
Configuration &
Control
OUTA
HGNDA
OCFG1
nERRORA
OCFG0
HSBSB
HVDDB
PWM1
OUTB
PWM2
PWM3
PWM4
HGNDB
Drivers
nERRORB
PWM5
HSBSC
PWM6
HVDDC
PWM7
OUTC
PWM8
HGNDC
nERRORC
HSBSD
VDDHV
REG5V
PWMGND
PWMVDD
HVDDD
Power Supply
OUTD
HGNDD
nERRORD
September 3, 2010
FN7678.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
D2-24044
Digital Audio Amplifier Power Stage
D2-24044
Ordering Information
PART
NUMBER
(Notes 2, 3)
PART
MARKING
APPLICATION
SUPPORT
TEMP.
RANGE (°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
D2-24044-MR
D2-24044-MR
Commercial
-10 to +85
38 Ld HTSSOP
M38.173C
D2-24044-MR-T (Note 1)
D2-24044-MR
Commercial
-10 to +85
38 Ld HTSSOP
M38.173C
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for the D2-24044. For more information on MSL
please see techbrief TB363.
2
FN7678.0
September 3, 2010
D2-24044
Table of Contents
Absolute Maximum Ratings ................................................................................................................. 4
Thermal Information ........................................................................................................................... 4
Recommended Operating Conditions ................................................................................................... 4
Electrical Specifications ....................................................................................................................... 4
Performance Specifications ................................................................................................................. 5
Pin Configuration................................................................................................................................. 6
Pin Description .................................................................................................................................... 6
Typical Performance Characteristics.................................................................................................... 8
Full-Bridge Typical Performance Curves ................................................................................................. 8
Half-Bridge Typical Performance Curves ................................................................................................ 9
Functional Overview .......................................................................................................................... 10
Output Options .................................................................................................................................. 10
Power Supply Requirements.............................................................................................................. 10
High Side Gate Drive Voltage ............................................................................................................. 10
Supply Bypass Connection................................................................................................................. 10
REG5V ............................................................................................................................................ 10
Input and Control Functions .............................................................................................................. 11
PWM Inputs..................................................................................................................................... 11
nPDN Input Pin ................................................................................................................................ 11
nERRORA-D Output Pins.................................................................................................................... 11
nOVRT Output Pin ............................................................................................................................ 11
IREF Pin.......................................................................................................................................... 11
OCFG0, OCFG1 Input Pins ................................................................................................................. 11
Protection.......................................................................................................................................... 11
Short-Circuit and Overcurrent Sensing ................................................................................................ 11
Thermal Protection and Monitoring ..................................................................................................... 12
Power Supply Voltage Monitoring ....................................................................................................... 12
Output Mode Configurations .............................................................................................................. 14
Typical Application Examples ............................................................................................................ 17
2-Channel Full Bridge Example........................................................................................................... 17
2.1-Channel Example........................................................................................................................ 18
4-Channel Half-Bridge Example.......................................................................................................... 19
Package Outline Drawing .................................................................................................................. 20
3
FN7678.0
September 3, 2010
D2-24044
Absolute Maximum Ratings
Thermal Information
Supply Voltage
HVDD[A:D], VDDHV. . . . . . . . . . . . . . . . . . 0V to +28.0V
PWMVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 4.0V
Input Voltage
Any Input . . . . . . . . . . . . . . . . . -0.3V to PWMVDD + 0.3V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
38 Ld HTSSOP Package (Notes 4, 5)
29
1.3
Maximum Storage Temperature . . . . . . . . -55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C
High Voltage Supply Voltage,
HVDD[A:D], VDDHV . . . . . . . . . . . . . . . . . . 9.0V to 26.5V
Digital I/O Supply Voltage, PWMVDD . . . . . . . . . . . . . . 3.3V
Minimum Load Impedance (HVDD[A:D] ≤24.0V), ZL . . . . 4Ω
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. Absolute Maximum parameters are not tested in production.
Electrical Specifications
TA = +25°C, PWMVDD = 3.3V ±10%. All grounds at 0.0V.
All voltages referenced to ground.
TEST
CONDITIONS
PARAMETER
SYMBOL
MIN
Digital Input High Logic Level
VIH
2
-
-
V
Digital Input Low Logic Level
VIL
-
-
0.4
V
High Level Output Drive Voltage
(IOUT at -Pin Drive Strength Current)
VOH
PWMVDD-0.4
-
-
V
Low Level Output Drive Voltage
(IOUT at +Pin Drive Strength Current)
VOL
-
-
0.4
V
IIN
-
-
±10
μA
-
-
±50
μA
CIN
-
9
-
pF
COUT
-
9
-
pF
-
190
-
-
100
-
kΩ
3
3.3
3.6
V
Active Current
-
0.47
-
mA
Power-Down Current
-
0.15
-
mA
Logic Supply Undervoltage Threshold
-
2.6
-
V
Logic Supply Undervoltage Threshold Hysteresis
-
200
-
mV
Logic Supply Undervoltage Glitch Rejection
-
50
-
ns
-
4.5
-
V
Input Leakage Current
Pins 1, 2, 3
PWM Input Pins
(includes 100kΩ internal pull-down
resistor current)
Input Capacitance
Output Capacitance
All Outputs Except OUT[A:D]
OUT[A:D]
Internal Pull-Up Resistance to PWMVDD
(for nERRORA-D, nOVRT)
Digital I/O Supply Pin Voltage, Current
PWMVDD
TYP MAX UNIT
3.3V (PWMVDD) BROWN-OUT DETECTION
GATE DRIVE INTERNAL +5V BROWN-OUT DETECTION
Gate Drive Supply Undervoltage Threshold
4
FN7678.0
September 3, 2010
D2-24044
Electrical Specifications
TA = +25°C, PWMVDD = 3.3V ±10%. All grounds at 0.0V.
All voltages referenced to ground. (Continued)
TEST
CONDITIONS
PARAMETER
SYMBOL
MIN
TYP MAX UNIT
Gate Drive Supply Undervoltage Threshold
Hysteresis
-
200
-
mV
Gate Drive Supply Undervoltage Threshold Glitch
Rejection
-
50
-
ns
High Voltage Undervoltage Protection
-
7
9
V
Overcurrent Trip Threshold
-
4
-
A
Overcurrent De-glitch
-
2.5
-
ns
Short-Circuit Current Limit (Peak)
-
8
-
A
Overcurrent Response Time
-
20
-
ns
Thermal Shut-Down OTmax
-
140
-
°C
Thermal Warning Temperature OTmin
-
125
-
°C
Thermal Shut-Down Hysteresis
-
30
-
°C
Thermal Warning Hysteresis
-
20
-
°C
PROTECTION DETECT
Performance Specifications
TA = +25°C, PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages referenced to
ground.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
rDS(ON)
-
200
-
mΩ
rDS(ON) Mismatch
-
1
-
%
PWM Switching Rate
-
384
-
kHz
Minimum PWM Pulse Width
-
3.5
-
ns
PWM Off Sensor Time
-
10
-
μs
PWM Input to Output Delay
-
50
ns
PWM Input to Output Delay Matching
-
3
-
ns
rDS(ON) (MOSFETs @ +25°C)
nPDN Input Off Delay
TPDNOFF
-
1.4
-
nPDN Input On Delay
TPDNON
-
1.4
-
<1% THD, Bridged, Load = 8Ω, HVDD[A:D] = 24V
POUT
-
25
-
W
<10% THD, Bridged, Load = 8Ω, HVDD[A:D] = 24V
POUT
-
30
-
W
<1% THD, Half-Bridge, Load = 8Ω, HVDD[A:D] = 24V
POUT
-
7
-
W
<10% THD, Half-Bridge, Load = 8Ω, HVDD[A:D] = 24V
POUT
-
9
-
W
THD+N
-
0.3
-
%
-
0.05
-
%
-
110
-
dB
-
90
-
%
POWER OUTPUT
THD+N
Load = 8Ω, Power = 25W, Bridged, 1kHz
Load = 8Ω, Power = 1W, Bridged, 1kHz
SNR
SNR
Efficiency (Load = 8Ω)
5
FN7678.0
September 3, 2010
D2-24044
Pin Configuration
D2-24044
38 LD HTSSOP
TOP VIEW
nPDN
OCFG1
OCFG0
PWMGND
PWMVDD
nOVRT
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWMGND2
nERRORA
nERRORB
nERRORC
nERRORD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
HVDDA
HGNDA
OUTA
HSBSA
HSBSB
OUTB
HGNDB
HVDDB
REG5V
VDDHV
IREF
HVDDC
HGNDC
OUTC
HSBSC
HSBSD
OUTD
HGNDD
HVDDD
Pin Description
PIN NAME
PIN (Note 7) TYPE
VOLTAGE
LEVEL
(V)
DESCRIPTION
1
nPDN
I
3.3
Power-down and mute input. Active low. When this input is low, all 4 outputs become
inactive and their output stages float, and their output is muted. Internal logic and other
references remain active during this power-down state.
2
OCFG1
I
3.3
Output configuration control select. OCFG0 and OCFG1 are logic inputs to select the
output configuration mode of the output stages. Connects to either PWMGND ground or
PWMVDD (+3.3V) through nominal 10kΩ resistor to select output configuration.
3
OCFG0
I
3.3
Output configuration control select. OCFG0 and OCFG1 are logic inputs to select the
output configuration mode of the output stages. Connects to either PWMGND ground or
PWMVDD (+3.3V) through nominal 10kΩ resistor to select output configuration.
4
PWMGND
GND
0
5
PWMVDD
P
3.3
Low-voltage power. This 3.3V supply connects to the same system low-voltage power
used for providing PWM inputs.
6
nOVRT
O
3.3
Over-temperature warning output. Open drain, 16mA drive strength output with pull-up.
Pulls low when active from over-temperature detection.
7
PWM1
I
3.3
PWM Input. Routes to output channel, dependent on output configuration settings.
8
PWM2
I
3.3
PWM Input. Routes to output channel, dependent on output configuration settings.
9
PWM3
I
3.3
PWM Input. Routes to output channel, dependent on output configuration settings.
10
PWM4
I
3.3
PWM Input. Routes to output channel, dependent on output configuration settings.
11
PWM5
I
3.3
PWM Input. Routes to output channel, dependent on output configuration settings.
12
PWM6
I
3.3
PWM Input. Routes to output channel, dependent on output configuration settings.
6
Low-voltage ground. Connects to ground of circuitry providing PWM inputs. Both
PWMGND and PWMGND2 are to tie together to the same ground.
FN7678.0
September 3, 2010
D2-24044
Pin Description
PIN NAME
PIN (Note 7) TYPE
(Continued)
VOLTAGE
LEVEL
(V)
DESCRIPTION
13
PWM7
I
3.3
PWM Input. Routes to output channel, dependent on output configuration settings.
14
PWM8
I
3.3
PWM Input. Routes to output channel, dependent on output configuration settings.
15
PWMGND2
GND
0
16
nERRORA
O
3.3
Overcurrent protection output, channel A output stage. Open drain, 16mA drive strength
output with pull-up. Pulls low when active from overcurrent detection of output stage.
17
nERRORB
O
3.3
Overcurrent protection output, channel B output stage. Open drain, 16mA drive strength
output with pull-up. Pulls low when active from overcurrent detection of output stage.
18
nERRORC
O
3.3
Overcurrent protection output, channel C output stage. Open drain, 16mA drive strength
output with pull-up. Pulls low when active from overcurrent detection of output stage.
19
nERRORD
O
3.3
Overcurrent protection output, channel D output stage. Open drain, 16mA drive strength
output with pull-up. Pulls low when active from overcurrent detection of output stage.
20
HVDDD
P
HV
Output stage D high voltage supply power. A separate power pin connection is provided
for each of the output stages. All of the HVDD[A:D] pins and the VDDHV pin connect to
the system “HV” power source.
21
HGNDD
GND
HV
Output stage D high voltage supply ground. A separate ground pin connection is provided
for each of the output stages. All of the HGND[A:D] pins connect to system “HV” power
ground (also see Note 8).
22
OUTD
O
HV
PWM power amplifier output, channel D.
23
HSBSD
I
HV
High side boot strap input, output channel D. Capacitor couples to OUTD amplifier output.
24
HSBSC
I
HV
High side boot strap input, output channel C. Capacitor couples to OUTC amplifier output.
25
OUTC
O
HV
PWM power amplifier output, channel C.
26
HGNDC
GND
HV
Output stage C high voltage supply ground. A separate ground pin connection is provided
for each of the output stages. All of the HGND[A:D] pins connect to system “HV” power
ground (also see Note 8).
27
HVDDC
P
HV
Output stage C high voltage supply power. A separate power pin connection is provided
for each of the output stages. All of the HVDD[A:D] pins and the VDDHV pin connect to
the system “HV” power source.
28
IREF
I
-
Overcurrent reference analog input. Used in setting the overcurrent error detect
externally-set threshold. The pin needs to be connected to a 100kΩ resistor to ground to
set the overcurrent threshold according to the specified limits.
29
VDDHV
P
+HV
High Voltage internal driver supply power. All of the HVDD[A:D] pins and the VDDHV pin
connect to the system “HV” power source. The internal +5V supply regulators also
operate from this VDDHV input.
30
REG5V
P
5
5V internal regulator filter connect. A +5V supply is internally generated from the voltage
source provided at the VDDHV pin. REG5V is used for external connection of a decoupling
capacitor.
31
HVDDB
P
HV
Output stage B high voltage supply power. A separate power pin connection is provided
for each of the output stages. All of the HVDD[A:D] pins and the VDDHV pin connect to
the system “HV” power source.
32
HGNDB
GND
HV
Output stage B high voltage supply ground. A separate ground pin connection is provided
for each of the output stages. All of the HGND[A:D] pins connect to system “HV” power
ground (also see Note 8).
33
OUTB
O
HV
PWM power amplifier output, channel B.
34
HSBSB
I
HV
High side boot strap input, output channel B. Capacitor couples to OUTB amplifier output.
35
HSBSA
I
HV
High side boot strap input, output channel A. Capacitor couples to OUTA amplifier output.
36
OUTA
O
HV
PWM power amplifier output, channel A.
7
Low-voltage ground. Connects to ground of circuitry providing PWM inputs. Both
PWMGND and PWMGND2 are to tie together to the same ground.
FN7678.0
September 3, 2010
D2-24044
Pin Description
PIN NAME
PIN (Note 7) TYPE
(Continued)
VOLTAGE
LEVEL
(V)
DESCRIPTION
37
HGNDA
GND
HV
Output stage A high voltage supply ground. A separate ground pin connection is provided
for each of the output stages. All of the HGND[A:D] pins connect to system “HV” power
ground (also see Note 8).
38
HVDDA
P
HV
Output stage A high voltage supply power. A separate power pin connection is provided
for each of the output stages. All of the HVDD[A:D] pins and the VDDHV pin connect to
the system “HV” power source.
NOTES:
7. Unless otherwise specified all pin names are active high. Those that are active low have an “n” prefix, such as nERRORA.
8. Thermal pad is internally connected to all 4 HGND ground pins (HGNDA, HGNDB, HGNDC, HGNDD). Any connection to the
thermal pad must be made to the common ground for these 4 ground pins.
Typical Performance Characteristics
Full-Bridge Typical Performance Curves
10.00
2.00
0.200
1.00
0.100
0.50
0.20
P = 14W
0.050
0.020
P = 7W
P = 1W
0.10
0.010
0.05
0.005
0.02
0.002 HVDD = 24.0V, 8Ω LOAD,
AT 1W, 7W, 14W, 25W POWER OUT
0.001
20
50 100 200
500 1k
2k
FREQUENCY (Hz)
0.01
0.06
0.1
0.2
0.5
1
2
POWER (W)
5
10
20
50
FIGURE 1. THD vs POWER, FULL-BRIDGE
5
4
HVDD = 24.0V,
8Ω LOAD, 3.5W
3
2
dBr A
1
-0
-1
-2
-3
-4
-5
-6
30 50
100
200
500
1k
2k
5k
10k
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE, FULL-BRIDGE
8
5k
10k 20k
FIGURE 2. THD vs FREQUENCY, FULL-BRIDGE
6
dBr A
P = 25W
0.500
THD (%)
THD (%)
5.00
1.000
HVDD = 24.0V,
8Ω LOAD, 1kHz
-50
-55 HVDD = 24.0V, 8Ω LOAD,
-60 AT 1kHz, REFERENCE TO 30W
-65
-70
-75
-80
-85
-90
-95
-100
< -115dB, UN-WEIGHTED
-105
-110
-115
-120
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
dBFS
+0
FIGURE 4. NOISE FLOOR, FULL-BRIDGE
FN7678.0
September 3, 2010
D2-24044
Half-Bridge Typical Performance Curves
1.000
10.00
HVDD = 24.0V,
8Ω LOAD, 1kHz
5.00
0.500
0.200
0.100
1.00
THD (%)
THD (%)
2.00
0.50
0.20
0.050
0.020
0.010
0.10
0.005
0.05
0.002
0.02
0.06
0.1
0.2
0.5
1
2
POWER (W)
5
10
0.001
20
20
FIGURE 5. THD vs POWER, HALF-BRIDGE
12
10
8
DC RESPONSE WITHOUT
DC BLOCKING CAPACITOR
2
dBr A
dBr A
4
-0
-2
-4
-6
AC RESPONSE DUE TO LOUDSPEAKER
DC BLOCKING CAPACITOR
-8
-10
-12
20
50
100 200
500 1k
2k
FREQUENCY (Hz)
5k
10k 20k
FIGURE 7. FREQUENCY RESPONSE, HALF-BRIDGE
9
50
100
200
500 1k
2k
FREQUENCY (Hz)
5k
10k
20k
FIGURE 6. THD vs FREQUENCY, HALF-BRIDGE
HVDD = 24.0V,
8Ω LOAD, 1W
6
HVDD = 24.0V, 8Ω LOAD,
2.4W POWER OUT
-30
-35 NOISE FLOOR @ 1kHz, +24V RAIL,
-40
-45 SPDIF INPUT, 8Ω LOAD, UNITY DSP GAIN
-50
-55
-60
-65
-70
-75
-80
-85
-90
< -110dB, UN-WEIGHTED
-95
-100
-105
-110
-115
-120
-125
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
dBFS
+0
FIGURE 8. NOISE FLOOR, HALF-BRIDGE
FN7678.0
September 3, 2010
D2-24044
Functional Overview
The devices include four independent output stages
(Figure 9) that are each implemented using a high side
(to positive VDDHV supply) and a low side (to HV supply
ground) FET pair. Drivers and overcurrent monitoring are
included in each of these four output stages. Depending
on the selected configuration mode, these four stages
can be used independently as single half-bridge outputs,
or as pairs for full-bridge outputs.
Digital PWM inputs are connected to the PWM input pins,
where their signals are routed through the configuration
select logic to the individual output FETs and drivers.
On-chip temperature and undervoltage monitoring, and
individual per-output current monitoring provides
protection and status reporting outputs to the system
controller.
Upon application of power, the on-chip voltage sensors
monitor presence of the required power voltages. Until all
voltages are at their design specifications, the outputs
remain off and floating.
After supply voltages are within limits and stable, the
output configuration is set by the logic levels at the
OCFG0 and OCFG1 input pins, and the PWM inputs are
routed to their appropriate output stage FETs.
HSBSA
(+)
OUT
LOW
SIDE
FET
LOW SIDE
PWM DRIVE
nERROR
(GND)
HGND
OVERCURRENT
FIGURE 9. OUTPUT STAGE
Output Options
The D2-24044 devices provide four configuration options
for the outputs. These options are selected by strapping
the OCFG0 and OCFG1 pins high or low. These defined
configurations include:
• 2 Channels of Full Bridge, 4-Quadrant Outputs,
• 2 Channels of Full Bridge, 2-Quadrant Outputs
• 4 Channels of Half-Bridge Outputs
• 2 Channels Half-Bridge, Plus 1 Channel Full Bridge
When a configuration is set that includes a full-bridge
output, each input channel’s PWM input signal is routed
to the high and low side FETs, appropriate for that full
bridge operation. Note however, that the device can be
configured as 4 independent half-bridge outputs (using
10
Power Supply Requirements
The device operates from two supply voltages:
• PWMVDD is a nominal 3.3V supply voltage, and
operates the logic and control.
• HVDD (HVDD[A:D], and VDDHV) is the “high
voltage” used for operating the output power stages.
Individual HVDD and its ground (HGND) pins are
included for each of the four power stage outputs,
providing channel isolation and low impedance source
connections to each of the outputs. A separate VDDHV
pin is used for the output drivers, and is the source for
the on-chip regulated 5V source needed for the drivers.
All the HVDD/VDDHV pins connect to the same voltage
source.
PWMVDD is the reference for the PWM inputs and device
control logic, and is the same voltage as used by the
PWM/system controller.
High Side Gate Drive Voltage
HVDD
HIGH
SIDE
FET
HIGH-SIDE
PWM DRIVE
mode “11” as described in the configuration assignment
table on page 14) and two of those outputs can be used
in a full bridge configuration, simply by connecting the
appropriate PWM input pins to the input source. This
allows flexibility in applications where combinations may
be desired other than the four defined by the output
configuration modes.
An on-chip bootstrap circuit provides the high-side gate
drive voltage used by each output stage. A pin is
included for each output channel (HSBS[A:D]) for
connection of a capacitor (nominal, 0.22μF/50V) from
this pin to that channel’s PWM output. The charge
pumping actions uses this capacitor to filter and hold this
gate drive voltage, and enables amplifier operation
without need of connection to an additional power supply
voltage.
Supply Bypass Connection
Power supply bypass capacitors should be connected
across each of the power supply connection pins, as:
• Four HVDD power pins and their respective HGND
ground pins. These should be a parallel combination
of a nominal 100μF and 0.1μF capacitors, located as
close as possible to the HVDD/HGND pin pair.
• A 0.1μF capacitor also is to connect at the VDDHV
pin.
• The PWMVDD power pin should include a 1μF and
0.1μF capacitor.
REG5V
The on-chip gate drive power supply operates from the
VDDHV power input, to produce the 5V supply voltage.
The REG5V pin is used for external capacitor connection
to filter this regulated voltage. A 1.0μF and 0.1μF
capacitor should be connected to this pin, and the
connection should be made as close as practical to the
pin. No other connection is to be made to this pin.
FN7678.0
September 3, 2010
D2-24044
Input and Control Functions
PWM Inputs
Eight PWM input pins provide the PWM inputs to the
amplifier’s output stages. The PWM input pins are
electrically single-ended, referenced to the PWMVDD and
PWMGND supplies.
PWM drive to the output stages is provided differentially
on-chip, with the PWM input channels mapped to each of
the high-side output FETs and the low-side output FETs
that implement the individual power stages. Routing and
assignment of the PWM input pins to the output FETS is
defined by the configuration mode. Figures 11, 12, 13,
and 14 show the mapping of these input pins to the
outputs for each of the four configuration modes.
All eight input pins however are not always used in each
of the configuration modes. For example, in mode “00”,
providing 3-level drive of two channels of full bridge
outputs, or in mode “11” providing four independent
half-bridge outputs, one PWM input is dedicated to each
of the FETs. But in mode “01” that implements two
2-quadrant full-bridge outputs, only four PWM inputs are
used, and the logical high/low states are routed to the
FETs as needed.
nPDN Input Pin
The nPDN pin is a control input that is used to set the
inactive (powered down) state, and also mute the
outputs. It operates by turning off drive and internal
sources to the PWM outputs, as well as turning off the
PWM drive to those outputs.
When an overcurrent condition is detected on an output,
causing its overcurrent protection to latch and turn off
that output, asserting the nPDN input resets the device,
and clears this overcurrent state.
The nPDN pin is active low, and inactive when at logic
high level.
nERRORA-D Output Pins
Each of the four outputs includes an overload and
overcurrent monitor. An overcurrent or overload
condition asserts the nERROR output for that channel.
These outputs are active low, open drain. Depending on
the output mode configuration and need to monitor more
than one output, these nERROR pins can be wire-or
connected together.
nOVRT Output Pin
The nOVRT pin is an output that provides warning of a
high temperature condition. It is an open drain, active
low output. This pin provides only indication of high
temperature.
OCFG0, OCFG1 Input Pins
These two pins are used to define the configuration of the
four output stages. They are connected to logic high
(PWMVDD) or logic ground (PWMGND) to set their level.
Refer to “Output Mode Configurations” on page 14 for
additional reference and definition.
Protection
The D2-24044 device includes monitors for protection of
the system as well as the device itself. Certain levels of
protection are managed on-chip, as shown in Figure 10.
Other protection is integrated at the system level
through the system controller, and involves system
design decisions based on:
• A short circuit, over-temperature, or undervoltage
event will shut down the outputs.
• Other operation depends on the PWM/system
controller to properly manage full system protection
operation.
• Power supply sensors shut down the device if supply
voltages drop below their design thresholds.
• Overload and overcurrent monitors provide dual
threshold status of high current conditions, providing
both indication, and device shutdown if needed.
• Chip temperature monitoring provides dual threshold
status of high temperature conditions, providing
both indication, and device shutdown if needed.
Short-Circuit and Overcurrent Sensing
Each PWM output FET includes a dual-threshold
overcurrent sensor. Multiple functions occur depending
on detection of overcurrent conditions:
• The lower threshold is used to monitor fault
conditions after the output stage filter inductor, such
as shorts or overloads on the loudspeaker outputs.
• The higher threshold monitors fault conditions of the
PWM output pin.
• The nERROR output asserts for the channel detecting
the fault.
• For the lower level threshold, nERROR remains
asserted only through the duration of the
overcurrent event.
• For the higher level threshold, the output is shut
down, and its nERROR output is asserted, and these
remain latched until the controller acknowledges the
fault event by turning off the channel’s PWM drive.
(When the output is shutdown, its PWM output pin
floats.)
IREF Pin
The IREF pin is used to control the overcurrent
monitoring threshold. A 100kΩ resistor connects from
this pin to ground.
11
FN7678.0
September 3, 2010
D2-24044
Thermal Protection and Monitoring
Power Supply Voltage Monitoring
An on-chip temperature sensor provides two thresholds
of temperature monitoring.
Undervoltage monitors are included for the output drive
(HVDD) supply voltage, the on-chip generated gate drive
(REG5V) supply voltage, and the low-level PWMVDD
supply voltage. Detection occurs at approximately 2.5V
for PWMVDD, approximately 4V for the gate drive supply,
and approximately 7V for the HVDD supply. (Limits are
listed in the electrical specification tables starting on
page 4.)
If the device reaches the lower threshold, the nOVRT
output is asserted, providing warning indication to an
external controller. The low threshold setting provides
indication only, and does not have any effect on device
operation.
• The lower high-temperature threshold (warning) is
set at approximately +125°C.
If the device reaches the higher threshold, it will drive all
four nERRORA-D outputs low (active) and shut down the
device, in addition to asserting the nOVRT output. This
shutdown in non-latching, and operation will resume
automatically when temperature returns to normal.
If any of the monitored voltages drop below their
threshold, the device shuts down its outputs and asserts
all four of the nERROR outputs. Operation resumes
normally after the undervoltage condition is cleared.
• The higher high-temperature threshold (over-temp)
is set at approximately +140°C.
12
FN7678.0
September 3, 2010
D2-24044
OT Warning
(Low-Limit)
Over-Temperature
OT Shut-Down
Detectors
(High-Limit)
nOVRT
Pin
Over-Current
Warning Detected
(OUTA)
nERRORA
Pin
HVDD
Undervoltage
Detector
Over-Current
Warning Detected
(OUTB)
nERRORB
Pin
+5V
Undervoltage
Detector
Over-Current
Warning Detected
(OUTC)
nERRORC
Pin
PWMVDD
Undervoltage
Detector
Over-Current
Warning Detected
(OUTD)
nERRORD
Pin
nPDN
Pin
Over-Current Shutdown
OUTA
Over-Current
Short Detect
(OUTA)
S
Power Down
OUTA
R
PWM Input to
OUTA From
PWM Controller
PWM
Present
Detector
Over-Current Shutdown
OUTB
Over-Current
Short Detect
(OUTB)
S
Power Down
OUTB
R
PWM Input to
OUTB From
PWM Controller
PWM
Present
Detector
Over-Current Shutdown
OUTC
Over-Current
Short Detect
(OUTC)
S
Power Down
OUTC
R
PWM Input to
OUTC From
PWM Controller
PWM
Present
Detector
Over-Current Shutdown
OUTD
Over-Current
Short Detect
(OUTD)
S
Power Down
OUTD
R
PWM Input to
OUTD From
PWM Controller
PWM
Present
Detector
Over-Current (OC) Shutdown: OC detect condition is latched, shutting down
output. Latched shutdown is then cleared after over-current condition has
cleared, AND PWM data clocking has stopped from PWM controller.
FIGURE 10. PROTECTION AND MONITORING HIGH-LEVEL FUNCTIONAL OPERATION
13
FN7678.0
September 3, 2010
D2-24044
Output Mode Configurations
The D2-24044 device supports four amplifier output
configuration modes, utilizing the device’s 4 power stage
outputs.
Configuration selection is controlled by the OCFG0 and
OCFG1 pins, by connecting them to either a high
(+3.3V, PWMVDD = 1) or low (ground = 0) level.
Settings are chosen based on the output configuration
and topology of the design. Their connection is to be
hard-connected on the design, and they are not
intended to be dynamic or subject to change during
system operation.
For each of the four configurations, the PWM input pin
signals route to the individual FETs of each of the power
stages to implement the channel drive and topology
needed for those configurations. Figures 11, 12, 13, and
14 show this routing of the PWM inputs to each of the
power stages, and how the particular topology is
implemented for that configuration. Table 1 shows the
configuration functions that are defined with the
combinations of the OCFG pins, and these diagrams
show the implementation that is listed in this table.
TABLE 1. D2-24044 CONFIGURATION PWM AND OUTPUT CHANNEL ASSIGNMENTS
CONFIG PINS
OCFG1 OCFG0 CONFIG
0
0
CONFIGURATION
DESCRIPTION
POWER STAGE OUTPUT
OUTA
Output
Channel 1
1
1
0
1
Output
Channel 2
(Ref. Figure 11)
Low-Side FET PWM Input Assignments
PWM1
PWM3
PWM4
Output
Channel 1
PWM5
PWM6
PWM7
Output
Channel 2
High-Side FET PWM Input Assignments
(Ref. Figure 12)
Low-Side FET PWM Input Assignments
2-Channel
Half-Bridge
plus
1-Channel
Full Bridge
“10”
4-Channel
Half-Bridge
“11”
PWM1
PWM2
PWM1
Output
Ch. 1
Output
Ch 2
PWM1
PWM4
PWM4
PWM3
Output
Channel 3
PWM5
PWM6
PWM2
PWM4
PWM6
PWM5
Output
Ch. 1
Output
Ch 2
Output
Ch. 3
Output
Ch 4
High-Side FET PWM Input Assignments
PWM3
PWM5
PWM7
Low-Side FET PWM Input Assignments
PWM4
PWM6
Connect (wire-or)
Connect (wire-or)
nERRORA & nERRORB nERRORC & nERRORD
together.
together.
Use for Output
Use for Output
Channel 1 Protect
Channel 2 Protect
Connect (wire-or)
Connect (wire-or)
nERRORA & nERRORB nERRORC & nERRORD
together.
together.
Use for Output
Use for Output
Channel 1 Protect
Channel 2 Protect
PWM3
Low-Side FET PWM Input Assignments
PWM2
14
PWM3
High-Side FET PWM Input Assignments
PWM1
(Ref. Figure 14)
PWM2
nERRORA nERRORB nERRORC nERRORD
PWM8
2-Channel
Full Bridge,
2-Quadrant PWM Drive
(Ref. Figure 13)
1
OUTD
High-Side FET PWM Input Assignments
“00”
“01”
OUTC
2-Channel
Full Bridge
3-Level
PWM Drive
PWM2
0
OUTB
nERROR CHANNEL USE
Connect (wire-or)
nERRORA nERRORB
nERRORC & nERRORD
Use for
Use for
together.
Channel 1 Channel 2
Use for Output
Protect
Protect
Channel 3 Protect
nERRORA nERRORB nERRORC nERRORD
Use for
Use for
Use for
Use for
Channel 1 Channel 2 Channel 3 Channel 4
Protect
Protect
Protect
Protect
PWM8
FN7678.0
September 3, 2010
D2-24044
PWM1
PWMIN1-HI-1
PWM Input Mapping To Output Stages
Configuration “00”
2 x 4-Quadrant Full-Bridge Outputs
PWM2
PWMIN1-LO-1
Channel 1
PWM Input PWMIN1-HI-2
PWM3
PWM4
PWMIN1-LO-2
PWM5
PWMIN2-HI-1
PWM6
Channel 2
PWM Input
PWMIN2-LO-1
PWM7
PWMIN2-HI-2
PWM8
PWMIN2-LO-2
PWM Inputs From
PWM/System Controller
PWM1-8
Input Pins
(HVDD)
(HVDD)
(HVDD)
(HVDD)
High
Side
FET
High
Side
FET
High
Side
FET
High
Side
FET
Low
Side
FET
Low
Side
FET
Low
Side
FET
Low
Side
FET
(HGND)
(HGND)
(HGND)
(HGND)
OUTA
OUTB
OUTC
OUTD
Channel 1
Output
Channel 2
Output
FIGURE 11. CONFIGURATION “00” PWM INPUT-TO-OUTPUT POWER STAGE MAPPING
Channel 1
PWM Input
Channel 2
PWM Input
PWMIN1-HI
PWMIN1-LO
PWMIN2-HI
PWMIN2-LO
PWM1
PWM Input Mapping To Output Stages
Configuration “01”
2 x Full Bridge , 2-Quadrant Output
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM Inputs From
PWM/System Controller
PWM1-8
Input Pins
(HVDD)
(HVDD)
(HVDD)
(HVDD)
High
Side
FET
High
Side
FET
High
Side
FET
High
Side
FET
Low
Side
FET
Low
Side
FET
Low
Side
FET
Low
Side
FET
(HGND)
(HGND)
(HGND)
(HGND)
OUTA
OUTB
OUTC
OUTD
Channel 1
Output
Channel 2
Output
FIGURE 12. CONFIGURATION “01” PWM INPUT-TO-OUTPUT POWER STAGE MAPPING
15
FN7678.0
September 3, 2010
D2-24044
Channel 1
PWM Input
Channel 2
PWM Input
Channel 3
PWM Input
PWMIN1-HI
PWMIN1-LO
PWMIN2-HI
PWMIN2-LO
PWMIN3-HI
PWMIN3-LO
PWM1
PWM Input Mapping To Output Stages
Configuration “10”
2 x Half-Bridge Outputs + 1 x Full Bridge Output
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM Inputs From
PWM/System Controller
PWM1-8
Input Pins
(HVDD)
(HVDD)
(HVDD)
(HVDD)
High
Side
FET
High
Side
FET
High
Side
FET
High
Side
FET
Low
Side
FET
Low
Side
FET
Low
Side
FET
Low
Side
FET
(HGND)
(HGND)
(HGND)
(HGND)
OUTA
OUTB
OUTC
OUTD
Channel 1
Output
Channel 2
Output
Channel 2
Output
FIGURE 13. CONFIGURATION “10” PWM INPUT-TO-OUTPUT POWER STAGE MAPPING
Channel 1
PWM Input
Channel 2
PWM Input
Channel 3
PWM Input
Channel 3
PWM Input
PWMIN1-HI
PWMIN1-LO
PWMIN2-HI
PWMIN2-LO
PWMIN3-HI
PWMIN3-LO
PWMIN4-HI
PWMIN4-LO
PWM Inputs From
PWM/System Controller
PWM1
PWM Input Mapping To Output Stages
Configuration “11”
4x Half-Bridge Outputs
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM1-8
Input Pins
(HVDD)
(HVDD)
(HVDD)
(HVDD)
High
Side
FET
High
Side
FET
High
Side
FET
High
Side
FET
Low
Side
FET
Low
Side
FET
Low
Side
FET
Low
Side
FET
(HGND)
(HGND)
(HGND)
(HGND)
OUTA
OUTB
OUTC
OUTD
Channel 1
Output
Channel 2
Output
Channel 3
Output
Channel 4
Output
FIGURE 14. CONFIGURATION “11” PWM INPUT-TO-OUTPUT POWER STAGE MAPPING
16
FN7678.0
September 3, 2010
D2-24044
Typical Application Examples
2-Channel Full Bridge Example
These examples show functional circuit examples of
typical applications using the D2-24044 device. (Note:
These examples are provided to show typical applications
only and are not intended to represent complete
production-qualified reference designs.)
This example (Figure 15) uses configuration mode “01”
to provide two full-bridge loudspeaker output channels.
The PWM controller provides input into four PWM input
pins.
nPDN
Configuration “01”
2x Full Bridge Outputs
PWMVDD/+3.3
10k
1
2
10k
3
nOVRT
4
5
6
7
PWMIN1-HI
PWMIN1-LO
Channel 1 In
8
9
PWMIN2-HI
PWMIN2-LO
Channel 2 In
10
(no connect)
PWM Inputs From
PWM/System
Controller
(no connect)
(no connect)
(no connect)
11
12
13
14
15
16
For Channel 1 Output
17
18
For Channel 2 Output
19
nERROR Reporting to
PWM/System Controller
nPDN
HVDDA
OCFG1
HGNDA
OUTA
OCFG0
PWMGND
HSBSA
PWMVDD
HSBSB
nOVRT
OUTB
PWM1
HGNDB
PWM2
HVDDB
PWM3
REG5V
PWM4
VDDHV
PWM5
IREF
PWM6
HVDDC
PWM7
HGNDC
PWM8
OUTC
PWMGND2
HSBSC
nERRORA
HSBSD
nERRORB
OUTD
nERRORC
HGNDD
nERRORD
HVDDD
38
37
+HV
GND
36
Full Bridge
35
34
Output
Filter
33
32
31
GND
Channel 1
+HV
30
+HV
29
28
27
26
0.1u
100K
1u
0.1u
+HV
GND
25
Full Bridge
24
23
Output
Filter
22
21
20
GND
Channel 2
+HV
D2-24044
FIGURE 15. 2-CHANNEL FULL BRIDGE EXAMPLE
17
FN7678.0
September 3, 2010
D2-24044
2.1-Channel Example
This example (Figure 16) uses configuration mode “10”
to provide two independent half-bridge loudspeaker
output channels, plus one full-bridge loudspeaker output.
The PWM controller provides input into all eight PWM
input pins.
nPDN
Configuration “10”
2x Half Bridge Outputs, plus
1x Full Bridge Output
PWMVDD/+3.3
10k
Half Bridge
1
2
10k
3
nOVRT
4
5
6
7
PWMIN1-HI
Channel 1
PWMIN1-LO
8
9
PWMIN2-HI
Channel 2
PWMIN2-LO
10
11
PWMIN3-HI
Channel 3
PWMIN3-LO
(no connect)
PWM Inputs From
PWM/System
Controller
(no connect)
12
13
14
15
16
For Channel 1 Output
17
For Channel 2 Output
18
For Channel 3 Output
19
nERROR Reporting to
PWM/System Controller
nPDN
HVDDA
OCFG1
HGNDA
OCFG0
OUTA
PWMGND
HSBSA
PWMVDD
HSBSB
nOVRT
OUTB
PWM1
HGNDB
PWM2
HVDDB
PWM3
REG5V
PWM4
VDDHV
PWM5
IREF
PWM6
HVDDC
PWM7
HGNDC
PWM8
OUTC
PWMGND2
HSBSC
nERRORA
HSBSD
nERRORB
OUTD
nERRORC
HGNDD
nERRORD
HVDDD
38
37
+HV
Output
Filter
+HV
GND
36
Bias
35
Channel 1
34
Half Bridge
33
32
31
Output
Filter
+HV
GND
Bias
+HV
Channel 2
30
+HV
29
28
27
26
0.1u
100K
1u
0.1u
+HV
GND
25
Full Bridge
24
23
Output
Filter
22
21
20
GND
Channel 3
+HV
D2-24044
FIGURE 16. 2-CHANNEL HALF BRIDGE PLUS 1-CHANNEL FULL BRIDGE EXAMPLE
18
FN7678.0
September 3, 2010
D2-24044
4-Channel Half-Bridge Example
This example (Figure 17) uses configuration mode “11”
to provide four independent half-bridge loudspeaker
output channels. The PWM controller provides input into
all eight PWM input pins.
nPDN
Configuration “11”
4x Half Bridge Outputs
Half Bridge
PWMVDD/+3.3
10k
10k
1
2
3
nOVRT
4
5
PWM Inputs From
PWM/System Controller
PWMIN1-HI
6
7
Channel 1
PWMIN1-LO
PWMIN2-HI
9
Channel 2
PWMIN2-LO
PWMIN3-HI
10
11
Channel 3
PWMIN3-LO
PWMIN4-HI
8
12
13
Channel 3
PWMIN4-LO
14
15
16
For Channel 1 Output
17
For Channel 2 Output
18
For Channel 3 Output
19
For Channel 4 Output
nERROR Reporting to
PWM/System Controller
nPDN
HVDDA
OCFG1
HGNDA
OUTA
OCFG0
PWMGND
HSBSA
PWMVDD
HSBSB
nOVRT
OUTB
PWM1
HGNDB
PWM2
HVDDB
PWM3
REG5V
PWM4
VDDHV
PWM5
IREF
PWM6
HVDDC
PWM7
HGNDC
PWM8
OUTC
PWMGND2
HSBSC
nERRORA
HSBSD
nERRORB
OUTD
nERRORC
HGNDD
nERRORD
HVDDD
38
37
+HV
Output
Filter
+HV
GND
36
Bias
35
Channel 1
34
Half Bridge
33
32
31
Output
Filter
+HV
GND
Bias
+HV
Channel 2
30
+HV
29
28
27
26
0.1u
100K
1u
0.1u
+HV
Half Bridge
GND
25
24
+HV
23
Bias
Output
Filter
Channel 3
22
21
20
Half Bridge
GND
+HV
D2-24044
+HV
Bias
Output
Filter
Channel 4
FIGURE 17. 4-CHANNEL HALF BRIDGE EXAMPLE
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
19
FN7678.0
September 3, 2010
D2-24044
Package Outline Drawing
M38.173C
38 LEAD HEAT-SINK THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE (HTSSOP)
Rev 0, 4/10
PIN 1 ID
B
4.6±0.10
0.09-0.20
D
3 2 1
12 3
C
L
6.4
3.20±0.10
4.4±0.10
4
38
0.17-0.27
A
0.20 C A-B D
2X N/2 TIPS
0.08 M C A-B D 5
SEE
DETAIL "A"
EXPOSED PAD VIEW
END VIEW
TOP VIEW
(14°) TYP
(1.00)
1.10 MAX
0.05 C
0.90±0.05
0.25
C
PARTING
LINE
0.10 C
0.50
9.70±0.10
0.05/0.15
4
SEATING
PLANE
SIDE VIEW
H 3
(0-8°)
0.6±0.10
DETAIL "A"
SCALE: 30/1
(VIEW ROTATED 90°C.W.)
(4.60)
NOTES:
1. Die thickness allowable is 0.279±0.0127 (0.0110±0.0005 inches).
2. Dimensioning & tolerances per ASME. Y14.5m-1994.
(1.30)
(5.80)
(3.20)
3. Datum plane H located at mold parting line and coincident
with lead where lead exits plastic body at bottom of parting line.
4. At reference datum and does not include mold flash or protrusions,
and is measured at the bottom parting line. Mold flash or protrusions
shall not exceed 0.15mm on the package ends and 0.25mm between
the leads.
5. The lead width dimension does not include dambar protrusion.
Allowable dambar protrusion shall be 0.07mm total in excess of
the lead width dimension at maximum material condition. Dambar
cannot be located on the lower radius or the foot. Minimum space
between protrusions and an adjacent lead should be 0.08mm.
(36X 0.50)
(38X 0.28)
6. This part is compliant with JEDEC specification MO-153 variation BDT-1
TYPICAL RECOMMENDED LAND PATTERN
20
FN7678.0
September 3, 2010
Similar pages